pmap.c revision 209314
1/* 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * Copyright (c) 1994 John S. Dyson 5 * All rights reserved. 6 * Copyright (c) 1994 David Greenman 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * the Systems Programming Group of the University of Utah Computer 11 * Science Department and William Jolitz of UUNET Technologies Inc. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 38 * from: src/sys/i386/i386/pmap.c,v 1.250.2.8 2000/11/21 00:09:14 ps 39 * JNPR: pmap.c,v 1.11.2.1 2007/08/16 11:51:06 girish 40 */ 41 42/* 43 * Manages physical address maps. 44 * 45 * In addition to hardware address maps, this 46 * module is called upon to provide software-use-only 47 * maps which may or may not be stored in the same 48 * form as hardware maps. These pseudo-maps are 49 * used to store intermediate results from copy 50 * operations to and from address spaces. 51 * 52 * Since the information managed by this module is 53 * also stored by the logical address mapping module, 54 * this module may throw away valid virtual-to-physical 55 * mappings at almost any time. However, invalidations 56 * of virtual-to-physical mappings must be done as 57 * requested. 58 * 59 * In order to cope with hardware architectures which 60 * make virtual-to-physical map invalidates expensive, 61 * this module may delay invalidate or reduced protection 62 * operations until such time as they are actually 63 * necessary. This module is given full information as 64 * to which processors are currently using which maps, 65 * and to when physical maps must be made correct. 66 */ 67 68#include <sys/cdefs.h> 69__FBSDID("$FreeBSD: head/sys/mips/mips/pmap.c 209314 2010-06-18 20:07:30Z jchandra $"); 70 71#include "opt_ddb.h" 72#include "opt_msgbuf.h" 73#include <sys/param.h> 74#include <sys/systm.h> 75#include <sys/proc.h> 76#include <sys/msgbuf.h> 77#include <sys/vmmeter.h> 78#include <sys/mman.h> 79#include <sys/smp.h> 80 81#include <vm/vm.h> 82#include <vm/vm_param.h> 83#include <vm/vm_phys.h> 84#include <sys/lock.h> 85#include <sys/mutex.h> 86#include <vm/vm_kern.h> 87#include <vm/vm_page.h> 88#include <vm/vm_map.h> 89#include <vm/vm_object.h> 90#include <vm/vm_extern.h> 91#include <vm/vm_pageout.h> 92#include <vm/vm_pager.h> 93#include <vm/uma.h> 94#include <sys/pcpu.h> 95#include <sys/sched.h> 96#ifdef SMP 97#include <sys/smp.h> 98#endif 99 100#include <machine/cache.h> 101#include <machine/md_var.h> 102#include <machine/tlb.h> 103 104#if defined(DIAGNOSTIC) 105#define PMAP_DIAGNOSTIC 106#endif 107 108#undef PMAP_DEBUG 109 110#ifndef PMAP_SHPGPERPROC 111#define PMAP_SHPGPERPROC 200 112#endif 113 114#if !defined(PMAP_DIAGNOSTIC) 115#define PMAP_INLINE __inline 116#else 117#define PMAP_INLINE 118#endif 119 120/* 121 * Get PDEs and PTEs for user/kernel address space 122 */ 123#define pmap_pde(m, v) (&((m)->pm_segtab[(vm_offset_t)(v) >> SEGSHIFT])) 124#define segtab_pde(m, v) (m[(vm_offset_t)(v) >> SEGSHIFT]) 125 126#define pmap_pte_w(pte) ((*(int *)pte & PTE_W) != 0) 127#define pmap_pde_v(pte) ((*(int *)pte) != 0) 128#define pmap_pte_m(pte) ((*(int *)pte & PTE_M) != 0) 129#define pmap_pte_v(pte) ((*(int *)pte & PTE_V) != 0) 130 131#define pmap_pte_set_w(pte, v) ((v)?(*(int *)pte |= PTE_W):(*(int *)pte &= ~PTE_W)) 132#define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v))) 133 134#define MIPS_SEGSIZE (1L << SEGSHIFT) 135#define mips_segtrunc(va) ((va) & ~(MIPS_SEGSIZE-1)) 136#define pmap_TLB_invalidate_all() MIPS_TBIAP() 137#define pmap_va_asid(pmap, va) ((va) | ((pmap)->pm_asid[PCPU_GET(cpuid)].asid << VMTLB_PID_SHIFT)) 138#define is_kernel_pmap(x) ((x) == kernel_pmap) 139 140struct pmap kernel_pmap_store; 141pd_entry_t *kernel_segmap; 142 143vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 144vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 145 146static int nkpt; 147unsigned pmap_max_asid; /* max ASID supported by the system */ 148 149 150#define PMAP_ASID_RESERVED 0 151 152vm_offset_t kernel_vm_end; 153 154static void pmap_asid_alloc(pmap_t pmap); 155 156/* 157 * Data for the pv entry allocation mechanism 158 */ 159static uma_zone_t pvzone; 160static struct vm_object pvzone_obj; 161static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 162 163static PMAP_INLINE void free_pv_entry(pv_entry_t pv); 164static pv_entry_t get_pv_entry(pmap_t locked_pmap); 165static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va); 166static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, 167 vm_offset_t va); 168static __inline void pmap_changebit(vm_page_t m, int bit, boolean_t setem); 169 170static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, 171 vm_page_t m, vm_prot_t prot, vm_page_t mpte); 172static int pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va); 173static void pmap_remove_page(struct pmap *pmap, vm_offset_t va); 174static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, vm_offset_t va); 175static boolean_t pmap_testbit(vm_page_t m, int bit); 176static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_page_t mpte, 177 vm_offset_t va, vm_page_t m); 178 179static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags); 180 181static vm_page_t _pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags); 182static int pmap_unuse_pt(pmap_t, vm_offset_t, vm_page_t); 183static int init_pte_prot(vm_offset_t va, vm_page_t m, vm_prot_t prot); 184static vm_page_t pmap_alloc_pte_page(pmap_t, unsigned int, int, vm_offset_t *); 185static void pmap_release_pte_page(vm_page_t); 186 187#ifdef SMP 188static void pmap_invalidate_page_action(void *arg); 189static void pmap_invalidate_all_action(void *arg); 190static void pmap_update_page_action(void *arg); 191#endif 192 193static void pmap_ptpgzone_dtor(void *mem, int size, void *arg); 194static void *pmap_ptpgzone_allocf(uma_zone_t, int, u_int8_t *, int); 195static uma_zone_t ptpgzone; 196 197struct local_sysmaps { 198 vm_offset_t base; 199 uint16_t valid1, valid2; 200}; 201 202/* This structure is for large memory 203 * above 512Meg. We can't (in 32 bit mode) 204 * just use the direct mapped MIPS_KSEG0_TO_PHYS() 205 * macros since we can't see the memory and must 206 * map it in when we need to access it. In 64 207 * bit mode this goes away. 208 */ 209static struct local_sysmaps sysmap_lmem[MAXCPU]; 210 211#define PMAP_LMEM_MAP1(va, phys) \ 212 int cpu; \ 213 struct local_sysmaps *sysm; \ 214 pt_entry_t *pte, npte; \ 215 \ 216 intr = intr_disable(); \ 217 cpu = PCPU_GET(cpuid); \ 218 sysm = &sysmap_lmem[cpu]; \ 219 va = sysm->base; \ 220 npte = TLBLO_PA_TO_PFN(phys) | \ 221 PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; \ 222 pte = pmap_pte(kernel_pmap, va); \ 223 *pte = npte; \ 224 sysm->valid1 = 1; 225 226#define PMAP_LMEM_MAP2(va1, phys1, va2, phys2) \ 227 int cpu; \ 228 struct local_sysmaps *sysm; \ 229 pt_entry_t *pte, npte; \ 230 \ 231 intr = intr_disable(); \ 232 cpu = PCPU_GET(cpuid); \ 233 sysm = &sysmap_lmem[cpu]; \ 234 va1 = sysm->base; \ 235 va2 = sysm->base + PAGE_SIZE; \ 236 npte = TLBLO_PA_TO_PFN(phys1) | \ 237 PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; \ 238 pte = pmap_pte(kernel_pmap, va1); \ 239 *pte = npte; \ 240 npte = TLBLO_PA_TO_PFN(phys2) | \ 241 PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; \ 242 pte = pmap_pte(kernel_pmap, va2); \ 243 *pte = npte; \ 244 sysm->valid1 = 1; \ 245 sysm->valid2 = 1; 246 247#define PMAP_LMEM_UNMAP() \ 248 pte = pmap_pte(kernel_pmap, sysm->base); \ 249 *pte = PTE_G; \ 250 tlb_invalidate_address(kernel_pmap, sysm->base); \ 251 sysm->valid1 = 0; \ 252 pte = pmap_pte(kernel_pmap, sysm->base + PAGE_SIZE); \ 253 *pte = PTE_G; \ 254 tlb_invalidate_address(kernel_pmap, sysm->base + PAGE_SIZE); \ 255 sysm->valid2 = 0; \ 256 intr_restore(intr) 257 258pd_entry_t 259pmap_segmap(pmap_t pmap, vm_offset_t va) 260{ 261 if (pmap->pm_segtab) 262 return (pmap->pm_segtab[((vm_offset_t)(va) >> SEGSHIFT)]); 263 else 264 return ((pd_entry_t)0); 265} 266 267/* 268 * Routine: pmap_pte 269 * Function: 270 * Extract the page table entry associated 271 * with the given map/virtual_address pair. 272 */ 273pt_entry_t * 274pmap_pte(pmap_t pmap, vm_offset_t va) 275{ 276 pt_entry_t *pdeaddr; 277 278 if (pmap) { 279 pdeaddr = (pt_entry_t *)pmap_segmap(pmap, va); 280 if (pdeaddr) { 281 return pdeaddr + vad_to_pte_offset(va); 282 } 283 } 284 return ((pt_entry_t *)0); 285} 286 287 288vm_offset_t 289pmap_steal_memory(vm_size_t size) 290{ 291 vm_size_t bank_size; 292 vm_offset_t pa, va; 293 294 size = round_page(size); 295 296 bank_size = phys_avail[1] - phys_avail[0]; 297 while (size > bank_size) { 298 int i; 299 300 for (i = 0; phys_avail[i + 2]; i += 2) { 301 phys_avail[i] = phys_avail[i + 2]; 302 phys_avail[i + 1] = phys_avail[i + 3]; 303 } 304 phys_avail[i] = 0; 305 phys_avail[i + 1] = 0; 306 if (!phys_avail[0]) 307 panic("pmap_steal_memory: out of memory"); 308 bank_size = phys_avail[1] - phys_avail[0]; 309 } 310 311 pa = phys_avail[0]; 312 phys_avail[0] += size; 313 if (pa >= MIPS_KSEG0_LARGEST_PHYS) { 314 panic("Out of memory below 512Meg?"); 315 } 316 va = MIPS_PHYS_TO_KSEG0(pa); 317 bzero((caddr_t)va, size); 318 return va; 319} 320 321/* 322 * Bootstrap the system enough to run with virtual memory. This 323 * assumes that the phys_avail array has been initialized. 324 */ 325void 326pmap_bootstrap(void) 327{ 328 pt_entry_t *pgtab; 329 pt_entry_t *pte; 330 int i, j; 331 int memory_larger_than_512meg = 0; 332 333 /* Sort. */ 334again: 335 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 336 /* 337 * Keep the memory aligned on page boundary. 338 */ 339 phys_avail[i] = round_page(phys_avail[i]); 340 phys_avail[i + 1] = trunc_page(phys_avail[i + 1]); 341 342 if (phys_avail[i + 1] >= MIPS_KSEG0_LARGEST_PHYS) 343 memory_larger_than_512meg++; 344 if (i < 2) 345 continue; 346 if (phys_avail[i - 2] > phys_avail[i]) { 347 vm_paddr_t ptemp[2]; 348 349 350 ptemp[0] = phys_avail[i + 0]; 351 ptemp[1] = phys_avail[i + 1]; 352 353 phys_avail[i + 0] = phys_avail[i - 2]; 354 phys_avail[i + 1] = phys_avail[i - 1]; 355 356 phys_avail[i - 2] = ptemp[0]; 357 phys_avail[i - 1] = ptemp[1]; 358 goto again; 359 } 360 } 361 362 /* 363 * Copy the phys_avail[] array before we start stealing memory from it. 364 */ 365 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 366 physmem_desc[i] = phys_avail[i]; 367 physmem_desc[i + 1] = phys_avail[i + 1]; 368 } 369 370 Maxmem = atop(phys_avail[i - 1]); 371 372 if (bootverbose) { 373 printf("Physical memory chunk(s):\n"); 374 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 375 vm_paddr_t size; 376 377 size = phys_avail[i + 1] - phys_avail[i]; 378 printf("%#08jx - %#08jx, %ju bytes (%ju pages)\n", 379 (uintmax_t) phys_avail[i], 380 (uintmax_t) phys_avail[i + 1] - 1, 381 (uintmax_t) size, (uintmax_t) size / PAGE_SIZE); 382 } 383 printf("Maxmem is 0x%0lx\n", ptoa(Maxmem)); 384 } 385 /* 386 * Steal the message buffer from the beginning of memory. 387 */ 388 msgbufp = (struct msgbuf *)pmap_steal_memory(MSGBUF_SIZE); 389 msgbufinit(msgbufp, MSGBUF_SIZE); 390 391 /* 392 * Steal thread0 kstack. 393 */ 394 kstack0 = pmap_steal_memory(KSTACK_PAGES << PAGE_SHIFT); 395 396 397 virtual_avail = VM_MIN_KERNEL_ADDRESS; 398 virtual_end = VM_MAX_KERNEL_ADDRESS; 399 400#ifdef SMP 401 /* 402 * Steal some virtual address space to map the pcpu area. 403 */ 404 virtual_avail = roundup2(virtual_avail, PAGE_SIZE * 2); 405 pcpup = (struct pcpu *)virtual_avail; 406 virtual_avail += PAGE_SIZE * 2; 407 408 /* 409 * Initialize the wired TLB entry mapping the pcpu region for 410 * the BSP at 'pcpup'. Up until this point we were operating 411 * with the 'pcpup' for the BSP pointing to a virtual address 412 * in KSEG0 so there was no need for a TLB mapping. 413 */ 414 mips_pcpu_tlb_init(PCPU_ADDR(0)); 415 416 if (bootverbose) 417 printf("pcpu is available at virtual address %p.\n", pcpup); 418#endif 419 420 /* 421 * Steal some virtual space that will not be in kernel_segmap. This 422 * va memory space will be used to map in kernel pages that are 423 * outside the 512Meg region. Note that we only do this steal when 424 * we do have memory in this region, that way for systems with 425 * smaller memory we don't "steal" any va ranges :-) 426 */ 427 if (memory_larger_than_512meg) { 428 for (i = 0; i < MAXCPU; i++) { 429 sysmap_lmem[i].base = virtual_avail; 430 virtual_avail += PAGE_SIZE * 2; 431 sysmap_lmem[i].valid1 = sysmap_lmem[i].valid2 = 0; 432 } 433 } 434 435 /* 436 * Allocate segment table for the kernel 437 */ 438 kernel_segmap = (pd_entry_t *)pmap_steal_memory(PAGE_SIZE); 439 440 /* 441 * Allocate second level page tables for the kernel 442 */ 443 nkpt = NKPT; 444 if (memory_larger_than_512meg) { 445 /* 446 * If we have a large memory system we CANNOT afford to hit 447 * pmap_growkernel() and allocate memory. Since we MAY end 448 * up with a page that is NOT mappable. For that reason we 449 * up front grab more. Normall NKPT is 120 (YMMV see pmap.h) 450 * this gives us 480meg of kernel virtual addresses at the 451 * cost of 120 pages (each page gets us 4 Meg). Since the 452 * kernel starts at virtual_avail, we can use this to 453 * calculate how many entris are left from there to the end 454 * of the segmap, we want to allocate all of it, which would 455 * be somewhere above 0xC0000000 - 0xFFFFFFFF which results 456 * in about 256 entries or so instead of the 120. 457 */ 458 nkpt = (PAGE_SIZE / sizeof(pd_entry_t)) - (virtual_avail >> SEGSHIFT); 459 } 460 pgtab = (pt_entry_t *)pmap_steal_memory(PAGE_SIZE * nkpt); 461 462 /* 463 * The R[4-7]?00 stores only one copy of the Global bit in the 464 * translation lookaside buffer for each 2 page entry. Thus invalid 465 * entrys must have the Global bit set so when Entry LO and Entry HI 466 * G bits are anded together they will produce a global bit to store 467 * in the tlb. 468 */ 469 for (i = 0, pte = pgtab; i < (nkpt * NPTEPG); i++, pte++) 470 *pte = PTE_G; 471 472 /* 473 * The segment table contains the KVA of the pages in the second 474 * level page table. 475 */ 476 for (i = 0, j = (virtual_avail >> SEGSHIFT); i < nkpt; i++, j++) 477 kernel_segmap[j] = (pd_entry_t)(pgtab + (i * NPTEPG)); 478 479 /* 480 * The kernel's pmap is statically allocated so we don't have to use 481 * pmap_create, which is unlikely to work correctly at this part of 482 * the boot sequence (XXX and which no longer exists). 483 */ 484 PMAP_LOCK_INIT(kernel_pmap); 485 kernel_pmap->pm_segtab = kernel_segmap; 486 kernel_pmap->pm_active = ~0; 487 TAILQ_INIT(&kernel_pmap->pm_pvlist); 488 kernel_pmap->pm_asid[0].asid = PMAP_ASID_RESERVED; 489 kernel_pmap->pm_asid[0].gen = 0; 490 pmap_max_asid = VMNUM_PIDS; 491 mips_wr_entryhi(0); 492} 493 494/* 495 * Initialize a vm_page's machine-dependent fields. 496 */ 497void 498pmap_page_init(vm_page_t m) 499{ 500 501 TAILQ_INIT(&m->md.pv_list); 502 m->md.pv_list_count = 0; 503 m->md.pv_flags = 0; 504} 505 506/* 507 * Initialize the pmap module. 508 * Called by vm_init, to initialize any structures that the pmap 509 * system needs to map virtual memory. 510 * pmap_init has been enhanced to support in a fairly consistant 511 * way, discontiguous physical memory. 512 */ 513void 514pmap_init(void) 515{ 516 517 /* 518 * Initialize the address space (zone) for the pv entries. Set a 519 * high water mark so that the system can recover from excessive 520 * numbers of pv entries. 521 */ 522 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL, 523 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 524 pv_entry_max = PMAP_SHPGPERPROC * maxproc + cnt.v_page_count; 525 pv_entry_high_water = 9 * (pv_entry_max / 10); 526 uma_zone_set_obj(pvzone, &pvzone_obj, pv_entry_max); 527 528 ptpgzone = uma_zcreate("PT ENTRY", PAGE_SIZE, NULL, pmap_ptpgzone_dtor, 529 NULL, NULL, PAGE_SIZE - 1, UMA_ZONE_NOFREE | UMA_ZONE_ZINIT); 530 uma_zone_set_allocf(ptpgzone, pmap_ptpgzone_allocf); 531} 532 533/*************************************************** 534 * Low level helper routines..... 535 ***************************************************/ 536 537#if defined(PMAP_DIAGNOSTIC) 538 539/* 540 * This code checks for non-writeable/modified pages. 541 * This should be an invalid condition. 542 */ 543static int 544pmap_nw_modified(pt_entry_t pte) 545{ 546 if ((pte & (PTE_M | PTE_RO)) == (PTE_M | PTE_RO)) 547 return (1); 548 else 549 return (0); 550} 551 552#endif 553 554static void 555pmap_invalidate_all(pmap_t pmap) 556{ 557#ifdef SMP 558 smp_rendezvous(0, pmap_invalidate_all_action, 0, (void *)pmap); 559} 560 561static void 562pmap_invalidate_all_action(void *arg) 563{ 564 pmap_t pmap = (pmap_t)arg; 565 566#endif 567 568 if (pmap == kernel_pmap) { 569 tlb_invalidate_all(); 570 return; 571 } 572 573 if (pmap->pm_active & PCPU_GET(cpumask)) 574 tlb_invalidate_all_user(pmap); 575 else 576 pmap->pm_asid[PCPU_GET(cpuid)].gen = 0; 577} 578 579struct pmap_invalidate_page_arg { 580 pmap_t pmap; 581 vm_offset_t va; 582}; 583 584static __inline void 585pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 586{ 587#ifdef SMP 588 struct pmap_invalidate_page_arg arg; 589 590 arg.pmap = pmap; 591 arg.va = va; 592 593 smp_rendezvous(0, pmap_invalidate_page_action, 0, (void *)&arg); 594} 595 596static void 597pmap_invalidate_page_action(void *arg) 598{ 599 pmap_t pmap = ((struct pmap_invalidate_page_arg *)arg)->pmap; 600 vm_offset_t va = ((struct pmap_invalidate_page_arg *)arg)->va; 601 602#endif 603 604 if (is_kernel_pmap(pmap)) { 605 tlb_invalidate_address(pmap, va); 606 return; 607 } 608 if (pmap->pm_asid[PCPU_GET(cpuid)].gen != PCPU_GET(asid_generation)) 609 return; 610 else if (!(pmap->pm_active & PCPU_GET(cpumask))) { 611 pmap->pm_asid[PCPU_GET(cpuid)].gen = 0; 612 return; 613 } 614 tlb_invalidate_address(pmap, va); 615} 616 617struct pmap_update_page_arg { 618 pmap_t pmap; 619 vm_offset_t va; 620 pt_entry_t pte; 621}; 622 623void 624pmap_update_page(pmap_t pmap, vm_offset_t va, pt_entry_t pte) 625{ 626#ifdef SMP 627 struct pmap_update_page_arg arg; 628 629 arg.pmap = pmap; 630 arg.va = va; 631 arg.pte = pte; 632 633 smp_rendezvous(0, pmap_update_page_action, 0, (void *)&arg); 634} 635 636static void 637pmap_update_page_action(void *arg) 638{ 639 pmap_t pmap = ((struct pmap_update_page_arg *)arg)->pmap; 640 vm_offset_t va = ((struct pmap_update_page_arg *)arg)->va; 641 pt_entry_t pte = ((struct pmap_update_page_arg *)arg)->pte; 642 643#endif 644 if (is_kernel_pmap(pmap)) { 645 tlb_update(pmap, va, pte); 646 return; 647 } 648 if (pmap->pm_asid[PCPU_GET(cpuid)].gen != PCPU_GET(asid_generation)) 649 return; 650 else if (!(pmap->pm_active & PCPU_GET(cpumask))) { 651 pmap->pm_asid[PCPU_GET(cpuid)].gen = 0; 652 return; 653 } 654 tlb_update(pmap, va, pte); 655} 656 657/* 658 * Routine: pmap_extract 659 * Function: 660 * Extract the physical page address associated 661 * with the given map/virtual_address pair. 662 */ 663vm_paddr_t 664pmap_extract(pmap_t pmap, vm_offset_t va) 665{ 666 pt_entry_t *pte; 667 vm_offset_t retval = 0; 668 669 PMAP_LOCK(pmap); 670 pte = pmap_pte(pmap, va); 671 if (pte) { 672 retval = TLBLO_PTE_TO_PA(*pte) | (va & PAGE_MASK); 673 } 674 PMAP_UNLOCK(pmap); 675 return retval; 676} 677 678/* 679 * Routine: pmap_extract_and_hold 680 * Function: 681 * Atomically extract and hold the physical page 682 * with the given pmap and virtual address pair 683 * if that mapping permits the given protection. 684 */ 685vm_page_t 686pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 687{ 688 pt_entry_t pte; 689 vm_page_t m; 690 vm_paddr_t pa; 691 692 m = NULL; 693 pa = 0; 694 PMAP_LOCK(pmap); 695retry: 696 pte = *pmap_pte(pmap, va); 697 if (pte != 0 && pmap_pte_v(&pte) && 698 ((pte & PTE_RW) || (prot & VM_PROT_WRITE) == 0)) { 699 if (vm_page_pa_tryrelock(pmap, TLBLO_PTE_TO_PA(pte), &pa)) 700 goto retry; 701 702 m = PHYS_TO_VM_PAGE(TLBLO_PTE_TO_PA(pte)); 703 vm_page_hold(m); 704 } 705 PA_UNLOCK_COND(pa); 706 PMAP_UNLOCK(pmap); 707 return (m); 708} 709 710/*************************************************** 711 * Low level mapping routines..... 712 ***************************************************/ 713 714/* 715 * add a wired page to the kva 716 */ 717 /* PMAP_INLINE */ void 718pmap_kenter(vm_offset_t va, vm_paddr_t pa) 719{ 720 register pt_entry_t *pte; 721 pt_entry_t npte, opte; 722 723#ifdef PMAP_DEBUG 724 printf("pmap_kenter: va: 0x%08x -> pa: 0x%08x\n", va, pa); 725#endif 726 npte = TLBLO_PA_TO_PFN(pa) | PTE_RW | PTE_V | PTE_G | PTE_W; 727 728 if (is_cacheable_mem(pa)) 729 npte |= PTE_CACHE; 730 else 731 npte |= PTE_UNCACHED; 732 733 pte = pmap_pte(kernel_pmap, va); 734 opte = *pte; 735 *pte = npte; 736 737 pmap_update_page(kernel_pmap, va, npte); 738} 739 740/* 741 * remove a page from the kernel pagetables 742 */ 743 /* PMAP_INLINE */ void 744pmap_kremove(vm_offset_t va) 745{ 746 register pt_entry_t *pte; 747 748 /* 749 * Write back all caches from the page being destroyed 750 */ 751 mips_dcache_wbinv_range_index(va, PAGE_SIZE); 752 753 pte = pmap_pte(kernel_pmap, va); 754 *pte = PTE_G; 755 pmap_invalidate_page(kernel_pmap, va); 756} 757 758/* 759 * Used to map a range of physical addresses into kernel 760 * virtual address space. 761 * 762 * The value passed in '*virt' is a suggested virtual address for 763 * the mapping. Architectures which can support a direct-mapped 764 * physical to virtual region can return the appropriate address 765 * within that region, leaving '*virt' unchanged. Other 766 * architectures should map the pages starting at '*virt' and 767 * update '*virt' with the first usable address after the mapped 768 * region. 769 */ 770vm_offset_t 771pmap_map(vm_offset_t *virt, vm_offset_t start, vm_offset_t end, int prot) 772{ 773 vm_offset_t va, sva; 774 775 va = sva = *virt; 776 while (start < end) { 777 pmap_kenter(va, start); 778 va += PAGE_SIZE; 779 start += PAGE_SIZE; 780 } 781 *virt = va; 782 return (sva); 783} 784 785/* 786 * Add a list of wired pages to the kva 787 * this routine is only used for temporary 788 * kernel mappings that do not need to have 789 * page modification or references recorded. 790 * Note that old mappings are simply written 791 * over. The page *must* be wired. 792 */ 793void 794pmap_qenter(vm_offset_t va, vm_page_t *m, int count) 795{ 796 int i; 797 vm_offset_t origva = va; 798 799 for (i = 0; i < count; i++) { 800 pmap_flush_pvcache(m[i]); 801 pmap_kenter(va, VM_PAGE_TO_PHYS(m[i])); 802 va += PAGE_SIZE; 803 } 804 805 mips_dcache_wbinv_range_index(origva, PAGE_SIZE*count); 806} 807 808/* 809 * this routine jerks page mappings from the 810 * kernel -- it is meant only for temporary mappings. 811 */ 812void 813pmap_qremove(vm_offset_t va, int count) 814{ 815 /* 816 * No need to wb/inv caches here, 817 * pmap_kremove will do it for us 818 */ 819 820 while (count-- > 0) { 821 pmap_kremove(va); 822 va += PAGE_SIZE; 823 } 824} 825 826/*************************************************** 827 * Page table page management routines..... 828 ***************************************************/ 829 830/* Revision 1.507 831 * 832 * Simplify the reference counting of page table pages. Specifically, use 833 * the page table page's wired count rather than its hold count to contain 834 * the reference count. 835 */ 836 837/* 838 * This routine unholds page table pages, and if the hold count 839 * drops to zero, then it decrements the wire count. 840 */ 841static int 842_pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m) 843{ 844 845 /* 846 * unmap the page table page 847 */ 848 pmap->pm_segtab[m->pindex] = 0; 849 --pmap->pm_stats.resident_count; 850 851 if (pmap->pm_ptphint == m) 852 pmap->pm_ptphint = NULL; 853 854 /* 855 * If the page is finally unwired, simply free it. 856 */ 857 atomic_subtract_int(&cnt.v_wire_count, 1); 858 PMAP_UNLOCK(pmap); 859 vm_page_unlock_queues(); 860 pmap_release_pte_page(m); 861 vm_page_lock_queues(); 862 PMAP_LOCK(pmap); 863 return (1); 864} 865 866static PMAP_INLINE int 867pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m) 868{ 869 --m->wire_count; 870 if (m->wire_count == 0) 871 return (_pmap_unwire_pte_hold(pmap, m)); 872 else 873 return (0); 874} 875 876/* 877 * After removing a page table entry, this routine is used to 878 * conditionally free the page, and manage the hold/wire counts. 879 */ 880static int 881pmap_unuse_pt(pmap_t pmap, vm_offset_t va, vm_page_t mpte) 882{ 883 unsigned ptepindex; 884 pd_entry_t pteva; 885 886 if (va >= VM_MAXUSER_ADDRESS) 887 return (0); 888 889 if (mpte == NULL) { 890 ptepindex = (va >> SEGSHIFT); 891 if (pmap->pm_ptphint && 892 (pmap->pm_ptphint->pindex == ptepindex)) { 893 mpte = pmap->pm_ptphint; 894 } else { 895 pteva = *pmap_pde(pmap, va); 896 mpte = PHYS_TO_VM_PAGE(MIPS_KSEG0_TO_PHYS(pteva)); 897 pmap->pm_ptphint = mpte; 898 } 899 } 900 return pmap_unwire_pte_hold(pmap, mpte); 901} 902 903void 904pmap_pinit0(pmap_t pmap) 905{ 906 int i; 907 908 PMAP_LOCK_INIT(pmap); 909 pmap->pm_segtab = kernel_segmap; 910 pmap->pm_active = 0; 911 pmap->pm_ptphint = NULL; 912 for (i = 0; i < MAXCPU; i++) { 913 pmap->pm_asid[i].asid = PMAP_ASID_RESERVED; 914 pmap->pm_asid[i].gen = 0; 915 } 916 PCPU_SET(curpmap, pmap); 917 TAILQ_INIT(&pmap->pm_pvlist); 918 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 919} 920 921static void 922pmap_ptpgzone_dtor(void *mem, int size, void *arg) 923{ 924#ifdef INVARIANTS 925 static char zeropage[PAGE_SIZE]; 926 927 KASSERT(size == PAGE_SIZE, 928 ("pmap_ptpgzone_dtor: invalid size %d", size)); 929 KASSERT(bcmp(mem, zeropage, PAGE_SIZE) == 0, 930 ("pmap_ptpgzone_dtor: freeing a non-zeroed page")); 931#endif 932} 933 934static void * 935pmap_ptpgzone_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait) 936{ 937 vm_page_t m; 938 vm_paddr_t paddr; 939 int tries; 940 941 KASSERT(bytes == PAGE_SIZE, 942 ("pmap_ptpgzone_allocf: invalid allocation size %d", bytes)); 943 944 *flags = UMA_SLAB_PRIV; 945 tries = 0; 946retry: 947 m = vm_phys_alloc_contig(1, 0, MIPS_KSEG0_LARGEST_PHYS, 948 PAGE_SIZE, PAGE_SIZE); 949 if (m == NULL) { 950 if (tries < ((wait & M_NOWAIT) != 0 ? 1 : 3)) { 951 vm_contig_grow_cache(tries, 0, MIPS_KSEG0_LARGEST_PHYS); 952 tries++; 953 goto retry; 954 } else 955 return (NULL); 956 } 957 958 paddr = VM_PAGE_TO_PHYS(m); 959 return ((void *)MIPS_PHYS_TO_KSEG0(paddr)); 960} 961 962static vm_page_t 963pmap_alloc_pte_page(pmap_t pmap, unsigned int index, int wait, vm_offset_t *vap) 964{ 965 vm_paddr_t paddr; 966 void *va; 967 vm_page_t m; 968 int locked; 969 970 locked = mtx_owned(&pmap->pm_mtx); 971 if (locked) { 972 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 973 PMAP_UNLOCK(pmap); 974 vm_page_unlock_queues(); 975 } 976 va = uma_zalloc(ptpgzone, wait); 977 if (locked) { 978 vm_page_lock_queues(); 979 PMAP_LOCK(pmap); 980 } 981 if (va == NULL) 982 return (NULL); 983 984 paddr = MIPS_KSEG0_TO_PHYS(va); 985 m = PHYS_TO_VM_PAGE(paddr); 986 987 if (!locked) 988 vm_page_lock_queues(); 989 m->pindex = index; 990 m->valid = VM_PAGE_BITS_ALL; 991 m->wire_count = 1; 992 if (!locked) 993 vm_page_unlock_queues(); 994 995 atomic_add_int(&cnt.v_wire_count, 1); 996 *vap = (vm_offset_t)va; 997 return (m); 998} 999 1000static void 1001pmap_release_pte_page(vm_page_t m) 1002{ 1003 void *va; 1004 vm_paddr_t paddr; 1005 1006 paddr = VM_PAGE_TO_PHYS(m); 1007 va = (void *)MIPS_PHYS_TO_KSEG0(paddr); 1008 uma_zfree(ptpgzone, va); 1009} 1010 1011/* 1012 * Initialize a preallocated and zeroed pmap structure, 1013 * such as one in a vmspace structure. 1014 */ 1015int 1016pmap_pinit(pmap_t pmap) 1017{ 1018 vm_offset_t ptdva; 1019 vm_page_t ptdpg; 1020 int i; 1021 1022 PMAP_LOCK_INIT(pmap); 1023 1024 /* 1025 * allocate the page directory page 1026 */ 1027 ptdpg = pmap_alloc_pte_page(pmap, NUSERPGTBLS, M_WAITOK, &ptdva); 1028 if (ptdpg == NULL) 1029 return (0); 1030 1031 pmap->pm_segtab = (pd_entry_t *)ptdva; 1032 pmap->pm_active = 0; 1033 pmap->pm_ptphint = NULL; 1034 for (i = 0; i < MAXCPU; i++) { 1035 pmap->pm_asid[i].asid = PMAP_ASID_RESERVED; 1036 pmap->pm_asid[i].gen = 0; 1037 } 1038 TAILQ_INIT(&pmap->pm_pvlist); 1039 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1040 1041 return (1); 1042} 1043 1044/* 1045 * this routine is called if the page table page is not 1046 * mapped correctly. 1047 */ 1048static vm_page_t 1049_pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags) 1050{ 1051 vm_offset_t pteva; 1052 vm_page_t m; 1053 1054 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1055 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1056 ("_pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1057 1058 /* 1059 * Find or fabricate a new pagetable page 1060 */ 1061 m = pmap_alloc_pte_page(pmap, ptepindex, flags, &pteva); 1062 if (m == NULL) 1063 return (NULL); 1064 1065 /* 1066 * Map the pagetable page into the process address space, if it 1067 * isn't already there. 1068 */ 1069 1070 pmap->pm_stats.resident_count++; 1071 pmap->pm_segtab[ptepindex] = (pd_entry_t)pteva; 1072 1073 /* 1074 * Set the page table hint 1075 */ 1076 pmap->pm_ptphint = m; 1077 return (m); 1078} 1079 1080static vm_page_t 1081pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags) 1082{ 1083 unsigned ptepindex; 1084 vm_offset_t pteva; 1085 vm_page_t m; 1086 1087 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1088 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1089 ("pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1090 1091 /* 1092 * Calculate pagetable page index 1093 */ 1094 ptepindex = va >> SEGSHIFT; 1095retry: 1096 /* 1097 * Get the page directory entry 1098 */ 1099 pteva = (vm_offset_t)pmap->pm_segtab[ptepindex]; 1100 1101 /* 1102 * If the page table page is mapped, we just increment the hold 1103 * count, and activate it. 1104 */ 1105 if (pteva) { 1106 /* 1107 * In order to get the page table page, try the hint first. 1108 */ 1109 if (pmap->pm_ptphint && 1110 (pmap->pm_ptphint->pindex == ptepindex)) { 1111 m = pmap->pm_ptphint; 1112 } else { 1113 m = PHYS_TO_VM_PAGE(MIPS_KSEG0_TO_PHYS(pteva)); 1114 pmap->pm_ptphint = m; 1115 } 1116 m->wire_count++; 1117 } else { 1118 /* 1119 * Here if the pte page isn't mapped, or if it has been 1120 * deallocated. 1121 */ 1122 m = _pmap_allocpte(pmap, ptepindex, flags); 1123 if (m == NULL && (flags & M_WAITOK)) 1124 goto retry; 1125 } 1126 return m; 1127} 1128 1129 1130/*************************************************** 1131* Pmap allocation/deallocation routines. 1132 ***************************************************/ 1133/* 1134 * Revision 1.397 1135 * - Merged pmap_release and pmap_release_free_page. When pmap_release is 1136 * called only the page directory page(s) can be left in the pmap pte 1137 * object, since all page table pages will have been freed by 1138 * pmap_remove_pages and pmap_remove. In addition, there can only be one 1139 * reference to the pmap and the page directory is wired, so the page(s) 1140 * can never be busy. So all there is to do is clear the magic mappings 1141 * from the page directory and free the page(s). 1142 */ 1143 1144 1145/* 1146 * Release any resources held by the given physical map. 1147 * Called when a pmap initialized by pmap_pinit is being released. 1148 * Should only be called if the map contains no valid mappings. 1149 */ 1150void 1151pmap_release(pmap_t pmap) 1152{ 1153 vm_offset_t ptdva; 1154 vm_page_t ptdpg; 1155 1156 KASSERT(pmap->pm_stats.resident_count == 0, 1157 ("pmap_release: pmap resident count %ld != 0", 1158 pmap->pm_stats.resident_count)); 1159 1160 ptdva = (vm_offset_t)pmap->pm_segtab; 1161 ptdpg = PHYS_TO_VM_PAGE(MIPS_KSEG0_TO_PHYS(ptdva)); 1162 1163 ptdpg->wire_count--; 1164 atomic_subtract_int(&cnt.v_wire_count, 1); 1165 pmap_release_pte_page(ptdpg); 1166 PMAP_LOCK_DESTROY(pmap); 1167} 1168 1169/* 1170 * grow the number of kernel page table entries, if needed 1171 */ 1172void 1173pmap_growkernel(vm_offset_t addr) 1174{ 1175 vm_offset_t pageva; 1176 vm_page_t nkpg; 1177 pt_entry_t *pte; 1178 int i; 1179 1180 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 1181 if (kernel_vm_end == 0) { 1182 kernel_vm_end = VM_MIN_KERNEL_ADDRESS; 1183 nkpt = 0; 1184 while (segtab_pde(kernel_segmap, kernel_vm_end)) { 1185 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & 1186 ~(PAGE_SIZE * NPTEPG - 1); 1187 nkpt++; 1188 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1189 kernel_vm_end = kernel_map->max_offset; 1190 break; 1191 } 1192 } 1193 } 1194 addr = (addr + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1195 if (addr - 1 >= kernel_map->max_offset) 1196 addr = kernel_map->max_offset; 1197 while (kernel_vm_end < addr) { 1198 if (segtab_pde(kernel_segmap, kernel_vm_end)) { 1199 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & 1200 ~(PAGE_SIZE * NPTEPG - 1); 1201 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1202 kernel_vm_end = kernel_map->max_offset; 1203 break; 1204 } 1205 continue; 1206 } 1207 /* 1208 * This index is bogus, but out of the way 1209 */ 1210 nkpg = pmap_alloc_pte_page(kernel_pmap, nkpt, M_NOWAIT, &pageva); 1211 1212 if (!nkpg) 1213 panic("pmap_growkernel: no memory to grow kernel"); 1214 1215 nkpt++; 1216 pte = (pt_entry_t *)pageva; 1217 segtab_pde(kernel_segmap, kernel_vm_end) = (pd_entry_t)pte; 1218 1219 /* 1220 * The R[4-7]?00 stores only one copy of the Global bit in 1221 * the translation lookaside buffer for each 2 page entry. 1222 * Thus invalid entrys must have the Global bit set so when 1223 * Entry LO and Entry HI G bits are anded together they will 1224 * produce a global bit to store in the tlb. 1225 */ 1226 for (i = 0; i < NPTEPG; i++, pte++) 1227 *pte = PTE_G; 1228 1229 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & 1230 ~(PAGE_SIZE * NPTEPG - 1); 1231 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1232 kernel_vm_end = kernel_map->max_offset; 1233 break; 1234 } 1235 } 1236} 1237 1238/*************************************************** 1239* page management routines. 1240 ***************************************************/ 1241 1242/* 1243 * free the pv_entry back to the free list 1244 */ 1245static PMAP_INLINE void 1246free_pv_entry(pv_entry_t pv) 1247{ 1248 1249 pv_entry_count--; 1250 uma_zfree(pvzone, pv); 1251} 1252 1253/* 1254 * get a new pv_entry, allocating a block from the system 1255 * when needed. 1256 * the memory allocation is performed bypassing the malloc code 1257 * because of the possibility of allocations at interrupt time. 1258 */ 1259static pv_entry_t 1260get_pv_entry(pmap_t locked_pmap) 1261{ 1262 static const struct timeval printinterval = { 60, 0 }; 1263 static struct timeval lastprint; 1264 struct vpgqueues *vpq; 1265 pt_entry_t *pte, oldpte; 1266 pmap_t pmap; 1267 pv_entry_t allocated_pv, next_pv, pv; 1268 vm_offset_t va; 1269 vm_page_t m; 1270 1271 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED); 1272 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1273 allocated_pv = uma_zalloc(pvzone, M_NOWAIT); 1274 if (allocated_pv != NULL) { 1275 pv_entry_count++; 1276 if (pv_entry_count > pv_entry_high_water) 1277 pagedaemon_wakeup(); 1278 else 1279 return (allocated_pv); 1280 } 1281 /* 1282 * Reclaim pv entries: At first, destroy mappings to inactive 1283 * pages. After that, if a pv entry is still needed, destroy 1284 * mappings to active pages. 1285 */ 1286 if (ratecheck(&lastprint, &printinterval)) 1287 printf("Approaching the limit on PV entries, " 1288 "increase the vm.pmap.shpgperproc tunable.\n"); 1289 vpq = &vm_page_queues[PQ_INACTIVE]; 1290retry: 1291 TAILQ_FOREACH(m, &vpq->pl, pageq) { 1292 if (m->hold_count || m->busy) 1293 continue; 1294 TAILQ_FOREACH_SAFE(pv, &m->md.pv_list, pv_list, next_pv) { 1295 va = pv->pv_va; 1296 pmap = pv->pv_pmap; 1297 /* Avoid deadlock and lock recursion. */ 1298 if (pmap > locked_pmap) 1299 PMAP_LOCK(pmap); 1300 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) 1301 continue; 1302 pmap->pm_stats.resident_count--; 1303 pte = pmap_pte(pmap, va); 1304 KASSERT(pte != NULL, ("pte")); 1305 oldpte = loadandclear((u_int *)pte); 1306 if (is_kernel_pmap(pmap)) 1307 *pte = PTE_G; 1308 KASSERT((oldpte & PTE_W) == 0, 1309 ("wired pte for unwired page")); 1310 if (m->md.pv_flags & PV_TABLE_REF) 1311 vm_page_flag_set(m, PG_REFERENCED); 1312 if (oldpte & PTE_M) 1313 vm_page_dirty(m); 1314 pmap_invalidate_page(pmap, va); 1315 TAILQ_REMOVE(&pmap->pm_pvlist, pv, pv_plist); 1316 m->md.pv_list_count--; 1317 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 1318 pmap_unuse_pt(pmap, va, pv->pv_ptem); 1319 if (pmap != locked_pmap) 1320 PMAP_UNLOCK(pmap); 1321 if (allocated_pv == NULL) 1322 allocated_pv = pv; 1323 else 1324 free_pv_entry(pv); 1325 } 1326 if (TAILQ_EMPTY(&m->md.pv_list)) { 1327 vm_page_flag_clear(m, PG_WRITEABLE); 1328 m->md.pv_flags &= ~(PV_TABLE_REF | PV_TABLE_MOD); 1329 } 1330 } 1331 if (allocated_pv == NULL) { 1332 if (vpq == &vm_page_queues[PQ_INACTIVE]) { 1333 vpq = &vm_page_queues[PQ_ACTIVE]; 1334 goto retry; 1335 } 1336 panic("get_pv_entry: increase the vm.pmap.shpgperproc tunable"); 1337 } 1338 return (allocated_pv); 1339} 1340 1341/* 1342 * Revision 1.370 1343 * 1344 * Move pmap_collect() out of the machine-dependent code, rename it 1345 * to reflect its new location, and add page queue and flag locking. 1346 * 1347 * Notes: (1) alpha, i386, and ia64 had identical implementations 1348 * of pmap_collect() in terms of machine-independent interfaces; 1349 * (2) sparc64 doesn't require it; (3) powerpc had it as a TODO. 1350 * 1351 * MIPS implementation was identical to alpha [Junos 8.2] 1352 */ 1353 1354/* 1355 * If it is the first entry on the list, it is actually 1356 * in the header and we must copy the following entry up 1357 * to the header. Otherwise we must search the list for 1358 * the entry. In either case we free the now unused entry. 1359 */ 1360 1361static pv_entry_t 1362pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 1363{ 1364 pv_entry_t pv; 1365 1366 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1367 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1368 if (pvh->pv_list_count < pmap->pm_stats.resident_count) { 1369 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) { 1370 if (pmap == pv->pv_pmap && va == pv->pv_va) 1371 break; 1372 } 1373 } else { 1374 TAILQ_FOREACH(pv, &pmap->pm_pvlist, pv_plist) { 1375 if (va == pv->pv_va) 1376 break; 1377 } 1378 } 1379 if (pv != NULL) { 1380 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list); 1381 pvh->pv_list_count--; 1382 TAILQ_REMOVE(&pmap->pm_pvlist, pv, pv_plist); 1383 } 1384 return (pv); 1385} 1386 1387static void 1388pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 1389{ 1390 pv_entry_t pv; 1391 1392 pv = pmap_pvh_remove(pvh, pmap, va); 1393 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found, pa %lx va %lx", 1394 (u_long)VM_PAGE_TO_PHYS(member2struct(vm_page, md, pvh)), 1395 (u_long)va)); 1396 free_pv_entry(pv); 1397} 1398 1399static void 1400pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va) 1401{ 1402 1403 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1404 pmap_pvh_free(&m->md, pmap, va); 1405 if (TAILQ_EMPTY(&m->md.pv_list)) 1406 vm_page_flag_clear(m, PG_WRITEABLE); 1407} 1408 1409/* 1410 * Conditionally create a pv entry. 1411 */ 1412static boolean_t 1413pmap_try_insert_pv_entry(pmap_t pmap, vm_page_t mpte, vm_offset_t va, 1414 vm_page_t m) 1415{ 1416 pv_entry_t pv; 1417 1418 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1419 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1420 if (pv_entry_count < pv_entry_high_water && 1421 (pv = uma_zalloc(pvzone, M_NOWAIT)) != NULL) { 1422 pv_entry_count++; 1423 pv->pv_va = va; 1424 pv->pv_pmap = pmap; 1425 pv->pv_ptem = mpte; 1426 pv->pv_wired = FALSE; 1427 TAILQ_INSERT_TAIL(&pmap->pm_pvlist, pv, pv_plist); 1428 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 1429 m->md.pv_list_count++; 1430 return (TRUE); 1431 } else 1432 return (FALSE); 1433} 1434 1435/* 1436 * pmap_remove_pte: do the things to unmap a page in a process 1437 */ 1438static int 1439pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va) 1440{ 1441 pt_entry_t oldpte; 1442 vm_page_t m; 1443 vm_offset_t pa; 1444 1445 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1446 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1447 1448 oldpte = loadandclear((u_int *)ptq); 1449 if (is_kernel_pmap(pmap)) 1450 *ptq = PTE_G; 1451 1452 if (oldpte & PTE_W) 1453 pmap->pm_stats.wired_count -= 1; 1454 1455 pmap->pm_stats.resident_count -= 1; 1456 pa = TLBLO_PTE_TO_PA(oldpte); 1457 1458 if (page_is_managed(pa)) { 1459 m = PHYS_TO_VM_PAGE(pa); 1460 if (oldpte & PTE_M) { 1461#if defined(PMAP_DIAGNOSTIC) 1462 if (pmap_nw_modified(oldpte)) { 1463 printf( 1464 "pmap_remove: modified page not writable: va: 0x%x, pte: 0x%x\n", 1465 va, oldpte); 1466 } 1467#endif 1468 vm_page_dirty(m); 1469 } 1470 if (m->md.pv_flags & PV_TABLE_REF) 1471 vm_page_flag_set(m, PG_REFERENCED); 1472 m->md.pv_flags &= ~(PV_TABLE_REF | PV_TABLE_MOD); 1473 1474 pmap_remove_entry(pmap, m, va); 1475 } 1476 return pmap_unuse_pt(pmap, va, NULL); 1477} 1478 1479/* 1480 * Remove a single page from a process address space 1481 */ 1482static void 1483pmap_remove_page(struct pmap *pmap, vm_offset_t va) 1484{ 1485 register pt_entry_t *ptq; 1486 1487 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1488 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1489 ptq = pmap_pte(pmap, va); 1490 1491 /* 1492 * if there is no pte for this address, just skip it!!! 1493 */ 1494 if (!ptq || !pmap_pte_v(ptq)) { 1495 return; 1496 } 1497 1498 /* 1499 * Write back all caches from the page being destroyed 1500 */ 1501 mips_dcache_wbinv_range_index(va, PAGE_SIZE); 1502 1503 /* 1504 * get a local va for mappings for this pmap. 1505 */ 1506 (void)pmap_remove_pte(pmap, ptq, va); 1507 pmap_invalidate_page(pmap, va); 1508 1509 return; 1510} 1511 1512/* 1513 * Remove the given range of addresses from the specified map. 1514 * 1515 * It is assumed that the start and end are properly 1516 * rounded to the page size. 1517 */ 1518void 1519pmap_remove(struct pmap *pmap, vm_offset_t sva, vm_offset_t eva) 1520{ 1521 vm_offset_t va, nva; 1522 1523 if (pmap == NULL) 1524 return; 1525 1526 if (pmap->pm_stats.resident_count == 0) 1527 return; 1528 1529 vm_page_lock_queues(); 1530 PMAP_LOCK(pmap); 1531 1532 /* 1533 * special handling of removing one page. a very common operation 1534 * and easy to short circuit some code. 1535 */ 1536 if ((sva + PAGE_SIZE) == eva) { 1537 pmap_remove_page(pmap, sva); 1538 goto out; 1539 } 1540 for (va = sva; va < eva; va = nva) { 1541 if (!*pmap_pde(pmap, va)) { 1542 nva = mips_segtrunc(va + MIPS_SEGSIZE); 1543 continue; 1544 } 1545 pmap_remove_page(pmap, va); 1546 nva = va + PAGE_SIZE; 1547 } 1548 1549out: 1550 vm_page_unlock_queues(); 1551 PMAP_UNLOCK(pmap); 1552} 1553 1554/* 1555 * Routine: pmap_remove_all 1556 * Function: 1557 * Removes this physical page from 1558 * all physical maps in which it resides. 1559 * Reflects back modify bits to the pager. 1560 * 1561 * Notes: 1562 * Original versions of this routine were very 1563 * inefficient because they iteratively called 1564 * pmap_remove (slow...) 1565 */ 1566 1567void 1568pmap_remove_all(vm_page_t m) 1569{ 1570 register pv_entry_t pv; 1571 register pt_entry_t *pte, tpte; 1572 1573 KASSERT((m->flags & PG_FICTITIOUS) == 0, 1574 ("pmap_remove_all: page %p is fictitious", m)); 1575 vm_page_lock_queues(); 1576 1577 if (m->md.pv_flags & PV_TABLE_REF) 1578 vm_page_flag_set(m, PG_REFERENCED); 1579 1580 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 1581 PMAP_LOCK(pv->pv_pmap); 1582 1583 /* 1584 * If it's last mapping writeback all caches from 1585 * the page being destroyed 1586 */ 1587 if (m->md.pv_list_count == 1) 1588 mips_dcache_wbinv_range_index(pv->pv_va, PAGE_SIZE); 1589 1590 pv->pv_pmap->pm_stats.resident_count--; 1591 1592 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 1593 1594 tpte = loadandclear((u_int *)pte); 1595 if (is_kernel_pmap(pv->pv_pmap)) 1596 *pte = PTE_G; 1597 1598 if (tpte & PTE_W) 1599 pv->pv_pmap->pm_stats.wired_count--; 1600 1601 /* 1602 * Update the vm_page_t clean and reference bits. 1603 */ 1604 if (tpte & PTE_M) { 1605#if defined(PMAP_DIAGNOSTIC) 1606 if (pmap_nw_modified(tpte)) { 1607 printf( 1608 "pmap_remove_all: modified page not writable: va: 0x%x, pte: 0x%x\n", 1609 pv->pv_va, tpte); 1610 } 1611#endif 1612 vm_page_dirty(m); 1613 } 1614 pmap_invalidate_page(pv->pv_pmap, pv->pv_va); 1615 1616 TAILQ_REMOVE(&pv->pv_pmap->pm_pvlist, pv, pv_plist); 1617 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 1618 m->md.pv_list_count--; 1619 pmap_unuse_pt(pv->pv_pmap, pv->pv_va, pv->pv_ptem); 1620 PMAP_UNLOCK(pv->pv_pmap); 1621 free_pv_entry(pv); 1622 } 1623 1624 vm_page_flag_clear(m, PG_WRITEABLE); 1625 m->md.pv_flags &= ~(PV_TABLE_REF | PV_TABLE_MOD); 1626 vm_page_unlock_queues(); 1627} 1628 1629/* 1630 * Set the physical protection on the 1631 * specified range of this map as requested. 1632 */ 1633void 1634pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 1635{ 1636 pt_entry_t *pte; 1637 1638 if (pmap == NULL) 1639 return; 1640 1641 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1642 pmap_remove(pmap, sva, eva); 1643 return; 1644 } 1645 if (prot & VM_PROT_WRITE) 1646 return; 1647 1648 vm_page_lock_queues(); 1649 PMAP_LOCK(pmap); 1650 while (sva < eva) { 1651 pt_entry_t pbits, obits; 1652 vm_page_t m; 1653 vm_offset_t pa; 1654 1655 /* 1656 * If segment table entry is empty, skip this segment. 1657 */ 1658 if (!*pmap_pde(pmap, sva)) { 1659 sva = mips_segtrunc(sva + MIPS_SEGSIZE); 1660 continue; 1661 } 1662 /* 1663 * If pte is invalid, skip this page 1664 */ 1665 pte = pmap_pte(pmap, sva); 1666 if (!pmap_pte_v(pte)) { 1667 sva += PAGE_SIZE; 1668 continue; 1669 } 1670retry: 1671 obits = pbits = *pte; 1672 pa = TLBLO_PTE_TO_PA(pbits); 1673 1674 if (page_is_managed(pa) && (pbits & PTE_M) != 0) { 1675 m = PHYS_TO_VM_PAGE(pa); 1676 vm_page_dirty(m); 1677 m->md.pv_flags &= ~PV_TABLE_MOD; 1678 } 1679 pbits = (pbits & ~PTE_M) | PTE_RO; 1680 1681 if (pbits != *pte) { 1682 if (!atomic_cmpset_int((u_int *)pte, obits, pbits)) 1683 goto retry; 1684 pmap_update_page(pmap, sva, pbits); 1685 } 1686 sva += PAGE_SIZE; 1687 } 1688 vm_page_unlock_queues(); 1689 PMAP_UNLOCK(pmap); 1690} 1691 1692/* 1693 * Insert the given physical page (p) at 1694 * the specified virtual address (v) in the 1695 * target physical map with the protection requested. 1696 * 1697 * If specified, the page will be wired down, meaning 1698 * that the related pte can not be reclaimed. 1699 * 1700 * NB: This is the only routine which MAY NOT lazy-evaluate 1701 * or lose information. That is, this routine must actually 1702 * insert this page into the given map NOW. 1703 */ 1704void 1705pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m, 1706 vm_prot_t prot, boolean_t wired) 1707{ 1708 vm_offset_t pa, opa; 1709 register pt_entry_t *pte; 1710 pt_entry_t origpte, newpte; 1711 pv_entry_t pv; 1712 vm_page_t mpte, om; 1713 int rw = 0; 1714 1715 if (pmap == NULL) 1716 return; 1717 1718 va &= ~PAGE_MASK; 1719 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig")); 1720 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0 || 1721 (m->oflags & VPO_BUSY) != 0, 1722 ("pmap_enter: page %p is not busy", m)); 1723 1724 mpte = NULL; 1725 1726 vm_page_lock_queues(); 1727 PMAP_LOCK(pmap); 1728 1729 /* 1730 * In the case that a page table page is not resident, we are 1731 * creating it here. 1732 */ 1733 if (va < VM_MAXUSER_ADDRESS) { 1734 mpte = pmap_allocpte(pmap, va, M_WAITOK); 1735 } 1736 pte = pmap_pte(pmap, va); 1737 1738 /* 1739 * Page Directory table entry not valid, we need a new PT page 1740 */ 1741 if (pte == NULL) { 1742 panic("pmap_enter: invalid page directory, pdir=%p, va=%p\n", 1743 (void *)pmap->pm_segtab, (void *)va); 1744 } 1745 pa = VM_PAGE_TO_PHYS(m); 1746 om = NULL; 1747 origpte = *pte; 1748 opa = TLBLO_PTE_TO_PA(origpte); 1749 1750 /* 1751 * Mapping has not changed, must be protection or wiring change. 1752 */ 1753 if ((origpte & PTE_V) && (opa == pa)) { 1754 /* 1755 * Wiring change, just update stats. We don't worry about 1756 * wiring PT pages as they remain resident as long as there 1757 * are valid mappings in them. Hence, if a user page is 1758 * wired, the PT page will be also. 1759 */ 1760 if (wired && ((origpte & PTE_W) == 0)) 1761 pmap->pm_stats.wired_count++; 1762 else if (!wired && (origpte & PTE_W)) 1763 pmap->pm_stats.wired_count--; 1764 1765#if defined(PMAP_DIAGNOSTIC) 1766 if (pmap_nw_modified(origpte)) { 1767 printf( 1768 "pmap_enter: modified page not writable: va: 0x%x, pte: 0x%x\n", 1769 va, origpte); 1770 } 1771#endif 1772 1773 /* 1774 * Remove extra pte reference 1775 */ 1776 if (mpte) 1777 mpte->wire_count--; 1778 1779 if (page_is_managed(opa)) { 1780 om = m; 1781 } 1782 goto validate; 1783 } 1784 1785 pv = NULL; 1786 1787 /* 1788 * Mapping has changed, invalidate old range and fall through to 1789 * handle validating new mapping. 1790 */ 1791 if (opa) { 1792 if (origpte & PTE_W) 1793 pmap->pm_stats.wired_count--; 1794 1795 if (page_is_managed(opa)) { 1796 om = PHYS_TO_VM_PAGE(opa); 1797 pv = pmap_pvh_remove(&om->md, pmap, va); 1798 } 1799 if (mpte != NULL) { 1800 mpte->wire_count--; 1801 KASSERT(mpte->wire_count > 0, 1802 ("pmap_enter: missing reference to page table page," 1803 " va: %p", (void *)va)); 1804 } 1805 } else 1806 pmap->pm_stats.resident_count++; 1807 1808 /* 1809 * Enter on the PV list if part of our managed memory. Note that we 1810 * raise IPL while manipulating pv_table since pmap_enter can be 1811 * called at interrupt time. 1812 */ 1813 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) { 1814 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva, 1815 ("pmap_enter: managed mapping within the clean submap")); 1816 if (pv == NULL) 1817 pv = get_pv_entry(pmap); 1818 pv->pv_va = va; 1819 pv->pv_pmap = pmap; 1820 pv->pv_ptem = mpte; 1821 pv->pv_wired = wired; 1822 TAILQ_INSERT_TAIL(&pmap->pm_pvlist, pv, pv_plist); 1823 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 1824 m->md.pv_list_count++; 1825 } else if (pv != NULL) 1826 free_pv_entry(pv); 1827 1828 /* 1829 * Increment counters 1830 */ 1831 if (wired) 1832 pmap->pm_stats.wired_count++; 1833 1834validate: 1835 if ((access & VM_PROT_WRITE) != 0) 1836 m->md.pv_flags |= PV_TABLE_MOD | PV_TABLE_REF; 1837 rw = init_pte_prot(va, m, prot); 1838 1839#ifdef PMAP_DEBUG 1840 printf("pmap_enter: va: 0x%08x -> pa: 0x%08x\n", va, pa); 1841#endif 1842 /* 1843 * Now validate mapping with desired protection/wiring. 1844 */ 1845 newpte = TLBLO_PA_TO_PFN(pa) | rw | PTE_V; 1846 1847 if (is_cacheable_mem(pa)) 1848 newpte |= PTE_CACHE; 1849 else 1850 newpte |= PTE_UNCACHED; 1851 1852 if (wired) 1853 newpte |= PTE_W; 1854 1855 if (is_kernel_pmap(pmap)) { 1856 newpte |= PTE_G; 1857 } 1858 1859 /* 1860 * if the mapping or permission bits are different, we need to 1861 * update the pte. 1862 */ 1863 if (origpte != newpte) { 1864 if (origpte & PTE_V) { 1865 *pte = newpte; 1866 if (page_is_managed(opa) && (opa != pa)) { 1867 if (om->md.pv_flags & PV_TABLE_REF) 1868 vm_page_flag_set(om, PG_REFERENCED); 1869 om->md.pv_flags &= 1870 ~(PV_TABLE_REF | PV_TABLE_MOD); 1871 } 1872 if (origpte & PTE_M) { 1873 KASSERT((origpte & PTE_RW), 1874 ("pmap_enter: modified page not writable:" 1875 " va: %p, pte: 0x%x", (void *)va, origpte)); 1876 if (page_is_managed(opa)) 1877 vm_page_dirty(om); 1878 } 1879 if (page_is_managed(opa) && 1880 TAILQ_EMPTY(&om->md.pv_list)) 1881 vm_page_flag_clear(om, PG_WRITEABLE); 1882 } else { 1883 *pte = newpte; 1884 } 1885 } 1886 pmap_update_page(pmap, va, newpte); 1887 1888 /* 1889 * Sync I & D caches for executable pages. Do this only if the the 1890 * target pmap belongs to the current process. Otherwise, an 1891 * unresolvable TLB miss may occur. 1892 */ 1893 if (!is_kernel_pmap(pmap) && (pmap == &curproc->p_vmspace->vm_pmap) && 1894 (prot & VM_PROT_EXECUTE)) { 1895 mips_icache_sync_range(va, PAGE_SIZE); 1896 mips_dcache_wbinv_range(va, PAGE_SIZE); 1897 } 1898 vm_page_unlock_queues(); 1899 PMAP_UNLOCK(pmap); 1900} 1901 1902/* 1903 * this code makes some *MAJOR* assumptions: 1904 * 1. Current pmap & pmap exists. 1905 * 2. Not wired. 1906 * 3. Read access. 1907 * 4. No page table pages. 1908 * but is *MUCH* faster than pmap_enter... 1909 */ 1910 1911void 1912pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 1913{ 1914 1915 vm_page_lock_queues(); 1916 PMAP_LOCK(pmap); 1917 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL); 1918 vm_page_unlock_queues(); 1919 PMAP_UNLOCK(pmap); 1920} 1921 1922static vm_page_t 1923pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, 1924 vm_prot_t prot, vm_page_t mpte) 1925{ 1926 pt_entry_t *pte; 1927 vm_offset_t pa; 1928 1929 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva || 1930 (m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0, 1931 ("pmap_enter_quick_locked: managed mapping within the clean submap")); 1932 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1933 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1934 1935 /* 1936 * In the case that a page table page is not resident, we are 1937 * creating it here. 1938 */ 1939 if (va < VM_MAXUSER_ADDRESS) { 1940 unsigned ptepindex; 1941 vm_offset_t pteva; 1942 1943 /* 1944 * Calculate pagetable page index 1945 */ 1946 ptepindex = va >> SEGSHIFT; 1947 if (mpte && (mpte->pindex == ptepindex)) { 1948 mpte->wire_count++; 1949 } else { 1950 /* 1951 * Get the page directory entry 1952 */ 1953 pteva = (vm_offset_t)pmap->pm_segtab[ptepindex]; 1954 1955 /* 1956 * If the page table page is mapped, we just 1957 * increment the hold count, and activate it. 1958 */ 1959 if (pteva) { 1960 if (pmap->pm_ptphint && 1961 (pmap->pm_ptphint->pindex == ptepindex)) { 1962 mpte = pmap->pm_ptphint; 1963 } else { 1964 mpte = PHYS_TO_VM_PAGE( 1965 MIPS_KSEG0_TO_PHYS(pteva)); 1966 pmap->pm_ptphint = mpte; 1967 } 1968 mpte->wire_count++; 1969 } else { 1970 mpte = _pmap_allocpte(pmap, ptepindex, 1971 M_NOWAIT); 1972 if (mpte == NULL) 1973 return (mpte); 1974 } 1975 } 1976 } else { 1977 mpte = NULL; 1978 } 1979 1980 pte = pmap_pte(pmap, va); 1981 if (pmap_pte_v(pte)) { 1982 if (mpte != NULL) { 1983 mpte->wire_count--; 1984 mpte = NULL; 1985 } 1986 return (mpte); 1987 } 1988 1989 /* 1990 * Enter on the PV list if part of our managed memory. 1991 */ 1992 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0 && 1993 !pmap_try_insert_pv_entry(pmap, mpte, va, m)) { 1994 if (mpte != NULL) { 1995 pmap_unwire_pte_hold(pmap, mpte); 1996 mpte = NULL; 1997 } 1998 return (mpte); 1999 } 2000 2001 /* 2002 * Increment counters 2003 */ 2004 pmap->pm_stats.resident_count++; 2005 2006 pa = VM_PAGE_TO_PHYS(m); 2007 2008 /* 2009 * Now validate mapping with RO protection 2010 */ 2011 *pte = TLBLO_PA_TO_PFN(pa) | PTE_V; 2012 2013 if (is_cacheable_mem(pa)) 2014 *pte |= PTE_CACHE; 2015 else 2016 *pte |= PTE_UNCACHED; 2017 2018 if (is_kernel_pmap(pmap)) 2019 *pte |= PTE_G; 2020 else { 2021 *pte |= PTE_RO; 2022 /* 2023 * Sync I & D caches. Do this only if the the target pmap 2024 * belongs to the current process. Otherwise, an 2025 * unresolvable TLB miss may occur. */ 2026 if (pmap == &curproc->p_vmspace->vm_pmap) { 2027 va &= ~PAGE_MASK; 2028 mips_icache_sync_range(va, PAGE_SIZE); 2029 mips_dcache_wbinv_range(va, PAGE_SIZE); 2030 } 2031 } 2032 return (mpte); 2033} 2034 2035/* 2036 * Make a temporary mapping for a physical address. This is only intended 2037 * to be used for panic dumps. 2038 */ 2039void * 2040pmap_kenter_temporary(vm_paddr_t pa, int i) 2041{ 2042 vm_offset_t va; 2043 register_t intr; 2044 if (i != 0) 2045 printf("%s: ERROR!!! More than one page of virtual address mapping not supported\n", 2046 __func__); 2047 2048 if (pa < MIPS_KSEG0_LARGEST_PHYS) { 2049 va = MIPS_PHYS_TO_KSEG0(pa); 2050 } else { 2051 int cpu; 2052 struct local_sysmaps *sysm; 2053 pt_entry_t *pte, npte; 2054 2055 /* If this is used other than for dumps, we may need to leave 2056 * interrupts disasbled on return. If crash dumps don't work when 2057 * we get to this point, we might want to consider this (leaving things 2058 * disabled as a starting point ;-) 2059 */ 2060 intr = intr_disable(); 2061 cpu = PCPU_GET(cpuid); 2062 sysm = &sysmap_lmem[cpu]; 2063 /* Since this is for the debugger, no locks or any other fun */ 2064 npte = TLBLO_PA_TO_PFN(pa) | PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; 2065 pte = pmap_pte(kernel_pmap, sysm->base); 2066 *pte = npte; 2067 sysm->valid1 = 1; 2068 pmap_update_page(kernel_pmap, sysm->base, npte); 2069 va = sysm->base; 2070 intr_restore(intr); 2071 } 2072 return ((void *)va); 2073} 2074 2075void 2076pmap_kenter_temporary_free(vm_paddr_t pa) 2077{ 2078 int cpu; 2079 register_t intr; 2080 struct local_sysmaps *sysm; 2081 2082 if (pa < MIPS_KSEG0_LARGEST_PHYS) { 2083 /* nothing to do for this case */ 2084 return; 2085 } 2086 cpu = PCPU_GET(cpuid); 2087 sysm = &sysmap_lmem[cpu]; 2088 if (sysm->valid1) { 2089 pt_entry_t *pte; 2090 2091 intr = intr_disable(); 2092 pte = pmap_pte(kernel_pmap, sysm->base); 2093 *pte = PTE_G; 2094 pmap_invalidate_page(kernel_pmap, sysm->base); 2095 intr_restore(intr); 2096 sysm->valid1 = 0; 2097 } 2098} 2099 2100/* 2101 * Moved the code to Machine Independent 2102 * vm_map_pmap_enter() 2103 */ 2104 2105/* 2106 * Maps a sequence of resident pages belonging to the same object. 2107 * The sequence begins with the given page m_start. This page is 2108 * mapped at the given virtual address start. Each subsequent page is 2109 * mapped at a virtual address that is offset from start by the same 2110 * amount as the page is offset from m_start within the object. The 2111 * last page in the sequence is the page with the largest offset from 2112 * m_start that can be mapped at a virtual address less than the given 2113 * virtual address end. Not every virtual page between start and end 2114 * is mapped; only those for which a resident page exists with the 2115 * corresponding offset from m_start are mapped. 2116 */ 2117void 2118pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 2119 vm_page_t m_start, vm_prot_t prot) 2120{ 2121 vm_page_t m, mpte; 2122 vm_pindex_t diff, psize; 2123 2124 VM_OBJECT_LOCK_ASSERT(m_start->object, MA_OWNED); 2125 psize = atop(end - start); 2126 mpte = NULL; 2127 m = m_start; 2128 vm_page_lock_queues(); 2129 PMAP_LOCK(pmap); 2130 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 2131 mpte = pmap_enter_quick_locked(pmap, start + ptoa(diff), m, 2132 prot, mpte); 2133 m = TAILQ_NEXT(m, listq); 2134 } 2135 vm_page_unlock_queues(); 2136 PMAP_UNLOCK(pmap); 2137} 2138 2139/* 2140 * pmap_object_init_pt preloads the ptes for a given object 2141 * into the specified pmap. This eliminates the blast of soft 2142 * faults on process startup and immediately after an mmap. 2143 */ 2144void 2145pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, 2146 vm_object_t object, vm_pindex_t pindex, vm_size_t size) 2147{ 2148 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 2149 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 2150 ("pmap_object_init_pt: non-device object")); 2151} 2152 2153/* 2154 * Routine: pmap_change_wiring 2155 * Function: Change the wiring attribute for a map/virtual-address 2156 * pair. 2157 * In/out conditions: 2158 * The mapping must already exist in the pmap. 2159 */ 2160void 2161pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 2162{ 2163 register pt_entry_t *pte; 2164 2165 if (pmap == NULL) 2166 return; 2167 2168 PMAP_LOCK(pmap); 2169 pte = pmap_pte(pmap, va); 2170 2171 if (wired && !pmap_pte_w(pte)) 2172 pmap->pm_stats.wired_count++; 2173 else if (!wired && pmap_pte_w(pte)) 2174 pmap->pm_stats.wired_count--; 2175 2176 /* 2177 * Wiring is not a hardware characteristic so there is no need to 2178 * invalidate TLB. 2179 */ 2180 pmap_pte_set_w(pte, wired); 2181 PMAP_UNLOCK(pmap); 2182} 2183 2184/* 2185 * Copy the range specified by src_addr/len 2186 * from the source map to the range dst_addr/len 2187 * in the destination map. 2188 * 2189 * This routine is only advisory and need not do anything. 2190 */ 2191 2192void 2193pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, 2194 vm_size_t len, vm_offset_t src_addr) 2195{ 2196} 2197 2198/* 2199 * pmap_zero_page zeros the specified hardware page by mapping 2200 * the page into KVM and using bzero to clear its contents. 2201 */ 2202void 2203pmap_zero_page(vm_page_t m) 2204{ 2205 vm_offset_t va; 2206 vm_paddr_t phys = VM_PAGE_TO_PHYS(m); 2207 register_t intr; 2208 2209 if (phys < MIPS_KSEG0_LARGEST_PHYS) { 2210 va = MIPS_PHYS_TO_KSEG0(phys); 2211 2212 bzero((caddr_t)va, PAGE_SIZE); 2213 mips_dcache_wbinv_range(va, PAGE_SIZE); 2214 } else { 2215 PMAP_LMEM_MAP1(va, phys); 2216 2217 bzero((caddr_t)va, PAGE_SIZE); 2218 mips_dcache_wbinv_range(va, PAGE_SIZE); 2219 2220 PMAP_LMEM_UNMAP(); 2221 } 2222} 2223 2224/* 2225 * pmap_zero_page_area zeros the specified hardware page by mapping 2226 * the page into KVM and using bzero to clear its contents. 2227 * 2228 * off and size may not cover an area beyond a single hardware page. 2229 */ 2230void 2231pmap_zero_page_area(vm_page_t m, int off, int size) 2232{ 2233 vm_offset_t va; 2234 vm_paddr_t phys = VM_PAGE_TO_PHYS(m); 2235 register_t intr; 2236 2237 if (phys < MIPS_KSEG0_LARGEST_PHYS) { 2238 va = MIPS_PHYS_TO_KSEG0(phys); 2239 bzero((char *)(caddr_t)va + off, size); 2240 mips_dcache_wbinv_range(va + off, size); 2241 } else { 2242 PMAP_LMEM_MAP1(va, phys); 2243 2244 bzero((char *)va + off, size); 2245 mips_dcache_wbinv_range(va + off, size); 2246 2247 PMAP_LMEM_UNMAP(); 2248 } 2249} 2250 2251void 2252pmap_zero_page_idle(vm_page_t m) 2253{ 2254 vm_offset_t va; 2255 vm_paddr_t phys = VM_PAGE_TO_PHYS(m); 2256 register_t intr; 2257 2258 if (phys < MIPS_KSEG0_LARGEST_PHYS) { 2259 va = MIPS_PHYS_TO_KSEG0(phys); 2260 bzero((caddr_t)va, PAGE_SIZE); 2261 mips_dcache_wbinv_range(va, PAGE_SIZE); 2262 } else { 2263 PMAP_LMEM_MAP1(va, phys); 2264 2265 bzero((caddr_t)va, PAGE_SIZE); 2266 mips_dcache_wbinv_range(va, PAGE_SIZE); 2267 2268 PMAP_LMEM_UNMAP(); 2269 } 2270} 2271 2272/* 2273 * pmap_copy_page copies the specified (machine independent) 2274 * page by mapping the page into virtual memory and using 2275 * bcopy to copy the page, one machine dependent page at a 2276 * time. 2277 */ 2278void 2279pmap_copy_page(vm_page_t src, vm_page_t dst) 2280{ 2281 vm_offset_t va_src, va_dst; 2282 vm_paddr_t phy_src = VM_PAGE_TO_PHYS(src); 2283 vm_paddr_t phy_dst = VM_PAGE_TO_PHYS(dst); 2284 register_t intr; 2285 2286 if ((phy_src < MIPS_KSEG0_LARGEST_PHYS) && (phy_dst < MIPS_KSEG0_LARGEST_PHYS)) { 2287 /* easy case, all can be accessed via KSEG0 */ 2288 /* 2289 * Flush all caches for VA that are mapped to this page 2290 * to make sure that data in SDRAM is up to date 2291 */ 2292 pmap_flush_pvcache(src); 2293 mips_dcache_wbinv_range_index( 2294 MIPS_PHYS_TO_KSEG0(phy_dst), PAGE_SIZE); 2295 va_src = MIPS_PHYS_TO_KSEG0(phy_src); 2296 va_dst = MIPS_PHYS_TO_KSEG0(phy_dst); 2297 bcopy((caddr_t)va_src, (caddr_t)va_dst, PAGE_SIZE); 2298 mips_dcache_wbinv_range(va_dst, PAGE_SIZE); 2299 } else { 2300 PMAP_LMEM_MAP2(va_src, phy_src, va_dst, phy_dst); 2301 2302 bcopy((void *)va_src, (void *)va_dst, PAGE_SIZE); 2303 mips_dcache_wbinv_range(va_dst, PAGE_SIZE); 2304 2305 PMAP_LMEM_UNMAP(); 2306 } 2307} 2308 2309/* 2310 * Returns true if the pmap's pv is one of the first 2311 * 16 pvs linked to from this page. This count may 2312 * be changed upwards or downwards in the future; it 2313 * is only necessary that true be returned for a small 2314 * subset of pmaps for proper page aging. 2315 */ 2316boolean_t 2317pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 2318{ 2319 pv_entry_t pv; 2320 int loops = 0; 2321 boolean_t rv; 2322 2323 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2324 ("pmap_page_exists_quick: page %p is not managed", m)); 2325 rv = FALSE; 2326 vm_page_lock_queues(); 2327 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2328 if (pv->pv_pmap == pmap) { 2329 rv = TRUE; 2330 break; 2331 } 2332 loops++; 2333 if (loops >= 16) 2334 break; 2335 } 2336 vm_page_unlock_queues(); 2337 return (rv); 2338} 2339 2340/* 2341 * Remove all pages from specified address space 2342 * this aids process exit speeds. Also, this code 2343 * is special cased for current process only, but 2344 * can have the more generic (and slightly slower) 2345 * mode enabled. This is much faster than pmap_remove 2346 * in the case of running down an entire address space. 2347 */ 2348void 2349pmap_remove_pages(pmap_t pmap) 2350{ 2351 pt_entry_t *pte, tpte; 2352 pv_entry_t pv, npv; 2353 vm_page_t m; 2354 2355 if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) { 2356 printf("warning: pmap_remove_pages called with non-current pmap\n"); 2357 return; 2358 } 2359 vm_page_lock_queues(); 2360 PMAP_LOCK(pmap); 2361 sched_pin(); 2362 //XXX need to be TAILQ_FOREACH_SAFE ? 2363 for (pv = TAILQ_FIRST(&pmap->pm_pvlist); pv; pv = npv) { 2364 2365 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 2366 if (!pmap_pte_v(pte)) 2367 panic("pmap_remove_pages: page on pm_pvlist has no pte\n"); 2368 tpte = *pte; 2369 2370/* 2371 * We cannot remove wired pages from a process' mapping at this time 2372 */ 2373 if (tpte & PTE_W) { 2374 npv = TAILQ_NEXT(pv, pv_plist); 2375 continue; 2376 } 2377 *pte = is_kernel_pmap(pmap) ? PTE_G : 0; 2378 2379 m = PHYS_TO_VM_PAGE(TLBLO_PTE_TO_PA(tpte)); 2380 KASSERT(m != NULL, 2381 ("pmap_remove_pages: bad tpte %x", tpte)); 2382 2383 pv->pv_pmap->pm_stats.resident_count--; 2384 2385 /* 2386 * Update the vm_page_t clean and reference bits. 2387 */ 2388 if (tpte & PTE_M) { 2389 vm_page_dirty(m); 2390 } 2391 npv = TAILQ_NEXT(pv, pv_plist); 2392 TAILQ_REMOVE(&pv->pv_pmap->pm_pvlist, pv, pv_plist); 2393 2394 m->md.pv_list_count--; 2395 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2396 if (TAILQ_FIRST(&m->md.pv_list) == NULL) { 2397 vm_page_flag_clear(m, PG_WRITEABLE); 2398 } 2399 pmap_unuse_pt(pv->pv_pmap, pv->pv_va, pv->pv_ptem); 2400 free_pv_entry(pv); 2401 } 2402 sched_unpin(); 2403 pmap_invalidate_all(pmap); 2404 PMAP_UNLOCK(pmap); 2405 vm_page_unlock_queues(); 2406} 2407 2408/* 2409 * pmap_testbit tests bits in pte's 2410 * note that the testbit/changebit routines are inline, 2411 * and a lot of things compile-time evaluate. 2412 */ 2413static boolean_t 2414pmap_testbit(vm_page_t m, int bit) 2415{ 2416 pv_entry_t pv; 2417 pt_entry_t *pte; 2418 boolean_t rv = FALSE; 2419 2420 if (m->flags & PG_FICTITIOUS) 2421 return rv; 2422 2423 if (TAILQ_FIRST(&m->md.pv_list) == NULL) 2424 return rv; 2425 2426 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2427 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2428#if defined(PMAP_DIAGNOSTIC) 2429 if (!pv->pv_pmap) { 2430 printf("Null pmap (tb) at va: 0x%x\n", pv->pv_va); 2431 continue; 2432 } 2433#endif 2434 PMAP_LOCK(pv->pv_pmap); 2435 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 2436 rv = (*pte & bit) != 0; 2437 PMAP_UNLOCK(pv->pv_pmap); 2438 if (rv) 2439 break; 2440 } 2441 return (rv); 2442} 2443 2444/* 2445 * this routine is used to modify bits in ptes 2446 */ 2447static __inline void 2448pmap_changebit(vm_page_t m, int bit, boolean_t setem) 2449{ 2450 register pv_entry_t pv; 2451 register pt_entry_t *pte; 2452 2453 if (m->flags & PG_FICTITIOUS) 2454 return; 2455 2456 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2457 /* 2458 * Loop over all current mappings setting/clearing as appropos If 2459 * setting RO do we need to clear the VAC? 2460 */ 2461 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2462#if defined(PMAP_DIAGNOSTIC) 2463 if (!pv->pv_pmap) { 2464 printf("Null pmap (cb) at va: 0x%x\n", pv->pv_va); 2465 continue; 2466 } 2467#endif 2468 2469 PMAP_LOCK(pv->pv_pmap); 2470 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 2471 2472 if (setem) { 2473 *(int *)pte |= bit; 2474 pmap_update_page(pv->pv_pmap, pv->pv_va, *pte); 2475 } else { 2476 vm_offset_t pbits = *(vm_offset_t *)pte; 2477 2478 if (pbits & bit) { 2479 if (bit == PTE_RW) { 2480 if (pbits & PTE_M) { 2481 vm_page_dirty(m); 2482 } 2483 *(int *)pte = (pbits & ~(PTE_M | PTE_RW)) | 2484 PTE_RO; 2485 } else { 2486 *(int *)pte = pbits & ~bit; 2487 } 2488 pmap_update_page(pv->pv_pmap, pv->pv_va, *pte); 2489 } 2490 } 2491 PMAP_UNLOCK(pv->pv_pmap); 2492 } 2493 if (!setem && bit == PTE_RW) 2494 vm_page_flag_clear(m, PG_WRITEABLE); 2495} 2496 2497/* 2498 * pmap_page_wired_mappings: 2499 * 2500 * Return the number of managed mappings to the given physical page 2501 * that are wired. 2502 */ 2503int 2504pmap_page_wired_mappings(vm_page_t m) 2505{ 2506 pv_entry_t pv; 2507 int count; 2508 2509 count = 0; 2510 if ((m->flags & PG_FICTITIOUS) != 0) 2511 return (count); 2512 vm_page_lock_queues(); 2513 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) 2514 if (pv->pv_wired) 2515 count++; 2516 vm_page_unlock_queues(); 2517 return (count); 2518} 2519 2520/* 2521 * Clear the write and modified bits in each of the given page's mappings. 2522 */ 2523void 2524pmap_remove_write(vm_page_t m) 2525{ 2526 pv_entry_t pv, npv; 2527 vm_offset_t va; 2528 pt_entry_t *pte; 2529 2530 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2531 ("pmap_remove_write: page %p is not managed", m)); 2532 2533 /* 2534 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be set by 2535 * another thread while the object is locked. Thus, if PG_WRITEABLE 2536 * is clear, no page table entries need updating. 2537 */ 2538 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 2539 if ((m->oflags & VPO_BUSY) == 0 && 2540 (m->flags & PG_WRITEABLE) == 0) 2541 return; 2542 2543 /* 2544 * Loop over all current mappings setting/clearing as appropos. 2545 */ 2546 vm_page_lock_queues(); 2547 for (pv = TAILQ_FIRST(&m->md.pv_list); pv; pv = npv) { 2548 npv = TAILQ_NEXT(pv, pv_plist); 2549 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 2550 2551 if ((pte == NULL) || !mips_pg_v(*pte)) 2552 panic("page on pm_pvlist has no pte\n"); 2553 2554 va = pv->pv_va; 2555 pmap_protect(pv->pv_pmap, va, va + PAGE_SIZE, 2556 VM_PROT_READ | VM_PROT_EXECUTE); 2557 } 2558 vm_page_flag_clear(m, PG_WRITEABLE); 2559 vm_page_unlock_queues(); 2560} 2561 2562/* 2563 * pmap_ts_referenced: 2564 * 2565 * Return the count of reference bits for a page, clearing all of them. 2566 */ 2567int 2568pmap_ts_referenced(vm_page_t m) 2569{ 2570 2571 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2572 ("pmap_ts_referenced: page %p is not managed", m)); 2573 if (m->md.pv_flags & PV_TABLE_REF) { 2574 vm_page_lock_queues(); 2575 m->md.pv_flags &= ~PV_TABLE_REF; 2576 vm_page_unlock_queues(); 2577 return (1); 2578 } 2579 return (0); 2580} 2581 2582/* 2583 * pmap_is_modified: 2584 * 2585 * Return whether or not the specified physical page was modified 2586 * in any physical maps. 2587 */ 2588boolean_t 2589pmap_is_modified(vm_page_t m) 2590{ 2591 boolean_t rv; 2592 2593 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2594 ("pmap_is_modified: page %p is not managed", m)); 2595 2596 /* 2597 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be 2598 * concurrently set while the object is locked. Thus, if PG_WRITEABLE 2599 * is clear, no PTEs can have PTE_M set. 2600 */ 2601 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 2602 if ((m->oflags & VPO_BUSY) == 0 && 2603 (m->flags & PG_WRITEABLE) == 0) 2604 return (FALSE); 2605 vm_page_lock_queues(); 2606 if (m->md.pv_flags & PV_TABLE_MOD) 2607 rv = TRUE; 2608 else 2609 rv = pmap_testbit(m, PTE_M); 2610 vm_page_unlock_queues(); 2611 return (rv); 2612} 2613 2614/* N/C */ 2615 2616/* 2617 * pmap_is_prefaultable: 2618 * 2619 * Return whether or not the specified virtual address is elgible 2620 * for prefault. 2621 */ 2622boolean_t 2623pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 2624{ 2625 pt_entry_t *pte; 2626 boolean_t rv; 2627 2628 rv = FALSE; 2629 PMAP_LOCK(pmap); 2630 if (*pmap_pde(pmap, addr)) { 2631 pte = pmap_pte(pmap, addr); 2632 rv = (*pte == 0); 2633 } 2634 PMAP_UNLOCK(pmap); 2635 return (rv); 2636} 2637 2638/* 2639 * Clear the modify bits on the specified physical page. 2640 */ 2641void 2642pmap_clear_modify(vm_page_t m) 2643{ 2644 2645 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2646 ("pmap_clear_modify: page %p is not managed", m)); 2647 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 2648 KASSERT((m->oflags & VPO_BUSY) == 0, 2649 ("pmap_clear_modify: page %p is busy", m)); 2650 2651 /* 2652 * If the page is not PG_WRITEABLE, then no PTEs can have PTE_M set. 2653 * If the object containing the page is locked and the page is not 2654 * VPO_BUSY, then PG_WRITEABLE cannot be concurrently set. 2655 */ 2656 if ((m->flags & PG_WRITEABLE) == 0) 2657 return; 2658 vm_page_lock_queues(); 2659 if (m->md.pv_flags & PV_TABLE_MOD) { 2660 pmap_changebit(m, PTE_M, FALSE); 2661 m->md.pv_flags &= ~PV_TABLE_MOD; 2662 } 2663 vm_page_unlock_queues(); 2664} 2665 2666/* 2667 * pmap_is_referenced: 2668 * 2669 * Return whether or not the specified physical page was referenced 2670 * in any physical maps. 2671 */ 2672boolean_t 2673pmap_is_referenced(vm_page_t m) 2674{ 2675 2676 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2677 ("pmap_is_referenced: page %p is not managed", m)); 2678 return ((m->md.pv_flags & PV_TABLE_REF) != 0); 2679} 2680 2681/* 2682 * pmap_clear_reference: 2683 * 2684 * Clear the reference bit on the specified physical page. 2685 */ 2686void 2687pmap_clear_reference(vm_page_t m) 2688{ 2689 2690 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2691 ("pmap_clear_reference: page %p is not managed", m)); 2692 vm_page_lock_queues(); 2693 if (m->md.pv_flags & PV_TABLE_REF) { 2694 m->md.pv_flags &= ~PV_TABLE_REF; 2695 } 2696 vm_page_unlock_queues(); 2697} 2698 2699/* 2700 * Miscellaneous support routines follow 2701 */ 2702 2703/* 2704 * Map a set of physical memory pages into the kernel virtual 2705 * address space. Return a pointer to where it is mapped. This 2706 * routine is intended to be used for mapping device memory, 2707 * NOT real memory. 2708 */ 2709 2710/* 2711 * Map a set of physical memory pages into the kernel virtual 2712 * address space. Return a pointer to where it is mapped. This 2713 * routine is intended to be used for mapping device memory, 2714 * NOT real memory. 2715 */ 2716void * 2717pmap_mapdev(vm_offset_t pa, vm_size_t size) 2718{ 2719 vm_offset_t va, tmpva, offset; 2720 2721 /* 2722 * KSEG1 maps only first 512M of phys address space. For 2723 * pa > 0x20000000 we should make proper mapping * using pmap_kenter. 2724 */ 2725 if ((pa + size - 1) < MIPS_KSEG0_LARGEST_PHYS) 2726 return (void *)MIPS_PHYS_TO_KSEG1(pa); 2727 else { 2728 offset = pa & PAGE_MASK; 2729 size = roundup(size + offset, PAGE_SIZE); 2730 2731 va = kmem_alloc_nofault(kernel_map, size); 2732 if (!va) 2733 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 2734 pa = trunc_page(pa); 2735 for (tmpva = va; size > 0;) { 2736 pmap_kenter(tmpva, pa); 2737 size -= PAGE_SIZE; 2738 tmpva += PAGE_SIZE; 2739 pa += PAGE_SIZE; 2740 } 2741 } 2742 2743 return ((void *)(va + offset)); 2744} 2745 2746void 2747pmap_unmapdev(vm_offset_t va, vm_size_t size) 2748{ 2749 vm_offset_t base, offset, tmpva; 2750 2751 /* If the address is within KSEG1 then there is nothing to do */ 2752 if (va >= MIPS_KSEG1_START && va <= MIPS_KSEG1_END) 2753 return; 2754 2755 base = trunc_page(va); 2756 offset = va & PAGE_MASK; 2757 size = roundup(size + offset, PAGE_SIZE); 2758 for (tmpva = base; tmpva < base + size; tmpva += PAGE_SIZE) 2759 pmap_kremove(tmpva); 2760 kmem_free(kernel_map, base, size); 2761} 2762 2763/* 2764 * perform the pmap work for mincore 2765 */ 2766int 2767pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa) 2768{ 2769 pt_entry_t *ptep, pte; 2770 vm_offset_t pa; 2771 vm_page_t m; 2772 int val; 2773 boolean_t managed; 2774 2775 PMAP_LOCK(pmap); 2776retry: 2777 ptep = pmap_pte(pmap, addr); 2778 pte = (ptep != NULL) ? *ptep : 0; 2779 if (!mips_pg_v(pte)) { 2780 val = 0; 2781 goto out; 2782 } 2783 val = MINCORE_INCORE; 2784 if ((pte & PTE_M) != 0) 2785 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 2786 pa = TLBLO_PTE_TO_PA(pte); 2787 managed = page_is_managed(pa); 2788 if (managed) { 2789 /* 2790 * This may falsely report the given address as 2791 * MINCORE_REFERENCED. Unfortunately, due to the lack of 2792 * per-PTE reference information, it is impossible to 2793 * determine if the address is MINCORE_REFERENCED. 2794 */ 2795 m = PHYS_TO_VM_PAGE(pa); 2796 if ((m->flags & PG_REFERENCED) != 0) 2797 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 2798 } 2799 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) != 2800 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) { 2801 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */ 2802 if (vm_page_pa_tryrelock(pmap, pa, locked_pa)) 2803 goto retry; 2804 } else 2805out: 2806 PA_UNLOCK_COND(*locked_pa); 2807 PMAP_UNLOCK(pmap); 2808 return (val); 2809} 2810 2811void 2812pmap_activate(struct thread *td) 2813{ 2814 pmap_t pmap, oldpmap; 2815 struct proc *p = td->td_proc; 2816 2817 critical_enter(); 2818 2819 pmap = vmspace_pmap(p->p_vmspace); 2820 oldpmap = PCPU_GET(curpmap); 2821 2822 if (oldpmap) 2823 atomic_clear_32(&oldpmap->pm_active, PCPU_GET(cpumask)); 2824 atomic_set_32(&pmap->pm_active, PCPU_GET(cpumask)); 2825 pmap_asid_alloc(pmap); 2826 if (td == curthread) { 2827 PCPU_SET(segbase, pmap->pm_segtab); 2828 mips_wr_entryhi(pmap->pm_asid[PCPU_GET(cpuid)].asid); 2829 } 2830 2831 PCPU_SET(curpmap, pmap); 2832 critical_exit(); 2833} 2834 2835void 2836pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 2837{ 2838} 2839 2840/* 2841 * Increase the starting virtual address of the given mapping if a 2842 * different alignment might result in more superpage mappings. 2843 */ 2844void 2845pmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 2846 vm_offset_t *addr, vm_size_t size) 2847{ 2848 vm_offset_t superpage_offset; 2849 2850 if (size < NBSEG) 2851 return; 2852 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 2853 offset += ptoa(object->pg_color); 2854 superpage_offset = offset & SEGOFSET; 2855 if (size - ((NBSEG - superpage_offset) & SEGOFSET) < NBSEG || 2856 (*addr & SEGOFSET) == superpage_offset) 2857 return; 2858 if ((*addr & SEGOFSET) < superpage_offset) 2859 *addr = (*addr & ~SEGOFSET) + superpage_offset; 2860 else 2861 *addr = ((*addr + SEGOFSET) & ~SEGOFSET) + superpage_offset; 2862} 2863 2864/* 2865 * Increase the starting virtual address of the given mapping so 2866 * that it is aligned to not be the second page in a TLB entry. 2867 * This routine assumes that the length is appropriately-sized so 2868 * that the allocation does not share a TLB entry at all if required. 2869 */ 2870void 2871pmap_align_tlb(vm_offset_t *addr) 2872{ 2873 if ((*addr & PAGE_SIZE) == 0) 2874 return; 2875 *addr += PAGE_SIZE; 2876 return; 2877} 2878 2879int pmap_pid_dump(int pid); 2880 2881int 2882pmap_pid_dump(int pid) 2883{ 2884 pmap_t pmap; 2885 struct proc *p; 2886 int npte = 0; 2887 int index; 2888 2889 sx_slock(&allproc_lock); 2890 LIST_FOREACH(p, &allproc, p_list) { 2891 if (p->p_pid != pid) 2892 continue; 2893 2894 if (p->p_vmspace) { 2895 int i, j; 2896 2897 printf("vmspace is %p\n", 2898 p->p_vmspace); 2899 index = 0; 2900 pmap = vmspace_pmap(p->p_vmspace); 2901 printf("pmap asid:%x generation:%x\n", 2902 pmap->pm_asid[0].asid, 2903 pmap->pm_asid[0].gen); 2904 for (i = 0; i < NUSERPGTBLS; i++) { 2905 pd_entry_t *pde; 2906 pt_entry_t *pte; 2907 unsigned base = i << SEGSHIFT; 2908 2909 pde = &pmap->pm_segtab[i]; 2910 if (pde && pmap_pde_v(pde)) { 2911 for (j = 0; j < 1024; j++) { 2912 vm_offset_t va = base + 2913 (j << PAGE_SHIFT); 2914 2915 pte = pmap_pte(pmap, va); 2916 if (pte && pmap_pte_v(pte)) { 2917 vm_offset_t pa; 2918 vm_page_t m; 2919 2920 pa = TLBLO_PFN_TO_PA(*pte); 2921 m = PHYS_TO_VM_PAGE(pa); 2922 printf("va: %p, pt: %p, h: %d, w: %d, f: 0x%x", 2923 (void *)va, 2924 (void *)pa, 2925 m->hold_count, 2926 m->wire_count, 2927 m->flags); 2928 npte++; 2929 index++; 2930 if (index >= 2) { 2931 index = 0; 2932 printf("\n"); 2933 } else { 2934 printf(" "); 2935 } 2936 } 2937 } 2938 } 2939 } 2940 } else { 2941 printf("Process pid:%d has no vm_space\n", pid); 2942 } 2943 break; 2944 } 2945 sx_sunlock(&allproc_lock); 2946 return npte; 2947} 2948 2949 2950#if defined(DEBUG) 2951 2952static void pads(pmap_t pm); 2953void pmap_pvdump(vm_offset_t pa); 2954 2955/* print address space of pmap*/ 2956static void 2957pads(pmap_t pm) 2958{ 2959 unsigned va, i, j; 2960 pt_entry_t *ptep; 2961 2962 if (pm == kernel_pmap) 2963 return; 2964 for (i = 0; i < NPTEPG; i++) 2965 if (pm->pm_segtab[i]) 2966 for (j = 0; j < NPTEPG; j++) { 2967 va = (i << SEGSHIFT) + (j << PAGE_SHIFT); 2968 if (pm == kernel_pmap && va < KERNBASE) 2969 continue; 2970 if (pm != kernel_pmap && 2971 va >= VM_MAXUSER_ADDRESS) 2972 continue; 2973 ptep = pmap_pte(pm, va); 2974 if (pmap_pte_v(ptep)) 2975 printf("%x:%x ", va, *(int *)ptep); 2976 } 2977 2978} 2979 2980void 2981pmap_pvdump(vm_offset_t pa) 2982{ 2983 register pv_entry_t pv; 2984 vm_page_t m; 2985 2986 printf("pa %x", pa); 2987 m = PHYS_TO_VM_PAGE(pa); 2988 for (pv = TAILQ_FIRST(&m->md.pv_list); pv; 2989 pv = TAILQ_NEXT(pv, pv_list)) { 2990 printf(" -> pmap %p, va %x", (void *)pv->pv_pmap, pv->pv_va); 2991 pads(pv->pv_pmap); 2992 } 2993 printf(" "); 2994} 2995 2996/* N/C */ 2997#endif 2998 2999 3000/* 3001 * Allocate TLB address space tag (called ASID or TLBPID) and return it. 3002 * It takes almost as much or more time to search the TLB for a 3003 * specific ASID and flush those entries as it does to flush the entire TLB. 3004 * Therefore, when we allocate a new ASID, we just take the next number. When 3005 * we run out of numbers, we flush the TLB, increment the generation count 3006 * and start over. ASID zero is reserved for kernel use. 3007 */ 3008static void 3009pmap_asid_alloc(pmap) 3010 pmap_t pmap; 3011{ 3012 if (pmap->pm_asid[PCPU_GET(cpuid)].asid != PMAP_ASID_RESERVED && 3013 pmap->pm_asid[PCPU_GET(cpuid)].gen == PCPU_GET(asid_generation)); 3014 else { 3015 if (PCPU_GET(next_asid) == pmap_max_asid) { 3016 tlb_invalidate_all_user(NULL); 3017 PCPU_SET(asid_generation, 3018 (PCPU_GET(asid_generation) + 1) & ASIDGEN_MASK); 3019 if (PCPU_GET(asid_generation) == 0) { 3020 PCPU_SET(asid_generation, 1); 3021 } 3022 PCPU_SET(next_asid, 1); /* 0 means invalid */ 3023 } 3024 pmap->pm_asid[PCPU_GET(cpuid)].asid = PCPU_GET(next_asid); 3025 pmap->pm_asid[PCPU_GET(cpuid)].gen = PCPU_GET(asid_generation); 3026 PCPU_SET(next_asid, PCPU_GET(next_asid) + 1); 3027 } 3028} 3029 3030int 3031page_is_managed(vm_offset_t pa) 3032{ 3033 vm_offset_t pgnum = mips_btop(pa); 3034 3035 if (pgnum >= first_page) { 3036 vm_page_t m; 3037 3038 m = PHYS_TO_VM_PAGE(pa); 3039 if (m == NULL) 3040 return 0; 3041 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) 3042 return 1; 3043 } 3044 return 0; 3045} 3046 3047static int 3048init_pte_prot(vm_offset_t va, vm_page_t m, vm_prot_t prot) 3049{ 3050 int rw; 3051 3052 if (!(prot & VM_PROT_WRITE)) 3053 rw = PTE_ROPAGE; 3054 else if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) { 3055 if ((m->md.pv_flags & PV_TABLE_MOD) != 0) 3056 rw = PTE_RWPAGE; 3057 else 3058 rw = PTE_CWPAGE; 3059 vm_page_flag_set(m, PG_WRITEABLE); 3060 } else 3061 /* Needn't emulate a modified bit for unmanaged pages. */ 3062 rw = PTE_RWPAGE; 3063 return (rw); 3064} 3065 3066/* 3067 * pmap_set_modified: 3068 * 3069 * Sets the page modified and reference bits for the specified page. 3070 */ 3071void 3072pmap_set_modified(vm_offset_t pa) 3073{ 3074 3075 PHYS_TO_VM_PAGE(pa)->md.pv_flags |= (PV_TABLE_REF | PV_TABLE_MOD); 3076} 3077 3078/* 3079 * Routine: pmap_kextract 3080 * Function: 3081 * Extract the physical page address associated 3082 * virtual address. 3083 */ 3084 /* PMAP_INLINE */ vm_offset_t 3085pmap_kextract(vm_offset_t va) 3086{ 3087 vm_offset_t pa = 0; 3088 3089 if (va < MIPS_KSEG0_START) { 3090 /* user virtual address */ 3091 pt_entry_t *ptep; 3092 3093 if (curproc && curproc->p_vmspace) { 3094 ptep = pmap_pte(&curproc->p_vmspace->vm_pmap, va); 3095 if (ptep) 3096 pa = TLBLO_PTE_TO_PA(*ptep) | 3097 (va & PAGE_MASK); 3098 } 3099 } else if (va >= MIPS_KSEG0_START && 3100 va < MIPS_KSEG1_START) 3101 pa = MIPS_KSEG0_TO_PHYS(va); 3102 else if (va >= MIPS_KSEG1_START && 3103 va < MIPS_KSEG2_START) 3104 pa = MIPS_KSEG1_TO_PHYS(va); 3105 else if (va >= MIPS_KSEG2_START && va < VM_MAX_KERNEL_ADDRESS) { 3106 pt_entry_t *ptep; 3107 3108 /* Is the kernel pmap initialized? */ 3109 if (kernel_pmap->pm_active) { 3110 /* Its inside the virtual address range */ 3111 ptep = pmap_pte(kernel_pmap, va); 3112 if (ptep) { 3113 return (TLBLO_PTE_TO_PA(*ptep) | 3114 (va & PAGE_MASK)); 3115 } 3116 return (0); 3117 } 3118 } 3119 return pa; 3120} 3121 3122void 3123pmap_flush_pvcache(vm_page_t m) 3124{ 3125 pv_entry_t pv; 3126 3127 if (m != NULL) { 3128 for (pv = TAILQ_FIRST(&m->md.pv_list); pv; 3129 pv = TAILQ_NEXT(pv, pv_list)) { 3130 mips_dcache_wbinv_range_index(pv->pv_va, PAGE_SIZE); 3131 } 3132 } 3133} 3134