pmap.c revision 208589
1139735Simp/* 2129198Scognet * Copyright (c) 1991 Regents of the University of California. 3129198Scognet * All rights reserved. 4129198Scognet * Copyright (c) 1994 John S. Dyson 5129198Scognet * All rights reserved. 6129198Scognet * Copyright (c) 1994 David Greenman 7129198Scognet * All rights reserved. 8129198Scognet * 9129198Scognet * This code is derived from software contributed to Berkeley by 10129198Scognet * the Systems Programming Group of the University of Utah Computer 11129198Scognet * Science Department and William Jolitz of UUNET Technologies Inc. 12129198Scognet * 13129198Scognet * Redistribution and use in source and binary forms, with or without 14129198Scognet * modification, are permitted provided that the following conditions 15129198Scognet * are met: 16129198Scognet * 1. Redistributions of source code must retain the above copyright 17129198Scognet * notice, this list of conditions and the following disclaimer. 18129198Scognet * 2. Redistributions in binary form must reproduce the above copyright 19129198Scognet * notice, this list of conditions and the following disclaimer in the 20129198Scognet * documentation and/or other materials provided with the distribution. 21129198Scognet * 4. Neither the name of the University nor the names of its contributors 22129198Scognet * may be used to endorse or promote products derived from this software 23129198Scognet * without specific prior written permission. 24129198Scognet * 25129198Scognet * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26129198Scognet * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27129198Scognet * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28129198Scognet * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29129198Scognet * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30129198Scognet * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31129198Scognet * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32217290Smarcel * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33217290Smarcel * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34129198Scognet * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35129198Scognet * SUCH DAMAGE. 36 * 37 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 38 * from: src/sys/i386/i386/pmap.c,v 1.250.2.8 2000/11/21 00:09:14 ps 39 * JNPR: pmap.c,v 1.11.2.1 2007/08/16 11:51:06 girish 40 */ 41 42/* 43 * Manages physical address maps. 44 * 45 * In addition to hardware address maps, this 46 * module is called upon to provide software-use-only 47 * maps which may or may not be stored in the same 48 * form as hardware maps. These pseudo-maps are 49 * used to store intermediate results from copy 50 * operations to and from address spaces. 51 * 52 * Since the information managed by this module is 53 * also stored by the logical address mapping module, 54 * this module may throw away valid virtual-to-physical 55 * mappings at almost any time. However, invalidations 56 * of virtual-to-physical mappings must be done as 57 * requested. 58 * 59 * In order to cope with hardware architectures which 60 * make virtual-to-physical map invalidates expensive, 61 * this module may delay invalidate or reduced protection 62 * operations until such time as they are actually 63 * necessary. This module is given full information as 64 * to which processors are currently using which maps, 65 * and to when physical maps must be made correct. 66 */ 67 68#include <sys/cdefs.h> 69__FBSDID("$FreeBSD: head/sys/mips/mips/pmap.c 208589 2010-05-27 10:05:40Z jchandra $"); 70 71#include "opt_ddb.h" 72#include "opt_msgbuf.h" 73#include <sys/param.h> 74#include <sys/systm.h> 75#include <sys/proc.h> 76#include <sys/msgbuf.h> 77#include <sys/vmmeter.h> 78#include <sys/mman.h> 79#include <sys/smp.h> 80 81#include <vm/vm.h> 82#include <vm/vm_param.h> 83#include <vm/vm_phys.h> 84#include <sys/lock.h> 85#include <sys/mutex.h> 86#include <vm/vm_kern.h> 87#include <vm/vm_page.h> 88#include <vm/vm_map.h> 89#include <vm/vm_object.h> 90#include <vm/vm_extern.h> 91#include <vm/vm_pageout.h> 92#include <vm/vm_pager.h> 93#include <vm/uma.h> 94#include <sys/pcpu.h> 95#include <sys/sched.h> 96#ifdef SMP 97#include <sys/smp.h> 98#endif 99 100#include <machine/cache.h> 101#include <machine/md_var.h> 102 103#if defined(DIAGNOSTIC) 104#define PMAP_DIAGNOSTIC 105#endif 106 107#undef PMAP_DEBUG 108 109#ifndef PMAP_SHPGPERPROC 110#define PMAP_SHPGPERPROC 200 111#endif 112 113#if !defined(PMAP_DIAGNOSTIC) 114#define PMAP_INLINE __inline 115#else 116#define PMAP_INLINE 117#endif 118 119/* 120 * Get PDEs and PTEs for user/kernel address space 121 */ 122#define pmap_pde(m, v) (&((m)->pm_segtab[(vm_offset_t)(v) >> SEGSHIFT])) 123#define segtab_pde(m, v) (m[(vm_offset_t)(v) >> SEGSHIFT]) 124 125#define pmap_pte_w(pte) ((*(int *)pte & PTE_W) != 0) 126#define pmap_pde_v(pte) ((*(int *)pte) != 0) 127#define pmap_pte_m(pte) ((*(int *)pte & PTE_M) != 0) 128#define pmap_pte_v(pte) ((*(int *)pte & PTE_V) != 0) 129 130#define pmap_pte_set_w(pte, v) ((v)?(*(int *)pte |= PTE_W):(*(int *)pte &= ~PTE_W)) 131#define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v))) 132 133#define MIPS_SEGSIZE (1L << SEGSHIFT) 134#define mips_segtrunc(va) ((va) & ~(MIPS_SEGSIZE-1)) 135#define pmap_TLB_invalidate_all() MIPS_TBIAP() 136#define pmap_va_asid(pmap, va) ((va) | ((pmap)->pm_asid[PCPU_GET(cpuid)].asid << VMTLB_PID_SHIFT)) 137#define is_kernel_pmap(x) ((x) == kernel_pmap) 138 139struct pmap kernel_pmap_store; 140pd_entry_t *kernel_segmap; 141 142vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 143vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 144 145static int nkpt; 146unsigned pmap_max_asid; /* max ASID supported by the system */ 147 148 149#define PMAP_ASID_RESERVED 0 150 151vm_offset_t kernel_vm_end; 152 153static struct tlb tlbstash[MAXCPU][MIPS_MAX_TLB_ENTRIES]; 154 155static void pmap_asid_alloc(pmap_t pmap); 156 157/* 158 * Data for the pv entry allocation mechanism 159 */ 160static uma_zone_t pvzone; 161static struct vm_object pvzone_obj; 162static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 163 164static PMAP_INLINE void free_pv_entry(pv_entry_t pv); 165static pv_entry_t get_pv_entry(pmap_t locked_pmap); 166static __inline void pmap_changebit(vm_page_t m, int bit, boolean_t setem); 167 168static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, 169 vm_page_t m, vm_prot_t prot, vm_page_t mpte); 170static int pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va); 171static void pmap_remove_page(struct pmap *pmap, vm_offset_t va); 172static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, vm_offset_t va); 173static boolean_t pmap_testbit(vm_page_t m, int bit); 174static void 175pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t mpte, 176 vm_page_t m, boolean_t wired); 177static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_page_t mpte, 178 vm_offset_t va, vm_page_t m); 179 180static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags); 181 182static vm_page_t _pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags); 183static int pmap_unuse_pt(pmap_t, vm_offset_t, vm_page_t); 184static int init_pte_prot(vm_offset_t va, vm_page_t m, vm_prot_t prot); 185static void pmap_TLB_invalidate_kernel(vm_offset_t); 186static void pmap_TLB_update_kernel(vm_offset_t, pt_entry_t); 187static vm_page_t pmap_alloc_pte_page(pmap_t, unsigned int, int, vm_offset_t *); 188static void pmap_release_pte_page(vm_page_t); 189 190#ifdef SMP 191static void pmap_invalidate_page_action(void *arg); 192static void pmap_invalidate_all_action(void *arg); 193static void pmap_update_page_action(void *arg); 194#endif 195 196static void pmap_ptpgzone_dtor(void *mem, int size, void *arg); 197static void *pmap_ptpgzone_allocf(uma_zone_t, int, u_int8_t *, int); 198static uma_zone_t ptpgzone; 199 200struct local_sysmaps { 201 struct mtx lock; 202 vm_offset_t base; 203 uint16_t valid1, valid2; 204}; 205 206/* This structure is for large memory 207 * above 512Meg. We can't (in 32 bit mode) 208 * just use the direct mapped MIPS_KSEG0_TO_PHYS() 209 * macros since we can't see the memory and must 210 * map it in when we need to access it. In 64 211 * bit mode this goes away. 212 */ 213static struct local_sysmaps sysmap_lmem[MAXCPU]; 214caddr_t virtual_sys_start = (caddr_t)0; 215 216#define PMAP_LMEM_MAP1(va, phys) \ 217 int cpu; \ 218 struct local_sysmaps *sysm; \ 219 pt_entry_t *pte, npte; \ 220 \ 221 cpu = PCPU_GET(cpuid); \ 222 sysm = &sysmap_lmem[cpu]; \ 223 PMAP_LGMEM_LOCK(sysm); \ 224 intr = intr_disable(); \ 225 sched_pin(); \ 226 va = sysm->base; \ 227 npte = mips_paddr_to_tlbpfn(phys) | \ 228 PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; \ 229 pte = pmap_pte(kernel_pmap, va); \ 230 *pte = npte; \ 231 sysm->valid1 = 1; 232 233#define PMAP_LMEM_MAP2(va1, phys1, va2, phys2) \ 234 int cpu; \ 235 struct local_sysmaps *sysm; \ 236 pt_entry_t *pte, npte; \ 237 \ 238 cpu = PCPU_GET(cpuid); \ 239 sysm = &sysmap_lmem[cpu]; \ 240 PMAP_LGMEM_LOCK(sysm); \ 241 intr = intr_disable(); \ 242 sched_pin(); \ 243 va1 = sysm->base; \ 244 va2 = sysm->base + PAGE_SIZE; \ 245 npte = mips_paddr_to_tlbpfn(phys1) | \ 246 PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; \ 247 pte = pmap_pte(kernel_pmap, va1); \ 248 *pte = npte; \ 249 npte = mips_paddr_to_tlbpfn(phys2) | \ 250 PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; \ 251 pte = pmap_pte(kernel_pmap, va2); \ 252 *pte = npte; \ 253 sysm->valid1 = 1; \ 254 sysm->valid2 = 1; 255 256#define PMAP_LMEM_UNMAP() \ 257 pte = pmap_pte(kernel_pmap, sysm->base); \ 258 *pte = PTE_G; \ 259 pmap_TLB_invalidate_kernel(sysm->base); \ 260 sysm->valid1 = 0; \ 261 pte = pmap_pte(kernel_pmap, sysm->base + PAGE_SIZE); \ 262 *pte = PTE_G; \ 263 pmap_TLB_invalidate_kernel(sysm->base + PAGE_SIZE); \ 264 sysm->valid2 = 0; \ 265 sched_unpin(); \ 266 intr_restore(intr); \ 267 PMAP_LGMEM_UNLOCK(sysm); 268 269pd_entry_t 270pmap_segmap(pmap_t pmap, vm_offset_t va) 271{ 272 if (pmap->pm_segtab) 273 return (pmap->pm_segtab[((vm_offset_t)(va) >> SEGSHIFT)]); 274 else 275 return ((pd_entry_t)0); 276} 277 278/* 279 * Routine: pmap_pte 280 * Function: 281 * Extract the page table entry associated 282 * with the given map/virtual_address pair. 283 */ 284pt_entry_t * 285pmap_pte(pmap_t pmap, vm_offset_t va) 286{ 287 pt_entry_t *pdeaddr; 288 289 if (pmap) { 290 pdeaddr = (pt_entry_t *)pmap_segmap(pmap, va); 291 if (pdeaddr) { 292 return pdeaddr + vad_to_pte_offset(va); 293 } 294 } 295 return ((pt_entry_t *)0); 296} 297 298 299vm_offset_t 300pmap_steal_memory(vm_size_t size) 301{ 302 vm_size_t bank_size; 303 vm_offset_t pa, va; 304 305 size = round_page(size); 306 307 bank_size = phys_avail[1] - phys_avail[0]; 308 while (size > bank_size) { 309 int i; 310 311 for (i = 0; phys_avail[i + 2]; i += 2) { 312 phys_avail[i] = phys_avail[i + 2]; 313 phys_avail[i + 1] = phys_avail[i + 3]; 314 } 315 phys_avail[i] = 0; 316 phys_avail[i + 1] = 0; 317 if (!phys_avail[0]) 318 panic("pmap_steal_memory: out of memory"); 319 bank_size = phys_avail[1] - phys_avail[0]; 320 } 321 322 pa = phys_avail[0]; 323 phys_avail[0] += size; 324 if (pa >= MIPS_KSEG0_LARGEST_PHYS) { 325 panic("Out of memory below 512Meg?"); 326 } 327 va = MIPS_PHYS_TO_KSEG0(pa); 328 bzero((caddr_t)va, size); 329 return va; 330} 331 332/* 333 * Bootstrap the system enough to run with virtual memory. This 334 * assumes that the phys_avail array has been initialized. 335 */ 336void 337pmap_bootstrap(void) 338{ 339 pt_entry_t *pgtab; 340 pt_entry_t *pte; 341 int i, j; 342 int memory_larger_than_512meg = 0; 343 344 /* Sort. */ 345again: 346 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 347 /* 348 * Keep the memory aligned on page boundary. 349 */ 350 phys_avail[i] = round_page(phys_avail[i]); 351 phys_avail[i + 1] = trunc_page(phys_avail[i + 1]); 352 353 if (phys_avail[i + 1] >= MIPS_KSEG0_LARGEST_PHYS) 354 memory_larger_than_512meg++; 355 if (i < 2) 356 continue; 357 if (phys_avail[i - 2] > phys_avail[i]) { 358 vm_paddr_t ptemp[2]; 359 360 361 ptemp[0] = phys_avail[i + 0]; 362 ptemp[1] = phys_avail[i + 1]; 363 364 phys_avail[i + 0] = phys_avail[i - 2]; 365 phys_avail[i + 1] = phys_avail[i - 1]; 366 367 phys_avail[i - 2] = ptemp[0]; 368 phys_avail[i - 1] = ptemp[1]; 369 goto again; 370 } 371 } 372 373 /* 374 * Copy the phys_avail[] array before we start stealing memory from it. 375 */ 376 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 377 physmem_desc[i] = phys_avail[i]; 378 physmem_desc[i + 1] = phys_avail[i + 1]; 379 } 380 381 Maxmem = atop(phys_avail[i - 1]); 382 383 if (bootverbose) { 384 printf("Physical memory chunk(s):\n"); 385 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 386 vm_paddr_t size; 387 388 size = phys_avail[i + 1] - phys_avail[i]; 389 printf("%#08jx - %#08jx, %ju bytes (%ju pages)\n", 390 (uintmax_t) phys_avail[i], 391 (uintmax_t) phys_avail[i + 1] - 1, 392 (uintmax_t) size, (uintmax_t) size / PAGE_SIZE); 393 } 394 printf("Maxmem is 0x%0lx\n", ptoa(Maxmem)); 395 } 396 /* 397 * Steal the message buffer from the beginning of memory. 398 */ 399 msgbufp = (struct msgbuf *)pmap_steal_memory(MSGBUF_SIZE); 400 msgbufinit(msgbufp, MSGBUF_SIZE); 401 402 /* 403 * Steal thread0 kstack. 404 */ 405 kstack0 = pmap_steal_memory(KSTACK_PAGES << PAGE_SHIFT); 406 407 408 virtual_avail = VM_MIN_KERNEL_ADDRESS; 409 virtual_end = VM_MAX_KERNEL_ADDRESS; 410 411#ifdef SMP 412 /* 413 * Steal some virtual address space to map the pcpu area. 414 */ 415 virtual_avail = roundup2(virtual_avail, PAGE_SIZE * 2); 416 pcpup = (struct pcpu *)virtual_avail; 417 virtual_avail += PAGE_SIZE * 2; 418 419 /* 420 * Initialize the wired TLB entry mapping the pcpu region for 421 * the BSP at 'pcpup'. Up until this point we were operating 422 * with the 'pcpup' for the BSP pointing to a virtual address 423 * in KSEG0 so there was no need for a TLB mapping. 424 */ 425 mips_pcpu_tlb_init(PCPU_ADDR(0)); 426 427 if (bootverbose) 428 printf("pcpu is available at virtual address %p.\n", pcpup); 429#endif 430 431 /* 432 * Steal some virtual space that will not be in kernel_segmap. This 433 * va memory space will be used to map in kernel pages that are 434 * outside the 512Meg region. Note that we only do this steal when 435 * we do have memory in this region, that way for systems with 436 * smaller memory we don't "steal" any va ranges :-) 437 */ 438 if (memory_larger_than_512meg) { 439 for (i = 0; i < MAXCPU; i++) { 440 sysmap_lmem[i].base = virtual_avail; 441 virtual_avail += PAGE_SIZE * 2; 442 sysmap_lmem[i].valid1 = sysmap_lmem[i].valid2 = 0; 443 PMAP_LGMEM_LOCK_INIT(&sysmap_lmem[i]); 444 } 445 } 446 virtual_sys_start = (caddr_t)virtual_avail; 447 /* 448 * Allocate segment table for the kernel 449 */ 450 kernel_segmap = (pd_entry_t *)pmap_steal_memory(PAGE_SIZE); 451 452 /* 453 * Allocate second level page tables for the kernel 454 */ 455 nkpt = NKPT; 456 if (memory_larger_than_512meg) { 457 /* 458 * If we have a large memory system we CANNOT afford to hit 459 * pmap_growkernel() and allocate memory. Since we MAY end 460 * up with a page that is NOT mappable. For that reason we 461 * up front grab more. Normall NKPT is 120 (YMMV see pmap.h) 462 * this gives us 480meg of kernel virtual addresses at the 463 * cost of 120 pages (each page gets us 4 Meg). Since the 464 * kernel starts at virtual_avail, we can use this to 465 * calculate how many entris are left from there to the end 466 * of the segmap, we want to allocate all of it, which would 467 * be somewhere above 0xC0000000 - 0xFFFFFFFF which results 468 * in about 256 entries or so instead of the 120. 469 */ 470 nkpt = (PAGE_SIZE / sizeof(pd_entry_t)) - (virtual_avail >> SEGSHIFT); 471 } 472 pgtab = (pt_entry_t *)pmap_steal_memory(PAGE_SIZE * nkpt); 473 474 /* 475 * The R[4-7]?00 stores only one copy of the Global bit in the 476 * translation lookaside buffer for each 2 page entry. Thus invalid 477 * entrys must have the Global bit set so when Entry LO and Entry HI 478 * G bits are anded together they will produce a global bit to store 479 * in the tlb. 480 */ 481 for (i = 0, pte = pgtab; i < (nkpt * NPTEPG); i++, pte++) 482 *pte = PTE_G; 483 484 /* 485 * The segment table contains the KVA of the pages in the second 486 * level page table. 487 */ 488 for (i = 0, j = (virtual_avail >> SEGSHIFT); i < nkpt; i++, j++) 489 kernel_segmap[j] = (pd_entry_t)(pgtab + (i * NPTEPG)); 490 491 /* 492 * The kernel's pmap is statically allocated so we don't have to use 493 * pmap_create, which is unlikely to work correctly at this part of 494 * the boot sequence (XXX and which no longer exists). 495 */ 496 PMAP_LOCK_INIT(kernel_pmap); 497 kernel_pmap->pm_segtab = kernel_segmap; 498 kernel_pmap->pm_active = ~0; 499 TAILQ_INIT(&kernel_pmap->pm_pvlist); 500 kernel_pmap->pm_asid[0].asid = PMAP_ASID_RESERVED; 501 kernel_pmap->pm_asid[0].gen = 0; 502 pmap_max_asid = VMNUM_PIDS; 503 MachSetPID(0); 504} 505 506/* 507 * Initialize a vm_page's machine-dependent fields. 508 */ 509void 510pmap_page_init(vm_page_t m) 511{ 512 513 TAILQ_INIT(&m->md.pv_list); 514 m->md.pv_list_count = 0; 515 m->md.pv_flags = 0; 516} 517 518/* 519 * Initialize the pmap module. 520 * Called by vm_init, to initialize any structures that the pmap 521 * system needs to map virtual memory. 522 * pmap_init has been enhanced to support in a fairly consistant 523 * way, discontiguous physical memory. 524 */ 525void 526pmap_init(void) 527{ 528 529 /* 530 * Initialize the address space (zone) for the pv entries. Set a 531 * high water mark so that the system can recover from excessive 532 * numbers of pv entries. 533 */ 534 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL, 535 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 536 pv_entry_max = PMAP_SHPGPERPROC * maxproc + cnt.v_page_count; 537 pv_entry_high_water = 9 * (pv_entry_max / 10); 538 uma_zone_set_obj(pvzone, &pvzone_obj, pv_entry_max); 539 540 ptpgzone = uma_zcreate("PT ENTRY", PAGE_SIZE, NULL, pmap_ptpgzone_dtor, 541 NULL, NULL, PAGE_SIZE - 1, UMA_ZONE_NOFREE | UMA_ZONE_ZINIT); 542 uma_zone_set_allocf(ptpgzone, pmap_ptpgzone_allocf); 543} 544 545/*************************************************** 546 * Low level helper routines..... 547 ***************************************************/ 548 549#if defined(PMAP_DIAGNOSTIC) 550 551/* 552 * This code checks for non-writeable/modified pages. 553 * This should be an invalid condition. 554 */ 555static int 556pmap_nw_modified(pt_entry_t pte) 557{ 558 if ((pte & (PTE_M | PTE_RO)) == (PTE_M | PTE_RO)) 559 return (1); 560 else 561 return (0); 562} 563 564#endif 565 566static void 567pmap_invalidate_all(pmap_t pmap) 568{ 569#ifdef SMP 570 smp_rendezvous(0, pmap_invalidate_all_action, 0, (void *)pmap); 571} 572 573static void 574pmap_invalidate_all_action(void *arg) 575{ 576 pmap_t pmap = (pmap_t)arg; 577 578#endif 579 580 if (pmap->pm_active & PCPU_GET(cpumask)) { 581 pmap_TLB_invalidate_all(); 582 } else 583 pmap->pm_asid[PCPU_GET(cpuid)].gen = 0; 584} 585 586struct pmap_invalidate_page_arg { 587 pmap_t pmap; 588 vm_offset_t va; 589}; 590 591static __inline void 592pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 593{ 594#ifdef SMP 595 struct pmap_invalidate_page_arg arg; 596 597 arg.pmap = pmap; 598 arg.va = va; 599 600 smp_rendezvous(0, pmap_invalidate_page_action, 0, (void *)&arg); 601} 602 603static void 604pmap_invalidate_page_action(void *arg) 605{ 606 pmap_t pmap = ((struct pmap_invalidate_page_arg *)arg)->pmap; 607 vm_offset_t va = ((struct pmap_invalidate_page_arg *)arg)->va; 608 609#endif 610 611 if (is_kernel_pmap(pmap)) { 612 pmap_TLB_invalidate_kernel(va); 613 return; 614 } 615 if (pmap->pm_asid[PCPU_GET(cpuid)].gen != PCPU_GET(asid_generation)) 616 return; 617 else if (!(pmap->pm_active & PCPU_GET(cpumask))) { 618 pmap->pm_asid[PCPU_GET(cpuid)].gen = 0; 619 return; 620 } 621 va = pmap_va_asid(pmap, (va & ~PAGE_MASK)); 622 mips_TBIS(va); 623} 624 625static void 626pmap_TLB_invalidate_kernel(vm_offset_t va) 627{ 628 u_int32_t pid; 629 630 MachTLBGetPID(pid); 631 va = va | (pid << VMTLB_PID_SHIFT); 632 mips_TBIS(va); 633} 634 635struct pmap_update_page_arg { 636 pmap_t pmap; 637 vm_offset_t va; 638 pt_entry_t pte; 639}; 640 641void 642pmap_update_page(pmap_t pmap, vm_offset_t va, pt_entry_t pte) 643{ 644#ifdef SMP 645 struct pmap_update_page_arg arg; 646 647 arg.pmap = pmap; 648 arg.va = va; 649 arg.pte = pte; 650 651 smp_rendezvous(0, pmap_update_page_action, 0, (void *)&arg); 652} 653 654static void 655pmap_update_page_action(void *arg) 656{ 657 pmap_t pmap = ((struct pmap_update_page_arg *)arg)->pmap; 658 vm_offset_t va = ((struct pmap_update_page_arg *)arg)->va; 659 pt_entry_t pte = ((struct pmap_update_page_arg *)arg)->pte; 660 661#endif 662 if (is_kernel_pmap(pmap)) { 663 pmap_TLB_update_kernel(va, pte); 664 return; 665 } 666 if (pmap->pm_asid[PCPU_GET(cpuid)].gen != PCPU_GET(asid_generation)) 667 return; 668 else if (!(pmap->pm_active & PCPU_GET(cpumask))) { 669 pmap->pm_asid[PCPU_GET(cpuid)].gen = 0; 670 return; 671 } 672 va = pmap_va_asid(pmap, (va & ~PAGE_MASK)); 673 MachTLBUpdate(va, pte); 674} 675 676static void 677pmap_TLB_update_kernel(vm_offset_t va, pt_entry_t pte) 678{ 679 u_int32_t pid; 680 681 va &= ~PAGE_MASK; 682 683 MachTLBGetPID(pid); 684 va = va | (pid << VMTLB_PID_SHIFT); 685 686 MachTLBUpdate(va, pte); 687} 688 689/* 690 * Routine: pmap_extract 691 * Function: 692 * Extract the physical page address associated 693 * with the given map/virtual_address pair. 694 */ 695vm_paddr_t 696pmap_extract(pmap_t pmap, vm_offset_t va) 697{ 698 pt_entry_t *pte; 699 vm_offset_t retval = 0; 700 701 PMAP_LOCK(pmap); 702 pte = pmap_pte(pmap, va); 703 if (pte) { 704 retval = mips_tlbpfn_to_paddr(*pte) | (va & PAGE_MASK); 705 } 706 PMAP_UNLOCK(pmap); 707 return retval; 708} 709 710/* 711 * Routine: pmap_extract_and_hold 712 * Function: 713 * Atomically extract and hold the physical page 714 * with the given pmap and virtual address pair 715 * if that mapping permits the given protection. 716 */ 717vm_page_t 718pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 719{ 720 pt_entry_t pte; 721 vm_page_t m; 722 vm_paddr_t pa; 723 724 m = NULL; 725 pa = 0; 726 PMAP_LOCK(pmap); 727retry: 728 pte = *pmap_pte(pmap, va); 729 if (pte != 0 && pmap_pte_v(&pte) && 730 ((pte & PTE_RW) || (prot & VM_PROT_WRITE) == 0)) { 731 if (vm_page_pa_tryrelock(pmap, mips_tlbpfn_to_paddr(pte), &pa)) 732 goto retry; 733 734 m = PHYS_TO_VM_PAGE(mips_tlbpfn_to_paddr(pte)); 735 vm_page_hold(m); 736 } 737 PA_UNLOCK_COND(pa); 738 PMAP_UNLOCK(pmap); 739 return (m); 740} 741 742/*************************************************** 743 * Low level mapping routines..... 744 ***************************************************/ 745 746/* 747 * add a wired page to the kva 748 */ 749 /* PMAP_INLINE */ void 750pmap_kenter(vm_offset_t va, vm_paddr_t pa) 751{ 752 register pt_entry_t *pte; 753 pt_entry_t npte, opte; 754 755#ifdef PMAP_DEBUG 756 printf("pmap_kenter: va: 0x%08x -> pa: 0x%08x\n", va, pa); 757#endif 758 npte = mips_paddr_to_tlbpfn(pa) | PTE_RW | PTE_V | PTE_G | PTE_W; 759 760 if (is_cacheable_mem(pa)) 761 npte |= PTE_CACHE; 762 else 763 npte |= PTE_UNCACHED; 764 765 pte = pmap_pte(kernel_pmap, va); 766 opte = *pte; 767 *pte = npte; 768 769 pmap_update_page(kernel_pmap, va, npte); 770} 771 772/* 773 * remove a page from the kernel pagetables 774 */ 775 /* PMAP_INLINE */ void 776pmap_kremove(vm_offset_t va) 777{ 778 register pt_entry_t *pte; 779 780 /* 781 * Write back all caches from the page being destroyed 782 */ 783 mips_dcache_wbinv_range_index(va, PAGE_SIZE); 784 785 pte = pmap_pte(kernel_pmap, va); 786 *pte = PTE_G; 787 pmap_invalidate_page(kernel_pmap, va); 788} 789 790/* 791 * Used to map a range of physical addresses into kernel 792 * virtual address space. 793 * 794 * The value passed in '*virt' is a suggested virtual address for 795 * the mapping. Architectures which can support a direct-mapped 796 * physical to virtual region can return the appropriate address 797 * within that region, leaving '*virt' unchanged. Other 798 * architectures should map the pages starting at '*virt' and 799 * update '*virt' with the first usable address after the mapped 800 * region. 801 */ 802vm_offset_t 803pmap_map(vm_offset_t *virt, vm_offset_t start, vm_offset_t end, int prot) 804{ 805 vm_offset_t va, sva; 806 807 va = sva = *virt; 808 while (start < end) { 809 pmap_kenter(va, start); 810 va += PAGE_SIZE; 811 start += PAGE_SIZE; 812 } 813 *virt = va; 814 return (sva); 815} 816 817/* 818 * Add a list of wired pages to the kva 819 * this routine is only used for temporary 820 * kernel mappings that do not need to have 821 * page modification or references recorded. 822 * Note that old mappings are simply written 823 * over. The page *must* be wired. 824 */ 825void 826pmap_qenter(vm_offset_t va, vm_page_t *m, int count) 827{ 828 int i; 829 vm_offset_t origva = va; 830 831 for (i = 0; i < count; i++) { 832 pmap_flush_pvcache(m[i]); 833 pmap_kenter(va, VM_PAGE_TO_PHYS(m[i])); 834 va += PAGE_SIZE; 835 } 836 837 mips_dcache_wbinv_range_index(origva, PAGE_SIZE*count); 838} 839 840/* 841 * this routine jerks page mappings from the 842 * kernel -- it is meant only for temporary mappings. 843 */ 844void 845pmap_qremove(vm_offset_t va, int count) 846{ 847 /* 848 * No need to wb/inv caches here, 849 * pmap_kremove will do it for us 850 */ 851 852 while (count-- > 0) { 853 pmap_kremove(va); 854 va += PAGE_SIZE; 855 } 856} 857 858/*************************************************** 859 * Page table page management routines..... 860 ***************************************************/ 861 862/* Revision 1.507 863 * 864 * Simplify the reference counting of page table pages. Specifically, use 865 * the page table page's wired count rather than its hold count to contain 866 * the reference count. 867 */ 868 869/* 870 * This routine unholds page table pages, and if the hold count 871 * drops to zero, then it decrements the wire count. 872 */ 873static int 874_pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m) 875{ 876 877 /* 878 * unmap the page table page 879 */ 880 pmap->pm_segtab[m->pindex] = 0; 881 --pmap->pm_stats.resident_count; 882 883 if (pmap->pm_ptphint == m) 884 pmap->pm_ptphint = NULL; 885 886 /* 887 * If the page is finally unwired, simply free it. 888 */ 889 pmap_release_pte_page(m); 890 atomic_subtract_int(&cnt.v_wire_count, 1); 891 return (1); 892} 893 894static PMAP_INLINE int 895pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m) 896{ 897 --m->wire_count; 898 if (m->wire_count == 0) 899 return (_pmap_unwire_pte_hold(pmap, m)); 900 else 901 return (0); 902} 903 904/* 905 * After removing a page table entry, this routine is used to 906 * conditionally free the page, and manage the hold/wire counts. 907 */ 908static int 909pmap_unuse_pt(pmap_t pmap, vm_offset_t va, vm_page_t mpte) 910{ 911 unsigned ptepindex; 912 pd_entry_t pteva; 913 914 if (va >= VM_MAXUSER_ADDRESS) 915 return (0); 916 917 if (mpte == NULL) { 918 ptepindex = (va >> SEGSHIFT); 919 if (pmap->pm_ptphint && 920 (pmap->pm_ptphint->pindex == ptepindex)) { 921 mpte = pmap->pm_ptphint; 922 } else { 923 pteva = *pmap_pde(pmap, va); 924 mpte = PHYS_TO_VM_PAGE(MIPS_KSEG0_TO_PHYS(pteva)); 925 pmap->pm_ptphint = mpte; 926 } 927 } 928 return pmap_unwire_pte_hold(pmap, mpte); 929} 930 931void 932pmap_pinit0(pmap_t pmap) 933{ 934 int i; 935 936 PMAP_LOCK_INIT(pmap); 937 pmap->pm_segtab = kernel_segmap; 938 pmap->pm_active = 0; 939 pmap->pm_ptphint = NULL; 940 for (i = 0; i < MAXCPU; i++) { 941 pmap->pm_asid[i].asid = PMAP_ASID_RESERVED; 942 pmap->pm_asid[i].gen = 0; 943 } 944 PCPU_SET(curpmap, pmap); 945 TAILQ_INIT(&pmap->pm_pvlist); 946 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 947} 948 949static void 950pmap_ptpgzone_dtor(void *mem, int size, void *arg) 951{ 952#ifdef INVARIANTS 953 static char zeropage[PAGE_SIZE]; 954 955 KASSERT(size == PAGE_SIZE, 956 ("pmap_ptpgzone_dtor: invalid size %d", size)); 957 KASSERT(bcmp(mem, zeropage, PAGE_SIZE) == 0, 958 ("pmap_ptpgzone_dtor: freeing a non-zeroed page")); 959#endif 960} 961 962static void * 963pmap_ptpgzone_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait) 964{ 965 vm_page_t m; 966 vm_paddr_t paddr; 967 968 KASSERT(bytes == PAGE_SIZE, 969 ("pmap_ptpgzone_allocf: invalid allocation size %d", bytes)); 970 971 *flags = UMA_SLAB_PRIV; 972 for (;;) { 973 m = vm_phys_alloc_contig(1, 0, MIPS_KSEG0_LARGEST_PHYS, 974 PAGE_SIZE, PAGE_SIZE); 975 if (m != NULL) 976 break; 977 if ((wait & M_WAITOK) == 0) 978 return (NULL); 979 VM_WAIT; 980 } 981 982 paddr = VM_PAGE_TO_PHYS(m); 983 return ((void *)MIPS_PHYS_TO_KSEG0(paddr)); 984} 985 986static vm_page_t 987pmap_alloc_pte_page(pmap_t pmap, unsigned int index, int wait, vm_offset_t *vap) 988{ 989 vm_paddr_t paddr; 990 void *va; 991 vm_page_t m; 992 int locked; 993 994 locked = mtx_owned(&pmap->pm_mtx); 995 if (locked) { 996 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 997 PMAP_UNLOCK(pmap); 998 vm_page_unlock_queues(); 999 } 1000 va = uma_zalloc(ptpgzone, wait); 1001 if (locked) { 1002 vm_page_lock_queues(); 1003 PMAP_LOCK(pmap); 1004 } 1005 if (va == NULL) 1006 return (NULL); 1007 1008 paddr = MIPS_KSEG0_TO_PHYS(va); 1009 m = PHYS_TO_VM_PAGE(paddr); 1010 1011 m->pindex = index; 1012 m->valid = VM_PAGE_BITS_ALL; 1013 m->wire_count = 1; 1014 atomic_add_int(&cnt.v_wire_count, 1); 1015 *vap = (vm_offset_t)va; 1016 return (m); 1017} 1018 1019static void 1020pmap_release_pte_page(vm_page_t m) 1021{ 1022 void *va; 1023 vm_paddr_t paddr; 1024 1025 paddr = VM_PAGE_TO_PHYS(m); 1026 va = (void *)MIPS_PHYS_TO_KSEG0(paddr); 1027 uma_zfree(ptpgzone, va); 1028} 1029 1030/* 1031 * Initialize a preallocated and zeroed pmap structure, 1032 * such as one in a vmspace structure. 1033 */ 1034int 1035pmap_pinit(pmap_t pmap) 1036{ 1037 vm_offset_t ptdva; 1038 vm_page_t ptdpg; 1039 int i; 1040 1041 PMAP_LOCK_INIT(pmap); 1042 1043 /* 1044 * allocate the page directory page 1045 */ 1046 ptdpg = pmap_alloc_pte_page(pmap, NUSERPGTBLS, M_WAITOK, &ptdva); 1047 if (ptdpg == NULL) 1048 return (0); 1049 1050 pmap->pm_segtab = (pd_entry_t *)ptdva; 1051 pmap->pm_active = 0; 1052 pmap->pm_ptphint = NULL; 1053 for (i = 0; i < MAXCPU; i++) { 1054 pmap->pm_asid[i].asid = PMAP_ASID_RESERVED; 1055 pmap->pm_asid[i].gen = 0; 1056 } 1057 TAILQ_INIT(&pmap->pm_pvlist); 1058 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1059 1060 return (1); 1061} 1062 1063/* 1064 * this routine is called if the page table page is not 1065 * mapped correctly. 1066 */ 1067static vm_page_t 1068_pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags) 1069{ 1070 vm_offset_t pteva; 1071 vm_page_t m; 1072 1073 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1074 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1075 ("_pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1076 1077 /* 1078 * Find or fabricate a new pagetable page 1079 */ 1080 m = pmap_alloc_pte_page(pmap, ptepindex, flags, &pteva); 1081 if (m == NULL) 1082 return (NULL); 1083 1084 /* 1085 * Map the pagetable page into the process address space, if it 1086 * isn't already there. 1087 */ 1088 1089 pmap->pm_stats.resident_count++; 1090 pmap->pm_segtab[ptepindex] = (pd_entry_t)pteva; 1091 1092 /* 1093 * Set the page table hint 1094 */ 1095 pmap->pm_ptphint = m; 1096 return (m); 1097} 1098 1099static vm_page_t 1100pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags) 1101{ 1102 unsigned ptepindex; 1103 vm_offset_t pteva; 1104 vm_page_t m; 1105 1106 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1107 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1108 ("pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1109 1110 /* 1111 * Calculate pagetable page index 1112 */ 1113 ptepindex = va >> SEGSHIFT; 1114retry: 1115 /* 1116 * Get the page directory entry 1117 */ 1118 pteva = (vm_offset_t)pmap->pm_segtab[ptepindex]; 1119 1120 /* 1121 * If the page table page is mapped, we just increment the hold 1122 * count, and activate it. 1123 */ 1124 if (pteva) { 1125 /* 1126 * In order to get the page table page, try the hint first. 1127 */ 1128 if (pmap->pm_ptphint && 1129 (pmap->pm_ptphint->pindex == ptepindex)) { 1130 m = pmap->pm_ptphint; 1131 } else { 1132 m = PHYS_TO_VM_PAGE(MIPS_KSEG0_TO_PHYS(pteva)); 1133 pmap->pm_ptphint = m; 1134 } 1135 m->wire_count++; 1136 } else { 1137 /* 1138 * Here if the pte page isn't mapped, or if it has been 1139 * deallocated. 1140 */ 1141 m = _pmap_allocpte(pmap, ptepindex, flags); 1142 if (m == NULL && (flags & M_WAITOK)) 1143 goto retry; 1144 } 1145 return m; 1146} 1147 1148 1149/*************************************************** 1150* Pmap allocation/deallocation routines. 1151 ***************************************************/ 1152/* 1153 * Revision 1.397 1154 * - Merged pmap_release and pmap_release_free_page. When pmap_release is 1155 * called only the page directory page(s) can be left in the pmap pte 1156 * object, since all page table pages will have been freed by 1157 * pmap_remove_pages and pmap_remove. In addition, there can only be one 1158 * reference to the pmap and the page directory is wired, so the page(s) 1159 * can never be busy. So all there is to do is clear the magic mappings 1160 * from the page directory and free the page(s). 1161 */ 1162 1163 1164/* 1165 * Release any resources held by the given physical map. 1166 * Called when a pmap initialized by pmap_pinit is being released. 1167 * Should only be called if the map contains no valid mappings. 1168 */ 1169void 1170pmap_release(pmap_t pmap) 1171{ 1172 vm_offset_t ptdva; 1173 vm_page_t ptdpg; 1174 1175 KASSERT(pmap->pm_stats.resident_count == 0, 1176 ("pmap_release: pmap resident count %ld != 0", 1177 pmap->pm_stats.resident_count)); 1178 1179 ptdva = (vm_offset_t)pmap->pm_segtab; 1180 ptdpg = PHYS_TO_VM_PAGE(MIPS_KSEG0_TO_PHYS(ptdva)); 1181 1182 ptdpg->wire_count--; 1183 atomic_subtract_int(&cnt.v_wire_count, 1); 1184 pmap_release_pte_page(ptdpg); 1185 PMAP_LOCK_DESTROY(pmap); 1186} 1187 1188/* 1189 * grow the number of kernel page table entries, if needed 1190 */ 1191void 1192pmap_growkernel(vm_offset_t addr) 1193{ 1194 vm_offset_t pageva; 1195 vm_page_t nkpg; 1196 pt_entry_t *pte; 1197 int i; 1198 1199 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 1200 if (kernel_vm_end == 0) { 1201 kernel_vm_end = VM_MIN_KERNEL_ADDRESS; 1202 nkpt = 0; 1203 while (segtab_pde(kernel_segmap, kernel_vm_end)) { 1204 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & 1205 ~(PAGE_SIZE * NPTEPG - 1); 1206 nkpt++; 1207 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1208 kernel_vm_end = kernel_map->max_offset; 1209 break; 1210 } 1211 } 1212 } 1213 addr = (addr + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1214 if (addr - 1 >= kernel_map->max_offset) 1215 addr = kernel_map->max_offset; 1216 while (kernel_vm_end < addr) { 1217 if (segtab_pde(kernel_segmap, kernel_vm_end)) { 1218 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & 1219 ~(PAGE_SIZE * NPTEPG - 1); 1220 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1221 kernel_vm_end = kernel_map->max_offset; 1222 break; 1223 } 1224 continue; 1225 } 1226 /* 1227 * This index is bogus, but out of the way 1228 */ 1229 nkpg = pmap_alloc_pte_page(kernel_pmap, nkpt, M_NOWAIT, &pageva); 1230 1231 if (!nkpg) 1232 panic("pmap_growkernel: no memory to grow kernel"); 1233 1234 nkpt++; 1235 pte = (pt_entry_t *)pageva; 1236 segtab_pde(kernel_segmap, kernel_vm_end) = (pd_entry_t)pte; 1237 1238 /* 1239 * The R[4-7]?00 stores only one copy of the Global bit in 1240 * the translation lookaside buffer for each 2 page entry. 1241 * Thus invalid entrys must have the Global bit set so when 1242 * Entry LO and Entry HI G bits are anded together they will 1243 * produce a global bit to store in the tlb. 1244 */ 1245 for (i = 0; i < NPTEPG; i++, pte++) 1246 *pte = PTE_G; 1247 1248 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & 1249 ~(PAGE_SIZE * NPTEPG - 1); 1250 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1251 kernel_vm_end = kernel_map->max_offset; 1252 break; 1253 } 1254 } 1255} 1256 1257/*************************************************** 1258* page management routines. 1259 ***************************************************/ 1260 1261/* 1262 * free the pv_entry back to the free list 1263 */ 1264static PMAP_INLINE void 1265free_pv_entry(pv_entry_t pv) 1266{ 1267 1268 pv_entry_count--; 1269 uma_zfree(pvzone, pv); 1270} 1271 1272/* 1273 * get a new pv_entry, allocating a block from the system 1274 * when needed. 1275 * the memory allocation is performed bypassing the malloc code 1276 * because of the possibility of allocations at interrupt time. 1277 */ 1278static pv_entry_t 1279get_pv_entry(pmap_t locked_pmap) 1280{ 1281 static const struct timeval printinterval = { 60, 0 }; 1282 static struct timeval lastprint; 1283 struct vpgqueues *vpq; 1284 pt_entry_t *pte, oldpte; 1285 pmap_t pmap; 1286 pv_entry_t allocated_pv, next_pv, pv; 1287 vm_offset_t va; 1288 vm_page_t m; 1289 1290 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED); 1291 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1292 allocated_pv = uma_zalloc(pvzone, M_NOWAIT); 1293 if (allocated_pv != NULL) { 1294 pv_entry_count++; 1295 if (pv_entry_count > pv_entry_high_water) 1296 pagedaemon_wakeup(); 1297 else 1298 return (allocated_pv); 1299 } 1300 /* 1301 * Reclaim pv entries: At first, destroy mappings to inactive 1302 * pages. After that, if a pv entry is still needed, destroy 1303 * mappings to active pages. 1304 */ 1305 if (ratecheck(&lastprint, &printinterval)) 1306 printf("Approaching the limit on PV entries, " 1307 "increase the vm.pmap.shpgperproc tunable.\n"); 1308 vpq = &vm_page_queues[PQ_INACTIVE]; 1309retry: 1310 TAILQ_FOREACH(m, &vpq->pl, pageq) { 1311 if (m->hold_count || m->busy) 1312 continue; 1313 TAILQ_FOREACH_SAFE(pv, &m->md.pv_list, pv_list, next_pv) { 1314 va = pv->pv_va; 1315 pmap = pv->pv_pmap; 1316 /* Avoid deadlock and lock recursion. */ 1317 if (pmap > locked_pmap) 1318 PMAP_LOCK(pmap); 1319 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) 1320 continue; 1321 pmap->pm_stats.resident_count--; 1322 pte = pmap_pte(pmap, va); 1323 KASSERT(pte != NULL, ("pte")); 1324 oldpte = loadandclear((u_int *)pte); 1325 if (is_kernel_pmap(pmap)) 1326 *pte = PTE_G; 1327 KASSERT((oldpte & PTE_W) == 0, 1328 ("wired pte for unwired page")); 1329 if (m->md.pv_flags & PV_TABLE_REF) 1330 vm_page_flag_set(m, PG_REFERENCED); 1331 if (oldpte & PTE_M) 1332 vm_page_dirty(m); 1333 pmap_invalidate_page(pmap, va); 1334 TAILQ_REMOVE(&pmap->pm_pvlist, pv, pv_plist); 1335 m->md.pv_list_count--; 1336 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 1337 if (TAILQ_EMPTY(&m->md.pv_list)) { 1338 vm_page_flag_clear(m, PG_WRITEABLE); 1339 m->md.pv_flags &= ~(PV_TABLE_REF | PV_TABLE_MOD); 1340 } 1341 pmap_unuse_pt(pmap, va, pv->pv_ptem); 1342 if (pmap != locked_pmap) 1343 PMAP_UNLOCK(pmap); 1344 if (allocated_pv == NULL) 1345 allocated_pv = pv; 1346 else 1347 free_pv_entry(pv); 1348 } 1349 } 1350 if (allocated_pv == NULL) { 1351 if (vpq == &vm_page_queues[PQ_INACTIVE]) { 1352 vpq = &vm_page_queues[PQ_ACTIVE]; 1353 goto retry; 1354 } 1355 panic("get_pv_entry: increase the vm.pmap.shpgperproc tunable"); 1356 } 1357 return (allocated_pv); 1358} 1359 1360/* 1361 * Revision 1.370 1362 * 1363 * Move pmap_collect() out of the machine-dependent code, rename it 1364 * to reflect its new location, and add page queue and flag locking. 1365 * 1366 * Notes: (1) alpha, i386, and ia64 had identical implementations 1367 * of pmap_collect() in terms of machine-independent interfaces; 1368 * (2) sparc64 doesn't require it; (3) powerpc had it as a TODO. 1369 * 1370 * MIPS implementation was identical to alpha [Junos 8.2] 1371 */ 1372 1373/* 1374 * If it is the first entry on the list, it is actually 1375 * in the header and we must copy the following entry up 1376 * to the header. Otherwise we must search the list for 1377 * the entry. In either case we free the now unused entry. 1378 */ 1379 1380static void 1381pmap_remove_entry(struct pmap *pmap, vm_page_t m, vm_offset_t va) 1382{ 1383 pv_entry_t pv; 1384 1385 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1386 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1387 if (m->md.pv_list_count < pmap->pm_stats.resident_count) { 1388 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 1389 if (pmap == pv->pv_pmap && va == pv->pv_va) 1390 break; 1391 } 1392 } else { 1393 TAILQ_FOREACH(pv, &pmap->pm_pvlist, pv_plist) { 1394 if (va == pv->pv_va) 1395 break; 1396 } 1397 } 1398 1399 KASSERT(pv != NULL, ("pmap_remove_entry: pv not found, pa %lx va %lx", 1400 (u_long)VM_PAGE_TO_PHYS(m), (u_long)va)); 1401 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 1402 m->md.pv_list_count--; 1403 if (TAILQ_FIRST(&m->md.pv_list) == NULL) 1404 vm_page_flag_clear(m, PG_WRITEABLE); 1405 1406 TAILQ_REMOVE(&pmap->pm_pvlist, pv, pv_plist); 1407 free_pv_entry(pv); 1408} 1409 1410/* 1411 * Create a pv entry for page at pa for 1412 * (pmap, va). 1413 */ 1414static void 1415pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t mpte, vm_page_t m, 1416 boolean_t wired) 1417{ 1418 pv_entry_t pv; 1419 1420 pv = get_pv_entry(pmap); 1421 pv->pv_va = va; 1422 pv->pv_pmap = pmap; 1423 pv->pv_ptem = mpte; 1424 pv->pv_wired = wired; 1425 1426 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1427 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1428 TAILQ_INSERT_TAIL(&pmap->pm_pvlist, pv, pv_plist); 1429 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 1430 m->md.pv_list_count++; 1431} 1432 1433/* 1434 * Conditionally create a pv entry. 1435 */ 1436static boolean_t 1437pmap_try_insert_pv_entry(pmap_t pmap, vm_page_t mpte, vm_offset_t va, 1438 vm_page_t m) 1439{ 1440 pv_entry_t pv; 1441 1442 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1443 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1444 if (pv_entry_count < pv_entry_high_water && 1445 (pv = uma_zalloc(pvzone, M_NOWAIT)) != NULL) { 1446 pv_entry_count++; 1447 pv->pv_va = va; 1448 pv->pv_pmap = pmap; 1449 pv->pv_ptem = mpte; 1450 pv->pv_wired = FALSE; 1451 TAILQ_INSERT_TAIL(&pmap->pm_pvlist, pv, pv_plist); 1452 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 1453 m->md.pv_list_count++; 1454 return (TRUE); 1455 } else 1456 return (FALSE); 1457} 1458 1459/* 1460 * pmap_remove_pte: do the things to unmap a page in a process 1461 */ 1462static int 1463pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va) 1464{ 1465 pt_entry_t oldpte; 1466 vm_page_t m; 1467 vm_offset_t pa; 1468 1469 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1470 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1471 1472 oldpte = loadandclear((u_int *)ptq); 1473 if (is_kernel_pmap(pmap)) 1474 *ptq = PTE_G; 1475 1476 if (oldpte & PTE_W) 1477 pmap->pm_stats.wired_count -= 1; 1478 1479 pmap->pm_stats.resident_count -= 1; 1480 pa = mips_tlbpfn_to_paddr(oldpte); 1481 1482 if (page_is_managed(pa)) { 1483 m = PHYS_TO_VM_PAGE(pa); 1484 if (oldpte & PTE_M) { 1485#if defined(PMAP_DIAGNOSTIC) 1486 if (pmap_nw_modified(oldpte)) { 1487 printf( 1488 "pmap_remove: modified page not writable: va: 0x%x, pte: 0x%x\n", 1489 va, oldpte); 1490 } 1491#endif 1492 vm_page_dirty(m); 1493 } 1494 if (m->md.pv_flags & PV_TABLE_REF) 1495 vm_page_flag_set(m, PG_REFERENCED); 1496 m->md.pv_flags &= ~(PV_TABLE_REF | PV_TABLE_MOD); 1497 1498 pmap_remove_entry(pmap, m, va); 1499 } 1500 return pmap_unuse_pt(pmap, va, NULL); 1501} 1502 1503/* 1504 * Remove a single page from a process address space 1505 */ 1506static void 1507pmap_remove_page(struct pmap *pmap, vm_offset_t va) 1508{ 1509 register pt_entry_t *ptq; 1510 1511 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1512 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1513 ptq = pmap_pte(pmap, va); 1514 1515 /* 1516 * if there is no pte for this address, just skip it!!! 1517 */ 1518 if (!ptq || !pmap_pte_v(ptq)) { 1519 return; 1520 } 1521 1522 /* 1523 * Write back all caches from the page being destroyed 1524 */ 1525 mips_dcache_wbinv_range_index(va, PAGE_SIZE); 1526 1527 /* 1528 * get a local va for mappings for this pmap. 1529 */ 1530 (void)pmap_remove_pte(pmap, ptq, va); 1531 pmap_invalidate_page(pmap, va); 1532 1533 return; 1534} 1535 1536/* 1537 * Remove the given range of addresses from the specified map. 1538 * 1539 * It is assumed that the start and end are properly 1540 * rounded to the page size. 1541 */ 1542void 1543pmap_remove(struct pmap *pmap, vm_offset_t sva, vm_offset_t eva) 1544{ 1545 vm_offset_t va, nva; 1546 1547 if (pmap == NULL) 1548 return; 1549 1550 if (pmap->pm_stats.resident_count == 0) 1551 return; 1552 1553 vm_page_lock_queues(); 1554 PMAP_LOCK(pmap); 1555 1556 /* 1557 * special handling of removing one page. a very common operation 1558 * and easy to short circuit some code. 1559 */ 1560 if ((sva + PAGE_SIZE) == eva) { 1561 pmap_remove_page(pmap, sva); 1562 goto out; 1563 } 1564 for (va = sva; va < eva; va = nva) { 1565 if (!*pmap_pde(pmap, va)) { 1566 nva = mips_segtrunc(va + MIPS_SEGSIZE); 1567 continue; 1568 } 1569 pmap_remove_page(pmap, va); 1570 nva = va + PAGE_SIZE; 1571 } 1572 1573out: 1574 vm_page_unlock_queues(); 1575 PMAP_UNLOCK(pmap); 1576} 1577 1578/* 1579 * Routine: pmap_remove_all 1580 * Function: 1581 * Removes this physical page from 1582 * all physical maps in which it resides. 1583 * Reflects back modify bits to the pager. 1584 * 1585 * Notes: 1586 * Original versions of this routine were very 1587 * inefficient because they iteratively called 1588 * pmap_remove (slow...) 1589 */ 1590 1591void 1592pmap_remove_all(vm_page_t m) 1593{ 1594 register pv_entry_t pv; 1595 register pt_entry_t *pte, tpte; 1596 1597 KASSERT((m->flags & PG_FICTITIOUS) == 0, 1598 ("pmap_remove_all: page %p is fictitious", m)); 1599 vm_page_lock_queues(); 1600 1601 if (m->md.pv_flags & PV_TABLE_REF) 1602 vm_page_flag_set(m, PG_REFERENCED); 1603 1604 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 1605 PMAP_LOCK(pv->pv_pmap); 1606 1607 /* 1608 * If it's last mapping writeback all caches from 1609 * the page being destroyed 1610 */ 1611 if (m->md.pv_list_count == 1) 1612 mips_dcache_wbinv_range_index(pv->pv_va, PAGE_SIZE); 1613 1614 pv->pv_pmap->pm_stats.resident_count--; 1615 1616 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 1617 1618 tpte = loadandclear((u_int *)pte); 1619 if (is_kernel_pmap(pv->pv_pmap)) 1620 *pte = PTE_G; 1621 1622 if (tpte & PTE_W) 1623 pv->pv_pmap->pm_stats.wired_count--; 1624 1625 /* 1626 * Update the vm_page_t clean and reference bits. 1627 */ 1628 if (tpte & PTE_M) { 1629#if defined(PMAP_DIAGNOSTIC) 1630 if (pmap_nw_modified(tpte)) { 1631 printf( 1632 "pmap_remove_all: modified page not writable: va: 0x%x, pte: 0x%x\n", 1633 pv->pv_va, tpte); 1634 } 1635#endif 1636 vm_page_dirty(m); 1637 } 1638 pmap_invalidate_page(pv->pv_pmap, pv->pv_va); 1639 1640 TAILQ_REMOVE(&pv->pv_pmap->pm_pvlist, pv, pv_plist); 1641 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 1642 m->md.pv_list_count--; 1643 pmap_unuse_pt(pv->pv_pmap, pv->pv_va, pv->pv_ptem); 1644 PMAP_UNLOCK(pv->pv_pmap); 1645 free_pv_entry(pv); 1646 } 1647 1648 vm_page_flag_clear(m, PG_WRITEABLE); 1649 m->md.pv_flags &= ~(PV_TABLE_REF | PV_TABLE_MOD); 1650 vm_page_unlock_queues(); 1651} 1652 1653/* 1654 * Set the physical protection on the 1655 * specified range of this map as requested. 1656 */ 1657void 1658pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 1659{ 1660 pt_entry_t *pte; 1661 1662 if (pmap == NULL) 1663 return; 1664 1665 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1666 pmap_remove(pmap, sva, eva); 1667 return; 1668 } 1669 if (prot & VM_PROT_WRITE) 1670 return; 1671 1672 vm_page_lock_queues(); 1673 PMAP_LOCK(pmap); 1674 while (sva < eva) { 1675 pt_entry_t pbits, obits; 1676 vm_page_t m; 1677 vm_offset_t pa; 1678 1679 /* 1680 * If segment table entry is empty, skip this segment. 1681 */ 1682 if (!*pmap_pde(pmap, sva)) { 1683 sva = mips_segtrunc(sva + MIPS_SEGSIZE); 1684 continue; 1685 } 1686 /* 1687 * If pte is invalid, skip this page 1688 */ 1689 pte = pmap_pte(pmap, sva); 1690 if (!pmap_pte_v(pte)) { 1691 sva += PAGE_SIZE; 1692 continue; 1693 } 1694retry: 1695 obits = pbits = *pte; 1696 pa = mips_tlbpfn_to_paddr(pbits); 1697 1698 if (page_is_managed(pa) && (pbits & PTE_M) != 0) { 1699 m = PHYS_TO_VM_PAGE(pa); 1700 vm_page_dirty(m); 1701 m->md.pv_flags &= ~PV_TABLE_MOD; 1702 } 1703 pbits = (pbits & ~PTE_M) | PTE_RO; 1704 1705 if (pbits != *pte) { 1706 if (!atomic_cmpset_int((u_int *)pte, obits, pbits)) 1707 goto retry; 1708 pmap_update_page(pmap, sva, pbits); 1709 } 1710 sva += PAGE_SIZE; 1711 } 1712 vm_page_unlock_queues(); 1713 PMAP_UNLOCK(pmap); 1714} 1715 1716/* 1717 * Insert the given physical page (p) at 1718 * the specified virtual address (v) in the 1719 * target physical map with the protection requested. 1720 * 1721 * If specified, the page will be wired down, meaning 1722 * that the related pte can not be reclaimed. 1723 * 1724 * NB: This is the only routine which MAY NOT lazy-evaluate 1725 * or lose information. That is, this routine must actually 1726 * insert this page into the given map NOW. 1727 */ 1728void 1729pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m, 1730 vm_prot_t prot, boolean_t wired) 1731{ 1732 vm_offset_t pa, opa; 1733 register pt_entry_t *pte; 1734 pt_entry_t origpte, newpte; 1735 vm_page_t mpte, om; 1736 int rw = 0; 1737 1738 if (pmap == NULL) 1739 return; 1740 1741 va &= ~PAGE_MASK; 1742 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig")); 1743 KASSERT((m->oflags & VPO_BUSY) != 0, 1744 ("pmap_enter: page %p is not busy", m)); 1745 1746 mpte = NULL; 1747 1748 vm_page_lock_queues(); 1749 PMAP_LOCK(pmap); 1750 1751 /* 1752 * In the case that a page table page is not resident, we are 1753 * creating it here. 1754 */ 1755 if (va < VM_MAXUSER_ADDRESS) { 1756 mpte = pmap_allocpte(pmap, va, M_WAITOK); 1757 } 1758 pte = pmap_pte(pmap, va); 1759 1760 /* 1761 * Page Directory table entry not valid, we need a new PT page 1762 */ 1763 if (pte == NULL) { 1764 panic("pmap_enter: invalid page directory, pdir=%p, va=%p\n", 1765 (void *)pmap->pm_segtab, (void *)va); 1766 } 1767 pa = VM_PAGE_TO_PHYS(m); 1768 om = NULL; 1769 origpte = *pte; 1770 opa = mips_tlbpfn_to_paddr(origpte); 1771 1772 /* 1773 * Mapping has not changed, must be protection or wiring change. 1774 */ 1775 if ((origpte & PTE_V) && (opa == pa)) { 1776 /* 1777 * Wiring change, just update stats. We don't worry about 1778 * wiring PT pages as they remain resident as long as there 1779 * are valid mappings in them. Hence, if a user page is 1780 * wired, the PT page will be also. 1781 */ 1782 if (wired && ((origpte & PTE_W) == 0)) 1783 pmap->pm_stats.wired_count++; 1784 else if (!wired && (origpte & PTE_W)) 1785 pmap->pm_stats.wired_count--; 1786 1787#if defined(PMAP_DIAGNOSTIC) 1788 if (pmap_nw_modified(origpte)) { 1789 printf( 1790 "pmap_enter: modified page not writable: va: 0x%x, pte: 0x%x\n", 1791 va, origpte); 1792 } 1793#endif 1794 1795 /* 1796 * Remove extra pte reference 1797 */ 1798 if (mpte) 1799 mpte->wire_count--; 1800 1801 /* 1802 * We might be turning off write access to the page, so we 1803 * go ahead and sense modify status. 1804 */ 1805 if (page_is_managed(opa)) { 1806 om = m; 1807 } 1808 goto validate; 1809 } 1810 /* 1811 * Mapping has changed, invalidate old range and fall through to 1812 * handle validating new mapping. 1813 */ 1814 if (opa) { 1815 if (origpte & PTE_W) 1816 pmap->pm_stats.wired_count--; 1817 1818 if (page_is_managed(opa)) { 1819 om = PHYS_TO_VM_PAGE(opa); 1820 pmap_remove_entry(pmap, om, va); 1821 } 1822 if (mpte != NULL) { 1823 mpte->wire_count--; 1824 KASSERT(mpte->wire_count > 0, 1825 ("pmap_enter: missing reference to page table page," 1826 " va: %p", (void *)va)); 1827 } 1828 } else 1829 pmap->pm_stats.resident_count++; 1830 1831 /* 1832 * Enter on the PV list if part of our managed memory. Note that we 1833 * raise IPL while manipulating pv_table since pmap_enter can be 1834 * called at interrupt time. 1835 */ 1836 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) { 1837 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva, 1838 ("pmap_enter: managed mapping within the clean submap")); 1839 pmap_insert_entry(pmap, va, mpte, m, wired); 1840 } 1841 /* 1842 * Increment counters 1843 */ 1844 if (wired) 1845 pmap->pm_stats.wired_count++; 1846 1847validate: 1848 if ((access & VM_PROT_WRITE) != 0) 1849 m->md.pv_flags |= PV_TABLE_MOD | PV_TABLE_REF; 1850 rw = init_pte_prot(va, m, prot); 1851 1852#ifdef PMAP_DEBUG 1853 printf("pmap_enter: va: 0x%08x -> pa: 0x%08x\n", va, pa); 1854#endif 1855 /* 1856 * Now validate mapping with desired protection/wiring. 1857 */ 1858 newpte = mips_paddr_to_tlbpfn(pa) | rw | PTE_V; 1859 1860 if (is_cacheable_mem(pa)) 1861 newpte |= PTE_CACHE; 1862 else 1863 newpte |= PTE_UNCACHED; 1864 1865 if (wired) 1866 newpte |= PTE_W; 1867 1868 if (is_kernel_pmap(pmap)) { 1869 newpte |= PTE_G; 1870 } 1871 1872 /* 1873 * if the mapping or permission bits are different, we need to 1874 * update the pte. 1875 */ 1876 if (origpte != newpte) { 1877 if (origpte & PTE_V) { 1878 *pte = newpte; 1879 if (page_is_managed(opa) && (opa != pa)) { 1880 if (om->md.pv_flags & PV_TABLE_REF) 1881 vm_page_flag_set(om, PG_REFERENCED); 1882 om->md.pv_flags &= 1883 ~(PV_TABLE_REF | PV_TABLE_MOD); 1884 } 1885 if (origpte & PTE_M) { 1886 KASSERT((origpte & PTE_RW), 1887 ("pmap_enter: modified page not writable:" 1888 " va: %p, pte: 0x%x", (void *)va, origpte)); 1889 if (page_is_managed(opa)) 1890 vm_page_dirty(om); 1891 } 1892 } else { 1893 *pte = newpte; 1894 } 1895 } 1896 pmap_update_page(pmap, va, newpte); 1897 1898 /* 1899 * Sync I & D caches for executable pages. Do this only if the the 1900 * target pmap belongs to the current process. Otherwise, an 1901 * unresolvable TLB miss may occur. 1902 */ 1903 if (!is_kernel_pmap(pmap) && (pmap == &curproc->p_vmspace->vm_pmap) && 1904 (prot & VM_PROT_EXECUTE)) { 1905 mips_icache_sync_range(va, PAGE_SIZE); 1906 mips_dcache_wbinv_range(va, PAGE_SIZE); 1907 } 1908 vm_page_unlock_queues(); 1909 PMAP_UNLOCK(pmap); 1910} 1911 1912/* 1913 * this code makes some *MAJOR* assumptions: 1914 * 1. Current pmap & pmap exists. 1915 * 2. Not wired. 1916 * 3. Read access. 1917 * 4. No page table pages. 1918 * but is *MUCH* faster than pmap_enter... 1919 */ 1920 1921void 1922pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 1923{ 1924 1925 vm_page_lock_queues(); 1926 PMAP_LOCK(pmap); 1927 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL); 1928 vm_page_unlock_queues(); 1929 PMAP_UNLOCK(pmap); 1930} 1931 1932static vm_page_t 1933pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, 1934 vm_prot_t prot, vm_page_t mpte) 1935{ 1936 pt_entry_t *pte; 1937 vm_offset_t pa; 1938 1939 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva || 1940 (m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0, 1941 ("pmap_enter_quick_locked: managed mapping within the clean submap")); 1942 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1943 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1944 1945 /* 1946 * In the case that a page table page is not resident, we are 1947 * creating it here. 1948 */ 1949 if (va < VM_MAXUSER_ADDRESS) { 1950 unsigned ptepindex; 1951 vm_offset_t pteva; 1952 1953 /* 1954 * Calculate pagetable page index 1955 */ 1956 ptepindex = va >> SEGSHIFT; 1957 if (mpte && (mpte->pindex == ptepindex)) { 1958 mpte->wire_count++; 1959 } else { 1960 /* 1961 * Get the page directory entry 1962 */ 1963 pteva = (vm_offset_t)pmap->pm_segtab[ptepindex]; 1964 1965 /* 1966 * If the page table page is mapped, we just 1967 * increment the hold count, and activate it. 1968 */ 1969 if (pteva) { 1970 if (pmap->pm_ptphint && 1971 (pmap->pm_ptphint->pindex == ptepindex)) { 1972 mpte = pmap->pm_ptphint; 1973 } else { 1974 mpte = PHYS_TO_VM_PAGE( 1975 MIPS_KSEG0_TO_PHYS(pteva)); 1976 pmap->pm_ptphint = mpte; 1977 } 1978 mpte->wire_count++; 1979 } else { 1980 mpte = _pmap_allocpte(pmap, ptepindex, 1981 M_NOWAIT); 1982 if (mpte == NULL) 1983 return (mpte); 1984 } 1985 } 1986 } else { 1987 mpte = NULL; 1988 } 1989 1990 pte = pmap_pte(pmap, va); 1991 if (pmap_pte_v(pte)) { 1992 if (mpte != NULL) { 1993 mpte->wire_count--; 1994 mpte = NULL; 1995 } 1996 return (mpte); 1997 } 1998 1999 /* 2000 * Enter on the PV list if part of our managed memory. 2001 */ 2002 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0 && 2003 !pmap_try_insert_pv_entry(pmap, mpte, va, m)) { 2004 if (mpte != NULL) { 2005 pmap_unwire_pte_hold(pmap, mpte); 2006 mpte = NULL; 2007 } 2008 return (mpte); 2009 } 2010 2011 /* 2012 * Increment counters 2013 */ 2014 pmap->pm_stats.resident_count++; 2015 2016 pa = VM_PAGE_TO_PHYS(m); 2017 2018 /* 2019 * Now validate mapping with RO protection 2020 */ 2021 *pte = mips_paddr_to_tlbpfn(pa) | PTE_V; 2022 2023 if (is_cacheable_mem(pa)) 2024 *pte |= PTE_CACHE; 2025 else 2026 *pte |= PTE_UNCACHED; 2027 2028 if (is_kernel_pmap(pmap)) 2029 *pte |= PTE_G; 2030 else { 2031 *pte |= PTE_RO; 2032 /* 2033 * Sync I & D caches. Do this only if the the target pmap 2034 * belongs to the current process. Otherwise, an 2035 * unresolvable TLB miss may occur. */ 2036 if (pmap == &curproc->p_vmspace->vm_pmap) { 2037 va &= ~PAGE_MASK; 2038 mips_icache_sync_range(va, PAGE_SIZE); 2039 mips_dcache_wbinv_range(va, PAGE_SIZE); 2040 } 2041 } 2042 return (mpte); 2043} 2044 2045/* 2046 * Make a temporary mapping for a physical address. This is only intended 2047 * to be used for panic dumps. 2048 */ 2049void * 2050pmap_kenter_temporary(vm_paddr_t pa, int i) 2051{ 2052 vm_offset_t va; 2053 register_t intr; 2054 if (i != 0) 2055 printf("%s: ERROR!!! More than one page of virtual address mapping not supported\n", 2056 __func__); 2057 2058 if (pa < MIPS_KSEG0_LARGEST_PHYS) { 2059 va = MIPS_PHYS_TO_KSEG0(pa); 2060 } else { 2061 int cpu; 2062 struct local_sysmaps *sysm; 2063 pt_entry_t *pte, npte; 2064 2065 /* If this is used other than for dumps, we may need to leave 2066 * interrupts disasbled on return. If crash dumps don't work when 2067 * we get to this point, we might want to consider this (leaving things 2068 * disabled as a starting point ;-) 2069 */ 2070 intr = intr_disable(); 2071 cpu = PCPU_GET(cpuid); 2072 sysm = &sysmap_lmem[cpu]; 2073 /* Since this is for the debugger, no locks or any other fun */ 2074 npte = mips_paddr_to_tlbpfn(pa) | PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; 2075 pte = pmap_pte(kernel_pmap, sysm->base); 2076 *pte = npte; 2077 sysm->valid1 = 1; 2078 pmap_update_page(kernel_pmap, sysm->base, npte); 2079 va = sysm->base; 2080 intr_restore(intr); 2081 } 2082 return ((void *)va); 2083} 2084 2085void 2086pmap_kenter_temporary_free(vm_paddr_t pa) 2087{ 2088 int cpu; 2089 register_t intr; 2090 struct local_sysmaps *sysm; 2091 2092 if (pa < MIPS_KSEG0_LARGEST_PHYS) { 2093 /* nothing to do for this case */ 2094 return; 2095 } 2096 cpu = PCPU_GET(cpuid); 2097 sysm = &sysmap_lmem[cpu]; 2098 if (sysm->valid1) { 2099 pt_entry_t *pte; 2100 2101 intr = intr_disable(); 2102 pte = pmap_pte(kernel_pmap, sysm->base); 2103 *pte = PTE_G; 2104 pmap_invalidate_page(kernel_pmap, sysm->base); 2105 intr_restore(intr); 2106 sysm->valid1 = 0; 2107 } 2108} 2109 2110/* 2111 * Moved the code to Machine Independent 2112 * vm_map_pmap_enter() 2113 */ 2114 2115/* 2116 * Maps a sequence of resident pages belonging to the same object. 2117 * The sequence begins with the given page m_start. This page is 2118 * mapped at the given virtual address start. Each subsequent page is 2119 * mapped at a virtual address that is offset from start by the same 2120 * amount as the page is offset from m_start within the object. The 2121 * last page in the sequence is the page with the largest offset from 2122 * m_start that can be mapped at a virtual address less than the given 2123 * virtual address end. Not every virtual page between start and end 2124 * is mapped; only those for which a resident page exists with the 2125 * corresponding offset from m_start are mapped. 2126 */ 2127void 2128pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 2129 vm_page_t m_start, vm_prot_t prot) 2130{ 2131 vm_page_t m, mpte; 2132 vm_pindex_t diff, psize; 2133 2134 VM_OBJECT_LOCK_ASSERT(m_start->object, MA_OWNED); 2135 psize = atop(end - start); 2136 mpte = NULL; 2137 m = m_start; 2138 vm_page_lock_queues(); 2139 PMAP_LOCK(pmap); 2140 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 2141 mpte = pmap_enter_quick_locked(pmap, start + ptoa(diff), m, 2142 prot, mpte); 2143 m = TAILQ_NEXT(m, listq); 2144 } 2145 vm_page_unlock_queues(); 2146 PMAP_UNLOCK(pmap); 2147} 2148 2149/* 2150 * pmap_object_init_pt preloads the ptes for a given object 2151 * into the specified pmap. This eliminates the blast of soft 2152 * faults on process startup and immediately after an mmap. 2153 */ 2154void 2155pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, 2156 vm_object_t object, vm_pindex_t pindex, vm_size_t size) 2157{ 2158 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 2159 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 2160 ("pmap_object_init_pt: non-device object")); 2161} 2162 2163/* 2164 * Routine: pmap_change_wiring 2165 * Function: Change the wiring attribute for a map/virtual-address 2166 * pair. 2167 * In/out conditions: 2168 * The mapping must already exist in the pmap. 2169 */ 2170void 2171pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 2172{ 2173 register pt_entry_t *pte; 2174 2175 if (pmap == NULL) 2176 return; 2177 2178 PMAP_LOCK(pmap); 2179 pte = pmap_pte(pmap, va); 2180 2181 if (wired && !pmap_pte_w(pte)) 2182 pmap->pm_stats.wired_count++; 2183 else if (!wired && pmap_pte_w(pte)) 2184 pmap->pm_stats.wired_count--; 2185 2186 /* 2187 * Wiring is not a hardware characteristic so there is no need to 2188 * invalidate TLB. 2189 */ 2190 pmap_pte_set_w(pte, wired); 2191 PMAP_UNLOCK(pmap); 2192} 2193 2194/* 2195 * Copy the range specified by src_addr/len 2196 * from the source map to the range dst_addr/len 2197 * in the destination map. 2198 * 2199 * This routine is only advisory and need not do anything. 2200 */ 2201 2202void 2203pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, 2204 vm_size_t len, vm_offset_t src_addr) 2205{ 2206} 2207 2208/* 2209 * pmap_zero_page zeros the specified hardware page by mapping 2210 * the page into KVM and using bzero to clear its contents. 2211 */ 2212void 2213pmap_zero_page(vm_page_t m) 2214{ 2215 vm_offset_t va; 2216 vm_paddr_t phys = VM_PAGE_TO_PHYS(m); 2217 register_t intr; 2218 2219 if (phys < MIPS_KSEG0_LARGEST_PHYS) { 2220 va = MIPS_PHYS_TO_KSEG0(phys); 2221 2222 bzero((caddr_t)va, PAGE_SIZE); 2223 mips_dcache_wbinv_range(va, PAGE_SIZE); 2224 } else { 2225 PMAP_LMEM_MAP1(va, phys); 2226 2227 bzero((caddr_t)va, PAGE_SIZE); 2228 mips_dcache_wbinv_range(va, PAGE_SIZE); 2229 2230 PMAP_LMEM_UNMAP(); 2231 } 2232} 2233 2234/* 2235 * pmap_zero_page_area zeros the specified hardware page by mapping 2236 * the page into KVM and using bzero to clear its contents. 2237 * 2238 * off and size may not cover an area beyond a single hardware page. 2239 */ 2240void 2241pmap_zero_page_area(vm_page_t m, int off, int size) 2242{ 2243 vm_offset_t va; 2244 vm_paddr_t phys = VM_PAGE_TO_PHYS(m); 2245 register_t intr; 2246 2247 if (phys < MIPS_KSEG0_LARGEST_PHYS) { 2248 va = MIPS_PHYS_TO_KSEG0(phys); 2249 bzero((char *)(caddr_t)va + off, size); 2250 mips_dcache_wbinv_range(va + off, size); 2251 } else { 2252 PMAP_LMEM_MAP1(va, phys); 2253 2254 bzero((char *)va + off, size); 2255 mips_dcache_wbinv_range(va + off, size); 2256 2257 PMAP_LMEM_UNMAP(); 2258 } 2259} 2260 2261void 2262pmap_zero_page_idle(vm_page_t m) 2263{ 2264 vm_offset_t va; 2265 vm_paddr_t phys = VM_PAGE_TO_PHYS(m); 2266 register_t intr; 2267 2268 if (phys < MIPS_KSEG0_LARGEST_PHYS) { 2269 va = MIPS_PHYS_TO_KSEG0(phys); 2270 bzero((caddr_t)va, PAGE_SIZE); 2271 mips_dcache_wbinv_range(va, PAGE_SIZE); 2272 } else { 2273 PMAP_LMEM_MAP1(va, phys); 2274 2275 bzero((caddr_t)va, PAGE_SIZE); 2276 mips_dcache_wbinv_range(va, PAGE_SIZE); 2277 2278 PMAP_LMEM_UNMAP(); 2279 } 2280} 2281 2282/* 2283 * pmap_copy_page copies the specified (machine independent) 2284 * page by mapping the page into virtual memory and using 2285 * bcopy to copy the page, one machine dependent page at a 2286 * time. 2287 */ 2288void 2289pmap_copy_page(vm_page_t src, vm_page_t dst) 2290{ 2291 vm_offset_t va_src, va_dst; 2292 vm_paddr_t phy_src = VM_PAGE_TO_PHYS(src); 2293 vm_paddr_t phy_dst = VM_PAGE_TO_PHYS(dst); 2294 register_t intr; 2295 2296 if ((phy_src < MIPS_KSEG0_LARGEST_PHYS) && (phy_dst < MIPS_KSEG0_LARGEST_PHYS)) { 2297 /* easy case, all can be accessed via KSEG0 */ 2298 /* 2299 * Flush all caches for VA that are mapped to this page 2300 * to make sure that data in SDRAM is up to date 2301 */ 2302 pmap_flush_pvcache(src); 2303 mips_dcache_wbinv_range_index( 2304 MIPS_PHYS_TO_KSEG0(phy_dst), PAGE_SIZE); 2305 va_src = MIPS_PHYS_TO_KSEG0(phy_src); 2306 va_dst = MIPS_PHYS_TO_KSEG0(phy_dst); 2307 bcopy((caddr_t)va_src, (caddr_t)va_dst, PAGE_SIZE); 2308 mips_dcache_wbinv_range(va_dst, PAGE_SIZE); 2309 } else { 2310 PMAP_LMEM_MAP2(va_src, phy_src, va_dst, phy_dst); 2311 2312 bcopy((void *)va_src, (void *)va_dst, PAGE_SIZE); 2313 mips_dcache_wbinv_range(va_dst, PAGE_SIZE); 2314 2315 PMAP_LMEM_UNMAP(); 2316 } 2317} 2318 2319/* 2320 * Returns true if the pmap's pv is one of the first 2321 * 16 pvs linked to from this page. This count may 2322 * be changed upwards or downwards in the future; it 2323 * is only necessary that true be returned for a small 2324 * subset of pmaps for proper page aging. 2325 */ 2326boolean_t 2327pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 2328{ 2329 pv_entry_t pv; 2330 int loops = 0; 2331 2332 if (m->flags & PG_FICTITIOUS) 2333 return FALSE; 2334 2335 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2336 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2337 if (pv->pv_pmap == pmap) { 2338 return TRUE; 2339 } 2340 loops++; 2341 if (loops >= 16) 2342 break; 2343 } 2344 return (FALSE); 2345} 2346 2347/* 2348 * Remove all pages from specified address space 2349 * this aids process exit speeds. Also, this code 2350 * is special cased for current process only, but 2351 * can have the more generic (and slightly slower) 2352 * mode enabled. This is much faster than pmap_remove 2353 * in the case of running down an entire address space. 2354 */ 2355void 2356pmap_remove_pages(pmap_t pmap) 2357{ 2358 pt_entry_t *pte, tpte; 2359 pv_entry_t pv, npv; 2360 vm_page_t m; 2361 2362 if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) { 2363 printf("warning: pmap_remove_pages called with non-current pmap\n"); 2364 return; 2365 } 2366 vm_page_lock_queues(); 2367 PMAP_LOCK(pmap); 2368 sched_pin(); 2369 //XXX need to be TAILQ_FOREACH_SAFE ? 2370 for (pv = TAILQ_FIRST(&pmap->pm_pvlist); pv; pv = npv) { 2371 2372 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 2373 if (!pmap_pte_v(pte)) 2374 panic("pmap_remove_pages: page on pm_pvlist has no pte\n"); 2375 tpte = *pte; 2376 2377/* 2378 * We cannot remove wired pages from a process' mapping at this time 2379 */ 2380 if (tpte & PTE_W) { 2381 npv = TAILQ_NEXT(pv, pv_plist); 2382 continue; 2383 } 2384 *pte = is_kernel_pmap(pmap) ? PTE_G : 0; 2385 2386 m = PHYS_TO_VM_PAGE(mips_tlbpfn_to_paddr(tpte)); 2387 KASSERT(m != NULL, 2388 ("pmap_remove_pages: bad tpte %x", tpte)); 2389 2390 pv->pv_pmap->pm_stats.resident_count--; 2391 2392 /* 2393 * Update the vm_page_t clean and reference bits. 2394 */ 2395 if (tpte & PTE_M) { 2396 vm_page_dirty(m); 2397 } 2398 npv = TAILQ_NEXT(pv, pv_plist); 2399 TAILQ_REMOVE(&pv->pv_pmap->pm_pvlist, pv, pv_plist); 2400 2401 m->md.pv_list_count--; 2402 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2403 if (TAILQ_FIRST(&m->md.pv_list) == NULL) { 2404 vm_page_flag_clear(m, PG_WRITEABLE); 2405 } 2406 pmap_unuse_pt(pv->pv_pmap, pv->pv_va, pv->pv_ptem); 2407 free_pv_entry(pv); 2408 } 2409 sched_unpin(); 2410 pmap_invalidate_all(pmap); 2411 PMAP_UNLOCK(pmap); 2412 vm_page_unlock_queues(); 2413} 2414 2415/* 2416 * pmap_testbit tests bits in pte's 2417 * note that the testbit/changebit routines are inline, 2418 * and a lot of things compile-time evaluate. 2419 */ 2420static boolean_t 2421pmap_testbit(vm_page_t m, int bit) 2422{ 2423 pv_entry_t pv; 2424 pt_entry_t *pte; 2425 boolean_t rv = FALSE; 2426 2427 if (m->flags & PG_FICTITIOUS) 2428 return rv; 2429 2430 if (TAILQ_FIRST(&m->md.pv_list) == NULL) 2431 return rv; 2432 2433 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2434 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2435#if defined(PMAP_DIAGNOSTIC) 2436 if (!pv->pv_pmap) { 2437 printf("Null pmap (tb) at va: 0x%x\n", pv->pv_va); 2438 continue; 2439 } 2440#endif 2441 PMAP_LOCK(pv->pv_pmap); 2442 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 2443 rv = (*pte & bit) != 0; 2444 PMAP_UNLOCK(pv->pv_pmap); 2445 if (rv) 2446 break; 2447 } 2448 return (rv); 2449} 2450 2451/* 2452 * this routine is used to modify bits in ptes 2453 */ 2454static __inline void 2455pmap_changebit(vm_page_t m, int bit, boolean_t setem) 2456{ 2457 register pv_entry_t pv; 2458 register pt_entry_t *pte; 2459 2460 if (m->flags & PG_FICTITIOUS) 2461 return; 2462 2463 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2464 /* 2465 * Loop over all current mappings setting/clearing as appropos If 2466 * setting RO do we need to clear the VAC? 2467 */ 2468 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2469#if defined(PMAP_DIAGNOSTIC) 2470 if (!pv->pv_pmap) { 2471 printf("Null pmap (cb) at va: 0x%x\n", pv->pv_va); 2472 continue; 2473 } 2474#endif 2475 2476 PMAP_LOCK(pv->pv_pmap); 2477 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 2478 2479 if (setem) { 2480 *(int *)pte |= bit; 2481 pmap_update_page(pv->pv_pmap, pv->pv_va, *pte); 2482 } else { 2483 vm_offset_t pbits = *(vm_offset_t *)pte; 2484 2485 if (pbits & bit) { 2486 if (bit == PTE_RW) { 2487 if (pbits & PTE_M) { 2488 vm_page_dirty(m); 2489 } 2490 *(int *)pte = (pbits & ~(PTE_M | PTE_RW)) | 2491 PTE_RO; 2492 } else { 2493 *(int *)pte = pbits & ~bit; 2494 } 2495 pmap_update_page(pv->pv_pmap, pv->pv_va, *pte); 2496 } 2497 } 2498 PMAP_UNLOCK(pv->pv_pmap); 2499 } 2500 if (!setem && bit == PTE_RW) 2501 vm_page_flag_clear(m, PG_WRITEABLE); 2502} 2503 2504/* 2505 * pmap_page_wired_mappings: 2506 * 2507 * Return the number of managed mappings to the given physical page 2508 * that are wired. 2509 */ 2510int 2511pmap_page_wired_mappings(vm_page_t m) 2512{ 2513 pv_entry_t pv; 2514 int count; 2515 2516 count = 0; 2517 if ((m->flags & PG_FICTITIOUS) != 0) 2518 return (count); 2519 vm_page_lock_queues(); 2520 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) 2521 if (pv->pv_wired) 2522 count++; 2523 vm_page_unlock_queues(); 2524 return (count); 2525} 2526 2527/* 2528 * Clear the write and modified bits in each of the given page's mappings. 2529 */ 2530void 2531pmap_remove_write(vm_page_t m) 2532{ 2533 pv_entry_t pv, npv; 2534 vm_offset_t va; 2535 pt_entry_t *pte; 2536 2537 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2538 ("pmap_remove_write: page %p is not managed", m)); 2539 2540 /* 2541 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be set by 2542 * another thread while the object is locked. Thus, if PG_WRITEABLE 2543 * is clear, no page table entries need updating. 2544 */ 2545 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 2546 if ((m->oflags & VPO_BUSY) == 0 && 2547 (m->flags & PG_WRITEABLE) == 0) 2548 return; 2549 2550 /* 2551 * Loop over all current mappings setting/clearing as appropos. 2552 */ 2553 vm_page_lock_queues(); 2554 for (pv = TAILQ_FIRST(&m->md.pv_list); pv; pv = npv) { 2555 npv = TAILQ_NEXT(pv, pv_plist); 2556 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 2557 2558 if ((pte == NULL) || !mips_pg_v(*pte)) 2559 panic("page on pm_pvlist has no pte\n"); 2560 2561 va = pv->pv_va; 2562 pmap_protect(pv->pv_pmap, va, va + PAGE_SIZE, 2563 VM_PROT_READ | VM_PROT_EXECUTE); 2564 } 2565 vm_page_flag_clear(m, PG_WRITEABLE); 2566 vm_page_unlock_queues(); 2567} 2568 2569/* 2570 * pmap_ts_referenced: 2571 * 2572 * Return the count of reference bits for a page, clearing all of them. 2573 */ 2574int 2575pmap_ts_referenced(vm_page_t m) 2576{ 2577 if (m->flags & PG_FICTITIOUS) 2578 return (0); 2579 2580 if (m->md.pv_flags & PV_TABLE_REF) { 2581 m->md.pv_flags &= ~PV_TABLE_REF; 2582 return 1; 2583 } 2584 return 0; 2585} 2586 2587/* 2588 * pmap_is_modified: 2589 * 2590 * Return whether or not the specified physical page was modified 2591 * in any physical maps. 2592 */ 2593boolean_t 2594pmap_is_modified(vm_page_t m) 2595{ 2596 boolean_t rv; 2597 2598 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2599 ("pmap_is_modified: page %p is not managed", m)); 2600 2601 /* 2602 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be 2603 * concurrently set while the object is locked. Thus, if PG_WRITEABLE 2604 * is clear, no PTEs can have PTE_M set. 2605 */ 2606 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 2607 if ((m->oflags & VPO_BUSY) == 0 && 2608 (m->flags & PG_WRITEABLE) == 0) 2609 return (FALSE); 2610 vm_page_lock_queues(); 2611 if (m->md.pv_flags & PV_TABLE_MOD) 2612 rv = TRUE; 2613 else 2614 rv = pmap_testbit(m, PTE_M); 2615 vm_page_unlock_queues(); 2616 return (rv); 2617} 2618 2619/* N/C */ 2620 2621/* 2622 * pmap_is_prefaultable: 2623 * 2624 * Return whether or not the specified virtual address is elgible 2625 * for prefault. 2626 */ 2627boolean_t 2628pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 2629{ 2630 pt_entry_t *pte; 2631 boolean_t rv; 2632 2633 rv = FALSE; 2634 PMAP_LOCK(pmap); 2635 if (*pmap_pde(pmap, addr)) { 2636 pte = pmap_pte(pmap, addr); 2637 rv = (*pte == 0); 2638 } 2639 PMAP_UNLOCK(pmap); 2640 return (rv); 2641} 2642 2643/* 2644 * Clear the modify bits on the specified physical page. 2645 */ 2646void 2647pmap_clear_modify(vm_page_t m) 2648{ 2649 2650 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2651 ("pmap_clear_modify: page %p is not managed", m)); 2652 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 2653 KASSERT((m->oflags & VPO_BUSY) == 0, 2654 ("pmap_clear_modify: page %p is busy", m)); 2655 2656 /* 2657 * If the page is not PG_WRITEABLE, then no PTEs can have PTE_M set. 2658 * If the object containing the page is locked and the page is not 2659 * VPO_BUSY, then PG_WRITEABLE cannot be concurrently set. 2660 */ 2661 if ((m->flags & PG_WRITEABLE) == 0) 2662 return; 2663 vm_page_lock_queues(); 2664 if (m->md.pv_flags & PV_TABLE_MOD) { 2665 pmap_changebit(m, PTE_M, FALSE); 2666 m->md.pv_flags &= ~PV_TABLE_MOD; 2667 } 2668 vm_page_unlock_queues(); 2669} 2670 2671/* 2672 * pmap_is_referenced: 2673 * 2674 * Return whether or not the specified physical page was referenced 2675 * in any physical maps. 2676 */ 2677boolean_t 2678pmap_is_referenced(vm_page_t m) 2679{ 2680 2681 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2682 ("pmap_is_referenced: page %p is not managed", m)); 2683 return ((m->md.pv_flags & PV_TABLE_REF) != 0); 2684} 2685 2686/* 2687 * pmap_clear_reference: 2688 * 2689 * Clear the reference bit on the specified physical page. 2690 */ 2691void 2692pmap_clear_reference(vm_page_t m) 2693{ 2694 2695 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2696 ("pmap_clear_reference: page %p is not managed", m)); 2697 vm_page_lock_queues(); 2698 if (m->md.pv_flags & PV_TABLE_REF) { 2699 m->md.pv_flags &= ~PV_TABLE_REF; 2700 } 2701 vm_page_unlock_queues(); 2702} 2703 2704/* 2705 * Miscellaneous support routines follow 2706 */ 2707 2708/* 2709 * Map a set of physical memory pages into the kernel virtual 2710 * address space. Return a pointer to where it is mapped. This 2711 * routine is intended to be used for mapping device memory, 2712 * NOT real memory. 2713 */ 2714 2715/* 2716 * Map a set of physical memory pages into the kernel virtual 2717 * address space. Return a pointer to where it is mapped. This 2718 * routine is intended to be used for mapping device memory, 2719 * NOT real memory. 2720 */ 2721void * 2722pmap_mapdev(vm_offset_t pa, vm_size_t size) 2723{ 2724 vm_offset_t va, tmpva, offset; 2725 2726 /* 2727 * KSEG1 maps only first 512M of phys address space. For 2728 * pa > 0x20000000 we should make proper mapping * using pmap_kenter. 2729 */ 2730 if ((pa + size - 1) < MIPS_KSEG0_LARGEST_PHYS) 2731 return (void *)MIPS_PHYS_TO_KSEG1(pa); 2732 else { 2733 offset = pa & PAGE_MASK; 2734 size = roundup(size + offset, PAGE_SIZE); 2735 2736 va = kmem_alloc_nofault(kernel_map, size); 2737 if (!va) 2738 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 2739 pa = trunc_page(pa); 2740 for (tmpva = va; size > 0;) { 2741 pmap_kenter(tmpva, pa); 2742 size -= PAGE_SIZE; 2743 tmpva += PAGE_SIZE; 2744 pa += PAGE_SIZE; 2745 } 2746 } 2747 2748 return ((void *)(va + offset)); 2749} 2750 2751void 2752pmap_unmapdev(vm_offset_t va, vm_size_t size) 2753{ 2754 vm_offset_t base, offset, tmpva; 2755 2756 /* If the address is within KSEG1 then there is nothing to do */ 2757 if (va >= MIPS_KSEG1_START && va <= MIPS_KSEG1_END) 2758 return; 2759 2760 base = trunc_page(va); 2761 offset = va & PAGE_MASK; 2762 size = roundup(size + offset, PAGE_SIZE); 2763 for (tmpva = base; tmpva < base + size; tmpva += PAGE_SIZE) 2764 pmap_kremove(tmpva); 2765 kmem_free(kernel_map, base, size); 2766} 2767 2768/* 2769 * perform the pmap work for mincore 2770 */ 2771int 2772pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa) 2773{ 2774 pt_entry_t *ptep, pte; 2775 vm_offset_t pa; 2776 vm_page_t m; 2777 int val; 2778 boolean_t managed; 2779 2780 PMAP_LOCK(pmap); 2781retry: 2782 ptep = pmap_pte(pmap, addr); 2783 pte = (ptep != NULL) ? *ptep : 0; 2784 if (!mips_pg_v(pte)) { 2785 val = 0; 2786 goto out; 2787 } 2788 val = MINCORE_INCORE; 2789 if ((pte & PTE_M) != 0) 2790 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 2791 pa = mips_tlbpfn_to_paddr(pte); 2792 managed = page_is_managed(pa); 2793 if (managed) { 2794 /* 2795 * This may falsely report the given address as 2796 * MINCORE_REFERENCED. Unfortunately, due to the lack of 2797 * per-PTE reference information, it is impossible to 2798 * determine if the address is MINCORE_REFERENCED. 2799 */ 2800 m = PHYS_TO_VM_PAGE(pa); 2801 if ((m->flags & PG_REFERENCED) != 0) 2802 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 2803 } 2804 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) != 2805 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) { 2806 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */ 2807 if (vm_page_pa_tryrelock(pmap, pa, locked_pa)) 2808 goto retry; 2809 } else 2810out: 2811 PA_UNLOCK_COND(*locked_pa); 2812 PMAP_UNLOCK(pmap); 2813 return (val); 2814} 2815 2816void 2817pmap_activate(struct thread *td) 2818{ 2819 pmap_t pmap, oldpmap; 2820 struct proc *p = td->td_proc; 2821 2822 critical_enter(); 2823 2824 pmap = vmspace_pmap(p->p_vmspace); 2825 oldpmap = PCPU_GET(curpmap); 2826 2827 if (oldpmap) 2828 atomic_clear_32(&oldpmap->pm_active, PCPU_GET(cpumask)); 2829 atomic_set_32(&pmap->pm_active, PCPU_GET(cpumask)); 2830 pmap_asid_alloc(pmap); 2831 if (td == curthread) { 2832 PCPU_SET(segbase, pmap->pm_segtab); 2833 MachSetPID(pmap->pm_asid[PCPU_GET(cpuid)].asid); 2834 } 2835 2836 PCPU_SET(curpmap, pmap); 2837 critical_exit(); 2838} 2839 2840void 2841pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 2842{ 2843} 2844 2845/* 2846 * Increase the starting virtual address of the given mapping if a 2847 * different alignment might result in more superpage mappings. 2848 */ 2849void 2850pmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 2851 vm_offset_t *addr, vm_size_t size) 2852{ 2853 vm_offset_t superpage_offset; 2854 2855 if (size < NBSEG) 2856 return; 2857 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 2858 offset += ptoa(object->pg_color); 2859 superpage_offset = offset & SEGOFSET; 2860 if (size - ((NBSEG - superpage_offset) & SEGOFSET) < NBSEG || 2861 (*addr & SEGOFSET) == superpage_offset) 2862 return; 2863 if ((*addr & SEGOFSET) < superpage_offset) 2864 *addr = (*addr & ~SEGOFSET) + superpage_offset; 2865 else 2866 *addr = ((*addr + SEGOFSET) & ~SEGOFSET) + superpage_offset; 2867} 2868 2869/* 2870 * Increase the starting virtual address of the given mapping so 2871 * that it is aligned to not be the second page in a TLB entry. 2872 * This routine assumes that the length is appropriately-sized so 2873 * that the allocation does not share a TLB entry at all if required. 2874 */ 2875void 2876pmap_align_tlb(vm_offset_t *addr) 2877{ 2878 if ((*addr & PAGE_SIZE) == 0) 2879 return; 2880 *addr += PAGE_SIZE; 2881 return; 2882} 2883 2884int pmap_pid_dump(int pid); 2885 2886int 2887pmap_pid_dump(int pid) 2888{ 2889 pmap_t pmap; 2890 struct proc *p; 2891 int npte = 0; 2892 int index; 2893 2894 sx_slock(&allproc_lock); 2895 LIST_FOREACH(p, &allproc, p_list) { 2896 if (p->p_pid != pid) 2897 continue; 2898 2899 if (p->p_vmspace) { 2900 int i, j; 2901 2902 printf("vmspace is %p\n", 2903 p->p_vmspace); 2904 index = 0; 2905 pmap = vmspace_pmap(p->p_vmspace); 2906 printf("pmap asid:%x generation:%x\n", 2907 pmap->pm_asid[0].asid, 2908 pmap->pm_asid[0].gen); 2909 for (i = 0; i < NUSERPGTBLS; i++) { 2910 pd_entry_t *pde; 2911 pt_entry_t *pte; 2912 unsigned base = i << SEGSHIFT; 2913 2914 pde = &pmap->pm_segtab[i]; 2915 if (pde && pmap_pde_v(pde)) { 2916 for (j = 0; j < 1024; j++) { 2917 vm_offset_t va = base + 2918 (j << PAGE_SHIFT); 2919 2920 pte = pmap_pte(pmap, va); 2921 if (pte && pmap_pte_v(pte)) { 2922 vm_offset_t pa; 2923 vm_page_t m; 2924 2925 pa = mips_tlbpfn_to_paddr(*pte); 2926 m = PHYS_TO_VM_PAGE(pa); 2927 printf("va: %p, pt: %p, h: %d, w: %d, f: 0x%x", 2928 (void *)va, 2929 (void *)pa, 2930 m->hold_count, 2931 m->wire_count, 2932 m->flags); 2933 npte++; 2934 index++; 2935 if (index >= 2) { 2936 index = 0; 2937 printf("\n"); 2938 } else { 2939 printf(" "); 2940 } 2941 } 2942 } 2943 } 2944 } 2945 } else { 2946 printf("Process pid:%d has no vm_space\n", pid); 2947 } 2948 break; 2949 } 2950 sx_sunlock(&allproc_lock); 2951 return npte; 2952} 2953 2954 2955#if defined(DEBUG) 2956 2957static void pads(pmap_t pm); 2958void pmap_pvdump(vm_offset_t pa); 2959 2960/* print address space of pmap*/ 2961static void 2962pads(pmap_t pm) 2963{ 2964 unsigned va, i, j; 2965 pt_entry_t *ptep; 2966 2967 if (pm == kernel_pmap) 2968 return; 2969 for (i = 0; i < NPTEPG; i++) 2970 if (pm->pm_segtab[i]) 2971 for (j = 0; j < NPTEPG; j++) { 2972 va = (i << SEGSHIFT) + (j << PAGE_SHIFT); 2973 if (pm == kernel_pmap && va < KERNBASE) 2974 continue; 2975 if (pm != kernel_pmap && 2976 va >= VM_MAXUSER_ADDRESS) 2977 continue; 2978 ptep = pmap_pte(pm, va); 2979 if (pmap_pte_v(ptep)) 2980 printf("%x:%x ", va, *(int *)ptep); 2981 } 2982 2983} 2984 2985void 2986pmap_pvdump(vm_offset_t pa) 2987{ 2988 register pv_entry_t pv; 2989 vm_page_t m; 2990 2991 printf("pa %x", pa); 2992 m = PHYS_TO_VM_PAGE(pa); 2993 for (pv = TAILQ_FIRST(&m->md.pv_list); pv; 2994 pv = TAILQ_NEXT(pv, pv_list)) { 2995 printf(" -> pmap %p, va %x", (void *)pv->pv_pmap, pv->pv_va); 2996 pads(pv->pv_pmap); 2997 } 2998 printf(" "); 2999} 3000 3001/* N/C */ 3002#endif 3003 3004 3005/* 3006 * Allocate TLB address space tag (called ASID or TLBPID) and return it. 3007 * It takes almost as much or more time to search the TLB for a 3008 * specific ASID and flush those entries as it does to flush the entire TLB. 3009 * Therefore, when we allocate a new ASID, we just take the next number. When 3010 * we run out of numbers, we flush the TLB, increment the generation count 3011 * and start over. ASID zero is reserved for kernel use. 3012 */ 3013static void 3014pmap_asid_alloc(pmap) 3015 pmap_t pmap; 3016{ 3017 if (pmap->pm_asid[PCPU_GET(cpuid)].asid != PMAP_ASID_RESERVED && 3018 pmap->pm_asid[PCPU_GET(cpuid)].gen == PCPU_GET(asid_generation)); 3019 else { 3020 if (PCPU_GET(next_asid) == pmap_max_asid) { 3021 MIPS_TBIAP(); 3022 PCPU_SET(asid_generation, 3023 (PCPU_GET(asid_generation) + 1) & ASIDGEN_MASK); 3024 if (PCPU_GET(asid_generation) == 0) { 3025 PCPU_SET(asid_generation, 1); 3026 } 3027 PCPU_SET(next_asid, 1); /* 0 means invalid */ 3028 } 3029 pmap->pm_asid[PCPU_GET(cpuid)].asid = PCPU_GET(next_asid); 3030 pmap->pm_asid[PCPU_GET(cpuid)].gen = PCPU_GET(asid_generation); 3031 PCPU_SET(next_asid, PCPU_GET(next_asid) + 1); 3032 } 3033} 3034 3035int 3036page_is_managed(vm_offset_t pa) 3037{ 3038 vm_offset_t pgnum = mips_btop(pa); 3039 3040 if (pgnum >= first_page) { 3041 vm_page_t m; 3042 3043 m = PHYS_TO_VM_PAGE(pa); 3044 if (m == NULL) 3045 return 0; 3046 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) 3047 return 1; 3048 } 3049 return 0; 3050} 3051 3052static int 3053init_pte_prot(vm_offset_t va, vm_page_t m, vm_prot_t prot) 3054{ 3055 int rw = 0; 3056 3057 if (!(prot & VM_PROT_WRITE)) 3058 rw = PTE_ROPAGE; 3059 else { 3060 if (va >= VM_MIN_KERNEL_ADDRESS) { 3061 /* 3062 * Don't bother to trap on kernel writes, just 3063 * record page as dirty. 3064 */ 3065 rw = PTE_RWPAGE; 3066 vm_page_dirty(m); 3067 } else if ((m->md.pv_flags & PV_TABLE_MOD) || 3068 m->dirty == VM_PAGE_BITS_ALL) 3069 rw = PTE_RWPAGE; 3070 else 3071 rw = PTE_CWPAGE; 3072 vm_page_flag_set(m, PG_WRITEABLE); 3073 } 3074 return rw; 3075} 3076 3077/* 3078 * pmap_set_modified: 3079 * 3080 * Sets the page modified and reference bits for the specified page. 3081 */ 3082void 3083pmap_set_modified(vm_offset_t pa) 3084{ 3085 3086 PHYS_TO_VM_PAGE(pa)->md.pv_flags |= (PV_TABLE_REF | PV_TABLE_MOD); 3087} 3088 3089/* 3090 * Routine: pmap_kextract 3091 * Function: 3092 * Extract the physical page address associated 3093 * virtual address. 3094 */ 3095 /* PMAP_INLINE */ vm_offset_t 3096pmap_kextract(vm_offset_t va) 3097{ 3098 vm_offset_t pa = 0; 3099 3100 if (va < MIPS_KSEG0_START) { 3101 /* user virtual address */ 3102 pt_entry_t *ptep; 3103 3104 if (curproc && curproc->p_vmspace) { 3105 ptep = pmap_pte(&curproc->p_vmspace->vm_pmap, va); 3106 if (ptep) 3107 pa = mips_tlbpfn_to_paddr(*ptep) | 3108 (va & PAGE_MASK); 3109 } 3110 } else if (va >= MIPS_KSEG0_START && 3111 va < MIPS_KSEG1_START) 3112 pa = MIPS_KSEG0_TO_PHYS(va); 3113 else if (va >= MIPS_KSEG1_START && 3114 va < MIPS_KSEG2_START) 3115 pa = MIPS_KSEG1_TO_PHYS(va); 3116 else if (va >= MIPS_KSEG2_START && va < VM_MAX_KERNEL_ADDRESS) { 3117 pt_entry_t *ptep; 3118 3119 /* Is the kernel pmap initialized? */ 3120 if (kernel_pmap->pm_active) { 3121 /* Its inside the virtual address range */ 3122 ptep = pmap_pte(kernel_pmap, va); 3123 if (ptep) 3124 pa = mips_tlbpfn_to_paddr(*ptep) | 3125 (va & PAGE_MASK); 3126 } 3127 } 3128 return pa; 3129} 3130 3131void 3132pmap_flush_pvcache(vm_page_t m) 3133{ 3134 pv_entry_t pv; 3135 3136 if (m != NULL) { 3137 for (pv = TAILQ_FIRST(&m->md.pv_list); pv; 3138 pv = TAILQ_NEXT(pv, pv_list)) { 3139 mips_dcache_wbinv_range_index(pv->pv_va, PAGE_SIZE); 3140 } 3141 } 3142} 3143 3144void 3145pmap_save_tlb(void) 3146{ 3147 int tlbno, cpu; 3148 3149 cpu = PCPU_GET(cpuid); 3150 3151 for (tlbno = 0; tlbno < num_tlbentries; ++tlbno) 3152 MachTLBRead(tlbno, &tlbstash[cpu][tlbno]); 3153} 3154 3155#ifdef DDB 3156#include <ddb/ddb.h> 3157 3158DB_SHOW_COMMAND(tlb, ddb_dump_tlb) 3159{ 3160 int cpu, tlbno; 3161 struct tlb *tlb; 3162 3163 if (have_addr) 3164 cpu = ((addr >> 4) % 16) * 10 + (addr % 16); 3165 else 3166 cpu = PCPU_GET(cpuid); 3167 3168 if (cpu < 0 || cpu >= mp_ncpus) { 3169 db_printf("Invalid CPU %d\n", cpu); 3170 return; 3171 } else 3172 db_printf("CPU %d:\n", cpu); 3173 3174 if (cpu == PCPU_GET(cpuid)) 3175 pmap_save_tlb(); 3176 3177 for (tlbno = 0; tlbno < num_tlbentries; ++tlbno) { 3178 tlb = &tlbstash[cpu][tlbno]; 3179 if (tlb->tlb_lo0 & PTE_V || tlb->tlb_lo1 & PTE_V) { 3180 printf("TLB %2d vad 0x%0lx ", 3181 tlbno, (long)(tlb->tlb_hi & 0xffffff00)); 3182 } else { 3183 printf("TLB*%2d vad 0x%0lx ", 3184 tlbno, (long)(tlb->tlb_hi & 0xffffff00)); 3185 } 3186 printf("0=0x%0lx ", pfn_to_vad((long)tlb->tlb_lo0)); 3187 printf("%c", tlb->tlb_lo0 & PTE_V ? 'V' : '-'); 3188 printf("%c", tlb->tlb_lo0 & PTE_M ? 'M' : '-'); 3189 printf("%c", tlb->tlb_lo0 & PTE_G ? 'G' : '-'); 3190 printf(" atr %x ", (tlb->tlb_lo0 >> 3) & 7); 3191 printf("1=0x%0lx ", pfn_to_vad((long)tlb->tlb_lo1)); 3192 printf("%c", tlb->tlb_lo1 & PTE_V ? 'V' : '-'); 3193 printf("%c", tlb->tlb_lo1 & PTE_M ? 'M' : '-'); 3194 printf("%c", tlb->tlb_lo1 & PTE_G ? 'G' : '-'); 3195 printf(" atr %x ", (tlb->tlb_lo1 >> 3) & 7); 3196 printf(" sz=%x pid=%x\n", tlb->tlb_mask, 3197 (tlb->tlb_hi & 0x000000ff)); 3198 } 3199} 3200#endif /* DDB */ 3201