pmap.c revision 208574
1/* 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * Copyright (c) 1994 John S. Dyson 5 * All rights reserved. 6 * Copyright (c) 1994 David Greenman 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * the Systems Programming Group of the University of Utah Computer 11 * Science Department and William Jolitz of UUNET Technologies Inc. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 38 * from: src/sys/i386/i386/pmap.c,v 1.250.2.8 2000/11/21 00:09:14 ps 39 * JNPR: pmap.c,v 1.11.2.1 2007/08/16 11:51:06 girish 40 */ 41 42/* 43 * Manages physical address maps. 44 * 45 * In addition to hardware address maps, this 46 * module is called upon to provide software-use-only 47 * maps which may or may not be stored in the same 48 * form as hardware maps. These pseudo-maps are 49 * used to store intermediate results from copy 50 * operations to and from address spaces. 51 * 52 * Since the information managed by this module is 53 * also stored by the logical address mapping module, 54 * this module may throw away valid virtual-to-physical 55 * mappings at almost any time. However, invalidations 56 * of virtual-to-physical mappings must be done as 57 * requested. 58 * 59 * In order to cope with hardware architectures which 60 * make virtual-to-physical map invalidates expensive, 61 * this module may delay invalidate or reduced protection 62 * operations until such time as they are actually 63 * necessary. This module is given full information as 64 * to which processors are currently using which maps, 65 * and to when physical maps must be made correct. 66 */ 67 68#include <sys/cdefs.h> 69__FBSDID("$FreeBSD: head/sys/mips/mips/pmap.c 208574 2010-05-26 18:00:44Z alc $"); 70 71#include "opt_ddb.h" 72#include "opt_msgbuf.h" 73#include <sys/param.h> 74#include <sys/systm.h> 75#include <sys/proc.h> 76#include <sys/msgbuf.h> 77#include <sys/vmmeter.h> 78#include <sys/mman.h> 79#include <sys/smp.h> 80 81#include <vm/vm.h> 82#include <vm/vm_param.h> 83#include <vm/vm_phys.h> 84#include <sys/lock.h> 85#include <sys/mutex.h> 86#include <vm/vm_kern.h> 87#include <vm/vm_page.h> 88#include <vm/vm_map.h> 89#include <vm/vm_object.h> 90#include <vm/vm_extern.h> 91#include <vm/vm_pageout.h> 92#include <vm/vm_pager.h> 93#include <vm/uma.h> 94#include <sys/pcpu.h> 95#include <sys/sched.h> 96#ifdef SMP 97#include <sys/smp.h> 98#endif 99 100#include <machine/cache.h> 101#include <machine/md_var.h> 102 103#if defined(DIAGNOSTIC) 104#define PMAP_DIAGNOSTIC 105#endif 106 107#undef PMAP_DEBUG 108 109#ifndef PMAP_SHPGPERPROC 110#define PMAP_SHPGPERPROC 200 111#endif 112 113#if !defined(PMAP_DIAGNOSTIC) 114#define PMAP_INLINE __inline 115#else 116#define PMAP_INLINE 117#endif 118 119/* 120 * Get PDEs and PTEs for user/kernel address space 121 */ 122#define pmap_pde(m, v) (&((m)->pm_segtab[(vm_offset_t)(v) >> SEGSHIFT])) 123#define segtab_pde(m, v) (m[(vm_offset_t)(v) >> SEGSHIFT]) 124 125#define pmap_pte_w(pte) ((*(int *)pte & PTE_W) != 0) 126#define pmap_pde_v(pte) ((*(int *)pte) != 0) 127#define pmap_pte_m(pte) ((*(int *)pte & PTE_M) != 0) 128#define pmap_pte_v(pte) ((*(int *)pte & PTE_V) != 0) 129 130#define pmap_pte_set_w(pte, v) ((v)?(*(int *)pte |= PTE_W):(*(int *)pte &= ~PTE_W)) 131#define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v))) 132 133#define MIPS_SEGSIZE (1L << SEGSHIFT) 134#define mips_segtrunc(va) ((va) & ~(MIPS_SEGSIZE-1)) 135#define pmap_TLB_invalidate_all() MIPS_TBIAP() 136#define pmap_va_asid(pmap, va) ((va) | ((pmap)->pm_asid[PCPU_GET(cpuid)].asid << VMTLB_PID_SHIFT)) 137#define is_kernel_pmap(x) ((x) == kernel_pmap) 138 139struct pmap kernel_pmap_store; 140pd_entry_t *kernel_segmap; 141 142vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 143vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 144 145static int nkpt; 146unsigned pmap_max_asid; /* max ASID supported by the system */ 147 148 149#define PMAP_ASID_RESERVED 0 150 151vm_offset_t kernel_vm_end; 152 153static struct tlb tlbstash[MAXCPU][MIPS_MAX_TLB_ENTRIES]; 154 155static void pmap_asid_alloc(pmap_t pmap); 156 157/* 158 * Data for the pv entry allocation mechanism 159 */ 160static uma_zone_t pvzone; 161static struct vm_object pvzone_obj; 162static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 163 164static PMAP_INLINE void free_pv_entry(pv_entry_t pv); 165static pv_entry_t get_pv_entry(pmap_t locked_pmap); 166static __inline void pmap_changebit(vm_page_t m, int bit, boolean_t setem); 167 168static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, 169 vm_page_t m, vm_prot_t prot, vm_page_t mpte); 170static int pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va); 171static void pmap_remove_page(struct pmap *pmap, vm_offset_t va); 172static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, vm_offset_t va); 173static boolean_t pmap_testbit(vm_page_t m, int bit); 174static void 175pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t mpte, 176 vm_page_t m, boolean_t wired); 177static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_page_t mpte, 178 vm_offset_t va, vm_page_t m); 179 180static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags); 181 182static vm_page_t _pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags); 183static int pmap_unuse_pt(pmap_t, vm_offset_t, vm_page_t); 184static int init_pte_prot(vm_offset_t va, vm_page_t m, vm_prot_t prot); 185static void pmap_TLB_invalidate_kernel(vm_offset_t); 186static void pmap_TLB_update_kernel(vm_offset_t, pt_entry_t); 187static vm_page_t pmap_alloc_pte_page(pmap_t, unsigned int, int, vm_offset_t *); 188static void pmap_release_pte_page(vm_page_t); 189 190#ifdef SMP 191static void pmap_invalidate_page_action(void *arg); 192static void pmap_invalidate_all_action(void *arg); 193static void pmap_update_page_action(void *arg); 194#endif 195 196static void pmap_ptpgzone_dtor(void *mem, int size, void *arg); 197static void *pmap_ptpgzone_allocf(uma_zone_t, int, u_int8_t *, int); 198static uma_zone_t ptpgzone; 199 200struct local_sysmaps { 201 struct mtx lock; 202 vm_offset_t base; 203 uint16_t valid1, valid2; 204}; 205 206/* This structure is for large memory 207 * above 512Meg. We can't (in 32 bit mode) 208 * just use the direct mapped MIPS_KSEG0_TO_PHYS() 209 * macros since we can't see the memory and must 210 * map it in when we need to access it. In 64 211 * bit mode this goes away. 212 */ 213static struct local_sysmaps sysmap_lmem[MAXCPU]; 214caddr_t virtual_sys_start = (caddr_t)0; 215 216#define PMAP_LMEM_MAP1(va, phys) \ 217 int cpu; \ 218 struct local_sysmaps *sysm; \ 219 pt_entry_t *pte, npte; \ 220 \ 221 cpu = PCPU_GET(cpuid); \ 222 sysm = &sysmap_lmem[cpu]; \ 223 PMAP_LGMEM_LOCK(sysm); \ 224 intr = intr_disable(); \ 225 sched_pin(); \ 226 va = sysm->base; \ 227 npte = mips_paddr_to_tlbpfn(phys) | \ 228 PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; \ 229 pte = pmap_pte(kernel_pmap, va); \ 230 *pte = npte; \ 231 sysm->valid1 = 1; 232 233#define PMAP_LMEM_MAP2(va1, phys1, va2, phys2) \ 234 int cpu; \ 235 struct local_sysmaps *sysm; \ 236 pt_entry_t *pte, npte; \ 237 \ 238 cpu = PCPU_GET(cpuid); \ 239 sysm = &sysmap_lmem[cpu]; \ 240 PMAP_LGMEM_LOCK(sysm); \ 241 intr = intr_disable(); \ 242 sched_pin(); \ 243 va1 = sysm->base; \ 244 va2 = sysm->base + PAGE_SIZE; \ 245 npte = mips_paddr_to_tlbpfn(phys1) | \ 246 PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; \ 247 pte = pmap_pte(kernel_pmap, va1); \ 248 *pte = npte; \ 249 npte = mips_paddr_to_tlbpfn(phys2) | \ 250 PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; \ 251 pte = pmap_pte(kernel_pmap, va2); \ 252 *pte = npte; \ 253 sysm->valid1 = 1; \ 254 sysm->valid2 = 1; 255 256#define PMAP_LMEM_UNMAP() \ 257 pte = pmap_pte(kernel_pmap, sysm->base); \ 258 *pte = PTE_G; \ 259 pmap_TLB_invalidate_kernel(sysm->base); \ 260 sysm->valid1 = 0; \ 261 pte = pmap_pte(kernel_pmap, sysm->base + PAGE_SIZE); \ 262 *pte = PTE_G; \ 263 pmap_TLB_invalidate_kernel(sysm->base + PAGE_SIZE); \ 264 sysm->valid2 = 0; \ 265 sched_unpin(); \ 266 intr_restore(intr); \ 267 PMAP_LGMEM_UNLOCK(sysm); 268 269pd_entry_t 270pmap_segmap(pmap_t pmap, vm_offset_t va) 271{ 272 if (pmap->pm_segtab) 273 return (pmap->pm_segtab[((vm_offset_t)(va) >> SEGSHIFT)]); 274 else 275 return ((pd_entry_t)0); 276} 277 278/* 279 * Routine: pmap_pte 280 * Function: 281 * Extract the page table entry associated 282 * with the given map/virtual_address pair. 283 */ 284pt_entry_t * 285pmap_pte(pmap_t pmap, vm_offset_t va) 286{ 287 pt_entry_t *pdeaddr; 288 289 if (pmap) { 290 pdeaddr = (pt_entry_t *)pmap_segmap(pmap, va); 291 if (pdeaddr) { 292 return pdeaddr + vad_to_pte_offset(va); 293 } 294 } 295 return ((pt_entry_t *)0); 296} 297 298 299vm_offset_t 300pmap_steal_memory(vm_size_t size) 301{ 302 vm_size_t bank_size; 303 vm_offset_t pa, va; 304 305 size = round_page(size); 306 307 bank_size = phys_avail[1] - phys_avail[0]; 308 while (size > bank_size) { 309 int i; 310 311 for (i = 0; phys_avail[i + 2]; i += 2) { 312 phys_avail[i] = phys_avail[i + 2]; 313 phys_avail[i + 1] = phys_avail[i + 3]; 314 } 315 phys_avail[i] = 0; 316 phys_avail[i + 1] = 0; 317 if (!phys_avail[0]) 318 panic("pmap_steal_memory: out of memory"); 319 bank_size = phys_avail[1] - phys_avail[0]; 320 } 321 322 pa = phys_avail[0]; 323 phys_avail[0] += size; 324 if (pa >= MIPS_KSEG0_LARGEST_PHYS) { 325 panic("Out of memory below 512Meg?"); 326 } 327 va = MIPS_PHYS_TO_KSEG0(pa); 328 bzero((caddr_t)va, size); 329 return va; 330} 331 332/* 333 * Bootstrap the system enough to run with virtual memory. This 334 * assumes that the phys_avail array has been initialized. 335 */ 336void 337pmap_bootstrap(void) 338{ 339 pt_entry_t *pgtab; 340 pt_entry_t *pte; 341 int i, j; 342 int memory_larger_than_512meg = 0; 343 344 /* Sort. */ 345again: 346 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 347 /* 348 * Keep the memory aligned on page boundary. 349 */ 350 phys_avail[i] = round_page(phys_avail[i]); 351 phys_avail[i + 1] = trunc_page(phys_avail[i + 1]); 352 353 if (phys_avail[i + 1] >= MIPS_KSEG0_LARGEST_PHYS) 354 memory_larger_than_512meg++; 355 if (i < 2) 356 continue; 357 if (phys_avail[i - 2] > phys_avail[i]) { 358 vm_paddr_t ptemp[2]; 359 360 361 ptemp[0] = phys_avail[i + 0]; 362 ptemp[1] = phys_avail[i + 1]; 363 364 phys_avail[i + 0] = phys_avail[i - 2]; 365 phys_avail[i + 1] = phys_avail[i - 1]; 366 367 phys_avail[i - 2] = ptemp[0]; 368 phys_avail[i - 1] = ptemp[1]; 369 goto again; 370 } 371 } 372 373 /* 374 * Copy the phys_avail[] array before we start stealing memory from it. 375 */ 376 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 377 physmem_desc[i] = phys_avail[i]; 378 physmem_desc[i + 1] = phys_avail[i + 1]; 379 } 380 381 Maxmem = atop(phys_avail[i - 1]); 382 383 if (bootverbose) { 384 printf("Physical memory chunk(s):\n"); 385 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 386 vm_paddr_t size; 387 388 size = phys_avail[i + 1] - phys_avail[i]; 389 printf("%#08jx - %#08jx, %ju bytes (%ju pages)\n", 390 (uintmax_t) phys_avail[i], 391 (uintmax_t) phys_avail[i + 1] - 1, 392 (uintmax_t) size, (uintmax_t) size / PAGE_SIZE); 393 } 394 printf("Maxmem is 0x%0lx\n", ptoa(Maxmem)); 395 } 396 /* 397 * Steal the message buffer from the beginning of memory. 398 */ 399 msgbufp = (struct msgbuf *)pmap_steal_memory(MSGBUF_SIZE); 400 msgbufinit(msgbufp, MSGBUF_SIZE); 401 402 /* 403 * Steal thread0 kstack. 404 */ 405 kstack0 = pmap_steal_memory(KSTACK_PAGES << PAGE_SHIFT); 406 407 408 virtual_avail = VM_MIN_KERNEL_ADDRESS; 409 virtual_end = VM_MAX_KERNEL_ADDRESS; 410 411#ifdef SMP 412 /* 413 * Steal some virtual address space to map the pcpu area. 414 */ 415 virtual_avail = roundup2(virtual_avail, PAGE_SIZE * 2); 416 pcpup = (struct pcpu *)virtual_avail; 417 virtual_avail += PAGE_SIZE * 2; 418 419 /* 420 * Initialize the wired TLB entry mapping the pcpu region for 421 * the BSP at 'pcpup'. Up until this point we were operating 422 * with the 'pcpup' for the BSP pointing to a virtual address 423 * in KSEG0 so there was no need for a TLB mapping. 424 */ 425 mips_pcpu_tlb_init(PCPU_ADDR(0)); 426 427 if (bootverbose) 428 printf("pcpu is available at virtual address %p.\n", pcpup); 429#endif 430 431 /* 432 * Steal some virtual space that will not be in kernel_segmap. This 433 * va memory space will be used to map in kernel pages that are 434 * outside the 512Meg region. Note that we only do this steal when 435 * we do have memory in this region, that way for systems with 436 * smaller memory we don't "steal" any va ranges :-) 437 */ 438 if (memory_larger_than_512meg) { 439 for (i = 0; i < MAXCPU; i++) { 440 sysmap_lmem[i].base = virtual_avail; 441 virtual_avail += PAGE_SIZE * 2; 442 sysmap_lmem[i].valid1 = sysmap_lmem[i].valid2 = 0; 443 PMAP_LGMEM_LOCK_INIT(&sysmap_lmem[i]); 444 } 445 } 446 virtual_sys_start = (caddr_t)virtual_avail; 447 /* 448 * Allocate segment table for the kernel 449 */ 450 kernel_segmap = (pd_entry_t *)pmap_steal_memory(PAGE_SIZE); 451 452 /* 453 * Allocate second level page tables for the kernel 454 */ 455 nkpt = NKPT; 456 if (memory_larger_than_512meg) { 457 /* 458 * If we have a large memory system we CANNOT afford to hit 459 * pmap_growkernel() and allocate memory. Since we MAY end 460 * up with a page that is NOT mappable. For that reason we 461 * up front grab more. Normall NKPT is 120 (YMMV see pmap.h) 462 * this gives us 480meg of kernel virtual addresses at the 463 * cost of 120 pages (each page gets us 4 Meg). Since the 464 * kernel starts at virtual_avail, we can use this to 465 * calculate how many entris are left from there to the end 466 * of the segmap, we want to allocate all of it, which would 467 * be somewhere above 0xC0000000 - 0xFFFFFFFF which results 468 * in about 256 entries or so instead of the 120. 469 */ 470 nkpt = (PAGE_SIZE / sizeof(pd_entry_t)) - (virtual_avail >> SEGSHIFT); 471 } 472 pgtab = (pt_entry_t *)pmap_steal_memory(PAGE_SIZE * nkpt); 473 474 /* 475 * The R[4-7]?00 stores only one copy of the Global bit in the 476 * translation lookaside buffer for each 2 page entry. Thus invalid 477 * entrys must have the Global bit set so when Entry LO and Entry HI 478 * G bits are anded together they will produce a global bit to store 479 * in the tlb. 480 */ 481 for (i = 0, pte = pgtab; i < (nkpt * NPTEPG); i++, pte++) 482 *pte = PTE_G; 483 484 /* 485 * The segment table contains the KVA of the pages in the second 486 * level page table. 487 */ 488 for (i = 0, j = (virtual_avail >> SEGSHIFT); i < nkpt; i++, j++) 489 kernel_segmap[j] = (pd_entry_t)(pgtab + (i * NPTEPG)); 490 491 /* 492 * The kernel's pmap is statically allocated so we don't have to use 493 * pmap_create, which is unlikely to work correctly at this part of 494 * the boot sequence (XXX and which no longer exists). 495 */ 496 PMAP_LOCK_INIT(kernel_pmap); 497 kernel_pmap->pm_segtab = kernel_segmap; 498 kernel_pmap->pm_active = ~0; 499 TAILQ_INIT(&kernel_pmap->pm_pvlist); 500 kernel_pmap->pm_asid[0].asid = PMAP_ASID_RESERVED; 501 kernel_pmap->pm_asid[0].gen = 0; 502 pmap_max_asid = VMNUM_PIDS; 503 MachSetPID(0); 504} 505 506/* 507 * Initialize a vm_page's machine-dependent fields. 508 */ 509void 510pmap_page_init(vm_page_t m) 511{ 512 513 TAILQ_INIT(&m->md.pv_list); 514 m->md.pv_list_count = 0; 515 m->md.pv_flags = 0; 516} 517 518/* 519 * Initialize the pmap module. 520 * Called by vm_init, to initialize any structures that the pmap 521 * system needs to map virtual memory. 522 * pmap_init has been enhanced to support in a fairly consistant 523 * way, discontiguous physical memory. 524 */ 525void 526pmap_init(void) 527{ 528 529 /* 530 * Initialize the address space (zone) for the pv entries. Set a 531 * high water mark so that the system can recover from excessive 532 * numbers of pv entries. 533 */ 534 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL, 535 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 536 pv_entry_max = PMAP_SHPGPERPROC * maxproc + cnt.v_page_count; 537 pv_entry_high_water = 9 * (pv_entry_max / 10); 538 uma_zone_set_obj(pvzone, &pvzone_obj, pv_entry_max); 539 540 ptpgzone = uma_zcreate("PT ENTRY", PAGE_SIZE, NULL, pmap_ptpgzone_dtor, 541 NULL, NULL, PAGE_SIZE - 1, UMA_ZONE_NOFREE | UMA_ZONE_ZINIT); 542 uma_zone_set_allocf(ptpgzone, pmap_ptpgzone_allocf); 543} 544 545/*************************************************** 546 * Low level helper routines..... 547 ***************************************************/ 548 549#if defined(PMAP_DIAGNOSTIC) 550 551/* 552 * This code checks for non-writeable/modified pages. 553 * This should be an invalid condition. 554 */ 555static int 556pmap_nw_modified(pt_entry_t pte) 557{ 558 if ((pte & (PTE_M | PTE_RO)) == (PTE_M | PTE_RO)) 559 return (1); 560 else 561 return (0); 562} 563 564#endif 565 566static void 567pmap_invalidate_all(pmap_t pmap) 568{ 569#ifdef SMP 570 smp_rendezvous(0, pmap_invalidate_all_action, 0, (void *)pmap); 571} 572 573static void 574pmap_invalidate_all_action(void *arg) 575{ 576 pmap_t pmap = (pmap_t)arg; 577 578#endif 579 580 if (pmap->pm_active & PCPU_GET(cpumask)) { 581 pmap_TLB_invalidate_all(); 582 } else 583 pmap->pm_asid[PCPU_GET(cpuid)].gen = 0; 584} 585 586struct pmap_invalidate_page_arg { 587 pmap_t pmap; 588 vm_offset_t va; 589}; 590 591static __inline void 592pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 593{ 594#ifdef SMP 595 struct pmap_invalidate_page_arg arg; 596 597 arg.pmap = pmap; 598 arg.va = va; 599 600 smp_rendezvous(0, pmap_invalidate_page_action, 0, (void *)&arg); 601} 602 603static void 604pmap_invalidate_page_action(void *arg) 605{ 606 pmap_t pmap = ((struct pmap_invalidate_page_arg *)arg)->pmap; 607 vm_offset_t va = ((struct pmap_invalidate_page_arg *)arg)->va; 608 609#endif 610 611 if (is_kernel_pmap(pmap)) { 612 pmap_TLB_invalidate_kernel(va); 613 return; 614 } 615 if (pmap->pm_asid[PCPU_GET(cpuid)].gen != PCPU_GET(asid_generation)) 616 return; 617 else if (!(pmap->pm_active & PCPU_GET(cpumask))) { 618 pmap->pm_asid[PCPU_GET(cpuid)].gen = 0; 619 return; 620 } 621 va = pmap_va_asid(pmap, (va & ~PAGE_MASK)); 622 mips_TBIS(va); 623} 624 625static void 626pmap_TLB_invalidate_kernel(vm_offset_t va) 627{ 628 u_int32_t pid; 629 630 MachTLBGetPID(pid); 631 va = va | (pid << VMTLB_PID_SHIFT); 632 mips_TBIS(va); 633} 634 635struct pmap_update_page_arg { 636 pmap_t pmap; 637 vm_offset_t va; 638 pt_entry_t pte; 639}; 640 641void 642pmap_update_page(pmap_t pmap, vm_offset_t va, pt_entry_t pte) 643{ 644#ifdef SMP 645 struct pmap_update_page_arg arg; 646 647 arg.pmap = pmap; 648 arg.va = va; 649 arg.pte = pte; 650 651 smp_rendezvous(0, pmap_update_page_action, 0, (void *)&arg); 652} 653 654static void 655pmap_update_page_action(void *arg) 656{ 657 pmap_t pmap = ((struct pmap_update_page_arg *)arg)->pmap; 658 vm_offset_t va = ((struct pmap_update_page_arg *)arg)->va; 659 pt_entry_t pte = ((struct pmap_update_page_arg *)arg)->pte; 660 661#endif 662 if (is_kernel_pmap(pmap)) { 663 pmap_TLB_update_kernel(va, pte); 664 return; 665 } 666 if (pmap->pm_asid[PCPU_GET(cpuid)].gen != PCPU_GET(asid_generation)) 667 return; 668 else if (!(pmap->pm_active & PCPU_GET(cpumask))) { 669 pmap->pm_asid[PCPU_GET(cpuid)].gen = 0; 670 return; 671 } 672 va = pmap_va_asid(pmap, (va & ~PAGE_MASK)); 673 MachTLBUpdate(va, pte); 674} 675 676static void 677pmap_TLB_update_kernel(vm_offset_t va, pt_entry_t pte) 678{ 679 u_int32_t pid; 680 681 va &= ~PAGE_MASK; 682 683 MachTLBGetPID(pid); 684 va = va | (pid << VMTLB_PID_SHIFT); 685 686 MachTLBUpdate(va, pte); 687} 688 689/* 690 * Routine: pmap_extract 691 * Function: 692 * Extract the physical page address associated 693 * with the given map/virtual_address pair. 694 */ 695vm_paddr_t 696pmap_extract(pmap_t pmap, vm_offset_t va) 697{ 698 pt_entry_t *pte; 699 vm_offset_t retval = 0; 700 701 PMAP_LOCK(pmap); 702 pte = pmap_pte(pmap, va); 703 if (pte) { 704 retval = mips_tlbpfn_to_paddr(*pte) | (va & PAGE_MASK); 705 } 706 PMAP_UNLOCK(pmap); 707 return retval; 708} 709 710/* 711 * Routine: pmap_extract_and_hold 712 * Function: 713 * Atomically extract and hold the physical page 714 * with the given pmap and virtual address pair 715 * if that mapping permits the given protection. 716 */ 717vm_page_t 718pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 719{ 720 pt_entry_t pte; 721 vm_page_t m; 722 vm_paddr_t pa; 723 724 m = NULL; 725 pa = 0; 726 PMAP_LOCK(pmap); 727retry: 728 pte = *pmap_pte(pmap, va); 729 if (pte != 0 && pmap_pte_v(&pte) && 730 ((pte & PTE_RW) || (prot & VM_PROT_WRITE) == 0)) { 731 if (vm_page_pa_tryrelock(pmap, mips_tlbpfn_to_paddr(pte), &pa)) 732 goto retry; 733 734 m = PHYS_TO_VM_PAGE(mips_tlbpfn_to_paddr(pte)); 735 vm_page_hold(m); 736 } 737 PA_UNLOCK_COND(pa); 738 PMAP_UNLOCK(pmap); 739 return (m); 740} 741 742/*************************************************** 743 * Low level mapping routines..... 744 ***************************************************/ 745 746/* 747 * add a wired page to the kva 748 */ 749 /* PMAP_INLINE */ void 750pmap_kenter(vm_offset_t va, vm_paddr_t pa) 751{ 752 register pt_entry_t *pte; 753 pt_entry_t npte, opte; 754 755#ifdef PMAP_DEBUG 756 printf("pmap_kenter: va: 0x%08x -> pa: 0x%08x\n", va, pa); 757#endif 758 npte = mips_paddr_to_tlbpfn(pa) | PTE_RW | PTE_V | PTE_G | PTE_W; 759 760 if (is_cacheable_mem(pa)) 761 npte |= PTE_CACHE; 762 else 763 npte |= PTE_UNCACHED; 764 765 pte = pmap_pte(kernel_pmap, va); 766 opte = *pte; 767 *pte = npte; 768 769 pmap_update_page(kernel_pmap, va, npte); 770} 771 772/* 773 * remove a page from the kernel pagetables 774 */ 775 /* PMAP_INLINE */ void 776pmap_kremove(vm_offset_t va) 777{ 778 register pt_entry_t *pte; 779 780 /* 781 * Write back all caches from the page being destroyed 782 */ 783 mips_dcache_wbinv_range_index(va, PAGE_SIZE); 784 785 pte = pmap_pte(kernel_pmap, va); 786 *pte = PTE_G; 787 pmap_invalidate_page(kernel_pmap, va); 788} 789 790/* 791 * Used to map a range of physical addresses into kernel 792 * virtual address space. 793 * 794 * The value passed in '*virt' is a suggested virtual address for 795 * the mapping. Architectures which can support a direct-mapped 796 * physical to virtual region can return the appropriate address 797 * within that region, leaving '*virt' unchanged. Other 798 * architectures should map the pages starting at '*virt' and 799 * update '*virt' with the first usable address after the mapped 800 * region. 801 */ 802vm_offset_t 803pmap_map(vm_offset_t *virt, vm_offset_t start, vm_offset_t end, int prot) 804{ 805 vm_offset_t va, sva; 806 807 va = sva = *virt; 808 while (start < end) { 809 pmap_kenter(va, start); 810 va += PAGE_SIZE; 811 start += PAGE_SIZE; 812 } 813 *virt = va; 814 return (sva); 815} 816 817/* 818 * Add a list of wired pages to the kva 819 * this routine is only used for temporary 820 * kernel mappings that do not need to have 821 * page modification or references recorded. 822 * Note that old mappings are simply written 823 * over. The page *must* be wired. 824 */ 825void 826pmap_qenter(vm_offset_t va, vm_page_t *m, int count) 827{ 828 int i; 829 vm_offset_t origva = va; 830 831 for (i = 0; i < count; i++) { 832 pmap_flush_pvcache(m[i]); 833 pmap_kenter(va, VM_PAGE_TO_PHYS(m[i])); 834 va += PAGE_SIZE; 835 } 836 837 mips_dcache_wbinv_range_index(origva, PAGE_SIZE*count); 838} 839 840/* 841 * this routine jerks page mappings from the 842 * kernel -- it is meant only for temporary mappings. 843 */ 844void 845pmap_qremove(vm_offset_t va, int count) 846{ 847 /* 848 * No need to wb/inv caches here, 849 * pmap_kremove will do it for us 850 */ 851 852 while (count-- > 0) { 853 pmap_kremove(va); 854 va += PAGE_SIZE; 855 } 856} 857 858/*************************************************** 859 * Page table page management routines..... 860 ***************************************************/ 861 862/* Revision 1.507 863 * 864 * Simplify the reference counting of page table pages. Specifically, use 865 * the page table page's wired count rather than its hold count to contain 866 * the reference count. 867 */ 868 869/* 870 * This routine unholds page table pages, and if the hold count 871 * drops to zero, then it decrements the wire count. 872 */ 873static int 874_pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m) 875{ 876 877 /* 878 * unmap the page table page 879 */ 880 pmap->pm_segtab[m->pindex] = 0; 881 --pmap->pm_stats.resident_count; 882 883 if (pmap->pm_ptphint == m) 884 pmap->pm_ptphint = NULL; 885 886 /* 887 * If the page is finally unwired, simply free it. 888 */ 889 pmap_release_pte_page(m); 890 atomic_subtract_int(&cnt.v_wire_count, 1); 891 return (1); 892} 893 894static PMAP_INLINE int 895pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m) 896{ 897 --m->wire_count; 898 if (m->wire_count == 0) 899 return (_pmap_unwire_pte_hold(pmap, m)); 900 else 901 return (0); 902} 903 904/* 905 * After removing a page table entry, this routine is used to 906 * conditionally free the page, and manage the hold/wire counts. 907 */ 908static int 909pmap_unuse_pt(pmap_t pmap, vm_offset_t va, vm_page_t mpte) 910{ 911 unsigned ptepindex; 912 pd_entry_t pteva; 913 914 if (va >= VM_MAXUSER_ADDRESS) 915 return (0); 916 917 if (mpte == NULL) { 918 ptepindex = (va >> SEGSHIFT); 919 if (pmap->pm_ptphint && 920 (pmap->pm_ptphint->pindex == ptepindex)) { 921 mpte = pmap->pm_ptphint; 922 } else { 923 pteva = *pmap_pde(pmap, va); 924 mpte = PHYS_TO_VM_PAGE(MIPS_KSEG0_TO_PHYS(pteva)); 925 pmap->pm_ptphint = mpte; 926 } 927 } 928 return pmap_unwire_pte_hold(pmap, mpte); 929} 930 931void 932pmap_pinit0(pmap_t pmap) 933{ 934 int i; 935 936 PMAP_LOCK_INIT(pmap); 937 pmap->pm_segtab = kernel_segmap; 938 pmap->pm_active = 0; 939 pmap->pm_ptphint = NULL; 940 for (i = 0; i < MAXCPU; i++) { 941 pmap->pm_asid[i].asid = PMAP_ASID_RESERVED; 942 pmap->pm_asid[i].gen = 0; 943 } 944 PCPU_SET(curpmap, pmap); 945 TAILQ_INIT(&pmap->pm_pvlist); 946 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 947} 948 949static void 950pmap_ptpgzone_dtor(void *mem, int size, void *arg) 951{ 952#ifdef INVARIANTS 953 static char zeropage[PAGE_SIZE]; 954 955 KASSERT(size == PAGE_SIZE, 956 ("pmap_ptpgzone_dtor: invalid size %d", size)); 957 KASSERT(bcmp(mem, zeropage, PAGE_SIZE) == 0, 958 ("pmap_ptpgzone_dtor: freeing a non-zeroed page")); 959#endif 960} 961 962static void * 963pmap_ptpgzone_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait) 964{ 965 vm_page_t m; 966 vm_paddr_t paddr; 967 968 KASSERT(bytes == PAGE_SIZE, 969 ("pmap_ptpgzone_allocf: invalid allocation size %d", bytes)); 970 971 *flags = UMA_SLAB_PRIV; 972 m = vm_phys_alloc_contig(1, 0, MIPS_KSEG0_LARGEST_PHYS, 973 PAGE_SIZE, PAGE_SIZE); 974 if (m == NULL) 975 return (NULL); 976 977 paddr = VM_PAGE_TO_PHYS(m); 978 return ((void *)MIPS_PHYS_TO_KSEG0(paddr)); 979} 980 981static vm_page_t 982pmap_alloc_pte_page(pmap_t pmap, unsigned int index, int wait, vm_offset_t *vap) 983{ 984 vm_paddr_t paddr; 985 void *va; 986 vm_page_t m; 987 int locked; 988 989 locked = mtx_owned(&pmap->pm_mtx); 990 if (locked) { 991 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 992 PMAP_UNLOCK(pmap); 993 vm_page_unlock_queues(); 994 } 995 va = uma_zalloc(ptpgzone, wait); 996 if (locked) { 997 vm_page_lock_queues(); 998 PMAP_LOCK(pmap); 999 } 1000 if (va == NULL) 1001 return (NULL); 1002 1003 paddr = MIPS_KSEG0_TO_PHYS(va); 1004 m = PHYS_TO_VM_PAGE(paddr); 1005 1006 m->pindex = index; 1007 m->valid = VM_PAGE_BITS_ALL; 1008 m->wire_count = 1; 1009 atomic_add_int(&cnt.v_wire_count, 1); 1010 *vap = (vm_offset_t)va; 1011 return (m); 1012} 1013 1014static void 1015pmap_release_pte_page(vm_page_t m) 1016{ 1017 void *va; 1018 vm_paddr_t paddr; 1019 1020 paddr = VM_PAGE_TO_PHYS(m); 1021 va = (void *)MIPS_PHYS_TO_KSEG0(paddr); 1022 uma_zfree(ptpgzone, va); 1023} 1024 1025/* 1026 * Initialize a preallocated and zeroed pmap structure, 1027 * such as one in a vmspace structure. 1028 */ 1029int 1030pmap_pinit(pmap_t pmap) 1031{ 1032 vm_offset_t ptdva; 1033 vm_page_t ptdpg; 1034 int i; 1035 1036 PMAP_LOCK_INIT(pmap); 1037 1038 /* 1039 * allocate the page directory page 1040 */ 1041 ptdpg = pmap_alloc_pte_page(pmap, NUSERPGTBLS, M_WAITOK, &ptdva); 1042 pmap->pm_segtab = (pd_entry_t *)ptdva; 1043 1044 pmap->pm_active = 0; 1045 pmap->pm_ptphint = NULL; 1046 for (i = 0; i < MAXCPU; i++) { 1047 pmap->pm_asid[i].asid = PMAP_ASID_RESERVED; 1048 pmap->pm_asid[i].gen = 0; 1049 } 1050 TAILQ_INIT(&pmap->pm_pvlist); 1051 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1052 1053 return (1); 1054} 1055 1056/* 1057 * this routine is called if the page table page is not 1058 * mapped correctly. 1059 */ 1060static vm_page_t 1061_pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags) 1062{ 1063 vm_offset_t pteva; 1064 vm_page_t m; 1065 int req; 1066 1067 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1068 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1069 ("_pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1070 1071 req = VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ; 1072 /* 1073 * Find or fabricate a new pagetable page 1074 */ 1075 m = pmap_alloc_pte_page(pmap, ptepindex, flags, &pteva); 1076 if (m == NULL) 1077 return (NULL); 1078 1079 /* 1080 * Map the pagetable page into the process address space, if it 1081 * isn't already there. 1082 */ 1083 1084 pmap->pm_stats.resident_count++; 1085 pmap->pm_segtab[ptepindex] = (pd_entry_t)pteva; 1086 1087 /* 1088 * Set the page table hint 1089 */ 1090 pmap->pm_ptphint = m; 1091 return (m); 1092} 1093 1094static vm_page_t 1095pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags) 1096{ 1097 unsigned ptepindex; 1098 vm_offset_t pteva; 1099 vm_page_t m; 1100 1101 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1102 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1103 ("pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1104 1105 /* 1106 * Calculate pagetable page index 1107 */ 1108 ptepindex = va >> SEGSHIFT; 1109retry: 1110 /* 1111 * Get the page directory entry 1112 */ 1113 pteva = (vm_offset_t)pmap->pm_segtab[ptepindex]; 1114 1115 /* 1116 * If the page table page is mapped, we just increment the hold 1117 * count, and activate it. 1118 */ 1119 if (pteva) { 1120 /* 1121 * In order to get the page table page, try the hint first. 1122 */ 1123 if (pmap->pm_ptphint && 1124 (pmap->pm_ptphint->pindex == ptepindex)) { 1125 m = pmap->pm_ptphint; 1126 } else { 1127 m = PHYS_TO_VM_PAGE(MIPS_KSEG0_TO_PHYS(pteva)); 1128 pmap->pm_ptphint = m; 1129 } 1130 m->wire_count++; 1131 } else { 1132 /* 1133 * Here if the pte page isn't mapped, or if it has been 1134 * deallocated. 1135 */ 1136 m = _pmap_allocpte(pmap, ptepindex, flags); 1137 if (m == NULL && (flags & M_WAITOK)) 1138 goto retry; 1139 } 1140 return m; 1141} 1142 1143 1144/*************************************************** 1145* Pmap allocation/deallocation routines. 1146 ***************************************************/ 1147/* 1148 * Revision 1.397 1149 * - Merged pmap_release and pmap_release_free_page. When pmap_release is 1150 * called only the page directory page(s) can be left in the pmap pte 1151 * object, since all page table pages will have been freed by 1152 * pmap_remove_pages and pmap_remove. In addition, there can only be one 1153 * reference to the pmap and the page directory is wired, so the page(s) 1154 * can never be busy. So all there is to do is clear the magic mappings 1155 * from the page directory and free the page(s). 1156 */ 1157 1158 1159/* 1160 * Release any resources held by the given physical map. 1161 * Called when a pmap initialized by pmap_pinit is being released. 1162 * Should only be called if the map contains no valid mappings. 1163 */ 1164void 1165pmap_release(pmap_t pmap) 1166{ 1167 vm_offset_t ptdva; 1168 vm_page_t ptdpg; 1169 1170 KASSERT(pmap->pm_stats.resident_count == 0, 1171 ("pmap_release: pmap resident count %ld != 0", 1172 pmap->pm_stats.resident_count)); 1173 1174 ptdva = (vm_offset_t)pmap->pm_segtab; 1175 ptdpg = PHYS_TO_VM_PAGE(MIPS_KSEG0_TO_PHYS(ptdva)); 1176 1177 ptdpg->wire_count--; 1178 atomic_subtract_int(&cnt.v_wire_count, 1); 1179 pmap_release_pte_page(ptdpg); 1180 PMAP_LOCK_DESTROY(pmap); 1181} 1182 1183/* 1184 * grow the number of kernel page table entries, if needed 1185 */ 1186void 1187pmap_growkernel(vm_offset_t addr) 1188{ 1189 vm_offset_t pageva; 1190 vm_page_t nkpg; 1191 pt_entry_t *pte; 1192 int i; 1193 1194 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 1195 if (kernel_vm_end == 0) { 1196 kernel_vm_end = VM_MIN_KERNEL_ADDRESS; 1197 nkpt = 0; 1198 while (segtab_pde(kernel_segmap, kernel_vm_end)) { 1199 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & 1200 ~(PAGE_SIZE * NPTEPG - 1); 1201 nkpt++; 1202 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1203 kernel_vm_end = kernel_map->max_offset; 1204 break; 1205 } 1206 } 1207 } 1208 addr = (addr + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1209 if (addr - 1 >= kernel_map->max_offset) 1210 addr = kernel_map->max_offset; 1211 while (kernel_vm_end < addr) { 1212 if (segtab_pde(kernel_segmap, kernel_vm_end)) { 1213 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & 1214 ~(PAGE_SIZE * NPTEPG - 1); 1215 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1216 kernel_vm_end = kernel_map->max_offset; 1217 break; 1218 } 1219 continue; 1220 } 1221 /* 1222 * This index is bogus, but out of the way 1223 */ 1224 nkpg = pmap_alloc_pte_page(kernel_pmap, nkpt, M_NOWAIT, &pageva); 1225 1226 if (!nkpg) 1227 panic("pmap_growkernel: no memory to grow kernel"); 1228 1229 nkpt++; 1230 pte = (pt_entry_t *)pageva; 1231 segtab_pde(kernel_segmap, kernel_vm_end) = (pd_entry_t)pte; 1232 1233 /* 1234 * The R[4-7]?00 stores only one copy of the Global bit in 1235 * the translation lookaside buffer for each 2 page entry. 1236 * Thus invalid entrys must have the Global bit set so when 1237 * Entry LO and Entry HI G bits are anded together they will 1238 * produce a global bit to store in the tlb. 1239 */ 1240 for (i = 0; i < NPTEPG; i++, pte++) 1241 *pte = PTE_G; 1242 1243 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & 1244 ~(PAGE_SIZE * NPTEPG - 1); 1245 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1246 kernel_vm_end = kernel_map->max_offset; 1247 break; 1248 } 1249 } 1250} 1251 1252/*************************************************** 1253* page management routines. 1254 ***************************************************/ 1255 1256/* 1257 * free the pv_entry back to the free list 1258 */ 1259static PMAP_INLINE void 1260free_pv_entry(pv_entry_t pv) 1261{ 1262 1263 pv_entry_count--; 1264 uma_zfree(pvzone, pv); 1265} 1266 1267/* 1268 * get a new pv_entry, allocating a block from the system 1269 * when needed. 1270 * the memory allocation is performed bypassing the malloc code 1271 * because of the possibility of allocations at interrupt time. 1272 */ 1273static pv_entry_t 1274get_pv_entry(pmap_t locked_pmap) 1275{ 1276 static const struct timeval printinterval = { 60, 0 }; 1277 static struct timeval lastprint; 1278 struct vpgqueues *vpq; 1279 pt_entry_t *pte, oldpte; 1280 pmap_t pmap; 1281 pv_entry_t allocated_pv, next_pv, pv; 1282 vm_offset_t va; 1283 vm_page_t m; 1284 1285 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED); 1286 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1287 allocated_pv = uma_zalloc(pvzone, M_NOWAIT); 1288 if (allocated_pv != NULL) { 1289 pv_entry_count++; 1290 if (pv_entry_count > pv_entry_high_water) 1291 pagedaemon_wakeup(); 1292 else 1293 return (allocated_pv); 1294 } 1295 /* 1296 * Reclaim pv entries: At first, destroy mappings to inactive 1297 * pages. After that, if a pv entry is still needed, destroy 1298 * mappings to active pages. 1299 */ 1300 if (ratecheck(&lastprint, &printinterval)) 1301 printf("Approaching the limit on PV entries, " 1302 "increase the vm.pmap.shpgperproc tunable.\n"); 1303 vpq = &vm_page_queues[PQ_INACTIVE]; 1304retry: 1305 TAILQ_FOREACH(m, &vpq->pl, pageq) { 1306 if (m->hold_count || m->busy) 1307 continue; 1308 TAILQ_FOREACH_SAFE(pv, &m->md.pv_list, pv_list, next_pv) { 1309 va = pv->pv_va; 1310 pmap = pv->pv_pmap; 1311 /* Avoid deadlock and lock recursion. */ 1312 if (pmap > locked_pmap) 1313 PMAP_LOCK(pmap); 1314 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) 1315 continue; 1316 pmap->pm_stats.resident_count--; 1317 pte = pmap_pte(pmap, va); 1318 KASSERT(pte != NULL, ("pte")); 1319 oldpte = loadandclear((u_int *)pte); 1320 if (is_kernel_pmap(pmap)) 1321 *pte = PTE_G; 1322 KASSERT((oldpte & PTE_W) == 0, 1323 ("wired pte for unwired page")); 1324 if (m->md.pv_flags & PV_TABLE_REF) 1325 vm_page_flag_set(m, PG_REFERENCED); 1326 if (oldpte & PTE_M) 1327 vm_page_dirty(m); 1328 pmap_invalidate_page(pmap, va); 1329 TAILQ_REMOVE(&pmap->pm_pvlist, pv, pv_plist); 1330 m->md.pv_list_count--; 1331 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 1332 if (TAILQ_EMPTY(&m->md.pv_list)) { 1333 vm_page_flag_clear(m, PG_WRITEABLE); 1334 m->md.pv_flags &= ~(PV_TABLE_REF | PV_TABLE_MOD); 1335 } 1336 pmap_unuse_pt(pmap, va, pv->pv_ptem); 1337 if (pmap != locked_pmap) 1338 PMAP_UNLOCK(pmap); 1339 if (allocated_pv == NULL) 1340 allocated_pv = pv; 1341 else 1342 free_pv_entry(pv); 1343 } 1344 } 1345 if (allocated_pv == NULL) { 1346 if (vpq == &vm_page_queues[PQ_INACTIVE]) { 1347 vpq = &vm_page_queues[PQ_ACTIVE]; 1348 goto retry; 1349 } 1350 panic("get_pv_entry: increase the vm.pmap.shpgperproc tunable"); 1351 } 1352 return (allocated_pv); 1353} 1354 1355/* 1356 * Revision 1.370 1357 * 1358 * Move pmap_collect() out of the machine-dependent code, rename it 1359 * to reflect its new location, and add page queue and flag locking. 1360 * 1361 * Notes: (1) alpha, i386, and ia64 had identical implementations 1362 * of pmap_collect() in terms of machine-independent interfaces; 1363 * (2) sparc64 doesn't require it; (3) powerpc had it as a TODO. 1364 * 1365 * MIPS implementation was identical to alpha [Junos 8.2] 1366 */ 1367 1368/* 1369 * If it is the first entry on the list, it is actually 1370 * in the header and we must copy the following entry up 1371 * to the header. Otherwise we must search the list for 1372 * the entry. In either case we free the now unused entry. 1373 */ 1374 1375static void 1376pmap_remove_entry(struct pmap *pmap, vm_page_t m, vm_offset_t va) 1377{ 1378 pv_entry_t pv; 1379 1380 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1381 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1382 if (m->md.pv_list_count < pmap->pm_stats.resident_count) { 1383 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 1384 if (pmap == pv->pv_pmap && va == pv->pv_va) 1385 break; 1386 } 1387 } else { 1388 TAILQ_FOREACH(pv, &pmap->pm_pvlist, pv_plist) { 1389 if (va == pv->pv_va) 1390 break; 1391 } 1392 } 1393 1394 KASSERT(pv != NULL, ("pmap_remove_entry: pv not found, pa %lx va %lx", 1395 (u_long)VM_PAGE_TO_PHYS(m), (u_long)va)); 1396 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 1397 m->md.pv_list_count--; 1398 if (TAILQ_FIRST(&m->md.pv_list) == NULL) 1399 vm_page_flag_clear(m, PG_WRITEABLE); 1400 1401 TAILQ_REMOVE(&pmap->pm_pvlist, pv, pv_plist); 1402 free_pv_entry(pv); 1403} 1404 1405/* 1406 * Create a pv entry for page at pa for 1407 * (pmap, va). 1408 */ 1409static void 1410pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t mpte, vm_page_t m, 1411 boolean_t wired) 1412{ 1413 pv_entry_t pv; 1414 1415 pv = get_pv_entry(pmap); 1416 pv->pv_va = va; 1417 pv->pv_pmap = pmap; 1418 pv->pv_ptem = mpte; 1419 pv->pv_wired = wired; 1420 1421 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1422 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1423 TAILQ_INSERT_TAIL(&pmap->pm_pvlist, pv, pv_plist); 1424 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 1425 m->md.pv_list_count++; 1426} 1427 1428/* 1429 * Conditionally create a pv entry. 1430 */ 1431static boolean_t 1432pmap_try_insert_pv_entry(pmap_t pmap, vm_page_t mpte, vm_offset_t va, 1433 vm_page_t m) 1434{ 1435 pv_entry_t pv; 1436 1437 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1438 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1439 if (pv_entry_count < pv_entry_high_water && 1440 (pv = uma_zalloc(pvzone, M_NOWAIT)) != NULL) { 1441 pv_entry_count++; 1442 pv->pv_va = va; 1443 pv->pv_pmap = pmap; 1444 pv->pv_ptem = mpte; 1445 pv->pv_wired = FALSE; 1446 TAILQ_INSERT_TAIL(&pmap->pm_pvlist, pv, pv_plist); 1447 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 1448 m->md.pv_list_count++; 1449 return (TRUE); 1450 } else 1451 return (FALSE); 1452} 1453 1454/* 1455 * pmap_remove_pte: do the things to unmap a page in a process 1456 */ 1457static int 1458pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va) 1459{ 1460 pt_entry_t oldpte; 1461 vm_page_t m; 1462 vm_offset_t pa; 1463 1464 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1465 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1466 1467 oldpte = loadandclear((u_int *)ptq); 1468 if (is_kernel_pmap(pmap)) 1469 *ptq = PTE_G; 1470 1471 if (oldpte & PTE_W) 1472 pmap->pm_stats.wired_count -= 1; 1473 1474 pmap->pm_stats.resident_count -= 1; 1475 pa = mips_tlbpfn_to_paddr(oldpte); 1476 1477 if (page_is_managed(pa)) { 1478 m = PHYS_TO_VM_PAGE(pa); 1479 if (oldpte & PTE_M) { 1480#if defined(PMAP_DIAGNOSTIC) 1481 if (pmap_nw_modified(oldpte)) { 1482 printf( 1483 "pmap_remove: modified page not writable: va: 0x%x, pte: 0x%x\n", 1484 va, oldpte); 1485 } 1486#endif 1487 vm_page_dirty(m); 1488 } 1489 if (m->md.pv_flags & PV_TABLE_REF) 1490 vm_page_flag_set(m, PG_REFERENCED); 1491 m->md.pv_flags &= ~(PV_TABLE_REF | PV_TABLE_MOD); 1492 1493 pmap_remove_entry(pmap, m, va); 1494 } 1495 return pmap_unuse_pt(pmap, va, NULL); 1496} 1497 1498/* 1499 * Remove a single page from a process address space 1500 */ 1501static void 1502pmap_remove_page(struct pmap *pmap, vm_offset_t va) 1503{ 1504 register pt_entry_t *ptq; 1505 1506 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1507 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1508 ptq = pmap_pte(pmap, va); 1509 1510 /* 1511 * if there is no pte for this address, just skip it!!! 1512 */ 1513 if (!ptq || !pmap_pte_v(ptq)) { 1514 return; 1515 } 1516 1517 /* 1518 * Write back all caches from the page being destroyed 1519 */ 1520 mips_dcache_wbinv_range_index(va, PAGE_SIZE); 1521 1522 /* 1523 * get a local va for mappings for this pmap. 1524 */ 1525 (void)pmap_remove_pte(pmap, ptq, va); 1526 pmap_invalidate_page(pmap, va); 1527 1528 return; 1529} 1530 1531/* 1532 * Remove the given range of addresses from the specified map. 1533 * 1534 * It is assumed that the start and end are properly 1535 * rounded to the page size. 1536 */ 1537void 1538pmap_remove(struct pmap *pmap, vm_offset_t sva, vm_offset_t eva) 1539{ 1540 vm_offset_t va, nva; 1541 1542 if (pmap == NULL) 1543 return; 1544 1545 if (pmap->pm_stats.resident_count == 0) 1546 return; 1547 1548 vm_page_lock_queues(); 1549 PMAP_LOCK(pmap); 1550 1551 /* 1552 * special handling of removing one page. a very common operation 1553 * and easy to short circuit some code. 1554 */ 1555 if ((sva + PAGE_SIZE) == eva) { 1556 pmap_remove_page(pmap, sva); 1557 goto out; 1558 } 1559 for (va = sva; va < eva; va = nva) { 1560 if (!*pmap_pde(pmap, va)) { 1561 nva = mips_segtrunc(va + MIPS_SEGSIZE); 1562 continue; 1563 } 1564 pmap_remove_page(pmap, va); 1565 nva = va + PAGE_SIZE; 1566 } 1567 1568out: 1569 vm_page_unlock_queues(); 1570 PMAP_UNLOCK(pmap); 1571} 1572 1573/* 1574 * Routine: pmap_remove_all 1575 * Function: 1576 * Removes this physical page from 1577 * all physical maps in which it resides. 1578 * Reflects back modify bits to the pager. 1579 * 1580 * Notes: 1581 * Original versions of this routine were very 1582 * inefficient because they iteratively called 1583 * pmap_remove (slow...) 1584 */ 1585 1586void 1587pmap_remove_all(vm_page_t m) 1588{ 1589 register pv_entry_t pv; 1590 register pt_entry_t *pte, tpte; 1591 1592 KASSERT((m->flags & PG_FICTITIOUS) == 0, 1593 ("pmap_remove_all: page %p is fictitious", m)); 1594 vm_page_lock_queues(); 1595 1596 if (m->md.pv_flags & PV_TABLE_REF) 1597 vm_page_flag_set(m, PG_REFERENCED); 1598 1599 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 1600 PMAP_LOCK(pv->pv_pmap); 1601 1602 /* 1603 * If it's last mapping writeback all caches from 1604 * the page being destroyed 1605 */ 1606 if (m->md.pv_list_count == 1) 1607 mips_dcache_wbinv_range_index(pv->pv_va, PAGE_SIZE); 1608 1609 pv->pv_pmap->pm_stats.resident_count--; 1610 1611 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 1612 1613 tpte = loadandclear((u_int *)pte); 1614 if (is_kernel_pmap(pv->pv_pmap)) 1615 *pte = PTE_G; 1616 1617 if (tpte & PTE_W) 1618 pv->pv_pmap->pm_stats.wired_count--; 1619 1620 /* 1621 * Update the vm_page_t clean and reference bits. 1622 */ 1623 if (tpte & PTE_M) { 1624#if defined(PMAP_DIAGNOSTIC) 1625 if (pmap_nw_modified(tpte)) { 1626 printf( 1627 "pmap_remove_all: modified page not writable: va: 0x%x, pte: 0x%x\n", 1628 pv->pv_va, tpte); 1629 } 1630#endif 1631 vm_page_dirty(m); 1632 } 1633 pmap_invalidate_page(pv->pv_pmap, pv->pv_va); 1634 1635 TAILQ_REMOVE(&pv->pv_pmap->pm_pvlist, pv, pv_plist); 1636 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 1637 m->md.pv_list_count--; 1638 pmap_unuse_pt(pv->pv_pmap, pv->pv_va, pv->pv_ptem); 1639 PMAP_UNLOCK(pv->pv_pmap); 1640 free_pv_entry(pv); 1641 } 1642 1643 vm_page_flag_clear(m, PG_WRITEABLE); 1644 m->md.pv_flags &= ~(PV_TABLE_REF | PV_TABLE_MOD); 1645 vm_page_unlock_queues(); 1646} 1647 1648/* 1649 * Set the physical protection on the 1650 * specified range of this map as requested. 1651 */ 1652void 1653pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 1654{ 1655 pt_entry_t *pte; 1656 1657 if (pmap == NULL) 1658 return; 1659 1660 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1661 pmap_remove(pmap, sva, eva); 1662 return; 1663 } 1664 if (prot & VM_PROT_WRITE) 1665 return; 1666 1667 vm_page_lock_queues(); 1668 PMAP_LOCK(pmap); 1669 while (sva < eva) { 1670 pt_entry_t pbits, obits; 1671 vm_page_t m; 1672 vm_offset_t pa; 1673 1674 /* 1675 * If segment table entry is empty, skip this segment. 1676 */ 1677 if (!*pmap_pde(pmap, sva)) { 1678 sva = mips_segtrunc(sva + MIPS_SEGSIZE); 1679 continue; 1680 } 1681 /* 1682 * If pte is invalid, skip this page 1683 */ 1684 pte = pmap_pte(pmap, sva); 1685 if (!pmap_pte_v(pte)) { 1686 sva += PAGE_SIZE; 1687 continue; 1688 } 1689retry: 1690 obits = pbits = *pte; 1691 pa = mips_tlbpfn_to_paddr(pbits); 1692 1693 if (page_is_managed(pa) && (pbits & PTE_M) != 0) { 1694 m = PHYS_TO_VM_PAGE(pa); 1695 vm_page_dirty(m); 1696 m->md.pv_flags &= ~PV_TABLE_MOD; 1697 } 1698 pbits = (pbits & ~PTE_M) | PTE_RO; 1699 1700 if (pbits != *pte) { 1701 if (!atomic_cmpset_int((u_int *)pte, obits, pbits)) 1702 goto retry; 1703 pmap_update_page(pmap, sva, pbits); 1704 } 1705 sva += PAGE_SIZE; 1706 } 1707 vm_page_unlock_queues(); 1708 PMAP_UNLOCK(pmap); 1709} 1710 1711/* 1712 * Insert the given physical page (p) at 1713 * the specified virtual address (v) in the 1714 * target physical map with the protection requested. 1715 * 1716 * If specified, the page will be wired down, meaning 1717 * that the related pte can not be reclaimed. 1718 * 1719 * NB: This is the only routine which MAY NOT lazy-evaluate 1720 * or lose information. That is, this routine must actually 1721 * insert this page into the given map NOW. 1722 */ 1723void 1724pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m, 1725 vm_prot_t prot, boolean_t wired) 1726{ 1727 vm_offset_t pa, opa; 1728 register pt_entry_t *pte; 1729 pt_entry_t origpte, newpte; 1730 vm_page_t mpte, om; 1731 int rw = 0; 1732 1733 if (pmap == NULL) 1734 return; 1735 1736 va &= ~PAGE_MASK; 1737 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig")); 1738 KASSERT((m->oflags & VPO_BUSY) != 0, 1739 ("pmap_enter: page %p is not busy", m)); 1740 1741 mpte = NULL; 1742 1743 vm_page_lock_queues(); 1744 PMAP_LOCK(pmap); 1745 1746 /* 1747 * In the case that a page table page is not resident, we are 1748 * creating it here. 1749 */ 1750 if (va < VM_MAXUSER_ADDRESS) { 1751 mpte = pmap_allocpte(pmap, va, M_WAITOK); 1752 } 1753 pte = pmap_pte(pmap, va); 1754 1755 /* 1756 * Page Directory table entry not valid, we need a new PT page 1757 */ 1758 if (pte == NULL) { 1759 panic("pmap_enter: invalid page directory, pdir=%p, va=%p\n", 1760 (void *)pmap->pm_segtab, (void *)va); 1761 } 1762 pa = VM_PAGE_TO_PHYS(m); 1763 om = NULL; 1764 origpte = *pte; 1765 opa = mips_tlbpfn_to_paddr(origpte); 1766 1767 /* 1768 * Mapping has not changed, must be protection or wiring change. 1769 */ 1770 if ((origpte & PTE_V) && (opa == pa)) { 1771 /* 1772 * Wiring change, just update stats. We don't worry about 1773 * wiring PT pages as they remain resident as long as there 1774 * are valid mappings in them. Hence, if a user page is 1775 * wired, the PT page will be also. 1776 */ 1777 if (wired && ((origpte & PTE_W) == 0)) 1778 pmap->pm_stats.wired_count++; 1779 else if (!wired && (origpte & PTE_W)) 1780 pmap->pm_stats.wired_count--; 1781 1782#if defined(PMAP_DIAGNOSTIC) 1783 if (pmap_nw_modified(origpte)) { 1784 printf( 1785 "pmap_enter: modified page not writable: va: 0x%x, pte: 0x%x\n", 1786 va, origpte); 1787 } 1788#endif 1789 1790 /* 1791 * Remove extra pte reference 1792 */ 1793 if (mpte) 1794 mpte->wire_count--; 1795 1796 /* 1797 * We might be turning off write access to the page, so we 1798 * go ahead and sense modify status. 1799 */ 1800 if (page_is_managed(opa)) { 1801 om = m; 1802 } 1803 goto validate; 1804 } 1805 /* 1806 * Mapping has changed, invalidate old range and fall through to 1807 * handle validating new mapping. 1808 */ 1809 if (opa) { 1810 if (origpte & PTE_W) 1811 pmap->pm_stats.wired_count--; 1812 1813 if (page_is_managed(opa)) { 1814 om = PHYS_TO_VM_PAGE(opa); 1815 pmap_remove_entry(pmap, om, va); 1816 } 1817 if (mpte != NULL) { 1818 mpte->wire_count--; 1819 KASSERT(mpte->wire_count > 0, 1820 ("pmap_enter: missing reference to page table page," 1821 " va: %p", (void *)va)); 1822 } 1823 } else 1824 pmap->pm_stats.resident_count++; 1825 1826 /* 1827 * Enter on the PV list if part of our managed memory. Note that we 1828 * raise IPL while manipulating pv_table since pmap_enter can be 1829 * called at interrupt time. 1830 */ 1831 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) { 1832 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva, 1833 ("pmap_enter: managed mapping within the clean submap")); 1834 pmap_insert_entry(pmap, va, mpte, m, wired); 1835 } 1836 /* 1837 * Increment counters 1838 */ 1839 if (wired) 1840 pmap->pm_stats.wired_count++; 1841 1842validate: 1843 if ((access & VM_PROT_WRITE) != 0) 1844 m->md.pv_flags |= PV_TABLE_MOD | PV_TABLE_REF; 1845 rw = init_pte_prot(va, m, prot); 1846 1847#ifdef PMAP_DEBUG 1848 printf("pmap_enter: va: 0x%08x -> pa: 0x%08x\n", va, pa); 1849#endif 1850 /* 1851 * Now validate mapping with desired protection/wiring. 1852 */ 1853 newpte = mips_paddr_to_tlbpfn(pa) | rw | PTE_V; 1854 1855 if (is_cacheable_mem(pa)) 1856 newpte |= PTE_CACHE; 1857 else 1858 newpte |= PTE_UNCACHED; 1859 1860 if (wired) 1861 newpte |= PTE_W; 1862 1863 if (is_kernel_pmap(pmap)) { 1864 newpte |= PTE_G; 1865 } 1866 1867 /* 1868 * if the mapping or permission bits are different, we need to 1869 * update the pte. 1870 */ 1871 if (origpte != newpte) { 1872 if (origpte & PTE_V) { 1873 *pte = newpte; 1874 if (page_is_managed(opa) && (opa != pa)) { 1875 if (om->md.pv_flags & PV_TABLE_REF) 1876 vm_page_flag_set(om, PG_REFERENCED); 1877 om->md.pv_flags &= 1878 ~(PV_TABLE_REF | PV_TABLE_MOD); 1879 } 1880 if (origpte & PTE_M) { 1881 KASSERT((origpte & PTE_RW), 1882 ("pmap_enter: modified page not writable:" 1883 " va: %p, pte: 0x%x", (void *)va, origpte)); 1884 if (page_is_managed(opa)) 1885 vm_page_dirty(om); 1886 } 1887 } else { 1888 *pte = newpte; 1889 } 1890 } 1891 pmap_update_page(pmap, va, newpte); 1892 1893 /* 1894 * Sync I & D caches for executable pages. Do this only if the the 1895 * target pmap belongs to the current process. Otherwise, an 1896 * unresolvable TLB miss may occur. 1897 */ 1898 if (!is_kernel_pmap(pmap) && (pmap == &curproc->p_vmspace->vm_pmap) && 1899 (prot & VM_PROT_EXECUTE)) { 1900 mips_icache_sync_range(va, PAGE_SIZE); 1901 mips_dcache_wbinv_range(va, PAGE_SIZE); 1902 } 1903 vm_page_unlock_queues(); 1904 PMAP_UNLOCK(pmap); 1905} 1906 1907/* 1908 * this code makes some *MAJOR* assumptions: 1909 * 1. Current pmap & pmap exists. 1910 * 2. Not wired. 1911 * 3. Read access. 1912 * 4. No page table pages. 1913 * but is *MUCH* faster than pmap_enter... 1914 */ 1915 1916void 1917pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 1918{ 1919 1920 vm_page_lock_queues(); 1921 PMAP_LOCK(pmap); 1922 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL); 1923 vm_page_unlock_queues(); 1924 PMAP_UNLOCK(pmap); 1925} 1926 1927static vm_page_t 1928pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, 1929 vm_prot_t prot, vm_page_t mpte) 1930{ 1931 pt_entry_t *pte; 1932 vm_offset_t pa; 1933 1934 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva || 1935 (m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0, 1936 ("pmap_enter_quick_locked: managed mapping within the clean submap")); 1937 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1938 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1939 1940 /* 1941 * In the case that a page table page is not resident, we are 1942 * creating it here. 1943 */ 1944 if (va < VM_MAXUSER_ADDRESS) { 1945 unsigned ptepindex; 1946 vm_offset_t pteva; 1947 1948 /* 1949 * Calculate pagetable page index 1950 */ 1951 ptepindex = va >> SEGSHIFT; 1952 if (mpte && (mpte->pindex == ptepindex)) { 1953 mpte->wire_count++; 1954 } else { 1955 /* 1956 * Get the page directory entry 1957 */ 1958 pteva = (vm_offset_t)pmap->pm_segtab[ptepindex]; 1959 1960 /* 1961 * If the page table page is mapped, we just 1962 * increment the hold count, and activate it. 1963 */ 1964 if (pteva) { 1965 if (pmap->pm_ptphint && 1966 (pmap->pm_ptphint->pindex == ptepindex)) { 1967 mpte = pmap->pm_ptphint; 1968 } else { 1969 mpte = PHYS_TO_VM_PAGE( 1970 MIPS_KSEG0_TO_PHYS(pteva)); 1971 pmap->pm_ptphint = mpte; 1972 } 1973 mpte->wire_count++; 1974 } else { 1975 mpte = _pmap_allocpte(pmap, ptepindex, 1976 M_NOWAIT); 1977 if (mpte == NULL) 1978 return (mpte); 1979 } 1980 } 1981 } else { 1982 mpte = NULL; 1983 } 1984 1985 pte = pmap_pte(pmap, va); 1986 if (pmap_pte_v(pte)) { 1987 if (mpte != NULL) { 1988 mpte->wire_count--; 1989 mpte = NULL; 1990 } 1991 return (mpte); 1992 } 1993 1994 /* 1995 * Enter on the PV list if part of our managed memory. 1996 */ 1997 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0 && 1998 !pmap_try_insert_pv_entry(pmap, mpte, va, m)) { 1999 if (mpte != NULL) { 2000 pmap_unwire_pte_hold(pmap, mpte); 2001 mpte = NULL; 2002 } 2003 return (mpte); 2004 } 2005 2006 /* 2007 * Increment counters 2008 */ 2009 pmap->pm_stats.resident_count++; 2010 2011 pa = VM_PAGE_TO_PHYS(m); 2012 2013 /* 2014 * Now validate mapping with RO protection 2015 */ 2016 *pte = mips_paddr_to_tlbpfn(pa) | PTE_V; 2017 2018 if (is_cacheable_mem(pa)) 2019 *pte |= PTE_CACHE; 2020 else 2021 *pte |= PTE_UNCACHED; 2022 2023 if (is_kernel_pmap(pmap)) 2024 *pte |= PTE_G; 2025 else { 2026 *pte |= PTE_RO; 2027 /* 2028 * Sync I & D caches. Do this only if the the target pmap 2029 * belongs to the current process. Otherwise, an 2030 * unresolvable TLB miss may occur. */ 2031 if (pmap == &curproc->p_vmspace->vm_pmap) { 2032 va &= ~PAGE_MASK; 2033 mips_icache_sync_range(va, PAGE_SIZE); 2034 mips_dcache_wbinv_range(va, PAGE_SIZE); 2035 } 2036 } 2037 return (mpte); 2038} 2039 2040/* 2041 * Make a temporary mapping for a physical address. This is only intended 2042 * to be used for panic dumps. 2043 */ 2044void * 2045pmap_kenter_temporary(vm_paddr_t pa, int i) 2046{ 2047 vm_offset_t va; 2048 register_t intr; 2049 if (i != 0) 2050 printf("%s: ERROR!!! More than one page of virtual address mapping not supported\n", 2051 __func__); 2052 2053 if (pa < MIPS_KSEG0_LARGEST_PHYS) { 2054 va = MIPS_PHYS_TO_KSEG0(pa); 2055 } else { 2056 int cpu; 2057 struct local_sysmaps *sysm; 2058 pt_entry_t *pte, npte; 2059 2060 /* If this is used other than for dumps, we may need to leave 2061 * interrupts disasbled on return. If crash dumps don't work when 2062 * we get to this point, we might want to consider this (leaving things 2063 * disabled as a starting point ;-) 2064 */ 2065 intr = intr_disable(); 2066 cpu = PCPU_GET(cpuid); 2067 sysm = &sysmap_lmem[cpu]; 2068 /* Since this is for the debugger, no locks or any other fun */ 2069 npte = mips_paddr_to_tlbpfn(pa) | PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; 2070 pte = pmap_pte(kernel_pmap, sysm->base); 2071 *pte = npte; 2072 sysm->valid1 = 1; 2073 pmap_update_page(kernel_pmap, sysm->base, npte); 2074 va = sysm->base; 2075 intr_restore(intr); 2076 } 2077 return ((void *)va); 2078} 2079 2080void 2081pmap_kenter_temporary_free(vm_paddr_t pa) 2082{ 2083 int cpu; 2084 register_t intr; 2085 struct local_sysmaps *sysm; 2086 2087 if (pa < MIPS_KSEG0_LARGEST_PHYS) { 2088 /* nothing to do for this case */ 2089 return; 2090 } 2091 cpu = PCPU_GET(cpuid); 2092 sysm = &sysmap_lmem[cpu]; 2093 if (sysm->valid1) { 2094 pt_entry_t *pte; 2095 2096 intr = intr_disable(); 2097 pte = pmap_pte(kernel_pmap, sysm->base); 2098 *pte = PTE_G; 2099 pmap_invalidate_page(kernel_pmap, sysm->base); 2100 intr_restore(intr); 2101 sysm->valid1 = 0; 2102 } 2103} 2104 2105/* 2106 * Moved the code to Machine Independent 2107 * vm_map_pmap_enter() 2108 */ 2109 2110/* 2111 * Maps a sequence of resident pages belonging to the same object. 2112 * The sequence begins with the given page m_start. This page is 2113 * mapped at the given virtual address start. Each subsequent page is 2114 * mapped at a virtual address that is offset from start by the same 2115 * amount as the page is offset from m_start within the object. The 2116 * last page in the sequence is the page with the largest offset from 2117 * m_start that can be mapped at a virtual address less than the given 2118 * virtual address end. Not every virtual page between start and end 2119 * is mapped; only those for which a resident page exists with the 2120 * corresponding offset from m_start are mapped. 2121 */ 2122void 2123pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 2124 vm_page_t m_start, vm_prot_t prot) 2125{ 2126 vm_page_t m, mpte; 2127 vm_pindex_t diff, psize; 2128 2129 VM_OBJECT_LOCK_ASSERT(m_start->object, MA_OWNED); 2130 psize = atop(end - start); 2131 mpte = NULL; 2132 m = m_start; 2133 vm_page_lock_queues(); 2134 PMAP_LOCK(pmap); 2135 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 2136 mpte = pmap_enter_quick_locked(pmap, start + ptoa(diff), m, 2137 prot, mpte); 2138 m = TAILQ_NEXT(m, listq); 2139 } 2140 vm_page_unlock_queues(); 2141 PMAP_UNLOCK(pmap); 2142} 2143 2144/* 2145 * pmap_object_init_pt preloads the ptes for a given object 2146 * into the specified pmap. This eliminates the blast of soft 2147 * faults on process startup and immediately after an mmap. 2148 */ 2149void 2150pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, 2151 vm_object_t object, vm_pindex_t pindex, vm_size_t size) 2152{ 2153 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 2154 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 2155 ("pmap_object_init_pt: non-device object")); 2156} 2157 2158/* 2159 * Routine: pmap_change_wiring 2160 * Function: Change the wiring attribute for a map/virtual-address 2161 * pair. 2162 * In/out conditions: 2163 * The mapping must already exist in the pmap. 2164 */ 2165void 2166pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 2167{ 2168 register pt_entry_t *pte; 2169 2170 if (pmap == NULL) 2171 return; 2172 2173 PMAP_LOCK(pmap); 2174 pte = pmap_pte(pmap, va); 2175 2176 if (wired && !pmap_pte_w(pte)) 2177 pmap->pm_stats.wired_count++; 2178 else if (!wired && pmap_pte_w(pte)) 2179 pmap->pm_stats.wired_count--; 2180 2181 /* 2182 * Wiring is not a hardware characteristic so there is no need to 2183 * invalidate TLB. 2184 */ 2185 pmap_pte_set_w(pte, wired); 2186 PMAP_UNLOCK(pmap); 2187} 2188 2189/* 2190 * Copy the range specified by src_addr/len 2191 * from the source map to the range dst_addr/len 2192 * in the destination map. 2193 * 2194 * This routine is only advisory and need not do anything. 2195 */ 2196 2197void 2198pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, 2199 vm_size_t len, vm_offset_t src_addr) 2200{ 2201} 2202 2203/* 2204 * pmap_zero_page zeros the specified hardware page by mapping 2205 * the page into KVM and using bzero to clear its contents. 2206 */ 2207void 2208pmap_zero_page(vm_page_t m) 2209{ 2210 vm_offset_t va; 2211 vm_paddr_t phys = VM_PAGE_TO_PHYS(m); 2212 register_t intr; 2213 2214 if (phys < MIPS_KSEG0_LARGEST_PHYS) { 2215 va = MIPS_PHYS_TO_KSEG0(phys); 2216 2217 bzero((caddr_t)va, PAGE_SIZE); 2218 mips_dcache_wbinv_range(va, PAGE_SIZE); 2219 } else { 2220 PMAP_LMEM_MAP1(va, phys); 2221 2222 bzero((caddr_t)va, PAGE_SIZE); 2223 mips_dcache_wbinv_range(va, PAGE_SIZE); 2224 2225 PMAP_LMEM_UNMAP(); 2226 } 2227} 2228 2229/* 2230 * pmap_zero_page_area zeros the specified hardware page by mapping 2231 * the page into KVM and using bzero to clear its contents. 2232 * 2233 * off and size may not cover an area beyond a single hardware page. 2234 */ 2235void 2236pmap_zero_page_area(vm_page_t m, int off, int size) 2237{ 2238 vm_offset_t va; 2239 vm_paddr_t phys = VM_PAGE_TO_PHYS(m); 2240 register_t intr; 2241 2242 if (phys < MIPS_KSEG0_LARGEST_PHYS) { 2243 va = MIPS_PHYS_TO_KSEG0(phys); 2244 bzero((char *)(caddr_t)va + off, size); 2245 mips_dcache_wbinv_range(va + off, size); 2246 } else { 2247 PMAP_LMEM_MAP1(va, phys); 2248 2249 bzero((char *)va + off, size); 2250 mips_dcache_wbinv_range(va + off, size); 2251 2252 PMAP_LMEM_UNMAP(); 2253 } 2254} 2255 2256void 2257pmap_zero_page_idle(vm_page_t m) 2258{ 2259 vm_offset_t va; 2260 vm_paddr_t phys = VM_PAGE_TO_PHYS(m); 2261 register_t intr; 2262 2263 if (phys < MIPS_KSEG0_LARGEST_PHYS) { 2264 va = MIPS_PHYS_TO_KSEG0(phys); 2265 bzero((caddr_t)va, PAGE_SIZE); 2266 mips_dcache_wbinv_range(va, PAGE_SIZE); 2267 } else { 2268 PMAP_LMEM_MAP1(va, phys); 2269 2270 bzero((caddr_t)va, PAGE_SIZE); 2271 mips_dcache_wbinv_range(va, PAGE_SIZE); 2272 2273 PMAP_LMEM_UNMAP(); 2274 } 2275} 2276 2277/* 2278 * pmap_copy_page copies the specified (machine independent) 2279 * page by mapping the page into virtual memory and using 2280 * bcopy to copy the page, one machine dependent page at a 2281 * time. 2282 */ 2283void 2284pmap_copy_page(vm_page_t src, vm_page_t dst) 2285{ 2286 vm_offset_t va_src, va_dst; 2287 vm_paddr_t phy_src = VM_PAGE_TO_PHYS(src); 2288 vm_paddr_t phy_dst = VM_PAGE_TO_PHYS(dst); 2289 register_t intr; 2290 2291 if ((phy_src < MIPS_KSEG0_LARGEST_PHYS) && (phy_dst < MIPS_KSEG0_LARGEST_PHYS)) { 2292 /* easy case, all can be accessed via KSEG0 */ 2293 /* 2294 * Flush all caches for VA that are mapped to this page 2295 * to make sure that data in SDRAM is up to date 2296 */ 2297 pmap_flush_pvcache(src); 2298 mips_dcache_wbinv_range_index( 2299 MIPS_PHYS_TO_KSEG0(phy_dst), PAGE_SIZE); 2300 va_src = MIPS_PHYS_TO_KSEG0(phy_src); 2301 va_dst = MIPS_PHYS_TO_KSEG0(phy_dst); 2302 bcopy((caddr_t)va_src, (caddr_t)va_dst, PAGE_SIZE); 2303 mips_dcache_wbinv_range(va_dst, PAGE_SIZE); 2304 } else { 2305 PMAP_LMEM_MAP2(va_src, phy_src, va_dst, phy_dst); 2306 2307 bcopy((void *)va_src, (void *)va_dst, PAGE_SIZE); 2308 mips_dcache_wbinv_range(va_dst, PAGE_SIZE); 2309 2310 PMAP_LMEM_UNMAP(); 2311 } 2312} 2313 2314/* 2315 * Returns true if the pmap's pv is one of the first 2316 * 16 pvs linked to from this page. This count may 2317 * be changed upwards or downwards in the future; it 2318 * is only necessary that true be returned for a small 2319 * subset of pmaps for proper page aging. 2320 */ 2321boolean_t 2322pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 2323{ 2324 pv_entry_t pv; 2325 int loops = 0; 2326 2327 if (m->flags & PG_FICTITIOUS) 2328 return FALSE; 2329 2330 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2331 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2332 if (pv->pv_pmap == pmap) { 2333 return TRUE; 2334 } 2335 loops++; 2336 if (loops >= 16) 2337 break; 2338 } 2339 return (FALSE); 2340} 2341 2342/* 2343 * Remove all pages from specified address space 2344 * this aids process exit speeds. Also, this code 2345 * is special cased for current process only, but 2346 * can have the more generic (and slightly slower) 2347 * mode enabled. This is much faster than pmap_remove 2348 * in the case of running down an entire address space. 2349 */ 2350void 2351pmap_remove_pages(pmap_t pmap) 2352{ 2353 pt_entry_t *pte, tpte; 2354 pv_entry_t pv, npv; 2355 vm_page_t m; 2356 2357 if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) { 2358 printf("warning: pmap_remove_pages called with non-current pmap\n"); 2359 return; 2360 } 2361 vm_page_lock_queues(); 2362 PMAP_LOCK(pmap); 2363 sched_pin(); 2364 //XXX need to be TAILQ_FOREACH_SAFE ? 2365 for (pv = TAILQ_FIRST(&pmap->pm_pvlist); pv; pv = npv) { 2366 2367 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 2368 if (!pmap_pte_v(pte)) 2369 panic("pmap_remove_pages: page on pm_pvlist has no pte\n"); 2370 tpte = *pte; 2371 2372/* 2373 * We cannot remove wired pages from a process' mapping at this time 2374 */ 2375 if (tpte & PTE_W) { 2376 npv = TAILQ_NEXT(pv, pv_plist); 2377 continue; 2378 } 2379 *pte = is_kernel_pmap(pmap) ? PTE_G : 0; 2380 2381 m = PHYS_TO_VM_PAGE(mips_tlbpfn_to_paddr(tpte)); 2382 KASSERT(m != NULL, 2383 ("pmap_remove_pages: bad tpte %x", tpte)); 2384 2385 pv->pv_pmap->pm_stats.resident_count--; 2386 2387 /* 2388 * Update the vm_page_t clean and reference bits. 2389 */ 2390 if (tpte & PTE_M) { 2391 vm_page_dirty(m); 2392 } 2393 npv = TAILQ_NEXT(pv, pv_plist); 2394 TAILQ_REMOVE(&pv->pv_pmap->pm_pvlist, pv, pv_plist); 2395 2396 m->md.pv_list_count--; 2397 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2398 if (TAILQ_FIRST(&m->md.pv_list) == NULL) { 2399 vm_page_flag_clear(m, PG_WRITEABLE); 2400 } 2401 pmap_unuse_pt(pv->pv_pmap, pv->pv_va, pv->pv_ptem); 2402 free_pv_entry(pv); 2403 } 2404 sched_unpin(); 2405 pmap_invalidate_all(pmap); 2406 PMAP_UNLOCK(pmap); 2407 vm_page_unlock_queues(); 2408} 2409 2410/* 2411 * pmap_testbit tests bits in pte's 2412 * note that the testbit/changebit routines are inline, 2413 * and a lot of things compile-time evaluate. 2414 */ 2415static boolean_t 2416pmap_testbit(vm_page_t m, int bit) 2417{ 2418 pv_entry_t pv; 2419 pt_entry_t *pte; 2420 boolean_t rv = FALSE; 2421 2422 if (m->flags & PG_FICTITIOUS) 2423 return rv; 2424 2425 if (TAILQ_FIRST(&m->md.pv_list) == NULL) 2426 return rv; 2427 2428 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2429 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2430#if defined(PMAP_DIAGNOSTIC) 2431 if (!pv->pv_pmap) { 2432 printf("Null pmap (tb) at va: 0x%x\n", pv->pv_va); 2433 continue; 2434 } 2435#endif 2436 PMAP_LOCK(pv->pv_pmap); 2437 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 2438 rv = (*pte & bit) != 0; 2439 PMAP_UNLOCK(pv->pv_pmap); 2440 if (rv) 2441 break; 2442 } 2443 return (rv); 2444} 2445 2446/* 2447 * this routine is used to modify bits in ptes 2448 */ 2449static __inline void 2450pmap_changebit(vm_page_t m, int bit, boolean_t setem) 2451{ 2452 register pv_entry_t pv; 2453 register pt_entry_t *pte; 2454 2455 if (m->flags & PG_FICTITIOUS) 2456 return; 2457 2458 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2459 /* 2460 * Loop over all current mappings setting/clearing as appropos If 2461 * setting RO do we need to clear the VAC? 2462 */ 2463 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2464#if defined(PMAP_DIAGNOSTIC) 2465 if (!pv->pv_pmap) { 2466 printf("Null pmap (cb) at va: 0x%x\n", pv->pv_va); 2467 continue; 2468 } 2469#endif 2470 2471 PMAP_LOCK(pv->pv_pmap); 2472 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 2473 2474 if (setem) { 2475 *(int *)pte |= bit; 2476 pmap_update_page(pv->pv_pmap, pv->pv_va, *pte); 2477 } else { 2478 vm_offset_t pbits = *(vm_offset_t *)pte; 2479 2480 if (pbits & bit) { 2481 if (bit == PTE_RW) { 2482 if (pbits & PTE_M) { 2483 vm_page_dirty(m); 2484 } 2485 *(int *)pte = (pbits & ~(PTE_M | PTE_RW)) | 2486 PTE_RO; 2487 } else { 2488 *(int *)pte = pbits & ~bit; 2489 } 2490 pmap_update_page(pv->pv_pmap, pv->pv_va, *pte); 2491 } 2492 } 2493 PMAP_UNLOCK(pv->pv_pmap); 2494 } 2495 if (!setem && bit == PTE_RW) 2496 vm_page_flag_clear(m, PG_WRITEABLE); 2497} 2498 2499/* 2500 * pmap_page_wired_mappings: 2501 * 2502 * Return the number of managed mappings to the given physical page 2503 * that are wired. 2504 */ 2505int 2506pmap_page_wired_mappings(vm_page_t m) 2507{ 2508 pv_entry_t pv; 2509 int count; 2510 2511 count = 0; 2512 if ((m->flags & PG_FICTITIOUS) != 0) 2513 return (count); 2514 vm_page_lock_queues(); 2515 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) 2516 if (pv->pv_wired) 2517 count++; 2518 vm_page_unlock_queues(); 2519 return (count); 2520} 2521 2522/* 2523 * Clear the write and modified bits in each of the given page's mappings. 2524 */ 2525void 2526pmap_remove_write(vm_page_t m) 2527{ 2528 pv_entry_t pv, npv; 2529 vm_offset_t va; 2530 pt_entry_t *pte; 2531 2532 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2533 ("pmap_remove_write: page %p is not managed", m)); 2534 2535 /* 2536 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be set by 2537 * another thread while the object is locked. Thus, if PG_WRITEABLE 2538 * is clear, no page table entries need updating. 2539 */ 2540 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 2541 if ((m->oflags & VPO_BUSY) == 0 && 2542 (m->flags & PG_WRITEABLE) == 0) 2543 return; 2544 2545 /* 2546 * Loop over all current mappings setting/clearing as appropos. 2547 */ 2548 vm_page_lock_queues(); 2549 for (pv = TAILQ_FIRST(&m->md.pv_list); pv; pv = npv) { 2550 npv = TAILQ_NEXT(pv, pv_plist); 2551 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 2552 2553 if ((pte == NULL) || !mips_pg_v(*pte)) 2554 panic("page on pm_pvlist has no pte\n"); 2555 2556 va = pv->pv_va; 2557 pmap_protect(pv->pv_pmap, va, va + PAGE_SIZE, 2558 VM_PROT_READ | VM_PROT_EXECUTE); 2559 } 2560 vm_page_flag_clear(m, PG_WRITEABLE); 2561 vm_page_unlock_queues(); 2562} 2563 2564/* 2565 * pmap_ts_referenced: 2566 * 2567 * Return the count of reference bits for a page, clearing all of them. 2568 */ 2569int 2570pmap_ts_referenced(vm_page_t m) 2571{ 2572 if (m->flags & PG_FICTITIOUS) 2573 return (0); 2574 2575 if (m->md.pv_flags & PV_TABLE_REF) { 2576 m->md.pv_flags &= ~PV_TABLE_REF; 2577 return 1; 2578 } 2579 return 0; 2580} 2581 2582/* 2583 * pmap_is_modified: 2584 * 2585 * Return whether or not the specified physical page was modified 2586 * in any physical maps. 2587 */ 2588boolean_t 2589pmap_is_modified(vm_page_t m) 2590{ 2591 boolean_t rv; 2592 2593 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2594 ("pmap_is_modified: page %p is not managed", m)); 2595 2596 /* 2597 * If the page is not VPO_BUSY, then PG_WRITEABLE cannot be 2598 * concurrently set while the object is locked. Thus, if PG_WRITEABLE 2599 * is clear, no PTEs can have PTE_M set. 2600 */ 2601 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 2602 if ((m->oflags & VPO_BUSY) == 0 && 2603 (m->flags & PG_WRITEABLE) == 0) 2604 return (FALSE); 2605 vm_page_lock_queues(); 2606 if (m->md.pv_flags & PV_TABLE_MOD) 2607 rv = TRUE; 2608 else 2609 rv = pmap_testbit(m, PTE_M); 2610 vm_page_unlock_queues(); 2611 return (rv); 2612} 2613 2614/* N/C */ 2615 2616/* 2617 * pmap_is_prefaultable: 2618 * 2619 * Return whether or not the specified virtual address is elgible 2620 * for prefault. 2621 */ 2622boolean_t 2623pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 2624{ 2625 pt_entry_t *pte; 2626 boolean_t rv; 2627 2628 rv = FALSE; 2629 PMAP_LOCK(pmap); 2630 if (*pmap_pde(pmap, addr)) { 2631 pte = pmap_pte(pmap, addr); 2632 rv = (*pte == 0); 2633 } 2634 PMAP_UNLOCK(pmap); 2635 return (rv); 2636} 2637 2638/* 2639 * Clear the modify bits on the specified physical page. 2640 */ 2641void 2642pmap_clear_modify(vm_page_t m) 2643{ 2644 2645 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2646 ("pmap_clear_modify: page %p is not managed", m)); 2647 VM_OBJECT_LOCK_ASSERT(m->object, MA_OWNED); 2648 KASSERT((m->oflags & VPO_BUSY) == 0, 2649 ("pmap_clear_modify: page %p is busy", m)); 2650 2651 /* 2652 * If the page is not PG_WRITEABLE, then no PTEs can have PTE_M set. 2653 * If the object containing the page is locked and the page is not 2654 * VPO_BUSY, then PG_WRITEABLE cannot be concurrently set. 2655 */ 2656 if ((m->flags & PG_WRITEABLE) == 0) 2657 return; 2658 vm_page_lock_queues(); 2659 if (m->md.pv_flags & PV_TABLE_MOD) { 2660 pmap_changebit(m, PTE_M, FALSE); 2661 m->md.pv_flags &= ~PV_TABLE_MOD; 2662 } 2663 vm_page_unlock_queues(); 2664} 2665 2666/* 2667 * pmap_is_referenced: 2668 * 2669 * Return whether or not the specified physical page was referenced 2670 * in any physical maps. 2671 */ 2672boolean_t 2673pmap_is_referenced(vm_page_t m) 2674{ 2675 2676 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2677 ("pmap_is_referenced: page %p is not managed", m)); 2678 return ((m->md.pv_flags & PV_TABLE_REF) != 0); 2679} 2680 2681/* 2682 * pmap_clear_reference: 2683 * 2684 * Clear the reference bit on the specified physical page. 2685 */ 2686void 2687pmap_clear_reference(vm_page_t m) 2688{ 2689 2690 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0, 2691 ("pmap_clear_reference: page %p is not managed", m)); 2692 vm_page_lock_queues(); 2693 if (m->md.pv_flags & PV_TABLE_REF) { 2694 m->md.pv_flags &= ~PV_TABLE_REF; 2695 } 2696 vm_page_unlock_queues(); 2697} 2698 2699/* 2700 * Miscellaneous support routines follow 2701 */ 2702 2703/* 2704 * Map a set of physical memory pages into the kernel virtual 2705 * address space. Return a pointer to where it is mapped. This 2706 * routine is intended to be used for mapping device memory, 2707 * NOT real memory. 2708 */ 2709 2710/* 2711 * Map a set of physical memory pages into the kernel virtual 2712 * address space. Return a pointer to where it is mapped. This 2713 * routine is intended to be used for mapping device memory, 2714 * NOT real memory. 2715 */ 2716void * 2717pmap_mapdev(vm_offset_t pa, vm_size_t size) 2718{ 2719 vm_offset_t va, tmpva, offset; 2720 2721 /* 2722 * KSEG1 maps only first 512M of phys address space. For 2723 * pa > 0x20000000 we should make proper mapping * using pmap_kenter. 2724 */ 2725 if ((pa + size - 1) < MIPS_KSEG0_LARGEST_PHYS) 2726 return (void *)MIPS_PHYS_TO_KSEG1(pa); 2727 else { 2728 offset = pa & PAGE_MASK; 2729 size = roundup(size + offset, PAGE_SIZE); 2730 2731 va = kmem_alloc_nofault(kernel_map, size); 2732 if (!va) 2733 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 2734 pa = trunc_page(pa); 2735 for (tmpva = va; size > 0;) { 2736 pmap_kenter(tmpva, pa); 2737 size -= PAGE_SIZE; 2738 tmpva += PAGE_SIZE; 2739 pa += PAGE_SIZE; 2740 } 2741 } 2742 2743 return ((void *)(va + offset)); 2744} 2745 2746void 2747pmap_unmapdev(vm_offset_t va, vm_size_t size) 2748{ 2749 vm_offset_t base, offset, tmpva; 2750 2751 /* If the address is within KSEG1 then there is nothing to do */ 2752 if (va >= MIPS_KSEG1_START && va <= MIPS_KSEG1_END) 2753 return; 2754 2755 base = trunc_page(va); 2756 offset = va & PAGE_MASK; 2757 size = roundup(size + offset, PAGE_SIZE); 2758 for (tmpva = base; tmpva < base + size; tmpva += PAGE_SIZE) 2759 pmap_kremove(tmpva); 2760 kmem_free(kernel_map, base, size); 2761} 2762 2763/* 2764 * perform the pmap work for mincore 2765 */ 2766int 2767pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa) 2768{ 2769 pt_entry_t *ptep, pte; 2770 vm_offset_t pa; 2771 vm_page_t m; 2772 int val; 2773 boolean_t managed; 2774 2775 PMAP_LOCK(pmap); 2776retry: 2777 ptep = pmap_pte(pmap, addr); 2778 pte = (ptep != NULL) ? *ptep : 0; 2779 if (!mips_pg_v(pte)) { 2780 val = 0; 2781 goto out; 2782 } 2783 val = MINCORE_INCORE; 2784 if ((pte & PTE_M) != 0) 2785 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 2786 pa = mips_tlbpfn_to_paddr(pte); 2787 managed = page_is_managed(pa); 2788 if (managed) { 2789 /* 2790 * This may falsely report the given address as 2791 * MINCORE_REFERENCED. Unfortunately, due to the lack of 2792 * per-PTE reference information, it is impossible to 2793 * determine if the address is MINCORE_REFERENCED. 2794 */ 2795 m = PHYS_TO_VM_PAGE(pa); 2796 if ((m->flags & PG_REFERENCED) != 0) 2797 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 2798 } 2799 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) != 2800 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && managed) { 2801 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */ 2802 if (vm_page_pa_tryrelock(pmap, pa, locked_pa)) 2803 goto retry; 2804 } else 2805out: 2806 PA_UNLOCK_COND(*locked_pa); 2807 PMAP_UNLOCK(pmap); 2808 return (val); 2809} 2810 2811void 2812pmap_activate(struct thread *td) 2813{ 2814 pmap_t pmap, oldpmap; 2815 struct proc *p = td->td_proc; 2816 2817 critical_enter(); 2818 2819 pmap = vmspace_pmap(p->p_vmspace); 2820 oldpmap = PCPU_GET(curpmap); 2821 2822 if (oldpmap) 2823 atomic_clear_32(&oldpmap->pm_active, PCPU_GET(cpumask)); 2824 atomic_set_32(&pmap->pm_active, PCPU_GET(cpumask)); 2825 pmap_asid_alloc(pmap); 2826 if (td == curthread) { 2827 PCPU_SET(segbase, pmap->pm_segtab); 2828 MachSetPID(pmap->pm_asid[PCPU_GET(cpuid)].asid); 2829 } 2830 2831 PCPU_SET(curpmap, pmap); 2832 critical_exit(); 2833} 2834 2835void 2836pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 2837{ 2838} 2839 2840/* 2841 * Increase the starting virtual address of the given mapping if a 2842 * different alignment might result in more superpage mappings. 2843 */ 2844void 2845pmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 2846 vm_offset_t *addr, vm_size_t size) 2847{ 2848 vm_offset_t superpage_offset; 2849 2850 if (size < NBSEG) 2851 return; 2852 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 2853 offset += ptoa(object->pg_color); 2854 superpage_offset = offset & SEGOFSET; 2855 if (size - ((NBSEG - superpage_offset) & SEGOFSET) < NBSEG || 2856 (*addr & SEGOFSET) == superpage_offset) 2857 return; 2858 if ((*addr & SEGOFSET) < superpage_offset) 2859 *addr = (*addr & ~SEGOFSET) + superpage_offset; 2860 else 2861 *addr = ((*addr + SEGOFSET) & ~SEGOFSET) + superpage_offset; 2862} 2863 2864/* 2865 * Increase the starting virtual address of the given mapping so 2866 * that it is aligned to not be the second page in a TLB entry. 2867 * This routine assumes that the length is appropriately-sized so 2868 * that the allocation does not share a TLB entry at all if required. 2869 */ 2870void 2871pmap_align_tlb(vm_offset_t *addr) 2872{ 2873 if ((*addr & PAGE_SIZE) == 0) 2874 return; 2875 *addr += PAGE_SIZE; 2876 return; 2877} 2878 2879int pmap_pid_dump(int pid); 2880 2881int 2882pmap_pid_dump(int pid) 2883{ 2884 pmap_t pmap; 2885 struct proc *p; 2886 int npte = 0; 2887 int index; 2888 2889 sx_slock(&allproc_lock); 2890 LIST_FOREACH(p, &allproc, p_list) { 2891 if (p->p_pid != pid) 2892 continue; 2893 2894 if (p->p_vmspace) { 2895 int i, j; 2896 2897 printf("vmspace is %p\n", 2898 p->p_vmspace); 2899 index = 0; 2900 pmap = vmspace_pmap(p->p_vmspace); 2901 printf("pmap asid:%x generation:%x\n", 2902 pmap->pm_asid[0].asid, 2903 pmap->pm_asid[0].gen); 2904 for (i = 0; i < NUSERPGTBLS; i++) { 2905 pd_entry_t *pde; 2906 pt_entry_t *pte; 2907 unsigned base = i << SEGSHIFT; 2908 2909 pde = &pmap->pm_segtab[i]; 2910 if (pde && pmap_pde_v(pde)) { 2911 for (j = 0; j < 1024; j++) { 2912 vm_offset_t va = base + 2913 (j << PAGE_SHIFT); 2914 2915 pte = pmap_pte(pmap, va); 2916 if (pte && pmap_pte_v(pte)) { 2917 vm_offset_t pa; 2918 vm_page_t m; 2919 2920 pa = mips_tlbpfn_to_paddr(*pte); 2921 m = PHYS_TO_VM_PAGE(pa); 2922 printf("va: %p, pt: %p, h: %d, w: %d, f: 0x%x", 2923 (void *)va, 2924 (void *)pa, 2925 m->hold_count, 2926 m->wire_count, 2927 m->flags); 2928 npte++; 2929 index++; 2930 if (index >= 2) { 2931 index = 0; 2932 printf("\n"); 2933 } else { 2934 printf(" "); 2935 } 2936 } 2937 } 2938 } 2939 } 2940 } else { 2941 printf("Process pid:%d has no vm_space\n", pid); 2942 } 2943 break; 2944 } 2945 sx_sunlock(&allproc_lock); 2946 return npte; 2947} 2948 2949 2950#if defined(DEBUG) 2951 2952static void pads(pmap_t pm); 2953void pmap_pvdump(vm_offset_t pa); 2954 2955/* print address space of pmap*/ 2956static void 2957pads(pmap_t pm) 2958{ 2959 unsigned va, i, j; 2960 pt_entry_t *ptep; 2961 2962 if (pm == kernel_pmap) 2963 return; 2964 for (i = 0; i < NPTEPG; i++) 2965 if (pm->pm_segtab[i]) 2966 for (j = 0; j < NPTEPG; j++) { 2967 va = (i << SEGSHIFT) + (j << PAGE_SHIFT); 2968 if (pm == kernel_pmap && va < KERNBASE) 2969 continue; 2970 if (pm != kernel_pmap && 2971 va >= VM_MAXUSER_ADDRESS) 2972 continue; 2973 ptep = pmap_pte(pm, va); 2974 if (pmap_pte_v(ptep)) 2975 printf("%x:%x ", va, *(int *)ptep); 2976 } 2977 2978} 2979 2980void 2981pmap_pvdump(vm_offset_t pa) 2982{ 2983 register pv_entry_t pv; 2984 vm_page_t m; 2985 2986 printf("pa %x", pa); 2987 m = PHYS_TO_VM_PAGE(pa); 2988 for (pv = TAILQ_FIRST(&m->md.pv_list); pv; 2989 pv = TAILQ_NEXT(pv, pv_list)) { 2990 printf(" -> pmap %p, va %x", (void *)pv->pv_pmap, pv->pv_va); 2991 pads(pv->pv_pmap); 2992 } 2993 printf(" "); 2994} 2995 2996/* N/C */ 2997#endif 2998 2999 3000/* 3001 * Allocate TLB address space tag (called ASID or TLBPID) and return it. 3002 * It takes almost as much or more time to search the TLB for a 3003 * specific ASID and flush those entries as it does to flush the entire TLB. 3004 * Therefore, when we allocate a new ASID, we just take the next number. When 3005 * we run out of numbers, we flush the TLB, increment the generation count 3006 * and start over. ASID zero is reserved for kernel use. 3007 */ 3008static void 3009pmap_asid_alloc(pmap) 3010 pmap_t pmap; 3011{ 3012 if (pmap->pm_asid[PCPU_GET(cpuid)].asid != PMAP_ASID_RESERVED && 3013 pmap->pm_asid[PCPU_GET(cpuid)].gen == PCPU_GET(asid_generation)); 3014 else { 3015 if (PCPU_GET(next_asid) == pmap_max_asid) { 3016 MIPS_TBIAP(); 3017 PCPU_SET(asid_generation, 3018 (PCPU_GET(asid_generation) + 1) & ASIDGEN_MASK); 3019 if (PCPU_GET(asid_generation) == 0) { 3020 PCPU_SET(asid_generation, 1); 3021 } 3022 PCPU_SET(next_asid, 1); /* 0 means invalid */ 3023 } 3024 pmap->pm_asid[PCPU_GET(cpuid)].asid = PCPU_GET(next_asid); 3025 pmap->pm_asid[PCPU_GET(cpuid)].gen = PCPU_GET(asid_generation); 3026 PCPU_SET(next_asid, PCPU_GET(next_asid) + 1); 3027 } 3028} 3029 3030int 3031page_is_managed(vm_offset_t pa) 3032{ 3033 vm_offset_t pgnum = mips_btop(pa); 3034 3035 if (pgnum >= first_page) { 3036 vm_page_t m; 3037 3038 m = PHYS_TO_VM_PAGE(pa); 3039 if (m == NULL) 3040 return 0; 3041 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) 3042 return 1; 3043 } 3044 return 0; 3045} 3046 3047static int 3048init_pte_prot(vm_offset_t va, vm_page_t m, vm_prot_t prot) 3049{ 3050 int rw = 0; 3051 3052 if (!(prot & VM_PROT_WRITE)) 3053 rw = PTE_ROPAGE; 3054 else { 3055 if (va >= VM_MIN_KERNEL_ADDRESS) { 3056 /* 3057 * Don't bother to trap on kernel writes, just 3058 * record page as dirty. 3059 */ 3060 rw = PTE_RWPAGE; 3061 vm_page_dirty(m); 3062 } else if ((m->md.pv_flags & PV_TABLE_MOD) || 3063 m->dirty == VM_PAGE_BITS_ALL) 3064 rw = PTE_RWPAGE; 3065 else 3066 rw = PTE_CWPAGE; 3067 vm_page_flag_set(m, PG_WRITEABLE); 3068 } 3069 return rw; 3070} 3071 3072/* 3073 * pmap_set_modified: 3074 * 3075 * Sets the page modified and reference bits for the specified page. 3076 */ 3077void 3078pmap_set_modified(vm_offset_t pa) 3079{ 3080 3081 PHYS_TO_VM_PAGE(pa)->md.pv_flags |= (PV_TABLE_REF | PV_TABLE_MOD); 3082} 3083 3084/* 3085 * Routine: pmap_kextract 3086 * Function: 3087 * Extract the physical page address associated 3088 * virtual address. 3089 */ 3090 /* PMAP_INLINE */ vm_offset_t 3091pmap_kextract(vm_offset_t va) 3092{ 3093 vm_offset_t pa = 0; 3094 3095 if (va < MIPS_KSEG0_START) { 3096 /* user virtual address */ 3097 pt_entry_t *ptep; 3098 3099 if (curproc && curproc->p_vmspace) { 3100 ptep = pmap_pte(&curproc->p_vmspace->vm_pmap, va); 3101 if (ptep) 3102 pa = mips_tlbpfn_to_paddr(*ptep) | 3103 (va & PAGE_MASK); 3104 } 3105 } else if (va >= MIPS_KSEG0_START && 3106 va < MIPS_KSEG1_START) 3107 pa = MIPS_KSEG0_TO_PHYS(va); 3108 else if (va >= MIPS_KSEG1_START && 3109 va < MIPS_KSEG2_START) 3110 pa = MIPS_KSEG1_TO_PHYS(va); 3111 else if (va >= MIPS_KSEG2_START && va < VM_MAX_KERNEL_ADDRESS) { 3112 pt_entry_t *ptep; 3113 3114 /* Is the kernel pmap initialized? */ 3115 if (kernel_pmap->pm_active) { 3116 /* Its inside the virtual address range */ 3117 ptep = pmap_pte(kernel_pmap, va); 3118 if (ptep) 3119 pa = mips_tlbpfn_to_paddr(*ptep) | 3120 (va & PAGE_MASK); 3121 } 3122 } 3123 return pa; 3124} 3125 3126void 3127pmap_flush_pvcache(vm_page_t m) 3128{ 3129 pv_entry_t pv; 3130 3131 if (m != NULL) { 3132 for (pv = TAILQ_FIRST(&m->md.pv_list); pv; 3133 pv = TAILQ_NEXT(pv, pv_list)) { 3134 mips_dcache_wbinv_range_index(pv->pv_va, PAGE_SIZE); 3135 } 3136 } 3137} 3138 3139void 3140pmap_save_tlb(void) 3141{ 3142 int tlbno, cpu; 3143 3144 cpu = PCPU_GET(cpuid); 3145 3146 for (tlbno = 0; tlbno < num_tlbentries; ++tlbno) 3147 MachTLBRead(tlbno, &tlbstash[cpu][tlbno]); 3148} 3149 3150#ifdef DDB 3151#include <ddb/ddb.h> 3152 3153DB_SHOW_COMMAND(tlb, ddb_dump_tlb) 3154{ 3155 int cpu, tlbno; 3156 struct tlb *tlb; 3157 3158 if (have_addr) 3159 cpu = ((addr >> 4) % 16) * 10 + (addr % 16); 3160 else 3161 cpu = PCPU_GET(cpuid); 3162 3163 if (cpu < 0 || cpu >= mp_ncpus) { 3164 db_printf("Invalid CPU %d\n", cpu); 3165 return; 3166 } else 3167 db_printf("CPU %d:\n", cpu); 3168 3169 if (cpu == PCPU_GET(cpuid)) 3170 pmap_save_tlb(); 3171 3172 for (tlbno = 0; tlbno < num_tlbentries; ++tlbno) { 3173 tlb = &tlbstash[cpu][tlbno]; 3174 if (tlb->tlb_lo0 & PTE_V || tlb->tlb_lo1 & PTE_V) { 3175 printf("TLB %2d vad 0x%0lx ", 3176 tlbno, (long)(tlb->tlb_hi & 0xffffff00)); 3177 } else { 3178 printf("TLB*%2d vad 0x%0lx ", 3179 tlbno, (long)(tlb->tlb_hi & 0xffffff00)); 3180 } 3181 printf("0=0x%0lx ", pfn_to_vad((long)tlb->tlb_lo0)); 3182 printf("%c", tlb->tlb_lo0 & PTE_V ? 'V' : '-'); 3183 printf("%c", tlb->tlb_lo0 & PTE_M ? 'M' : '-'); 3184 printf("%c", tlb->tlb_lo0 & PTE_G ? 'G' : '-'); 3185 printf(" atr %x ", (tlb->tlb_lo0 >> 3) & 7); 3186 printf("1=0x%0lx ", pfn_to_vad((long)tlb->tlb_lo1)); 3187 printf("%c", tlb->tlb_lo1 & PTE_V ? 'V' : '-'); 3188 printf("%c", tlb->tlb_lo1 & PTE_M ? 'M' : '-'); 3189 printf("%c", tlb->tlb_lo1 & PTE_G ? 'G' : '-'); 3190 printf(" atr %x ", (tlb->tlb_lo1 >> 3) & 7); 3191 printf(" sz=%x pid=%x\n", tlb->tlb_mask, 3192 (tlb->tlb_hi & 0x000000ff)); 3193 } 3194} 3195#endif /* DDB */ 3196