pmap.c revision 207796
1/* 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * Copyright (c) 1994 John S. Dyson 5 * All rights reserved. 6 * Copyright (c) 1994 David Greenman 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * the Systems Programming Group of the University of Utah Computer 11 * Science Department and William Jolitz of UUNET Technologies Inc. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 38 * from: src/sys/i386/i386/pmap.c,v 1.250.2.8 2000/11/21 00:09:14 ps 39 * JNPR: pmap.c,v 1.11.2.1 2007/08/16 11:51:06 girish 40 */ 41 42/* 43 * Manages physical address maps. 44 * 45 * In addition to hardware address maps, this 46 * module is called upon to provide software-use-only 47 * maps which may or may not be stored in the same 48 * form as hardware maps. These pseudo-maps are 49 * used to store intermediate results from copy 50 * operations to and from address spaces. 51 * 52 * Since the information managed by this module is 53 * also stored by the logical address mapping module, 54 * this module may throw away valid virtual-to-physical 55 * mappings at almost any time. However, invalidations 56 * of virtual-to-physical mappings must be done as 57 * requested. 58 * 59 * In order to cope with hardware architectures which 60 * make virtual-to-physical map invalidates expensive, 61 * this module may delay invalidate or reduced protection 62 * operations until such time as they are actually 63 * necessary. This module is given full information as 64 * to which processors are currently using which maps, 65 * and to when physical maps must be made correct. 66 */ 67 68#include <sys/cdefs.h> 69__FBSDID("$FreeBSD: head/sys/mips/mips/pmap.c 207796 2010-05-08 20:34:01Z alc $"); 70 71#include "opt_ddb.h" 72#include "opt_msgbuf.h" 73#include <sys/param.h> 74#include <sys/systm.h> 75#include <sys/proc.h> 76#include <sys/msgbuf.h> 77#include <sys/vmmeter.h> 78#include <sys/mman.h> 79#include <sys/smp.h> 80 81#include <vm/vm.h> 82#include <vm/vm_param.h> 83#include <sys/lock.h> 84#include <sys/mutex.h> 85#include <vm/vm_kern.h> 86#include <vm/vm_page.h> 87#include <vm/vm_map.h> 88#include <vm/vm_object.h> 89#include <vm/vm_extern.h> 90#include <vm/vm_pageout.h> 91#include <vm/vm_pager.h> 92#include <vm/uma.h> 93#include <sys/pcpu.h> 94#include <sys/sched.h> 95#ifdef SMP 96#include <sys/smp.h> 97#endif 98 99#include <machine/cache.h> 100#include <machine/md_var.h> 101 102#if defined(DIAGNOSTIC) 103#define PMAP_DIAGNOSTIC 104#endif 105 106#undef PMAP_DEBUG 107 108#ifndef PMAP_SHPGPERPROC 109#define PMAP_SHPGPERPROC 200 110#endif 111 112#if !defined(PMAP_DIAGNOSTIC) 113#define PMAP_INLINE __inline 114#else 115#define PMAP_INLINE 116#endif 117 118/* 119 * Get PDEs and PTEs for user/kernel address space 120 */ 121#define pmap_pde(m, v) (&((m)->pm_segtab[(vm_offset_t)(v) >> SEGSHIFT])) 122#define segtab_pde(m, v) (m[(vm_offset_t)(v) >> SEGSHIFT]) 123 124#define pmap_pte_w(pte) ((*(int *)pte & PTE_W) != 0) 125#define pmap_pde_v(pte) ((*(int *)pte) != 0) 126#define pmap_pte_m(pte) ((*(int *)pte & PTE_M) != 0) 127#define pmap_pte_v(pte) ((*(int *)pte & PTE_V) != 0) 128 129#define pmap_pte_set_w(pte, v) ((v)?(*(int *)pte |= PTE_W):(*(int *)pte &= ~PTE_W)) 130#define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v))) 131 132#define MIPS_SEGSIZE (1L << SEGSHIFT) 133#define mips_segtrunc(va) ((va) & ~(MIPS_SEGSIZE-1)) 134#define pmap_TLB_invalidate_all() MIPS_TBIAP() 135#define pmap_va_asid(pmap, va) ((va) | ((pmap)->pm_asid[PCPU_GET(cpuid)].asid << VMTLB_PID_SHIFT)) 136#define is_kernel_pmap(x) ((x) == kernel_pmap) 137 138struct pmap kernel_pmap_store; 139pd_entry_t *kernel_segmap; 140 141vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 142vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 143 144static int nkpt; 145unsigned pmap_max_asid; /* max ASID supported by the system */ 146 147 148#define PMAP_ASID_RESERVED 0 149 150vm_offset_t kernel_vm_end; 151 152static struct tlb tlbstash[MAXCPU][MIPS_MAX_TLB_ENTRIES]; 153 154static void pmap_asid_alloc(pmap_t pmap); 155 156/* 157 * Data for the pv entry allocation mechanism 158 */ 159static uma_zone_t pvzone; 160static struct vm_object pvzone_obj; 161static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 162 163static PMAP_INLINE void free_pv_entry(pv_entry_t pv); 164static pv_entry_t get_pv_entry(pmap_t locked_pmap); 165static __inline void pmap_changebit(vm_page_t m, int bit, boolean_t setem); 166 167static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, 168 vm_page_t m, vm_prot_t prot, vm_page_t mpte); 169static int pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va); 170static void pmap_remove_page(struct pmap *pmap, vm_offset_t va); 171static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, vm_offset_t va); 172static boolean_t pmap_testbit(vm_page_t m, int bit); 173static void 174pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t mpte, 175 vm_page_t m, boolean_t wired); 176static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_page_t mpte, 177 vm_offset_t va, vm_page_t m); 178 179static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags); 180 181static vm_page_t _pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags); 182static int pmap_unuse_pt(pmap_t, vm_offset_t, vm_page_t); 183static int init_pte_prot(vm_offset_t va, vm_page_t m, vm_prot_t prot); 184static void pmap_TLB_invalidate_kernel(vm_offset_t); 185static void pmap_TLB_update_kernel(vm_offset_t, pt_entry_t); 186 187#ifdef SMP 188static void pmap_invalidate_page_action(void *arg); 189static void pmap_invalidate_all_action(void *arg); 190static void pmap_update_page_action(void *arg); 191 192#endif 193 194struct local_sysmaps { 195 struct mtx lock; 196 vm_offset_t base; 197 uint16_t valid1, valid2; 198}; 199 200/* This structure is for large memory 201 * above 512Meg. We can't (in 32 bit mode) 202 * just use the direct mapped MIPS_KSEG0_TO_PHYS() 203 * macros since we can't see the memory and must 204 * map it in when we need to access it. In 64 205 * bit mode this goes away. 206 */ 207static struct local_sysmaps sysmap_lmem[MAXCPU]; 208caddr_t virtual_sys_start = (caddr_t)0; 209 210#define PMAP_LMEM_MAP1(va, phys) \ 211 int cpu; \ 212 struct local_sysmaps *sysm; \ 213 pt_entry_t *pte, npte; \ 214 \ 215 cpu = PCPU_GET(cpuid); \ 216 sysm = &sysmap_lmem[cpu]; \ 217 PMAP_LGMEM_LOCK(sysm); \ 218 intr = intr_disable(); \ 219 sched_pin(); \ 220 va = sysm->base; \ 221 npte = mips_paddr_to_tlbpfn(phys) | \ 222 PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; \ 223 pte = pmap_pte(kernel_pmap, va); \ 224 *pte = npte; \ 225 sysm->valid1 = 1; 226 227#define PMAP_LMEM_MAP2(va1, phys1, va2, phys2) \ 228 int cpu; \ 229 struct local_sysmaps *sysm; \ 230 pt_entry_t *pte, npte; \ 231 \ 232 cpu = PCPU_GET(cpuid); \ 233 sysm = &sysmap_lmem[cpu]; \ 234 PMAP_LGMEM_LOCK(sysm); \ 235 intr = intr_disable(); \ 236 sched_pin(); \ 237 va1 = sysm->base; \ 238 va2 = sysm->base + PAGE_SIZE; \ 239 npte = mips_paddr_to_tlbpfn(phys1) | \ 240 PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; \ 241 pte = pmap_pte(kernel_pmap, va1); \ 242 *pte = npte; \ 243 npte = mips_paddr_to_tlbpfn(phys2) | \ 244 PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; \ 245 pte = pmap_pte(kernel_pmap, va2); \ 246 *pte = npte; \ 247 sysm->valid1 = 1; \ 248 sysm->valid2 = 1; 249 250#define PMAP_LMEM_UNMAP() \ 251 pte = pmap_pte(kernel_pmap, sysm->base); \ 252 *pte = PTE_G; \ 253 pmap_TLB_invalidate_kernel(sysm->base); \ 254 sysm->valid1 = 0; \ 255 pte = pmap_pte(kernel_pmap, sysm->base + PAGE_SIZE); \ 256 *pte = PTE_G; \ 257 pmap_TLB_invalidate_kernel(sysm->base + PAGE_SIZE); \ 258 sysm->valid2 = 0; \ 259 sched_unpin(); \ 260 intr_restore(intr); \ 261 PMAP_LGMEM_UNLOCK(sysm); 262 263pd_entry_t 264pmap_segmap(pmap_t pmap, vm_offset_t va) 265{ 266 if (pmap->pm_segtab) 267 return (pmap->pm_segtab[((vm_offset_t)(va) >> SEGSHIFT)]); 268 else 269 return ((pd_entry_t)0); 270} 271 272/* 273 * Routine: pmap_pte 274 * Function: 275 * Extract the page table entry associated 276 * with the given map/virtual_address pair. 277 */ 278pt_entry_t * 279pmap_pte(pmap_t pmap, vm_offset_t va) 280{ 281 pt_entry_t *pdeaddr; 282 283 if (pmap) { 284 pdeaddr = (pt_entry_t *)pmap_segmap(pmap, va); 285 if (pdeaddr) { 286 return pdeaddr + vad_to_pte_offset(va); 287 } 288 } 289 return ((pt_entry_t *)0); 290} 291 292 293vm_offset_t 294pmap_steal_memory(vm_size_t size) 295{ 296 vm_size_t bank_size; 297 vm_offset_t pa, va; 298 299 size = round_page(size); 300 301 bank_size = phys_avail[1] - phys_avail[0]; 302 while (size > bank_size) { 303 int i; 304 305 for (i = 0; phys_avail[i + 2]; i += 2) { 306 phys_avail[i] = phys_avail[i + 2]; 307 phys_avail[i + 1] = phys_avail[i + 3]; 308 } 309 phys_avail[i] = 0; 310 phys_avail[i + 1] = 0; 311 if (!phys_avail[0]) 312 panic("pmap_steal_memory: out of memory"); 313 bank_size = phys_avail[1] - phys_avail[0]; 314 } 315 316 pa = phys_avail[0]; 317 phys_avail[0] += size; 318 if (pa >= MIPS_KSEG0_LARGEST_PHYS) { 319 panic("Out of memory below 512Meg?"); 320 } 321 va = MIPS_PHYS_TO_KSEG0(pa); 322 bzero((caddr_t)va, size); 323 return va; 324} 325 326/* 327 * Bootstrap the system enough to run with virtual memory. This 328 * assumes that the phys_avail array has been initialized. 329 */ 330void 331pmap_bootstrap(void) 332{ 333 pt_entry_t *pgtab; 334 pt_entry_t *pte; 335 int i, j; 336 int memory_larger_than_512meg = 0; 337 338 /* Sort. */ 339again: 340 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 341 /* 342 * Keep the memory aligned on page boundary. 343 */ 344 phys_avail[i] = round_page(phys_avail[i]); 345 phys_avail[i + 1] = trunc_page(phys_avail[i + 1]); 346 347 if (phys_avail[i + 1] >= MIPS_KSEG0_LARGEST_PHYS) 348 memory_larger_than_512meg++; 349 if (i < 2) 350 continue; 351 if (phys_avail[i - 2] > phys_avail[i]) { 352 vm_paddr_t ptemp[2]; 353 354 355 ptemp[0] = phys_avail[i + 0]; 356 ptemp[1] = phys_avail[i + 1]; 357 358 phys_avail[i + 0] = phys_avail[i - 2]; 359 phys_avail[i + 1] = phys_avail[i - 1]; 360 361 phys_avail[i - 2] = ptemp[0]; 362 phys_avail[i - 1] = ptemp[1]; 363 goto again; 364 } 365 } 366 367 /* 368 * Copy the phys_avail[] array before we start stealing memory from it. 369 */ 370 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 371 physmem_desc[i] = phys_avail[i]; 372 physmem_desc[i + 1] = phys_avail[i + 1]; 373 } 374 375 Maxmem = atop(phys_avail[i - 1]); 376 377 if (bootverbose) { 378 printf("Physical memory chunk(s):\n"); 379 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 380 vm_paddr_t size; 381 382 size = phys_avail[i + 1] - phys_avail[i]; 383 printf("%#08jx - %#08jx, %ju bytes (%ju pages)\n", 384 (uintmax_t) phys_avail[i], 385 (uintmax_t) phys_avail[i + 1] - 1, 386 (uintmax_t) size, (uintmax_t) size / PAGE_SIZE); 387 } 388 printf("Maxmem is 0x%0lx\n", ptoa(Maxmem)); 389 } 390 /* 391 * Steal the message buffer from the beginning of memory. 392 */ 393 msgbufp = (struct msgbuf *)pmap_steal_memory(MSGBUF_SIZE); 394 msgbufinit(msgbufp, MSGBUF_SIZE); 395 396 /* 397 * Steal thread0 kstack. 398 */ 399 kstack0 = pmap_steal_memory(KSTACK_PAGES << PAGE_SHIFT); 400 401 402 virtual_avail = VM_MIN_KERNEL_ADDRESS; 403 virtual_end = VM_MAX_KERNEL_ADDRESS; 404 405#ifdef SMP 406 /* 407 * Steal some virtual address space to map the pcpu area. 408 */ 409 virtual_avail = roundup2(virtual_avail, PAGE_SIZE * 2); 410 pcpup = (struct pcpu *)virtual_avail; 411 virtual_avail += PAGE_SIZE * 2; 412 413 /* 414 * Initialize the wired TLB entry mapping the pcpu region for 415 * the BSP at 'pcpup'. Up until this point we were operating 416 * with the 'pcpup' for the BSP pointing to a virtual address 417 * in KSEG0 so there was no need for a TLB mapping. 418 */ 419 mips_pcpu_tlb_init(PCPU_ADDR(0)); 420 421 if (bootverbose) 422 printf("pcpu is available at virtual address %p.\n", pcpup); 423#endif 424 425 /* 426 * Steal some virtual space that will not be in kernel_segmap. This 427 * va memory space will be used to map in kernel pages that are 428 * outside the 512Meg region. Note that we only do this steal when 429 * we do have memory in this region, that way for systems with 430 * smaller memory we don't "steal" any va ranges :-) 431 */ 432 if (memory_larger_than_512meg) { 433 for (i = 0; i < MAXCPU; i++) { 434 sysmap_lmem[i].base = virtual_avail; 435 virtual_avail += PAGE_SIZE * 2; 436 sysmap_lmem[i].valid1 = sysmap_lmem[i].valid2 = 0; 437 PMAP_LGMEM_LOCK_INIT(&sysmap_lmem[i]); 438 } 439 } 440 virtual_sys_start = (caddr_t)virtual_avail; 441 /* 442 * Allocate segment table for the kernel 443 */ 444 kernel_segmap = (pd_entry_t *)pmap_steal_memory(PAGE_SIZE); 445 446 /* 447 * Allocate second level page tables for the kernel 448 */ 449 nkpt = NKPT; 450 if (memory_larger_than_512meg) { 451 /* 452 * If we have a large memory system we CANNOT afford to hit 453 * pmap_growkernel() and allocate memory. Since we MAY end 454 * up with a page that is NOT mappable. For that reason we 455 * up front grab more. Normall NKPT is 120 (YMMV see pmap.h) 456 * this gives us 480meg of kernel virtual addresses at the 457 * cost of 120 pages (each page gets us 4 Meg). Since the 458 * kernel starts at virtual_avail, we can use this to 459 * calculate how many entris are left from there to the end 460 * of the segmap, we want to allocate all of it, which would 461 * be somewhere above 0xC0000000 - 0xFFFFFFFF which results 462 * in about 256 entries or so instead of the 120. 463 */ 464 nkpt = (PAGE_SIZE / sizeof(pd_entry_t)) - (virtual_avail >> SEGSHIFT); 465 } 466 pgtab = (pt_entry_t *)pmap_steal_memory(PAGE_SIZE * nkpt); 467 468 /* 469 * The R[4-7]?00 stores only one copy of the Global bit in the 470 * translation lookaside buffer for each 2 page entry. Thus invalid 471 * entrys must have the Global bit set so when Entry LO and Entry HI 472 * G bits are anded together they will produce a global bit to store 473 * in the tlb. 474 */ 475 for (i = 0, pte = pgtab; i < (nkpt * NPTEPG); i++, pte++) 476 *pte = PTE_G; 477 478 /* 479 * The segment table contains the KVA of the pages in the second 480 * level page table. 481 */ 482 for (i = 0, j = (virtual_avail >> SEGSHIFT); i < nkpt; i++, j++) 483 kernel_segmap[j] = (pd_entry_t)(pgtab + (i * NPTEPG)); 484 485 /* 486 * The kernel's pmap is statically allocated so we don't have to use 487 * pmap_create, which is unlikely to work correctly at this part of 488 * the boot sequence (XXX and which no longer exists). 489 */ 490 PMAP_LOCK_INIT(kernel_pmap); 491 kernel_pmap->pm_segtab = kernel_segmap; 492 kernel_pmap->pm_active = ~0; 493 TAILQ_INIT(&kernel_pmap->pm_pvlist); 494 kernel_pmap->pm_asid[0].asid = PMAP_ASID_RESERVED; 495 kernel_pmap->pm_asid[0].gen = 0; 496 pmap_max_asid = VMNUM_PIDS; 497 MachSetPID(0); 498} 499 500/* 501 * Initialize a vm_page's machine-dependent fields. 502 */ 503void 504pmap_page_init(vm_page_t m) 505{ 506 507 TAILQ_INIT(&m->md.pv_list); 508 m->md.pv_list_count = 0; 509 m->md.pv_flags = 0; 510} 511 512/* 513 * Initialize the pmap module. 514 * Called by vm_init, to initialize any structures that the pmap 515 * system needs to map virtual memory. 516 * pmap_init has been enhanced to support in a fairly consistant 517 * way, discontiguous physical memory. 518 */ 519void 520pmap_init(void) 521{ 522 523 /* 524 * Initialize the address space (zone) for the pv entries. Set a 525 * high water mark so that the system can recover from excessive 526 * numbers of pv entries. 527 */ 528 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL, 529 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 530 pv_entry_max = PMAP_SHPGPERPROC * maxproc + cnt.v_page_count; 531 pv_entry_high_water = 9 * (pv_entry_max / 10); 532 uma_zone_set_obj(pvzone, &pvzone_obj, pv_entry_max); 533} 534 535/*************************************************** 536 * Low level helper routines..... 537 ***************************************************/ 538 539#if defined(PMAP_DIAGNOSTIC) 540 541/* 542 * This code checks for non-writeable/modified pages. 543 * This should be an invalid condition. 544 */ 545static int 546pmap_nw_modified(pt_entry_t pte) 547{ 548 if ((pte & (PTE_M | PTE_RO)) == (PTE_M | PTE_RO)) 549 return (1); 550 else 551 return (0); 552} 553 554#endif 555 556static void 557pmap_invalidate_all(pmap_t pmap) 558{ 559#ifdef SMP 560 smp_rendezvous(0, pmap_invalidate_all_action, 0, (void *)pmap); 561} 562 563static void 564pmap_invalidate_all_action(void *arg) 565{ 566 pmap_t pmap = (pmap_t)arg; 567 568#endif 569 570 if (pmap->pm_active & PCPU_GET(cpumask)) { 571 pmap_TLB_invalidate_all(); 572 } else 573 pmap->pm_asid[PCPU_GET(cpuid)].gen = 0; 574} 575 576struct pmap_invalidate_page_arg { 577 pmap_t pmap; 578 vm_offset_t va; 579}; 580 581static __inline void 582pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 583{ 584#ifdef SMP 585 struct pmap_invalidate_page_arg arg; 586 587 arg.pmap = pmap; 588 arg.va = va; 589 590 smp_rendezvous(0, pmap_invalidate_page_action, 0, (void *)&arg); 591} 592 593static void 594pmap_invalidate_page_action(void *arg) 595{ 596 pmap_t pmap = ((struct pmap_invalidate_page_arg *)arg)->pmap; 597 vm_offset_t va = ((struct pmap_invalidate_page_arg *)arg)->va; 598 599#endif 600 601 if (is_kernel_pmap(pmap)) { 602 pmap_TLB_invalidate_kernel(va); 603 return; 604 } 605 if (pmap->pm_asid[PCPU_GET(cpuid)].gen != PCPU_GET(asid_generation)) 606 return; 607 else if (!(pmap->pm_active & PCPU_GET(cpumask))) { 608 pmap->pm_asid[PCPU_GET(cpuid)].gen = 0; 609 return; 610 } 611 va = pmap_va_asid(pmap, (va & ~PAGE_MASK)); 612 mips_TBIS(va); 613} 614 615static void 616pmap_TLB_invalidate_kernel(vm_offset_t va) 617{ 618 u_int32_t pid; 619 620 MachTLBGetPID(pid); 621 va = va | (pid << VMTLB_PID_SHIFT); 622 mips_TBIS(va); 623} 624 625struct pmap_update_page_arg { 626 pmap_t pmap; 627 vm_offset_t va; 628 pt_entry_t pte; 629}; 630 631void 632pmap_update_page(pmap_t pmap, vm_offset_t va, pt_entry_t pte) 633{ 634#ifdef SMP 635 struct pmap_update_page_arg arg; 636 637 arg.pmap = pmap; 638 arg.va = va; 639 arg.pte = pte; 640 641 smp_rendezvous(0, pmap_update_page_action, 0, (void *)&arg); 642} 643 644static void 645pmap_update_page_action(void *arg) 646{ 647 pmap_t pmap = ((struct pmap_update_page_arg *)arg)->pmap; 648 vm_offset_t va = ((struct pmap_update_page_arg *)arg)->va; 649 pt_entry_t pte = ((struct pmap_update_page_arg *)arg)->pte; 650 651#endif 652 if (is_kernel_pmap(pmap)) { 653 pmap_TLB_update_kernel(va, pte); 654 return; 655 } 656 if (pmap->pm_asid[PCPU_GET(cpuid)].gen != PCPU_GET(asid_generation)) 657 return; 658 else if (!(pmap->pm_active & PCPU_GET(cpumask))) { 659 pmap->pm_asid[PCPU_GET(cpuid)].gen = 0; 660 return; 661 } 662 va = pmap_va_asid(pmap, (va & ~PAGE_MASK)); 663 MachTLBUpdate(va, pte); 664} 665 666static void 667pmap_TLB_update_kernel(vm_offset_t va, pt_entry_t pte) 668{ 669 u_int32_t pid; 670 671 va &= ~PAGE_MASK; 672 673 MachTLBGetPID(pid); 674 va = va | (pid << VMTLB_PID_SHIFT); 675 676 MachTLBUpdate(va, pte); 677} 678 679/* 680 * Routine: pmap_extract 681 * Function: 682 * Extract the physical page address associated 683 * with the given map/virtual_address pair. 684 */ 685vm_paddr_t 686pmap_extract(pmap_t pmap, vm_offset_t va) 687{ 688 pt_entry_t *pte; 689 vm_offset_t retval = 0; 690 691 PMAP_LOCK(pmap); 692 pte = pmap_pte(pmap, va); 693 if (pte) { 694 retval = mips_tlbpfn_to_paddr(*pte) | (va & PAGE_MASK); 695 } 696 PMAP_UNLOCK(pmap); 697 return retval; 698} 699 700/* 701 * Routine: pmap_extract_and_hold 702 * Function: 703 * Atomically extract and hold the physical page 704 * with the given pmap and virtual address pair 705 * if that mapping permits the given protection. 706 */ 707vm_page_t 708pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 709{ 710 pt_entry_t pte; 711 vm_page_t m; 712 vm_paddr_t pa; 713 714 m = NULL; 715 pa = 0; 716 PMAP_LOCK(pmap); 717retry: 718 pte = *pmap_pte(pmap, va); 719 if (pte != 0 && pmap_pte_v(&pte) && 720 ((pte & PTE_RW) || (prot & VM_PROT_WRITE) == 0)) { 721 if (vm_page_pa_tryrelock(pmap, mips_tlbpfn_to_paddr(pte), &pa)) 722 goto retry; 723 724 m = PHYS_TO_VM_PAGE(mips_tlbpfn_to_paddr(pte)); 725 vm_page_hold(m); 726 } 727 PA_UNLOCK_COND(pa); 728 PMAP_UNLOCK(pmap); 729 return (m); 730} 731 732/*************************************************** 733 * Low level mapping routines..... 734 ***************************************************/ 735 736/* 737 * add a wired page to the kva 738 */ 739 /* PMAP_INLINE */ void 740pmap_kenter(vm_offset_t va, vm_paddr_t pa) 741{ 742 register pt_entry_t *pte; 743 pt_entry_t npte, opte; 744 745#ifdef PMAP_DEBUG 746 printf("pmap_kenter: va: 0x%08x -> pa: 0x%08x\n", va, pa); 747#endif 748 npte = mips_paddr_to_tlbpfn(pa) | PTE_RW | PTE_V | PTE_G | PTE_W; 749 750 if (is_cacheable_mem(pa)) 751 npte |= PTE_CACHE; 752 else 753 npte |= PTE_UNCACHED; 754 755 pte = pmap_pte(kernel_pmap, va); 756 opte = *pte; 757 *pte = npte; 758 759 pmap_update_page(kernel_pmap, va, npte); 760} 761 762/* 763 * remove a page from the kernel pagetables 764 */ 765 /* PMAP_INLINE */ void 766pmap_kremove(vm_offset_t va) 767{ 768 register pt_entry_t *pte; 769 770 /* 771 * Write back all caches from the page being destroyed 772 */ 773 mips_dcache_wbinv_range_index(va, PAGE_SIZE); 774 775 pte = pmap_pte(kernel_pmap, va); 776 *pte = PTE_G; 777 pmap_invalidate_page(kernel_pmap, va); 778} 779 780/* 781 * Used to map a range of physical addresses into kernel 782 * virtual address space. 783 * 784 * The value passed in '*virt' is a suggested virtual address for 785 * the mapping. Architectures which can support a direct-mapped 786 * physical to virtual region can return the appropriate address 787 * within that region, leaving '*virt' unchanged. Other 788 * architectures should map the pages starting at '*virt' and 789 * update '*virt' with the first usable address after the mapped 790 * region. 791 */ 792vm_offset_t 793pmap_map(vm_offset_t *virt, vm_offset_t start, vm_offset_t end, int prot) 794{ 795 vm_offset_t va, sva; 796 797 va = sva = *virt; 798 while (start < end) { 799 pmap_kenter(va, start); 800 va += PAGE_SIZE; 801 start += PAGE_SIZE; 802 } 803 *virt = va; 804 return (sva); 805} 806 807/* 808 * Add a list of wired pages to the kva 809 * this routine is only used for temporary 810 * kernel mappings that do not need to have 811 * page modification or references recorded. 812 * Note that old mappings are simply written 813 * over. The page *must* be wired. 814 */ 815void 816pmap_qenter(vm_offset_t va, vm_page_t *m, int count) 817{ 818 int i; 819 vm_offset_t origva = va; 820 821 for (i = 0; i < count; i++) { 822 pmap_flush_pvcache(m[i]); 823 pmap_kenter(va, VM_PAGE_TO_PHYS(m[i])); 824 va += PAGE_SIZE; 825 } 826 827 mips_dcache_wbinv_range_index(origva, PAGE_SIZE*count); 828} 829 830/* 831 * this routine jerks page mappings from the 832 * kernel -- it is meant only for temporary mappings. 833 */ 834void 835pmap_qremove(vm_offset_t va, int count) 836{ 837 /* 838 * No need to wb/inv caches here, 839 * pmap_kremove will do it for us 840 */ 841 842 while (count-- > 0) { 843 pmap_kremove(va); 844 va += PAGE_SIZE; 845 } 846} 847 848/*************************************************** 849 * Page table page management routines..... 850 ***************************************************/ 851 852/* Revision 1.507 853 * 854 * Simplify the reference counting of page table pages. Specifically, use 855 * the page table page's wired count rather than its hold count to contain 856 * the reference count. 857 */ 858 859/* 860 * This routine unholds page table pages, and if the hold count 861 * drops to zero, then it decrements the wire count. 862 */ 863static int 864_pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m) 865{ 866 vm_offset_t pteva; 867 868 /* 869 * unmap the page table page 870 */ 871 pteva = (vm_offset_t)pmap->pm_segtab[m->pindex]; 872 if (pteva >= VM_MIN_KERNEL_ADDRESS) { 873 pmap_kremove(pteva); 874 kmem_free(kernel_map, pteva, PAGE_SIZE); 875 } else { 876 KASSERT(MIPS_IS_KSEG0_ADDR(pteva), 877 ("_pmap_unwire_pte_hold: 0x%0lx is not in kseg0", 878 (long)pteva)); 879 } 880 881 pmap->pm_segtab[m->pindex] = 0; 882 --pmap->pm_stats.resident_count; 883 884 if (pmap->pm_ptphint == m) 885 pmap->pm_ptphint = NULL; 886 887 /* 888 * If the page is finally unwired, simply free it. 889 */ 890 vm_page_free_zero(m); 891 atomic_subtract_int(&cnt.v_wire_count, 1); 892 return (1); 893} 894 895static PMAP_INLINE int 896pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m) 897{ 898 --m->wire_count; 899 if (m->wire_count == 0) 900 return (_pmap_unwire_pte_hold(pmap, m)); 901 else 902 return (0); 903} 904 905/* 906 * After removing a page table entry, this routine is used to 907 * conditionally free the page, and manage the hold/wire counts. 908 */ 909static int 910pmap_unuse_pt(pmap_t pmap, vm_offset_t va, vm_page_t mpte) 911{ 912 unsigned ptepindex; 913 pd_entry_t pteva; 914 915 if (va >= VM_MAXUSER_ADDRESS) 916 return (0); 917 918 if (mpte == NULL) { 919 ptepindex = (va >> SEGSHIFT); 920 if (pmap->pm_ptphint && 921 (pmap->pm_ptphint->pindex == ptepindex)) { 922 mpte = pmap->pm_ptphint; 923 } else { 924 pteva = *pmap_pde(pmap, va); 925 mpte = PHYS_TO_VM_PAGE(vtophys(pteva)); 926 pmap->pm_ptphint = mpte; 927 } 928 } 929 return pmap_unwire_pte_hold(pmap, mpte); 930} 931 932void 933pmap_pinit0(pmap_t pmap) 934{ 935 int i; 936 937 PMAP_LOCK_INIT(pmap); 938 pmap->pm_segtab = kernel_segmap; 939 pmap->pm_active = 0; 940 pmap->pm_ptphint = NULL; 941 for (i = 0; i < MAXCPU; i++) { 942 pmap->pm_asid[i].asid = PMAP_ASID_RESERVED; 943 pmap->pm_asid[i].gen = 0; 944 } 945 PCPU_SET(curpmap, pmap); 946 TAILQ_INIT(&pmap->pm_pvlist); 947 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 948} 949 950/* 951 * Initialize a preallocated and zeroed pmap structure, 952 * such as one in a vmspace structure. 953 */ 954int 955pmap_pinit(pmap_t pmap) 956{ 957 vm_offset_t ptdva; 958 vm_paddr_t ptdpa; 959 vm_page_t ptdpg; 960 int i; 961 int req; 962 963 PMAP_LOCK_INIT(pmap); 964 965 req = VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL | VM_ALLOC_WIRED | 966 VM_ALLOC_ZERO; 967 968 /* 969 * allocate the page directory page 970 */ 971 while ((ptdpg = vm_page_alloc(NULL, NUSERPGTBLS, req)) == NULL) 972 VM_WAIT; 973 974 ptdpg->valid = VM_PAGE_BITS_ALL; 975 976 ptdpa = VM_PAGE_TO_PHYS(ptdpg); 977 if (ptdpa < MIPS_KSEG0_LARGEST_PHYS) { 978 ptdva = MIPS_PHYS_TO_KSEG0(ptdpa); 979 } else { 980 ptdva = kmem_alloc_nofault(kernel_map, PAGE_SIZE); 981 if (ptdva == 0) 982 panic("pmap_pinit: unable to allocate kva"); 983 pmap_kenter(ptdva, ptdpa); 984 } 985 986 pmap->pm_segtab = (pd_entry_t *)ptdva; 987 if ((ptdpg->flags & PG_ZERO) == 0) 988 bzero(pmap->pm_segtab, PAGE_SIZE); 989 990 pmap->pm_active = 0; 991 pmap->pm_ptphint = NULL; 992 for (i = 0; i < MAXCPU; i++) { 993 pmap->pm_asid[i].asid = PMAP_ASID_RESERVED; 994 pmap->pm_asid[i].gen = 0; 995 } 996 TAILQ_INIT(&pmap->pm_pvlist); 997 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 998 999 return (1); 1000} 1001 1002/* 1003 * this routine is called if the page table page is not 1004 * mapped correctly. 1005 */ 1006static vm_page_t 1007_pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags) 1008{ 1009 vm_offset_t pteva, ptepa; 1010 vm_page_t m; 1011 int req; 1012 1013 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1014 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1015 ("_pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1016 1017 req = VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ; 1018 /* 1019 * Find or fabricate a new pagetable page 1020 */ 1021 if ((m = vm_page_alloc(NULL, ptepindex, req)) == NULL) { 1022 if (flags & M_WAITOK) { 1023 PMAP_UNLOCK(pmap); 1024 vm_page_unlock_queues(); 1025 VM_WAIT; 1026 vm_page_lock_queues(); 1027 PMAP_LOCK(pmap); 1028 } 1029 /* 1030 * Indicate the need to retry. While waiting, the page 1031 * table page may have been allocated. 1032 */ 1033 return (NULL); 1034 } 1035 if ((m->flags & PG_ZERO) == 0) 1036 pmap_zero_page(m); 1037 1038 KASSERT(m->queue == PQ_NONE, 1039 ("_pmap_allocpte: %p->queue != PQ_NONE", m)); 1040 1041 /* 1042 * Map the pagetable page into the process address space, if it 1043 * isn't already there. 1044 */ 1045 1046 pmap->pm_stats.resident_count++; 1047 1048 ptepa = VM_PAGE_TO_PHYS(m); 1049 if (ptepa < MIPS_KSEG0_LARGEST_PHYS) { 1050 pteva = MIPS_PHYS_TO_KSEG0(ptepa); 1051 } else { 1052 pteva = kmem_alloc_nofault(kernel_map, PAGE_SIZE); 1053 if (pteva == 0) 1054 panic("_pmap_allocpte: unable to allocate kva"); 1055 pmap_kenter(pteva, ptepa); 1056 } 1057 1058 pmap->pm_segtab[ptepindex] = (pd_entry_t)pteva; 1059 1060 /* 1061 * Set the page table hint 1062 */ 1063 pmap->pm_ptphint = m; 1064 1065 /* 1066 * Kernel page tables are allocated in pmap_bootstrap() or 1067 * pmap_growkernel(). 1068 */ 1069 if (is_kernel_pmap(pmap)) 1070 panic("_pmap_allocpte() called for kernel pmap\n"); 1071 1072 m->valid = VM_PAGE_BITS_ALL; 1073 vm_page_flag_clear(m, PG_ZERO); 1074 1075 return (m); 1076} 1077 1078static vm_page_t 1079pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags) 1080{ 1081 unsigned ptepindex; 1082 vm_offset_t pteva; 1083 vm_page_t m; 1084 1085 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1086 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1087 ("pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1088 1089 /* 1090 * Calculate pagetable page index 1091 */ 1092 ptepindex = va >> SEGSHIFT; 1093retry: 1094 /* 1095 * Get the page directory entry 1096 */ 1097 pteva = (vm_offset_t)pmap->pm_segtab[ptepindex]; 1098 1099 /* 1100 * If the page table page is mapped, we just increment the hold 1101 * count, and activate it. 1102 */ 1103 if (pteva) { 1104 /* 1105 * In order to get the page table page, try the hint first. 1106 */ 1107 if (pmap->pm_ptphint && 1108 (pmap->pm_ptphint->pindex == ptepindex)) { 1109 m = pmap->pm_ptphint; 1110 } else { 1111 m = PHYS_TO_VM_PAGE(vtophys(pteva)); 1112 pmap->pm_ptphint = m; 1113 } 1114 m->wire_count++; 1115 } else { 1116 /* 1117 * Here if the pte page isn't mapped, or if it has been 1118 * deallocated. 1119 */ 1120 m = _pmap_allocpte(pmap, ptepindex, flags); 1121 if (m == NULL && (flags & M_WAITOK)) 1122 goto retry; 1123 } 1124 return m; 1125} 1126 1127 1128/*************************************************** 1129* Pmap allocation/deallocation routines. 1130 ***************************************************/ 1131/* 1132 * Revision 1.397 1133 * - Merged pmap_release and pmap_release_free_page. When pmap_release is 1134 * called only the page directory page(s) can be left in the pmap pte 1135 * object, since all page table pages will have been freed by 1136 * pmap_remove_pages and pmap_remove. In addition, there can only be one 1137 * reference to the pmap and the page directory is wired, so the page(s) 1138 * can never be busy. So all there is to do is clear the magic mappings 1139 * from the page directory and free the page(s). 1140 */ 1141 1142 1143/* 1144 * Release any resources held by the given physical map. 1145 * Called when a pmap initialized by pmap_pinit is being released. 1146 * Should only be called if the map contains no valid mappings. 1147 */ 1148void 1149pmap_release(pmap_t pmap) 1150{ 1151 vm_offset_t ptdva; 1152 vm_page_t ptdpg; 1153 1154 KASSERT(pmap->pm_stats.resident_count == 0, 1155 ("pmap_release: pmap resident count %ld != 0", 1156 pmap->pm_stats.resident_count)); 1157 1158 ptdva = (vm_offset_t)pmap->pm_segtab; 1159 ptdpg = PHYS_TO_VM_PAGE(vtophys(ptdva)); 1160 1161 if (ptdva >= VM_MIN_KERNEL_ADDRESS) { 1162 pmap_kremove(ptdva); 1163 kmem_free(kernel_map, ptdva, PAGE_SIZE); 1164 } else { 1165 KASSERT(MIPS_IS_KSEG0_ADDR(ptdva), 1166 ("pmap_release: 0x%0lx is not in kseg0", (long)ptdva)); 1167 } 1168 1169 ptdpg->wire_count--; 1170 atomic_subtract_int(&cnt.v_wire_count, 1); 1171 vm_page_free_zero(ptdpg); 1172 PMAP_LOCK_DESTROY(pmap); 1173} 1174 1175/* 1176 * grow the number of kernel page table entries, if needed 1177 */ 1178void 1179pmap_growkernel(vm_offset_t addr) 1180{ 1181 vm_offset_t ptppaddr; 1182 vm_page_t nkpg; 1183 pt_entry_t *pte; 1184 int i, req; 1185 1186 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 1187 if (kernel_vm_end == 0) { 1188 kernel_vm_end = VM_MIN_KERNEL_ADDRESS; 1189 nkpt = 0; 1190 while (segtab_pde(kernel_segmap, kernel_vm_end)) { 1191 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & 1192 ~(PAGE_SIZE * NPTEPG - 1); 1193 nkpt++; 1194 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1195 kernel_vm_end = kernel_map->max_offset; 1196 break; 1197 } 1198 } 1199 } 1200 addr = (addr + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1201 if (addr - 1 >= kernel_map->max_offset) 1202 addr = kernel_map->max_offset; 1203 while (kernel_vm_end < addr) { 1204 if (segtab_pde(kernel_segmap, kernel_vm_end)) { 1205 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & 1206 ~(PAGE_SIZE * NPTEPG - 1); 1207 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1208 kernel_vm_end = kernel_map->max_offset; 1209 break; 1210 } 1211 continue; 1212 } 1213 /* 1214 * This index is bogus, but out of the way 1215 */ 1216 req = VM_ALLOC_INTERRUPT | VM_ALLOC_WIRED | VM_ALLOC_NOOBJ; 1217 nkpg = vm_page_alloc(NULL, nkpt, req); 1218 if (!nkpg) 1219 panic("pmap_growkernel: no memory to grow kernel"); 1220 1221 nkpt++; 1222 1223 ptppaddr = VM_PAGE_TO_PHYS(nkpg); 1224 if (ptppaddr >= MIPS_KSEG0_LARGEST_PHYS) { 1225 /* 1226 * We need to do something here, but I am not sure 1227 * what. We can access anything in the 0 - 512Meg 1228 * region, but if we get a page to go in the kernel 1229 * segmap that is outside of of that we really need 1230 * to have another mapping beyond the temporary ones 1231 * I have. Not sure how to do this yet. FIXME FIXME. 1232 */ 1233 panic("Gak, can't handle a k-page table outside of lower 512Meg"); 1234 } 1235 pte = (pt_entry_t *)MIPS_PHYS_TO_KSEG0(ptppaddr); 1236 segtab_pde(kernel_segmap, kernel_vm_end) = (pd_entry_t)pte; 1237 1238 /* 1239 * The R[4-7]?00 stores only one copy of the Global bit in 1240 * the translation lookaside buffer for each 2 page entry. 1241 * Thus invalid entrys must have the Global bit set so when 1242 * Entry LO and Entry HI G bits are anded together they will 1243 * produce a global bit to store in the tlb. 1244 */ 1245 for (i = 0; i < NPTEPG; i++, pte++) 1246 *pte = PTE_G; 1247 1248 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & 1249 ~(PAGE_SIZE * NPTEPG - 1); 1250 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1251 kernel_vm_end = kernel_map->max_offset; 1252 break; 1253 } 1254 } 1255} 1256 1257/*************************************************** 1258* page management routines. 1259 ***************************************************/ 1260 1261/* 1262 * free the pv_entry back to the free list 1263 */ 1264static PMAP_INLINE void 1265free_pv_entry(pv_entry_t pv) 1266{ 1267 1268 pv_entry_count--; 1269 uma_zfree(pvzone, pv); 1270} 1271 1272/* 1273 * get a new pv_entry, allocating a block from the system 1274 * when needed. 1275 * the memory allocation is performed bypassing the malloc code 1276 * because of the possibility of allocations at interrupt time. 1277 */ 1278static pv_entry_t 1279get_pv_entry(pmap_t locked_pmap) 1280{ 1281 static const struct timeval printinterval = { 60, 0 }; 1282 static struct timeval lastprint; 1283 struct vpgqueues *vpq; 1284 pt_entry_t *pte, oldpte; 1285 pmap_t pmap; 1286 pv_entry_t allocated_pv, next_pv, pv; 1287 vm_offset_t va; 1288 vm_page_t m; 1289 1290 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED); 1291 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1292 allocated_pv = uma_zalloc(pvzone, M_NOWAIT); 1293 if (allocated_pv != NULL) { 1294 pv_entry_count++; 1295 if (pv_entry_count > pv_entry_high_water) 1296 pagedaemon_wakeup(); 1297 else 1298 return (allocated_pv); 1299 } 1300 /* 1301 * Reclaim pv entries: At first, destroy mappings to inactive 1302 * pages. After that, if a pv entry is still needed, destroy 1303 * mappings to active pages. 1304 */ 1305 if (ratecheck(&lastprint, &printinterval)) 1306 printf("Approaching the limit on PV entries, " 1307 "increase the vm.pmap.shpgperproc tunable.\n"); 1308 vpq = &vm_page_queues[PQ_INACTIVE]; 1309retry: 1310 TAILQ_FOREACH(m, &vpq->pl, pageq) { 1311 if (m->hold_count || m->busy) 1312 continue; 1313 TAILQ_FOREACH_SAFE(pv, &m->md.pv_list, pv_list, next_pv) { 1314 va = pv->pv_va; 1315 pmap = pv->pv_pmap; 1316 /* Avoid deadlock and lock recursion. */ 1317 if (pmap > locked_pmap) 1318 PMAP_LOCK(pmap); 1319 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) 1320 continue; 1321 pmap->pm_stats.resident_count--; 1322 pte = pmap_pte(pmap, va); 1323 KASSERT(pte != NULL, ("pte")); 1324 oldpte = loadandclear((u_int *)pte); 1325 if (is_kernel_pmap(pmap)) 1326 *pte = PTE_G; 1327 KASSERT((oldpte & PTE_W) == 0, 1328 ("wired pte for unwired page")); 1329 if (m->md.pv_flags & PV_TABLE_REF) 1330 vm_page_flag_set(m, PG_REFERENCED); 1331 if (oldpte & PTE_M) 1332 vm_page_dirty(m); 1333 pmap_invalidate_page(pmap, va); 1334 TAILQ_REMOVE(&pmap->pm_pvlist, pv, pv_plist); 1335 m->md.pv_list_count--; 1336 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 1337 if (TAILQ_EMPTY(&m->md.pv_list)) { 1338 vm_page_flag_clear(m, PG_WRITEABLE); 1339 m->md.pv_flags &= ~(PV_TABLE_REF | PV_TABLE_MOD); 1340 } 1341 pmap_unuse_pt(pmap, va, pv->pv_ptem); 1342 if (pmap != locked_pmap) 1343 PMAP_UNLOCK(pmap); 1344 if (allocated_pv == NULL) 1345 allocated_pv = pv; 1346 else 1347 free_pv_entry(pv); 1348 } 1349 } 1350 if (allocated_pv == NULL) { 1351 if (vpq == &vm_page_queues[PQ_INACTIVE]) { 1352 vpq = &vm_page_queues[PQ_ACTIVE]; 1353 goto retry; 1354 } 1355 panic("get_pv_entry: increase the vm.pmap.shpgperproc tunable"); 1356 } 1357 return (allocated_pv); 1358} 1359 1360/* 1361 * Revision 1.370 1362 * 1363 * Move pmap_collect() out of the machine-dependent code, rename it 1364 * to reflect its new location, and add page queue and flag locking. 1365 * 1366 * Notes: (1) alpha, i386, and ia64 had identical implementations 1367 * of pmap_collect() in terms of machine-independent interfaces; 1368 * (2) sparc64 doesn't require it; (3) powerpc had it as a TODO. 1369 * 1370 * MIPS implementation was identical to alpha [Junos 8.2] 1371 */ 1372 1373/* 1374 * If it is the first entry on the list, it is actually 1375 * in the header and we must copy the following entry up 1376 * to the header. Otherwise we must search the list for 1377 * the entry. In either case we free the now unused entry. 1378 */ 1379 1380static void 1381pmap_remove_entry(struct pmap *pmap, vm_page_t m, vm_offset_t va) 1382{ 1383 pv_entry_t pv; 1384 1385 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1386 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1387 if (m->md.pv_list_count < pmap->pm_stats.resident_count) { 1388 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 1389 if (pmap == pv->pv_pmap && va == pv->pv_va) 1390 break; 1391 } 1392 } else { 1393 TAILQ_FOREACH(pv, &pmap->pm_pvlist, pv_plist) { 1394 if (va == pv->pv_va) 1395 break; 1396 } 1397 } 1398 1399 KASSERT(pv != NULL, ("pmap_remove_entry: pv not found")); 1400 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 1401 m->md.pv_list_count--; 1402 if (TAILQ_FIRST(&m->md.pv_list) == NULL) 1403 vm_page_flag_clear(m, PG_WRITEABLE); 1404 1405 TAILQ_REMOVE(&pmap->pm_pvlist, pv, pv_plist); 1406 free_pv_entry(pv); 1407} 1408 1409/* 1410 * Create a pv entry for page at pa for 1411 * (pmap, va). 1412 */ 1413static void 1414pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t mpte, vm_page_t m, 1415 boolean_t wired) 1416{ 1417 pv_entry_t pv; 1418 1419 pv = get_pv_entry(pmap); 1420 pv->pv_va = va; 1421 pv->pv_pmap = pmap; 1422 pv->pv_ptem = mpte; 1423 pv->pv_wired = wired; 1424 1425 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1426 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1427 TAILQ_INSERT_TAIL(&pmap->pm_pvlist, pv, pv_plist); 1428 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 1429 m->md.pv_list_count++; 1430} 1431 1432/* 1433 * Conditionally create a pv entry. 1434 */ 1435static boolean_t 1436pmap_try_insert_pv_entry(pmap_t pmap, vm_page_t mpte, vm_offset_t va, 1437 vm_page_t m) 1438{ 1439 pv_entry_t pv; 1440 1441 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1442 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1443 if (pv_entry_count < pv_entry_high_water && 1444 (pv = uma_zalloc(pvzone, M_NOWAIT)) != NULL) { 1445 pv_entry_count++; 1446 pv->pv_va = va; 1447 pv->pv_pmap = pmap; 1448 pv->pv_ptem = mpte; 1449 pv->pv_wired = FALSE; 1450 TAILQ_INSERT_TAIL(&pmap->pm_pvlist, pv, pv_plist); 1451 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 1452 m->md.pv_list_count++; 1453 return (TRUE); 1454 } else 1455 return (FALSE); 1456} 1457 1458/* 1459 * pmap_remove_pte: do the things to unmap a page in a process 1460 */ 1461static int 1462pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va) 1463{ 1464 pt_entry_t oldpte; 1465 vm_page_t m; 1466 vm_offset_t pa; 1467 1468 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1469 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1470 1471 oldpte = loadandclear((u_int *)ptq); 1472 if (is_kernel_pmap(pmap)) 1473 *ptq = PTE_G; 1474 1475 if (oldpte & PTE_W) 1476 pmap->pm_stats.wired_count -= 1; 1477 1478 pmap->pm_stats.resident_count -= 1; 1479 pa = mips_tlbpfn_to_paddr(oldpte); 1480 1481 if (page_is_managed(pa)) { 1482 m = PHYS_TO_VM_PAGE(pa); 1483 if (oldpte & PTE_M) { 1484#if defined(PMAP_DIAGNOSTIC) 1485 if (pmap_nw_modified(oldpte)) { 1486 printf( 1487 "pmap_remove: modified page not writable: va: 0x%x, pte: 0x%x\n", 1488 va, oldpte); 1489 } 1490#endif 1491 vm_page_dirty(m); 1492 } 1493 if (m->md.pv_flags & PV_TABLE_REF) 1494 vm_page_flag_set(m, PG_REFERENCED); 1495 m->md.pv_flags &= ~(PV_TABLE_REF | PV_TABLE_MOD); 1496 1497 pmap_remove_entry(pmap, m, va); 1498 } 1499 return pmap_unuse_pt(pmap, va, NULL); 1500} 1501 1502/* 1503 * Remove a single page from a process address space 1504 */ 1505static void 1506pmap_remove_page(struct pmap *pmap, vm_offset_t va) 1507{ 1508 register pt_entry_t *ptq; 1509 1510 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1511 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1512 ptq = pmap_pte(pmap, va); 1513 1514 /* 1515 * if there is no pte for this address, just skip it!!! 1516 */ 1517 if (!ptq || !pmap_pte_v(ptq)) { 1518 return; 1519 } 1520 1521 /* 1522 * Write back all caches from the page being destroyed 1523 */ 1524 mips_dcache_wbinv_range_index(va, PAGE_SIZE); 1525 1526 /* 1527 * get a local va for mappings for this pmap. 1528 */ 1529 (void)pmap_remove_pte(pmap, ptq, va); 1530 pmap_invalidate_page(pmap, va); 1531 1532 return; 1533} 1534 1535/* 1536 * Remove the given range of addresses from the specified map. 1537 * 1538 * It is assumed that the start and end are properly 1539 * rounded to the page size. 1540 */ 1541void 1542pmap_remove(struct pmap *pmap, vm_offset_t sva, vm_offset_t eva) 1543{ 1544 vm_offset_t va, nva; 1545 1546 if (pmap == NULL) 1547 return; 1548 1549 if (pmap->pm_stats.resident_count == 0) 1550 return; 1551 1552 vm_page_lock_queues(); 1553 PMAP_LOCK(pmap); 1554 1555 /* 1556 * special handling of removing one page. a very common operation 1557 * and easy to short circuit some code. 1558 */ 1559 if ((sva + PAGE_SIZE) == eva) { 1560 pmap_remove_page(pmap, sva); 1561 goto out; 1562 } 1563 for (va = sva; va < eva; va = nva) { 1564 if (!*pmap_pde(pmap, va)) { 1565 nva = mips_segtrunc(va + MIPS_SEGSIZE); 1566 continue; 1567 } 1568 pmap_remove_page(pmap, va); 1569 nva = va + PAGE_SIZE; 1570 } 1571 1572out: 1573 vm_page_unlock_queues(); 1574 PMAP_UNLOCK(pmap); 1575} 1576 1577/* 1578 * Routine: pmap_remove_all 1579 * Function: 1580 * Removes this physical page from 1581 * all physical maps in which it resides. 1582 * Reflects back modify bits to the pager. 1583 * 1584 * Notes: 1585 * Original versions of this routine were very 1586 * inefficient because they iteratively called 1587 * pmap_remove (slow...) 1588 */ 1589 1590void 1591pmap_remove_all(vm_page_t m) 1592{ 1593 register pv_entry_t pv; 1594 register pt_entry_t *pte, tpte; 1595 1596 KASSERT((m->flags & PG_FICTITIOUS) == 0, 1597 ("pmap_remove_all: page %p is fictitious", m)); 1598 vm_page_lock_queues(); 1599 1600 if (m->md.pv_flags & PV_TABLE_REF) 1601 vm_page_flag_set(m, PG_REFERENCED); 1602 1603 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 1604 PMAP_LOCK(pv->pv_pmap); 1605 1606 /* 1607 * If it's last mapping writeback all caches from 1608 * the page being destroyed 1609 */ 1610 if (m->md.pv_list_count == 1) 1611 mips_dcache_wbinv_range_index(pv->pv_va, PAGE_SIZE); 1612 1613 pv->pv_pmap->pm_stats.resident_count--; 1614 1615 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 1616 1617 tpte = loadandclear((u_int *)pte); 1618 if (is_kernel_pmap(pv->pv_pmap)) 1619 *pte = PTE_G; 1620 1621 if (tpte & PTE_W) 1622 pv->pv_pmap->pm_stats.wired_count--; 1623 1624 /* 1625 * Update the vm_page_t clean and reference bits. 1626 */ 1627 if (tpte & PTE_M) { 1628#if defined(PMAP_DIAGNOSTIC) 1629 if (pmap_nw_modified(tpte)) { 1630 printf( 1631 "pmap_remove_all: modified page not writable: va: 0x%x, pte: 0x%x\n", 1632 pv->pv_va, tpte); 1633 } 1634#endif 1635 vm_page_dirty(m); 1636 } 1637 pmap_invalidate_page(pv->pv_pmap, pv->pv_va); 1638 1639 TAILQ_REMOVE(&pv->pv_pmap->pm_pvlist, pv, pv_plist); 1640 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 1641 m->md.pv_list_count--; 1642 pmap_unuse_pt(pv->pv_pmap, pv->pv_va, pv->pv_ptem); 1643 PMAP_UNLOCK(pv->pv_pmap); 1644 free_pv_entry(pv); 1645 } 1646 1647 vm_page_flag_clear(m, PG_WRITEABLE); 1648 m->md.pv_flags &= ~(PV_TABLE_REF | PV_TABLE_MOD); 1649 vm_page_unlock_queues(); 1650} 1651 1652/* 1653 * Set the physical protection on the 1654 * specified range of this map as requested. 1655 */ 1656void 1657pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 1658{ 1659 pt_entry_t *pte; 1660 1661 if (pmap == NULL) 1662 return; 1663 1664 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1665 pmap_remove(pmap, sva, eva); 1666 return; 1667 } 1668 if (prot & VM_PROT_WRITE) 1669 return; 1670 1671 vm_page_lock_queues(); 1672 PMAP_LOCK(pmap); 1673 while (sva < eva) { 1674 pt_entry_t pbits, obits; 1675 vm_page_t m; 1676 vm_offset_t pa; 1677 1678 /* 1679 * If segment table entry is empty, skip this segment. 1680 */ 1681 if (!*pmap_pde(pmap, sva)) { 1682 sva = mips_segtrunc(sva + MIPS_SEGSIZE); 1683 continue; 1684 } 1685 /* 1686 * If pte is invalid, skip this page 1687 */ 1688 pte = pmap_pte(pmap, sva); 1689 if (!pmap_pte_v(pte)) { 1690 sva += PAGE_SIZE; 1691 continue; 1692 } 1693retry: 1694 obits = pbits = *pte; 1695 pa = mips_tlbpfn_to_paddr(pbits); 1696 1697 if (page_is_managed(pa) && (pbits & PTE_M) != 0) { 1698 m = PHYS_TO_VM_PAGE(pa); 1699 vm_page_dirty(m); 1700 m->md.pv_flags &= ~PV_TABLE_MOD; 1701 } 1702 pbits = (pbits & ~PTE_M) | PTE_RO; 1703 1704 if (pbits != *pte) { 1705 if (!atomic_cmpset_int((u_int *)pte, obits, pbits)) 1706 goto retry; 1707 pmap_update_page(pmap, sva, pbits); 1708 } 1709 sva += PAGE_SIZE; 1710 } 1711 vm_page_unlock_queues(); 1712 PMAP_UNLOCK(pmap); 1713} 1714 1715/* 1716 * Insert the given physical page (p) at 1717 * the specified virtual address (v) in the 1718 * target physical map with the protection requested. 1719 * 1720 * If specified, the page will be wired down, meaning 1721 * that the related pte can not be reclaimed. 1722 * 1723 * NB: This is the only routine which MAY NOT lazy-evaluate 1724 * or lose information. That is, this routine must actually 1725 * insert this page into the given map NOW. 1726 */ 1727void 1728pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m, 1729 vm_prot_t prot, boolean_t wired) 1730{ 1731 vm_offset_t pa, opa; 1732 register pt_entry_t *pte; 1733 pt_entry_t origpte, newpte; 1734 vm_page_t mpte, om; 1735 int rw = 0; 1736 1737 if (pmap == NULL) 1738 return; 1739 1740 va &= ~PAGE_MASK; 1741#ifdef PMAP_DIAGNOSTIC 1742 if (va > VM_MAX_KERNEL_ADDRESS) 1743 panic("pmap_enter: toobig"); 1744#endif 1745 1746 mpte = NULL; 1747 1748 vm_page_lock_queues(); 1749 PMAP_LOCK(pmap); 1750 1751 /* 1752 * In the case that a page table page is not resident, we are 1753 * creating it here. 1754 */ 1755 if (va < VM_MAXUSER_ADDRESS) { 1756 mpte = pmap_allocpte(pmap, va, M_WAITOK); 1757 } 1758 pte = pmap_pte(pmap, va); 1759 1760 /* 1761 * Page Directory table entry not valid, we need a new PT page 1762 */ 1763 if (pte == NULL) { 1764 panic("pmap_enter: invalid page directory, pdir=%p, va=%p\n", 1765 (void *)pmap->pm_segtab, (void *)va); 1766 } 1767 pa = VM_PAGE_TO_PHYS(m); 1768 om = NULL; 1769 origpte = *pte; 1770 opa = mips_tlbpfn_to_paddr(origpte); 1771 1772 /* 1773 * Mapping has not changed, must be protection or wiring change. 1774 */ 1775 if ((origpte & PTE_V) && (opa == pa)) { 1776 /* 1777 * Wiring change, just update stats. We don't worry about 1778 * wiring PT pages as they remain resident as long as there 1779 * are valid mappings in them. Hence, if a user page is 1780 * wired, the PT page will be also. 1781 */ 1782 if (wired && ((origpte & PTE_W) == 0)) 1783 pmap->pm_stats.wired_count++; 1784 else if (!wired && (origpte & PTE_W)) 1785 pmap->pm_stats.wired_count--; 1786 1787#if defined(PMAP_DIAGNOSTIC) 1788 if (pmap_nw_modified(origpte)) { 1789 printf( 1790 "pmap_enter: modified page not writable: va: 0x%x, pte: 0x%x\n", 1791 va, origpte); 1792 } 1793#endif 1794 1795 /* 1796 * Remove extra pte reference 1797 */ 1798 if (mpte) 1799 mpte->wire_count--; 1800 1801 /* 1802 * We might be turning off write access to the page, so we 1803 * go ahead and sense modify status. 1804 */ 1805 if (page_is_managed(opa)) { 1806 om = m; 1807 } 1808 goto validate; 1809 } 1810 /* 1811 * Mapping has changed, invalidate old range and fall through to 1812 * handle validating new mapping. 1813 */ 1814 if (opa) { 1815 if (origpte & PTE_W) 1816 pmap->pm_stats.wired_count--; 1817 1818 if (page_is_managed(opa)) { 1819 om = PHYS_TO_VM_PAGE(opa); 1820 pmap_remove_entry(pmap, om, va); 1821 } 1822 if (mpte != NULL) { 1823 mpte->wire_count--; 1824 KASSERT(mpte->wire_count > 0, 1825 ("pmap_enter: missing reference to page table page," 1826 " va: %p", (void *)va)); 1827 } 1828 } else 1829 pmap->pm_stats.resident_count++; 1830 1831 /* 1832 * Enter on the PV list if part of our managed memory. Note that we 1833 * raise IPL while manipulating pv_table since pmap_enter can be 1834 * called at interrupt time. 1835 */ 1836 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) { 1837 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva, 1838 ("pmap_enter: managed mapping within the clean submap")); 1839 pmap_insert_entry(pmap, va, mpte, m, wired); 1840 } 1841 /* 1842 * Increment counters 1843 */ 1844 if (wired) 1845 pmap->pm_stats.wired_count++; 1846 1847validate: 1848 if ((access & VM_PROT_WRITE) != 0) 1849 m->md.pv_flags |= PV_TABLE_MOD | PV_TABLE_REF; 1850 rw = init_pte_prot(va, m, prot); 1851 1852#ifdef PMAP_DEBUG 1853 printf("pmap_enter: va: 0x%08x -> pa: 0x%08x\n", va, pa); 1854#endif 1855 /* 1856 * Now validate mapping with desired protection/wiring. 1857 */ 1858 newpte = mips_paddr_to_tlbpfn(pa) | rw | PTE_V; 1859 1860 if (is_cacheable_mem(pa)) 1861 newpte |= PTE_CACHE; 1862 else 1863 newpte |= PTE_UNCACHED; 1864 1865 if (wired) 1866 newpte |= PTE_W; 1867 1868 if (is_kernel_pmap(pmap)) { 1869 newpte |= PTE_G; 1870 } 1871 1872 /* 1873 * if the mapping or permission bits are different, we need to 1874 * update the pte. 1875 */ 1876 if (origpte != newpte) { 1877 if (origpte & PTE_V) { 1878 *pte = newpte; 1879 if (page_is_managed(opa) && (opa != pa)) { 1880 if (om->md.pv_flags & PV_TABLE_REF) 1881 vm_page_flag_set(om, PG_REFERENCED); 1882 om->md.pv_flags &= 1883 ~(PV_TABLE_REF | PV_TABLE_MOD); 1884 } 1885 if (origpte & PTE_M) { 1886 KASSERT((origpte & PTE_RW), 1887 ("pmap_enter: modified page not writable:" 1888 " va: %p, pte: 0x%x", (void *)va, origpte)); 1889 if (page_is_managed(opa)) 1890 vm_page_dirty(om); 1891 } 1892 } else { 1893 *pte = newpte; 1894 } 1895 } 1896 pmap_update_page(pmap, va, newpte); 1897 1898 /* 1899 * Sync I & D caches for executable pages. Do this only if the the 1900 * target pmap belongs to the current process. Otherwise, an 1901 * unresolvable TLB miss may occur. 1902 */ 1903 if (!is_kernel_pmap(pmap) && (pmap == &curproc->p_vmspace->vm_pmap) && 1904 (prot & VM_PROT_EXECUTE)) { 1905 mips_icache_sync_range(va, PAGE_SIZE); 1906 mips_dcache_wbinv_range(va, PAGE_SIZE); 1907 } 1908 vm_page_unlock_queues(); 1909 PMAP_UNLOCK(pmap); 1910} 1911 1912/* 1913 * this code makes some *MAJOR* assumptions: 1914 * 1. Current pmap & pmap exists. 1915 * 2. Not wired. 1916 * 3. Read access. 1917 * 4. No page table pages. 1918 * but is *MUCH* faster than pmap_enter... 1919 */ 1920 1921void 1922pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 1923{ 1924 1925 vm_page_lock_queues(); 1926 PMAP_LOCK(pmap); 1927 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL); 1928 vm_page_unlock_queues(); 1929 PMAP_UNLOCK(pmap); 1930} 1931 1932static vm_page_t 1933pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, 1934 vm_prot_t prot, vm_page_t mpte) 1935{ 1936 pt_entry_t *pte; 1937 vm_offset_t pa; 1938 1939 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva || 1940 (m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0, 1941 ("pmap_enter_quick_locked: managed mapping within the clean submap")); 1942 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1943 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1944 1945 /* 1946 * In the case that a page table page is not resident, we are 1947 * creating it here. 1948 */ 1949 if (va < VM_MAXUSER_ADDRESS) { 1950 unsigned ptepindex; 1951 vm_offset_t pteva; 1952 1953 /* 1954 * Calculate pagetable page index 1955 */ 1956 ptepindex = va >> SEGSHIFT; 1957 if (mpte && (mpte->pindex == ptepindex)) { 1958 mpte->wire_count++; 1959 } else { 1960 /* 1961 * Get the page directory entry 1962 */ 1963 pteva = (vm_offset_t)pmap->pm_segtab[ptepindex]; 1964 1965 /* 1966 * If the page table page is mapped, we just 1967 * increment the hold count, and activate it. 1968 */ 1969 if (pteva) { 1970 if (pmap->pm_ptphint && 1971 (pmap->pm_ptphint->pindex == ptepindex)) { 1972 mpte = pmap->pm_ptphint; 1973 } else { 1974 mpte = PHYS_TO_VM_PAGE(vtophys(pteva)); 1975 pmap->pm_ptphint = mpte; 1976 } 1977 mpte->wire_count++; 1978 } else { 1979 mpte = _pmap_allocpte(pmap, ptepindex, 1980 M_NOWAIT); 1981 if (mpte == NULL) 1982 return (mpte); 1983 } 1984 } 1985 } else { 1986 mpte = NULL; 1987 } 1988 1989 pte = pmap_pte(pmap, va); 1990 if (pmap_pte_v(pte)) { 1991 if (mpte != NULL) { 1992 mpte->wire_count--; 1993 mpte = NULL; 1994 } 1995 return (mpte); 1996 } 1997 1998 /* 1999 * Enter on the PV list if part of our managed memory. 2000 */ 2001 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0 && 2002 !pmap_try_insert_pv_entry(pmap, mpte, va, m)) { 2003 if (mpte != NULL) { 2004 pmap_unwire_pte_hold(pmap, mpte); 2005 mpte = NULL; 2006 } 2007 return (mpte); 2008 } 2009 2010 /* 2011 * Increment counters 2012 */ 2013 pmap->pm_stats.resident_count++; 2014 2015 pa = VM_PAGE_TO_PHYS(m); 2016 2017 /* 2018 * Now validate mapping with RO protection 2019 */ 2020 *pte = mips_paddr_to_tlbpfn(pa) | PTE_V; 2021 2022 if (is_cacheable_mem(pa)) 2023 *pte |= PTE_CACHE; 2024 else 2025 *pte |= PTE_UNCACHED; 2026 2027 if (is_kernel_pmap(pmap)) 2028 *pte |= PTE_G; 2029 else { 2030 *pte |= PTE_RO; 2031 /* 2032 * Sync I & D caches. Do this only if the the target pmap 2033 * belongs to the current process. Otherwise, an 2034 * unresolvable TLB miss may occur. */ 2035 if (pmap == &curproc->p_vmspace->vm_pmap) { 2036 va &= ~PAGE_MASK; 2037 mips_icache_sync_range(va, PAGE_SIZE); 2038 mips_dcache_wbinv_range(va, PAGE_SIZE); 2039 } 2040 } 2041 return (mpte); 2042} 2043 2044/* 2045 * Make a temporary mapping for a physical address. This is only intended 2046 * to be used for panic dumps. 2047 */ 2048void * 2049pmap_kenter_temporary(vm_paddr_t pa, int i) 2050{ 2051 vm_offset_t va; 2052 register_t intr; 2053 if (i != 0) 2054 printf("%s: ERROR!!! More than one page of virtual address mapping not supported\n", 2055 __func__); 2056 2057 if (pa < MIPS_KSEG0_LARGEST_PHYS) { 2058 va = MIPS_PHYS_TO_KSEG0(pa); 2059 } else { 2060 int cpu; 2061 struct local_sysmaps *sysm; 2062 pt_entry_t *pte, npte; 2063 2064 /* If this is used other than for dumps, we may need to leave 2065 * interrupts disasbled on return. If crash dumps don't work when 2066 * we get to this point, we might want to consider this (leaving things 2067 * disabled as a starting point ;-) 2068 */ 2069 intr = intr_disable(); 2070 cpu = PCPU_GET(cpuid); 2071 sysm = &sysmap_lmem[cpu]; 2072 /* Since this is for the debugger, no locks or any other fun */ 2073 npte = mips_paddr_to_tlbpfn(pa) | PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; 2074 pte = pmap_pte(kernel_pmap, sysm->base); 2075 *pte = npte; 2076 sysm->valid1 = 1; 2077 pmap_update_page(kernel_pmap, sysm->base, npte); 2078 va = sysm->base; 2079 intr_restore(intr); 2080 } 2081 return ((void *)va); 2082} 2083 2084void 2085pmap_kenter_temporary_free(vm_paddr_t pa) 2086{ 2087 int cpu; 2088 register_t intr; 2089 struct local_sysmaps *sysm; 2090 2091 if (pa < MIPS_KSEG0_LARGEST_PHYS) { 2092 /* nothing to do for this case */ 2093 return; 2094 } 2095 cpu = PCPU_GET(cpuid); 2096 sysm = &sysmap_lmem[cpu]; 2097 if (sysm->valid1) { 2098 pt_entry_t *pte; 2099 2100 intr = intr_disable(); 2101 pte = pmap_pte(kernel_pmap, sysm->base); 2102 *pte = PTE_G; 2103 pmap_invalidate_page(kernel_pmap, sysm->base); 2104 intr_restore(intr); 2105 sysm->valid1 = 0; 2106 } 2107} 2108 2109/* 2110 * Moved the code to Machine Independent 2111 * vm_map_pmap_enter() 2112 */ 2113 2114/* 2115 * Maps a sequence of resident pages belonging to the same object. 2116 * The sequence begins with the given page m_start. This page is 2117 * mapped at the given virtual address start. Each subsequent page is 2118 * mapped at a virtual address that is offset from start by the same 2119 * amount as the page is offset from m_start within the object. The 2120 * last page in the sequence is the page with the largest offset from 2121 * m_start that can be mapped at a virtual address less than the given 2122 * virtual address end. Not every virtual page between start and end 2123 * is mapped; only those for which a resident page exists with the 2124 * corresponding offset from m_start are mapped. 2125 */ 2126void 2127pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 2128 vm_page_t m_start, vm_prot_t prot) 2129{ 2130 vm_page_t m, mpte; 2131 vm_pindex_t diff, psize; 2132 2133 VM_OBJECT_LOCK_ASSERT(m_start->object, MA_OWNED); 2134 psize = atop(end - start); 2135 mpte = NULL; 2136 m = m_start; 2137 PMAP_LOCK(pmap); 2138 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 2139 mpte = pmap_enter_quick_locked(pmap, start + ptoa(diff), m, 2140 prot, mpte); 2141 m = TAILQ_NEXT(m, listq); 2142 } 2143 PMAP_UNLOCK(pmap); 2144} 2145 2146/* 2147 * pmap_object_init_pt preloads the ptes for a given object 2148 * into the specified pmap. This eliminates the blast of soft 2149 * faults on process startup and immediately after an mmap. 2150 */ 2151void 2152pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, 2153 vm_object_t object, vm_pindex_t pindex, vm_size_t size) 2154{ 2155 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 2156 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 2157 ("pmap_object_init_pt: non-device object")); 2158} 2159 2160/* 2161 * Routine: pmap_change_wiring 2162 * Function: Change the wiring attribute for a map/virtual-address 2163 * pair. 2164 * In/out conditions: 2165 * The mapping must already exist in the pmap. 2166 */ 2167void 2168pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 2169{ 2170 register pt_entry_t *pte; 2171 2172 if (pmap == NULL) 2173 return; 2174 2175 PMAP_LOCK(pmap); 2176 pte = pmap_pte(pmap, va); 2177 2178 if (wired && !pmap_pte_w(pte)) 2179 pmap->pm_stats.wired_count++; 2180 else if (!wired && pmap_pte_w(pte)) 2181 pmap->pm_stats.wired_count--; 2182 2183 /* 2184 * Wiring is not a hardware characteristic so there is no need to 2185 * invalidate TLB. 2186 */ 2187 pmap_pte_set_w(pte, wired); 2188 PMAP_UNLOCK(pmap); 2189} 2190 2191/* 2192 * Copy the range specified by src_addr/len 2193 * from the source map to the range dst_addr/len 2194 * in the destination map. 2195 * 2196 * This routine is only advisory and need not do anything. 2197 */ 2198 2199void 2200pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, 2201 vm_size_t len, vm_offset_t src_addr) 2202{ 2203} 2204 2205/* 2206 * pmap_zero_page zeros the specified hardware page by mapping 2207 * the page into KVM and using bzero to clear its contents. 2208 */ 2209void 2210pmap_zero_page(vm_page_t m) 2211{ 2212 vm_offset_t va; 2213 vm_paddr_t phys = VM_PAGE_TO_PHYS(m); 2214 register_t intr; 2215 2216 if (phys < MIPS_KSEG0_LARGEST_PHYS) { 2217 va = MIPS_PHYS_TO_KSEG0(phys); 2218 2219 bzero((caddr_t)va, PAGE_SIZE); 2220 mips_dcache_wbinv_range(va, PAGE_SIZE); 2221 } else { 2222 PMAP_LMEM_MAP1(va, phys); 2223 2224 bzero((caddr_t)va, PAGE_SIZE); 2225 mips_dcache_wbinv_range(va, PAGE_SIZE); 2226 2227 PMAP_LMEM_UNMAP(); 2228 } 2229} 2230 2231/* 2232 * pmap_zero_page_area zeros the specified hardware page by mapping 2233 * the page into KVM and using bzero to clear its contents. 2234 * 2235 * off and size may not cover an area beyond a single hardware page. 2236 */ 2237void 2238pmap_zero_page_area(vm_page_t m, int off, int size) 2239{ 2240 vm_offset_t va; 2241 vm_paddr_t phys = VM_PAGE_TO_PHYS(m); 2242 register_t intr; 2243 2244 if (phys < MIPS_KSEG0_LARGEST_PHYS) { 2245 va = MIPS_PHYS_TO_KSEG0(phys); 2246 bzero((char *)(caddr_t)va + off, size); 2247 mips_dcache_wbinv_range(va + off, size); 2248 } else { 2249 PMAP_LMEM_MAP1(va, phys); 2250 2251 bzero((char *)va + off, size); 2252 mips_dcache_wbinv_range(va + off, size); 2253 2254 PMAP_LMEM_UNMAP(); 2255 } 2256} 2257 2258void 2259pmap_zero_page_idle(vm_page_t m) 2260{ 2261 vm_offset_t va; 2262 vm_paddr_t phys = VM_PAGE_TO_PHYS(m); 2263 register_t intr; 2264 2265 if (phys < MIPS_KSEG0_LARGEST_PHYS) { 2266 va = MIPS_PHYS_TO_KSEG0(phys); 2267 bzero((caddr_t)va, PAGE_SIZE); 2268 mips_dcache_wbinv_range(va, PAGE_SIZE); 2269 } else { 2270 PMAP_LMEM_MAP1(va, phys); 2271 2272 bzero((caddr_t)va, PAGE_SIZE); 2273 mips_dcache_wbinv_range(va, PAGE_SIZE); 2274 2275 PMAP_LMEM_UNMAP(); 2276 } 2277} 2278 2279/* 2280 * pmap_copy_page copies the specified (machine independent) 2281 * page by mapping the page into virtual memory and using 2282 * bcopy to copy the page, one machine dependent page at a 2283 * time. 2284 */ 2285void 2286pmap_copy_page(vm_page_t src, vm_page_t dst) 2287{ 2288 vm_offset_t va_src, va_dst; 2289 vm_paddr_t phy_src = VM_PAGE_TO_PHYS(src); 2290 vm_paddr_t phy_dst = VM_PAGE_TO_PHYS(dst); 2291 register_t intr; 2292 2293 if ((phy_src < MIPS_KSEG0_LARGEST_PHYS) && (phy_dst < MIPS_KSEG0_LARGEST_PHYS)) { 2294 /* easy case, all can be accessed via KSEG0 */ 2295 /* 2296 * Flush all caches for VA that are mapped to this page 2297 * to make sure that data in SDRAM is up to date 2298 */ 2299 pmap_flush_pvcache(src); 2300 mips_dcache_wbinv_range_index( 2301 MIPS_PHYS_TO_KSEG0(phy_dst), PAGE_SIZE); 2302 va_src = MIPS_PHYS_TO_KSEG0(phy_src); 2303 va_dst = MIPS_PHYS_TO_KSEG0(phy_dst); 2304 bcopy((caddr_t)va_src, (caddr_t)va_dst, PAGE_SIZE); 2305 mips_dcache_wbinv_range(va_dst, PAGE_SIZE); 2306 } else { 2307 PMAP_LMEM_MAP2(va_src, phy_src, va_dst, phy_dst); 2308 2309 bcopy((void *)va_src, (void *)va_dst, PAGE_SIZE); 2310 mips_dcache_wbinv_range(va_dst, PAGE_SIZE); 2311 2312 PMAP_LMEM_UNMAP(); 2313 } 2314} 2315 2316/* 2317 * Returns true if the pmap's pv is one of the first 2318 * 16 pvs linked to from this page. This count may 2319 * be changed upwards or downwards in the future; it 2320 * is only necessary that true be returned for a small 2321 * subset of pmaps for proper page aging. 2322 */ 2323boolean_t 2324pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 2325{ 2326 pv_entry_t pv; 2327 int loops = 0; 2328 2329 if (m->flags & PG_FICTITIOUS) 2330 return FALSE; 2331 2332 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2333 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2334 if (pv->pv_pmap == pmap) { 2335 return TRUE; 2336 } 2337 loops++; 2338 if (loops >= 16) 2339 break; 2340 } 2341 return (FALSE); 2342} 2343 2344/* 2345 * Remove all pages from specified address space 2346 * this aids process exit speeds. Also, this code 2347 * is special cased for current process only, but 2348 * can have the more generic (and slightly slower) 2349 * mode enabled. This is much faster than pmap_remove 2350 * in the case of running down an entire address space. 2351 */ 2352void 2353pmap_remove_pages(pmap_t pmap) 2354{ 2355 pt_entry_t *pte, tpte; 2356 pv_entry_t pv, npv; 2357 vm_page_t m; 2358 2359 if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) { 2360 printf("warning: pmap_remove_pages called with non-current pmap\n"); 2361 return; 2362 } 2363 vm_page_lock_queues(); 2364 PMAP_LOCK(pmap); 2365 sched_pin(); 2366 //XXX need to be TAILQ_FOREACH_SAFE ? 2367 for (pv = TAILQ_FIRST(&pmap->pm_pvlist); pv; pv = npv) { 2368 2369 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 2370 if (!pmap_pte_v(pte)) 2371 panic("pmap_remove_pages: page on pm_pvlist has no pte\n"); 2372 tpte = *pte; 2373 2374/* 2375 * We cannot remove wired pages from a process' mapping at this time 2376 */ 2377 if (tpte & PTE_W) { 2378 npv = TAILQ_NEXT(pv, pv_plist); 2379 continue; 2380 } 2381 *pte = is_kernel_pmap(pmap) ? PTE_G : 0; 2382 2383 m = PHYS_TO_VM_PAGE(mips_tlbpfn_to_paddr(tpte)); 2384 KASSERT(m != NULL, 2385 ("pmap_remove_pages: bad tpte %x", tpte)); 2386 2387 pv->pv_pmap->pm_stats.resident_count--; 2388 2389 /* 2390 * Update the vm_page_t clean and reference bits. 2391 */ 2392 if (tpte & PTE_M) { 2393 vm_page_dirty(m); 2394 } 2395 npv = TAILQ_NEXT(pv, pv_plist); 2396 TAILQ_REMOVE(&pv->pv_pmap->pm_pvlist, pv, pv_plist); 2397 2398 m->md.pv_list_count--; 2399 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2400 if (TAILQ_FIRST(&m->md.pv_list) == NULL) { 2401 vm_page_flag_clear(m, PG_WRITEABLE); 2402 } 2403 pmap_unuse_pt(pv->pv_pmap, pv->pv_va, pv->pv_ptem); 2404 free_pv_entry(pv); 2405 } 2406 sched_unpin(); 2407 pmap_invalidate_all(pmap); 2408 PMAP_UNLOCK(pmap); 2409 vm_page_unlock_queues(); 2410} 2411 2412/* 2413 * pmap_testbit tests bits in pte's 2414 * note that the testbit/changebit routines are inline, 2415 * and a lot of things compile-time evaluate. 2416 */ 2417static boolean_t 2418pmap_testbit(vm_page_t m, int bit) 2419{ 2420 pv_entry_t pv; 2421 pt_entry_t *pte; 2422 boolean_t rv = FALSE; 2423 2424 if (m->flags & PG_FICTITIOUS) 2425 return rv; 2426 2427 if (TAILQ_FIRST(&m->md.pv_list) == NULL) 2428 return rv; 2429 2430 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2431 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2432#if defined(PMAP_DIAGNOSTIC) 2433 if (!pv->pv_pmap) { 2434 printf("Null pmap (tb) at va: 0x%x\n", pv->pv_va); 2435 continue; 2436 } 2437#endif 2438 PMAP_LOCK(pv->pv_pmap); 2439 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 2440 rv = (*pte & bit) != 0; 2441 PMAP_UNLOCK(pv->pv_pmap); 2442 if (rv) 2443 break; 2444 } 2445 return (rv); 2446} 2447 2448/* 2449 * this routine is used to modify bits in ptes 2450 */ 2451static __inline void 2452pmap_changebit(vm_page_t m, int bit, boolean_t setem) 2453{ 2454 register pv_entry_t pv; 2455 register pt_entry_t *pte; 2456 2457 if (m->flags & PG_FICTITIOUS) 2458 return; 2459 2460 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2461 /* 2462 * Loop over all current mappings setting/clearing as appropos If 2463 * setting RO do we need to clear the VAC? 2464 */ 2465 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2466#if defined(PMAP_DIAGNOSTIC) 2467 if (!pv->pv_pmap) { 2468 printf("Null pmap (cb) at va: 0x%x\n", pv->pv_va); 2469 continue; 2470 } 2471#endif 2472 2473 PMAP_LOCK(pv->pv_pmap); 2474 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 2475 2476 if (setem) { 2477 *(int *)pte |= bit; 2478 pmap_update_page(pv->pv_pmap, pv->pv_va, *pte); 2479 } else { 2480 vm_offset_t pbits = *(vm_offset_t *)pte; 2481 2482 if (pbits & bit) { 2483 if (bit == PTE_RW) { 2484 if (pbits & PTE_M) { 2485 vm_page_dirty(m); 2486 } 2487 *(int *)pte = (pbits & ~(PTE_M | PTE_RW)) | 2488 PTE_RO; 2489 } else { 2490 *(int *)pte = pbits & ~bit; 2491 } 2492 pmap_update_page(pv->pv_pmap, pv->pv_va, *pte); 2493 } 2494 } 2495 PMAP_UNLOCK(pv->pv_pmap); 2496 } 2497 if (!setem && bit == PTE_RW) 2498 vm_page_flag_clear(m, PG_WRITEABLE); 2499} 2500 2501/* 2502 * pmap_page_wired_mappings: 2503 * 2504 * Return the number of managed mappings to the given physical page 2505 * that are wired. 2506 */ 2507int 2508pmap_page_wired_mappings(vm_page_t m) 2509{ 2510 pv_entry_t pv; 2511 int count; 2512 2513 count = 0; 2514 if ((m->flags & PG_FICTITIOUS) != 0) 2515 return (count); 2516 vm_page_lock_queues(); 2517 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) 2518 if (pv->pv_wired) 2519 count++; 2520 vm_page_unlock_queues(); 2521 return (count); 2522} 2523 2524/* 2525 * Clear the write and modified bits in each of the given page's mappings. 2526 */ 2527void 2528pmap_remove_write(vm_page_t m) 2529{ 2530 pv_entry_t pv, npv; 2531 vm_offset_t va; 2532 pt_entry_t *pte; 2533 2534 if ((m->flags & PG_FICTITIOUS) != 0 || 2535 (m->flags & PG_WRITEABLE) == 0) 2536 return; 2537 2538 /* 2539 * Loop over all current mappings setting/clearing as appropos. 2540 */ 2541 vm_page_lock_queues(); 2542 for (pv = TAILQ_FIRST(&m->md.pv_list); pv; pv = npv) { 2543 npv = TAILQ_NEXT(pv, pv_plist); 2544 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 2545 2546 if ((pte == NULL) || !mips_pg_v(*pte)) 2547 panic("page on pm_pvlist has no pte\n"); 2548 2549 va = pv->pv_va; 2550 pmap_protect(pv->pv_pmap, va, va + PAGE_SIZE, 2551 VM_PROT_READ | VM_PROT_EXECUTE); 2552 } 2553 vm_page_flag_clear(m, PG_WRITEABLE); 2554 vm_page_unlock_queues(); 2555} 2556 2557/* 2558 * pmap_ts_referenced: 2559 * 2560 * Return the count of reference bits for a page, clearing all of them. 2561 */ 2562int 2563pmap_ts_referenced(vm_page_t m) 2564{ 2565 if (m->flags & PG_FICTITIOUS) 2566 return (0); 2567 2568 if (m->md.pv_flags & PV_TABLE_REF) { 2569 m->md.pv_flags &= ~PV_TABLE_REF; 2570 return 1; 2571 } 2572 return 0; 2573} 2574 2575/* 2576 * pmap_is_modified: 2577 * 2578 * Return whether or not the specified physical page was modified 2579 * in any physical maps. 2580 */ 2581boolean_t 2582pmap_is_modified(vm_page_t m) 2583{ 2584 if (m->flags & PG_FICTITIOUS) 2585 return FALSE; 2586 2587 if (m->md.pv_flags & PV_TABLE_MOD) 2588 return TRUE; 2589 else 2590 return pmap_testbit(m, PTE_M); 2591} 2592 2593/* N/C */ 2594 2595/* 2596 * pmap_is_prefaultable: 2597 * 2598 * Return whether or not the specified virtual address is elgible 2599 * for prefault. 2600 */ 2601boolean_t 2602pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 2603{ 2604 pt_entry_t *pte; 2605 boolean_t rv; 2606 2607 rv = FALSE; 2608 PMAP_LOCK(pmap); 2609 if (*pmap_pde(pmap, addr)) { 2610 pte = pmap_pte(pmap, addr); 2611 rv = (*pte == 0); 2612 } 2613 PMAP_UNLOCK(pmap); 2614 return (rv); 2615} 2616 2617/* 2618 * Clear the modify bits on the specified physical page. 2619 */ 2620void 2621pmap_clear_modify(vm_page_t m) 2622{ 2623 if (m->flags & PG_FICTITIOUS) 2624 return; 2625 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2626 if (m->md.pv_flags & PV_TABLE_MOD) { 2627 pmap_changebit(m, PTE_M, FALSE); 2628 m->md.pv_flags &= ~PV_TABLE_MOD; 2629 } 2630} 2631 2632/* 2633 * pmap_is_referenced: 2634 * 2635 * Return whether or not the specified physical page was referenced 2636 * in any physical maps. 2637 */ 2638boolean_t 2639pmap_is_referenced(vm_page_t m) 2640{ 2641 2642 return ((m->flags & PG_FICTITIOUS) == 0 && 2643 (m->md.pv_flags & PV_TABLE_REF) != 0); 2644} 2645 2646/* 2647 * pmap_clear_reference: 2648 * 2649 * Clear the reference bit on the specified physical page. 2650 */ 2651void 2652pmap_clear_reference(vm_page_t m) 2653{ 2654 if (m->flags & PG_FICTITIOUS) 2655 return; 2656 2657 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2658 if (m->md.pv_flags & PV_TABLE_REF) { 2659 m->md.pv_flags &= ~PV_TABLE_REF; 2660 } 2661} 2662 2663/* 2664 * Miscellaneous support routines follow 2665 */ 2666 2667/* 2668 * Map a set of physical memory pages into the kernel virtual 2669 * address space. Return a pointer to where it is mapped. This 2670 * routine is intended to be used for mapping device memory, 2671 * NOT real memory. 2672 */ 2673 2674/* 2675 * Map a set of physical memory pages into the kernel virtual 2676 * address space. Return a pointer to where it is mapped. This 2677 * routine is intended to be used for mapping device memory, 2678 * NOT real memory. 2679 */ 2680void * 2681pmap_mapdev(vm_offset_t pa, vm_size_t size) 2682{ 2683 vm_offset_t va, tmpva, offset; 2684 2685 /* 2686 * KSEG1 maps only first 512M of phys address space. For 2687 * pa > 0x20000000 we should make proper mapping * using pmap_kenter. 2688 */ 2689 if ((pa + size - 1) < MIPS_KSEG0_LARGEST_PHYS) 2690 return (void *)MIPS_PHYS_TO_KSEG1(pa); 2691 else { 2692 offset = pa & PAGE_MASK; 2693 size = roundup(size + offset, PAGE_SIZE); 2694 2695 va = kmem_alloc_nofault(kernel_map, size); 2696 if (!va) 2697 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 2698 pa = trunc_page(pa); 2699 for (tmpva = va; size > 0;) { 2700 pmap_kenter(tmpva, pa); 2701 size -= PAGE_SIZE; 2702 tmpva += PAGE_SIZE; 2703 pa += PAGE_SIZE; 2704 } 2705 } 2706 2707 return ((void *)(va + offset)); 2708} 2709 2710void 2711pmap_unmapdev(vm_offset_t va, vm_size_t size) 2712{ 2713 vm_offset_t base, offset, tmpva; 2714 2715 /* If the address is within KSEG1 then there is nothing to do */ 2716 if (va >= MIPS_KSEG1_START && va <= MIPS_KSEG1_END) 2717 return; 2718 2719 base = trunc_page(va); 2720 offset = va & PAGE_MASK; 2721 size = roundup(size + offset, PAGE_SIZE); 2722 for (tmpva = base; tmpva < base + size; tmpva += PAGE_SIZE) 2723 pmap_kremove(tmpva); 2724 kmem_free(kernel_map, base, size); 2725} 2726 2727/* 2728 * perform the pmap work for mincore 2729 */ 2730int 2731pmap_mincore(pmap_t pmap, vm_offset_t addr) 2732{ 2733 2734 pt_entry_t *ptep, pte; 2735 vm_page_t m; 2736 int val = 0; 2737 2738 PMAP_LOCK(pmap); 2739 ptep = pmap_pte(pmap, addr); 2740 pte = (ptep != NULL) ? *ptep : 0; 2741 PMAP_UNLOCK(pmap); 2742 2743 if (mips_pg_v(pte)) { 2744 vm_offset_t pa; 2745 2746 val = MINCORE_INCORE; 2747 pa = mips_tlbpfn_to_paddr(pte); 2748 if (!page_is_managed(pa)) 2749 return val; 2750 2751 m = PHYS_TO_VM_PAGE(pa); 2752 2753 /* 2754 * Modified by us 2755 */ 2756 if (pte & PTE_M) 2757 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 2758 /* 2759 * Modified by someone 2760 */ 2761 else { 2762 vm_page_lock_queues(); 2763 if (m->dirty || pmap_is_modified(m)) 2764 val |= MINCORE_MODIFIED_OTHER; 2765 vm_page_unlock_queues(); 2766 } 2767 /* 2768 * Referenced by us or someone 2769 */ 2770 vm_page_lock_queues(); 2771 if ((m->flags & PG_REFERENCED) || pmap_is_referenced(m)) 2772 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 2773 vm_page_unlock_queues(); 2774 } 2775 return val; 2776} 2777 2778void 2779pmap_activate(struct thread *td) 2780{ 2781 pmap_t pmap, oldpmap; 2782 struct proc *p = td->td_proc; 2783 2784 critical_enter(); 2785 2786 pmap = vmspace_pmap(p->p_vmspace); 2787 oldpmap = PCPU_GET(curpmap); 2788 2789 if (oldpmap) 2790 atomic_clear_32(&oldpmap->pm_active, PCPU_GET(cpumask)); 2791 atomic_set_32(&pmap->pm_active, PCPU_GET(cpumask)); 2792 pmap_asid_alloc(pmap); 2793 if (td == curthread) { 2794 PCPU_SET(segbase, pmap->pm_segtab); 2795 MachSetPID(pmap->pm_asid[PCPU_GET(cpuid)].asid); 2796 } 2797 2798 PCPU_SET(curpmap, pmap); 2799 critical_exit(); 2800} 2801 2802void 2803pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 2804{ 2805} 2806 2807/* 2808 * Increase the starting virtual address of the given mapping if a 2809 * different alignment might result in more superpage mappings. 2810 */ 2811void 2812pmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 2813 vm_offset_t *addr, vm_size_t size) 2814{ 2815 vm_offset_t superpage_offset; 2816 2817 if (size < NBSEG) 2818 return; 2819 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 2820 offset += ptoa(object->pg_color); 2821 superpage_offset = offset & SEGOFSET; 2822 if (size - ((NBSEG - superpage_offset) & SEGOFSET) < NBSEG || 2823 (*addr & SEGOFSET) == superpage_offset) 2824 return; 2825 if ((*addr & SEGOFSET) < superpage_offset) 2826 *addr = (*addr & ~SEGOFSET) + superpage_offset; 2827 else 2828 *addr = ((*addr + SEGOFSET) & ~SEGOFSET) + superpage_offset; 2829} 2830 2831/* 2832 * Increase the starting virtual address of the given mapping so 2833 * that it is aligned to not be the second page in a TLB entry. 2834 * This routine assumes that the length is appropriately-sized so 2835 * that the allocation does not share a TLB entry at all if required. 2836 */ 2837void 2838pmap_align_tlb(vm_offset_t *addr) 2839{ 2840 if ((*addr & PAGE_SIZE) == 0) 2841 return; 2842 *addr += PAGE_SIZE; 2843 return; 2844} 2845 2846int pmap_pid_dump(int pid); 2847 2848int 2849pmap_pid_dump(int pid) 2850{ 2851 pmap_t pmap; 2852 struct proc *p; 2853 int npte = 0; 2854 int index; 2855 2856 sx_slock(&allproc_lock); 2857 LIST_FOREACH(p, &allproc, p_list) { 2858 if (p->p_pid != pid) 2859 continue; 2860 2861 if (p->p_vmspace) { 2862 int i, j; 2863 2864 printf("vmspace is %p\n", 2865 p->p_vmspace); 2866 index = 0; 2867 pmap = vmspace_pmap(p->p_vmspace); 2868 printf("pmap asid:%x generation:%x\n", 2869 pmap->pm_asid[0].asid, 2870 pmap->pm_asid[0].gen); 2871 for (i = 0; i < NUSERPGTBLS; i++) { 2872 pd_entry_t *pde; 2873 pt_entry_t *pte; 2874 unsigned base = i << SEGSHIFT; 2875 2876 pde = &pmap->pm_segtab[i]; 2877 if (pde && pmap_pde_v(pde)) { 2878 for (j = 0; j < 1024; j++) { 2879 vm_offset_t va = base + 2880 (j << PAGE_SHIFT); 2881 2882 pte = pmap_pte(pmap, va); 2883 if (pte && pmap_pte_v(pte)) { 2884 vm_offset_t pa; 2885 vm_page_t m; 2886 2887 pa = mips_tlbpfn_to_paddr(*pte); 2888 m = PHYS_TO_VM_PAGE(pa); 2889 printf("va: %p, pt: %p, h: %d, w: %d, f: 0x%x", 2890 (void *)va, 2891 (void *)pa, 2892 m->hold_count, 2893 m->wire_count, 2894 m->flags); 2895 npte++; 2896 index++; 2897 if (index >= 2) { 2898 index = 0; 2899 printf("\n"); 2900 } else { 2901 printf(" "); 2902 } 2903 } 2904 } 2905 } 2906 } 2907 } else { 2908 printf("Process pid:%d has no vm_space\n", pid); 2909 } 2910 break; 2911 } 2912 sx_sunlock(&allproc_lock); 2913 return npte; 2914} 2915 2916 2917#if defined(DEBUG) 2918 2919static void pads(pmap_t pm); 2920void pmap_pvdump(vm_offset_t pa); 2921 2922/* print address space of pmap*/ 2923static void 2924pads(pmap_t pm) 2925{ 2926 unsigned va, i, j; 2927 pt_entry_t *ptep; 2928 2929 if (pm == kernel_pmap) 2930 return; 2931 for (i = 0; i < NPTEPG; i++) 2932 if (pm->pm_segtab[i]) 2933 for (j = 0; j < NPTEPG; j++) { 2934 va = (i << SEGSHIFT) + (j << PAGE_SHIFT); 2935 if (pm == kernel_pmap && va < KERNBASE) 2936 continue; 2937 if (pm != kernel_pmap && 2938 va >= VM_MAXUSER_ADDRESS) 2939 continue; 2940 ptep = pmap_pte(pm, va); 2941 if (pmap_pte_v(ptep)) 2942 printf("%x:%x ", va, *(int *)ptep); 2943 } 2944 2945} 2946 2947void 2948pmap_pvdump(vm_offset_t pa) 2949{ 2950 register pv_entry_t pv; 2951 vm_page_t m; 2952 2953 printf("pa %x", pa); 2954 m = PHYS_TO_VM_PAGE(pa); 2955 for (pv = TAILQ_FIRST(&m->md.pv_list); pv; 2956 pv = TAILQ_NEXT(pv, pv_list)) { 2957 printf(" -> pmap %p, va %x", (void *)pv->pv_pmap, pv->pv_va); 2958 pads(pv->pv_pmap); 2959 } 2960 printf(" "); 2961} 2962 2963/* N/C */ 2964#endif 2965 2966 2967/* 2968 * Allocate TLB address space tag (called ASID or TLBPID) and return it. 2969 * It takes almost as much or more time to search the TLB for a 2970 * specific ASID and flush those entries as it does to flush the entire TLB. 2971 * Therefore, when we allocate a new ASID, we just take the next number. When 2972 * we run out of numbers, we flush the TLB, increment the generation count 2973 * and start over. ASID zero is reserved for kernel use. 2974 */ 2975static void 2976pmap_asid_alloc(pmap) 2977 pmap_t pmap; 2978{ 2979 if (pmap->pm_asid[PCPU_GET(cpuid)].asid != PMAP_ASID_RESERVED && 2980 pmap->pm_asid[PCPU_GET(cpuid)].gen == PCPU_GET(asid_generation)); 2981 else { 2982 if (PCPU_GET(next_asid) == pmap_max_asid) { 2983 MIPS_TBIAP(); 2984 PCPU_SET(asid_generation, 2985 (PCPU_GET(asid_generation) + 1) & ASIDGEN_MASK); 2986 if (PCPU_GET(asid_generation) == 0) { 2987 PCPU_SET(asid_generation, 1); 2988 } 2989 PCPU_SET(next_asid, 1); /* 0 means invalid */ 2990 } 2991 pmap->pm_asid[PCPU_GET(cpuid)].asid = PCPU_GET(next_asid); 2992 pmap->pm_asid[PCPU_GET(cpuid)].gen = PCPU_GET(asid_generation); 2993 PCPU_SET(next_asid, PCPU_GET(next_asid) + 1); 2994 } 2995} 2996 2997int 2998page_is_managed(vm_offset_t pa) 2999{ 3000 vm_offset_t pgnum = mips_btop(pa); 3001 3002 if (pgnum >= first_page) { 3003 vm_page_t m; 3004 3005 m = PHYS_TO_VM_PAGE(pa); 3006 if (m == NULL) 3007 return 0; 3008 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) 3009 return 1; 3010 } 3011 return 0; 3012} 3013 3014static int 3015init_pte_prot(vm_offset_t va, vm_page_t m, vm_prot_t prot) 3016{ 3017 int rw = 0; 3018 3019 if (!(prot & VM_PROT_WRITE)) 3020 rw = PTE_ROPAGE; 3021 else { 3022 if (va >= VM_MIN_KERNEL_ADDRESS) { 3023 /* 3024 * Don't bother to trap on kernel writes, just 3025 * record page as dirty. 3026 */ 3027 rw = PTE_RWPAGE; 3028 vm_page_dirty(m); 3029 } else if ((m->md.pv_flags & PV_TABLE_MOD) || 3030 m->dirty == VM_PAGE_BITS_ALL) 3031 rw = PTE_RWPAGE; 3032 else 3033 rw = PTE_CWPAGE; 3034 vm_page_flag_set(m, PG_WRITEABLE); 3035 } 3036 return rw; 3037} 3038 3039/* 3040 * pmap_set_modified: 3041 * 3042 * Sets the page modified and reference bits for the specified page. 3043 */ 3044void 3045pmap_set_modified(vm_offset_t pa) 3046{ 3047 3048 PHYS_TO_VM_PAGE(pa)->md.pv_flags |= (PV_TABLE_REF | PV_TABLE_MOD); 3049} 3050 3051/* 3052 * Routine: pmap_kextract 3053 * Function: 3054 * Extract the physical page address associated 3055 * virtual address. 3056 */ 3057 /* PMAP_INLINE */ vm_offset_t 3058pmap_kextract(vm_offset_t va) 3059{ 3060 vm_offset_t pa = 0; 3061 3062 if (va < MIPS_KSEG0_START) { 3063 /* user virtual address */ 3064 pt_entry_t *ptep; 3065 3066 if (curproc && curproc->p_vmspace) { 3067 ptep = pmap_pte(&curproc->p_vmspace->vm_pmap, va); 3068 if (ptep) 3069 pa = mips_tlbpfn_to_paddr(*ptep) | 3070 (va & PAGE_MASK); 3071 } 3072 } else if (va >= MIPS_KSEG0_START && 3073 va < MIPS_KSEG1_START) 3074 pa = MIPS_KSEG0_TO_PHYS(va); 3075 else if (va >= MIPS_KSEG1_START && 3076 va < MIPS_KSEG2_START) 3077 pa = MIPS_KSEG1_TO_PHYS(va); 3078 else if (va >= MIPS_KSEG2_START && va < VM_MAX_KERNEL_ADDRESS) { 3079 pt_entry_t *ptep; 3080 3081 /* Is the kernel pmap initialized? */ 3082 if (kernel_pmap->pm_active) { 3083 /* Its inside the virtual address range */ 3084 ptep = pmap_pte(kernel_pmap, va); 3085 if (ptep) 3086 pa = mips_tlbpfn_to_paddr(*ptep) | 3087 (va & PAGE_MASK); 3088 } 3089 } 3090 return pa; 3091} 3092 3093void 3094pmap_flush_pvcache(vm_page_t m) 3095{ 3096 pv_entry_t pv; 3097 3098 if (m != NULL) { 3099 for (pv = TAILQ_FIRST(&m->md.pv_list); pv; 3100 pv = TAILQ_NEXT(pv, pv_list)) { 3101 mips_dcache_wbinv_range_index(pv->pv_va, PAGE_SIZE); 3102 } 3103 } 3104} 3105 3106void 3107pmap_save_tlb(void) 3108{ 3109 int tlbno, cpu; 3110 3111 cpu = PCPU_GET(cpuid); 3112 3113 for (tlbno = 0; tlbno < num_tlbentries; ++tlbno) 3114 MachTLBRead(tlbno, &tlbstash[cpu][tlbno]); 3115} 3116 3117#ifdef DDB 3118#include <ddb/ddb.h> 3119 3120DB_SHOW_COMMAND(tlb, ddb_dump_tlb) 3121{ 3122 int cpu, tlbno; 3123 struct tlb *tlb; 3124 3125 if (have_addr) 3126 cpu = ((addr >> 4) % 16) * 10 + (addr % 16); 3127 else 3128 cpu = PCPU_GET(cpuid); 3129 3130 if (cpu < 0 || cpu >= mp_ncpus) { 3131 db_printf("Invalid CPU %d\n", cpu); 3132 return; 3133 } else 3134 db_printf("CPU %d:\n", cpu); 3135 3136 if (cpu == PCPU_GET(cpuid)) 3137 pmap_save_tlb(); 3138 3139 for (tlbno = 0; tlbno < num_tlbentries; ++tlbno) { 3140 tlb = &tlbstash[cpu][tlbno]; 3141 if (tlb->tlb_lo0 & PTE_V || tlb->tlb_lo1 & PTE_V) { 3142 printf("TLB %2d vad 0x%0lx ", 3143 tlbno, (long)(tlb->tlb_hi & 0xffffff00)); 3144 } else { 3145 printf("TLB*%2d vad 0x%0lx ", 3146 tlbno, (long)(tlb->tlb_hi & 0xffffff00)); 3147 } 3148 printf("0=0x%0lx ", pfn_to_vad((long)tlb->tlb_lo0)); 3149 printf("%c", tlb->tlb_lo0 & PTE_V ? 'V' : '-'); 3150 printf("%c", tlb->tlb_lo0 & PTE_M ? 'M' : '-'); 3151 printf("%c", tlb->tlb_lo0 & PTE_G ? 'G' : '-'); 3152 printf(" atr %x ", (tlb->tlb_lo0 >> 3) & 7); 3153 printf("1=0x%0lx ", pfn_to_vad((long)tlb->tlb_lo1)); 3154 printf("%c", tlb->tlb_lo1 & PTE_V ? 'V' : '-'); 3155 printf("%c", tlb->tlb_lo1 & PTE_M ? 'M' : '-'); 3156 printf("%c", tlb->tlb_lo1 & PTE_G ? 'G' : '-'); 3157 printf(" atr %x ", (tlb->tlb_lo1 >> 3) & 7); 3158 printf(" sz=%x pid=%x\n", tlb->tlb_mask, 3159 (tlb->tlb_hi & 0x000000ff)); 3160 } 3161} 3162#endif /* DDB */ 3163