pmap.c revision 206717
1/* 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * Copyright (c) 1994 John S. Dyson 5 * All rights reserved. 6 * Copyright (c) 1994 David Greenman 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * the Systems Programming Group of the University of Utah Computer 11 * Science Department and William Jolitz of UUNET Technologies Inc. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 38 * from: src/sys/i386/i386/pmap.c,v 1.250.2.8 2000/11/21 00:09:14 ps 39 * JNPR: pmap.c,v 1.11.2.1 2007/08/16 11:51:06 girish 40 */ 41 42/* 43 * Manages physical address maps. 44 * 45 * In addition to hardware address maps, this 46 * module is called upon to provide software-use-only 47 * maps which may or may not be stored in the same 48 * form as hardware maps. These pseudo-maps are 49 * used to store intermediate results from copy 50 * operations to and from address spaces. 51 * 52 * Since the information managed by this module is 53 * also stored by the logical address mapping module, 54 * this module may throw away valid virtual-to-physical 55 * mappings at almost any time. However, invalidations 56 * of virtual-to-physical mappings must be done as 57 * requested. 58 * 59 * In order to cope with hardware architectures which 60 * make virtual-to-physical map invalidates expensive, 61 * this module may delay invalidate or reduced protection 62 * operations until such time as they are actually 63 * necessary. This module is given full information as 64 * to which processors are currently using which maps, 65 * and to when physical maps must be made correct. 66 */ 67 68#include <sys/cdefs.h> 69__FBSDID("$FreeBSD: head/sys/mips/mips/pmap.c 206717 2010-04-17 01:17:31Z jmallett $"); 70 71#include "opt_ddb.h" 72#include "opt_msgbuf.h" 73#include <sys/param.h> 74#include <sys/systm.h> 75#include <sys/proc.h> 76#include <sys/msgbuf.h> 77#include <sys/vmmeter.h> 78#include <sys/mman.h> 79#include <sys/smp.h> 80 81#include <vm/vm.h> 82#include <vm/vm_param.h> 83#include <sys/lock.h> 84#include <sys/mutex.h> 85#include <vm/vm_kern.h> 86#include <vm/vm_page.h> 87#include <vm/vm_map.h> 88#include <vm/vm_object.h> 89#include <vm/vm_extern.h> 90#include <vm/vm_pageout.h> 91#include <vm/vm_pager.h> 92#include <vm/uma.h> 93#include <sys/pcpu.h> 94#include <sys/sched.h> 95#ifdef SMP 96#include <sys/smp.h> 97#endif 98 99#include <machine/cache.h> 100#include <machine/md_var.h> 101 102#if defined(DIAGNOSTIC) 103#define PMAP_DIAGNOSTIC 104#endif 105 106#undef PMAP_DEBUG 107 108#ifndef PMAP_SHPGPERPROC 109#define PMAP_SHPGPERPROC 200 110#endif 111 112#if !defined(PMAP_DIAGNOSTIC) 113#define PMAP_INLINE __inline 114#else 115#define PMAP_INLINE 116#endif 117 118/* 119 * Get PDEs and PTEs for user/kernel address space 120 */ 121#define pmap_pde(m, v) (&((m)->pm_segtab[(vm_offset_t)(v) >> SEGSHIFT])) 122#define segtab_pde(m, v) (m[(vm_offset_t)(v) >> SEGSHIFT]) 123 124#define pmap_pte_w(pte) ((*(int *)pte & PTE_W) != 0) 125#define pmap_pde_v(pte) ((*(int *)pte) != 0) 126#define pmap_pte_m(pte) ((*(int *)pte & PTE_M) != 0) 127#define pmap_pte_v(pte) ((*(int *)pte & PTE_V) != 0) 128 129#define pmap_pte_set_w(pte, v) ((v)?(*(int *)pte |= PTE_W):(*(int *)pte &= ~PTE_W)) 130#define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v))) 131 132#define MIPS_SEGSIZE (1L << SEGSHIFT) 133#define mips_segtrunc(va) ((va) & ~(MIPS_SEGSIZE-1)) 134#define pmap_TLB_invalidate_all() MIPS_TBIAP() 135#define pmap_va_asid(pmap, va) ((va) | ((pmap)->pm_asid[PCPU_GET(cpuid)].asid << VMTLB_PID_SHIFT)) 136#define is_kernel_pmap(x) ((x) == kernel_pmap) 137 138struct pmap kernel_pmap_store; 139pd_entry_t *kernel_segmap; 140 141vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 142vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 143 144static int nkpt; 145unsigned pmap_max_asid; /* max ASID supported by the system */ 146 147 148#define PMAP_ASID_RESERVED 0 149 150 151vm_offset_t kernel_vm_end; 152 153static struct tlb tlbstash[MAXCPU][MIPS_MAX_TLB_ENTRIES]; 154 155static void pmap_asid_alloc(pmap_t pmap); 156 157/* 158 * Data for the pv entry allocation mechanism 159 */ 160static uma_zone_t pvzone; 161static struct vm_object pvzone_obj; 162static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 163 164static PMAP_INLINE void free_pv_entry(pv_entry_t pv); 165static pv_entry_t get_pv_entry(pmap_t locked_pmap); 166static __inline void pmap_changebit(vm_page_t m, int bit, boolean_t setem); 167 168static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, 169 vm_page_t m, vm_prot_t prot, vm_page_t mpte); 170static int pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va); 171static void pmap_remove_page(struct pmap *pmap, vm_offset_t va); 172static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, vm_offset_t va); 173static boolean_t pmap_testbit(vm_page_t m, int bit); 174static void 175pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t mpte, 176 vm_page_t m, boolean_t wired); 177static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_page_t mpte, 178 vm_offset_t va, vm_page_t m); 179 180static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags); 181 182static vm_page_t _pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags); 183static int pmap_unuse_pt(pmap_t, vm_offset_t, vm_page_t); 184static int init_pte_prot(vm_offset_t va, vm_page_t m, vm_prot_t prot); 185static void pmap_TLB_invalidate_kernel(vm_offset_t); 186static void pmap_TLB_update_kernel(vm_offset_t, pt_entry_t); 187 188#ifdef SMP 189static void pmap_invalidate_page_action(void *arg); 190static void pmap_invalidate_all_action(void *arg); 191static void pmap_update_page_action(void *arg); 192 193#endif 194 195struct local_sysmaps { 196 struct mtx lock; 197 vm_offset_t base; 198 uint16_t valid1, valid2; 199}; 200 201/* This structure is for large memory 202 * above 512Meg. We can't (in 32 bit mode) 203 * just use the direct mapped MIPS_KSEG0_TO_PHYS() 204 * macros since we can't see the memory and must 205 * map it in when we need to access it. In 64 206 * bit mode this goes away. 207 */ 208static struct local_sysmaps sysmap_lmem[MAXCPU]; 209caddr_t virtual_sys_start = (caddr_t)0; 210 211#define PMAP_LMEM_MAP1(va, phys) \ 212 int cpu; \ 213 struct local_sysmaps *sysm; \ 214 pt_entry_t *pte, npte; \ 215 \ 216 cpu = PCPU_GET(cpuid); \ 217 sysm = &sysmap_lmem[cpu]; \ 218 PMAP_LGMEM_LOCK(sysm); \ 219 intr = intr_disable(); \ 220 sched_pin(); \ 221 va = sysm->base; \ 222 npte = mips_paddr_to_tlbpfn(phys) | \ 223 PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; \ 224 pte = pmap_pte(kernel_pmap, va); \ 225 *pte = npte; \ 226 sysm->valid1 = 1; 227 228#define PMAP_LMEM_MAP2(va1, phys1, va2, phys2) \ 229 int cpu; \ 230 struct local_sysmaps *sysm; \ 231 pt_entry_t *pte, npte; \ 232 \ 233 cpu = PCPU_GET(cpuid); \ 234 sysm = &sysmap_lmem[cpu]; \ 235 PMAP_LGMEM_LOCK(sysm); \ 236 intr = intr_disable(); \ 237 sched_pin(); \ 238 va1 = sysm->base; \ 239 va2 = sysm->base + PAGE_SIZE; \ 240 npte = mips_paddr_to_tlbpfn(phys2) | \ 241 PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; \ 242 pte = pmap_pte(kernel_pmap, va1); \ 243 *pte = npte; \ 244 npte = mips_paddr_to_tlbpfn(phys2) | \ 245 PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; \ 246 pte = pmap_pte(kernel_pmap, va2); \ 247 *pte = npte; \ 248 sysm->valid1 = 1; \ 249 sysm->valid2 = 1; 250 251#define PMAP_LMEM_UNMAP() \ 252 pte = pmap_pte(kernel_pmap, sysm->base); \ 253 *pte = PTE_G; \ 254 pmap_invalidate_page(kernel_pmap, sysm->base); \ 255 sysm->valid1 = 0; \ 256 pte = pmap_pte(kernel_pmap, sysm->base + PAGE_SIZE); \ 257 *pte = PTE_G; \ 258 pmap_invalidate_page(kernel_pmap, sysm->base + PAGE_SIZE); \ 259 sysm->valid2 = 0; \ 260 sched_unpin(); \ 261 intr_restore(intr); \ 262 PMAP_LGMEM_UNLOCK(sysm); 263 264pd_entry_t 265pmap_segmap(pmap_t pmap, vm_offset_t va) 266{ 267 if (pmap->pm_segtab) 268 return (pmap->pm_segtab[((vm_offset_t)(va) >> SEGSHIFT)]); 269 else 270 return ((pd_entry_t)0); 271} 272 273/* 274 * Routine: pmap_pte 275 * Function: 276 * Extract the page table entry associated 277 * with the given map/virtual_address pair. 278 */ 279pt_entry_t * 280pmap_pte(pmap_t pmap, vm_offset_t va) 281{ 282 pt_entry_t *pdeaddr; 283 284 if (pmap) { 285 pdeaddr = (pt_entry_t *)pmap_segmap(pmap, va); 286 if (pdeaddr) { 287 return pdeaddr + vad_to_pte_offset(va); 288 } 289 } 290 return ((pt_entry_t *)0); 291} 292 293 294vm_offset_t 295pmap_steal_memory(vm_size_t size) 296{ 297 vm_size_t bank_size; 298 vm_offset_t pa, va; 299 300 size = round_page(size); 301 302 bank_size = phys_avail[1] - phys_avail[0]; 303 while (size > bank_size) { 304 int i; 305 306 for (i = 0; phys_avail[i + 2]; i += 2) { 307 phys_avail[i] = phys_avail[i + 2]; 308 phys_avail[i + 1] = phys_avail[i + 3]; 309 } 310 phys_avail[i] = 0; 311 phys_avail[i + 1] = 0; 312 if (!phys_avail[0]) 313 panic("pmap_steal_memory: out of memory"); 314 bank_size = phys_avail[1] - phys_avail[0]; 315 } 316 317 pa = phys_avail[0]; 318 phys_avail[0] += size; 319 if (pa >= MIPS_KSEG0_LARGEST_PHYS) { 320 panic("Out of memory below 512Meg?"); 321 } 322 va = MIPS_PHYS_TO_KSEG0(pa); 323 bzero((caddr_t)va, size); 324 return va; 325} 326 327/* 328 * Bootstrap the system enough to run with virtual memory. This 329 * assumes that the phys_avail array has been initialized. 330 */ 331void 332pmap_bootstrap(void) 333{ 334 pt_entry_t *pgtab; 335 pt_entry_t *pte; 336 int i, j; 337 int memory_larger_than_512meg = 0; 338 339 /* Sort. */ 340again: 341 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 342 /* 343 * Keep the memory aligned on page boundary. 344 */ 345 phys_avail[i] = round_page(phys_avail[i]); 346 phys_avail[i + 1] = trunc_page(phys_avail[i + 1]); 347 348 if (phys_avail[i + 1] >= MIPS_KSEG0_LARGEST_PHYS) 349 memory_larger_than_512meg++; 350 if (i < 2) 351 continue; 352 if (phys_avail[i - 2] > phys_avail[i]) { 353 vm_paddr_t ptemp[2]; 354 355 356 ptemp[0] = phys_avail[i + 0]; 357 ptemp[1] = phys_avail[i + 1]; 358 359 phys_avail[i + 0] = phys_avail[i - 2]; 360 phys_avail[i + 1] = phys_avail[i - 1]; 361 362 phys_avail[i - 2] = ptemp[0]; 363 phys_avail[i - 1] = ptemp[1]; 364 goto again; 365 } 366 } 367 368 /* 369 * Copy the phys_avail[] array before we start stealing memory from it. 370 */ 371 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 372 physmem_desc[i] = phys_avail[i]; 373 physmem_desc[i + 1] = phys_avail[i + 1]; 374 } 375 376 Maxmem = atop(phys_avail[i - 1]); 377 378 if (bootverbose) { 379 printf("Physical memory chunk(s):\n"); 380 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 381 vm_paddr_t size; 382 383 size = phys_avail[i + 1] - phys_avail[i]; 384 printf("%#08jx - %#08jx, %ju bytes (%ju pages)\n", 385 (uintmax_t) phys_avail[i], 386 (uintmax_t) phys_avail[i + 1] - 1, 387 (uintmax_t) size, (uintmax_t) size / PAGE_SIZE); 388 } 389 printf("Maxmem is 0x%0lx\n", ptoa(Maxmem)); 390 } 391 /* 392 * Steal the message buffer from the beginning of memory. 393 */ 394 msgbufp = (struct msgbuf *)pmap_steal_memory(MSGBUF_SIZE); 395 msgbufinit(msgbufp, MSGBUF_SIZE); 396 397 /* 398 * Steal thread0 kstack. 399 */ 400 kstack0 = pmap_steal_memory(KSTACK_PAGES << PAGE_SHIFT); 401 402 403 virtual_avail = VM_MIN_KERNEL_ADDRESS; 404 virtual_end = VM_MAX_KERNEL_ADDRESS; 405 406#ifdef SMP 407 /* 408 * Steal some virtual address space to map the pcpu area. 409 */ 410 virtual_avail = roundup2(virtual_avail, PAGE_SIZE * 2); 411 pcpup = (struct pcpu *)virtual_avail; 412 virtual_avail += PAGE_SIZE * 2; 413 414 /* 415 * Initialize the wired TLB entry mapping the pcpu region for 416 * the BSP at 'pcpup'. Up until this point we were operating 417 * with the 'pcpup' for the BSP pointing to a virtual address 418 * in KSEG0 so there was no need for a TLB mapping. 419 */ 420 mips_pcpu_tlb_init(PCPU_ADDR(0)); 421 422 if (bootverbose) 423 printf("pcpu is available at virtual address %p.\n", pcpup); 424#endif 425 426 /* 427 * Steal some virtual space that will not be in kernel_segmap. This 428 * va memory space will be used to map in kernel pages that are 429 * outside the 512Meg region. Note that we only do this steal when 430 * we do have memory in this region, that way for systems with 431 * smaller memory we don't "steal" any va ranges :-) 432 */ 433 if (memory_larger_than_512meg) { 434 for (i = 0; i < MAXCPU; i++) { 435 sysmap_lmem[i].base = virtual_avail; 436 virtual_avail += PAGE_SIZE * 2; 437 sysmap_lmem[i].valid1 = sysmap_lmem[i].valid2 = 0; 438 PMAP_LGMEM_LOCK_INIT(&sysmap_lmem[i]); 439 } 440 } 441 virtual_sys_start = (caddr_t)virtual_avail; 442 /* 443 * Allocate segment table for the kernel 444 */ 445 kernel_segmap = (pd_entry_t *)pmap_steal_memory(PAGE_SIZE); 446 447 /* 448 * Allocate second level page tables for the kernel 449 */ 450 nkpt = NKPT; 451 if (memory_larger_than_512meg) { 452 /* 453 * If we have a large memory system we CANNOT afford to hit 454 * pmap_growkernel() and allocate memory. Since we MAY end 455 * up with a page that is NOT mappable. For that reason we 456 * up front grab more. Normall NKPT is 120 (YMMV see pmap.h) 457 * this gives us 480meg of kernel virtual addresses at the 458 * cost of 120 pages (each page gets us 4 Meg). Since the 459 * kernel starts at virtual_avail, we can use this to 460 * calculate how many entris are left from there to the end 461 * of the segmap, we want to allocate all of it, which would 462 * be somewhere above 0xC0000000 - 0xFFFFFFFF which results 463 * in about 256 entries or so instead of the 120. 464 */ 465 nkpt = (PAGE_SIZE / sizeof(pd_entry_t)) - (virtual_avail >> SEGSHIFT); 466 } 467 pgtab = (pt_entry_t *)pmap_steal_memory(PAGE_SIZE * nkpt); 468 469 /* 470 * The R[4-7]?00 stores only one copy of the Global bit in the 471 * translation lookaside buffer for each 2 page entry. Thus invalid 472 * entrys must have the Global bit set so when Entry LO and Entry HI 473 * G bits are anded together they will produce a global bit to store 474 * in the tlb. 475 */ 476 for (i = 0, pte = pgtab; i < (nkpt * NPTEPG); i++, pte++) 477 *pte = PTE_G; 478 479 /* 480 * The segment table contains the KVA of the pages in the second 481 * level page table. 482 */ 483 for (i = 0, j = (virtual_avail >> SEGSHIFT); i < nkpt; i++, j++) 484 kernel_segmap[j] = (pd_entry_t)(pgtab + (i * NPTEPG)); 485 486 /* 487 * The kernel's pmap is statically allocated so we don't have to use 488 * pmap_create, which is unlikely to work correctly at this part of 489 * the boot sequence (XXX and which no longer exists). 490 */ 491 PMAP_LOCK_INIT(kernel_pmap); 492 kernel_pmap->pm_segtab = kernel_segmap; 493 kernel_pmap->pm_active = ~0; 494 TAILQ_INIT(&kernel_pmap->pm_pvlist); 495 kernel_pmap->pm_asid[0].asid = PMAP_ASID_RESERVED; 496 kernel_pmap->pm_asid[0].gen = 0; 497 pmap_max_asid = VMNUM_PIDS; 498 MachSetPID(0); 499} 500 501/* 502 * Initialize a vm_page's machine-dependent fields. 503 */ 504void 505pmap_page_init(vm_page_t m) 506{ 507 508 TAILQ_INIT(&m->md.pv_list); 509 m->md.pv_list_count = 0; 510 m->md.pv_flags = 0; 511} 512 513/* 514 * Initialize the pmap module. 515 * Called by vm_init, to initialize any structures that the pmap 516 * system needs to map virtual memory. 517 * pmap_init has been enhanced to support in a fairly consistant 518 * way, discontiguous physical memory. 519 */ 520void 521pmap_init(void) 522{ 523 524 /* 525 * Initialize the address space (zone) for the pv entries. Set a 526 * high water mark so that the system can recover from excessive 527 * numbers of pv entries. 528 */ 529 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL, 530 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 531 pv_entry_max = PMAP_SHPGPERPROC * maxproc + cnt.v_page_count; 532 pv_entry_high_water = 9 * (pv_entry_max / 10); 533 uma_zone_set_obj(pvzone, &pvzone_obj, pv_entry_max); 534} 535 536/*************************************************** 537 * Low level helper routines..... 538 ***************************************************/ 539 540#if defined(PMAP_DIAGNOSTIC) 541 542/* 543 * This code checks for non-writeable/modified pages. 544 * This should be an invalid condition. 545 */ 546static int 547pmap_nw_modified(pt_entry_t pte) 548{ 549 if ((pte & (PTE_M | PTE_RO)) == (PTE_M | PTE_RO)) 550 return (1); 551 else 552 return (0); 553} 554 555#endif 556 557static void 558pmap_invalidate_all(pmap_t pmap) 559{ 560#ifdef SMP 561 smp_rendezvous(0, pmap_invalidate_all_action, 0, (void *)pmap); 562} 563 564static void 565pmap_invalidate_all_action(void *arg) 566{ 567 pmap_t pmap = (pmap_t)arg; 568 569#endif 570 571 if (pmap->pm_active & PCPU_GET(cpumask)) { 572 pmap_TLB_invalidate_all(); 573 } else 574 pmap->pm_asid[PCPU_GET(cpuid)].gen = 0; 575} 576 577struct pmap_invalidate_page_arg { 578 pmap_t pmap; 579 vm_offset_t va; 580}; 581 582static __inline void 583pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 584{ 585#ifdef SMP 586 struct pmap_invalidate_page_arg arg; 587 588 arg.pmap = pmap; 589 arg.va = va; 590 591 smp_rendezvous(0, pmap_invalidate_page_action, 0, (void *)&arg); 592} 593 594static void 595pmap_invalidate_page_action(void *arg) 596{ 597 pmap_t pmap = ((struct pmap_invalidate_page_arg *)arg)->pmap; 598 vm_offset_t va = ((struct pmap_invalidate_page_arg *)arg)->va; 599 600#endif 601 602 if (is_kernel_pmap(pmap)) { 603 pmap_TLB_invalidate_kernel(va); 604 return; 605 } 606 if (pmap->pm_asid[PCPU_GET(cpuid)].gen != PCPU_GET(asid_generation)) 607 return; 608 else if (!(pmap->pm_active & PCPU_GET(cpumask))) { 609 pmap->pm_asid[PCPU_GET(cpuid)].gen = 0; 610 return; 611 } 612 va = pmap_va_asid(pmap, (va & ~PGOFSET)); 613 mips_TBIS(va); 614} 615 616static void 617pmap_TLB_invalidate_kernel(vm_offset_t va) 618{ 619 u_int32_t pid; 620 621 MachTLBGetPID(pid); 622 va = va | (pid << VMTLB_PID_SHIFT); 623 mips_TBIS(va); 624} 625 626struct pmap_update_page_arg { 627 pmap_t pmap; 628 vm_offset_t va; 629 pt_entry_t pte; 630}; 631 632void 633pmap_update_page(pmap_t pmap, vm_offset_t va, pt_entry_t pte) 634{ 635#ifdef SMP 636 struct pmap_update_page_arg arg; 637 638 arg.pmap = pmap; 639 arg.va = va; 640 arg.pte = pte; 641 642 smp_rendezvous(0, pmap_update_page_action, 0, (void *)&arg); 643} 644 645static void 646pmap_update_page_action(void *arg) 647{ 648 pmap_t pmap = ((struct pmap_update_page_arg *)arg)->pmap; 649 vm_offset_t va = ((struct pmap_update_page_arg *)arg)->va; 650 pt_entry_t pte = ((struct pmap_update_page_arg *)arg)->pte; 651 652#endif 653 if (is_kernel_pmap(pmap)) { 654 pmap_TLB_update_kernel(va, pte); 655 return; 656 } 657 if (pmap->pm_asid[PCPU_GET(cpuid)].gen != PCPU_GET(asid_generation)) 658 return; 659 else if (!(pmap->pm_active & PCPU_GET(cpumask))) { 660 pmap->pm_asid[PCPU_GET(cpuid)].gen = 0; 661 return; 662 } 663 va = pmap_va_asid(pmap, va); 664 MachTLBUpdate(va, pte); 665} 666 667static void 668pmap_TLB_update_kernel(vm_offset_t va, pt_entry_t pte) 669{ 670 u_int32_t pid; 671 672 MachTLBGetPID(pid); 673 va = va | (pid << VMTLB_PID_SHIFT); 674 675 MachTLBUpdate(va, pte); 676} 677 678/* 679 * Routine: pmap_extract 680 * Function: 681 * Extract the physical page address associated 682 * with the given map/virtual_address pair. 683 */ 684vm_paddr_t 685pmap_extract(pmap_t pmap, vm_offset_t va) 686{ 687 pt_entry_t *pte; 688 vm_offset_t retval = 0; 689 690 PMAP_LOCK(pmap); 691 pte = pmap_pte(pmap, va); 692 if (pte) { 693 retval = mips_tlbpfn_to_paddr(*pte) | (va & PAGE_MASK); 694 } 695 PMAP_UNLOCK(pmap); 696 return retval; 697} 698 699/* 700 * Routine: pmap_extract_and_hold 701 * Function: 702 * Atomically extract and hold the physical page 703 * with the given pmap and virtual address pair 704 * if that mapping permits the given protection. 705 */ 706vm_page_t 707pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 708{ 709 pt_entry_t pte; 710 vm_page_t m; 711 712 m = NULL; 713 vm_page_lock_queues(); 714 PMAP_LOCK(pmap); 715 716 pte = *pmap_pte(pmap, va); 717 if (pte != 0 && pmap_pte_v(&pte) && 718 ((pte & PTE_RW) || (prot & VM_PROT_WRITE) == 0)) { 719 m = PHYS_TO_VM_PAGE(mips_tlbpfn_to_paddr(pte)); 720 vm_page_hold(m); 721 } 722 vm_page_unlock_queues(); 723 PMAP_UNLOCK(pmap); 724 return (m); 725} 726 727/*************************************************** 728 * Low level mapping routines..... 729 ***************************************************/ 730 731/* 732 * add a wired page to the kva 733 */ 734 /* PMAP_INLINE */ void 735pmap_kenter(vm_offset_t va, vm_paddr_t pa) 736{ 737 register pt_entry_t *pte; 738 pt_entry_t npte, opte; 739 740#ifdef PMAP_DEBUG 741 printf("pmap_kenter: va: 0x%08x -> pa: 0x%08x\n", va, pa); 742#endif 743 npte = mips_paddr_to_tlbpfn(pa) | PTE_RW | PTE_V | PTE_G | PTE_W; 744 745 if (is_cacheable_mem(pa)) 746 npte |= PTE_CACHE; 747 else 748 npte |= PTE_UNCACHED; 749 750 pte = pmap_pte(kernel_pmap, va); 751 opte = *pte; 752 *pte = npte; 753 754 pmap_update_page(kernel_pmap, va, npte); 755} 756 757/* 758 * remove a page from the kernel pagetables 759 */ 760 /* PMAP_INLINE */ void 761pmap_kremove(vm_offset_t va) 762{ 763 register pt_entry_t *pte; 764 765 /* 766 * Write back all caches from the page being destroyed 767 */ 768 mips_dcache_wbinv_range_index(va, NBPG); 769 770 pte = pmap_pte(kernel_pmap, va); 771 *pte = PTE_G; 772 pmap_invalidate_page(kernel_pmap, va); 773} 774 775/* 776 * Used to map a range of physical addresses into kernel 777 * virtual address space. 778 * 779 * The value passed in '*virt' is a suggested virtual address for 780 * the mapping. Architectures which can support a direct-mapped 781 * physical to virtual region can return the appropriate address 782 * within that region, leaving '*virt' unchanged. Other 783 * architectures should map the pages starting at '*virt' and 784 * update '*virt' with the first usable address after the mapped 785 * region. 786 */ 787vm_offset_t 788pmap_map(vm_offset_t *virt, vm_offset_t start, vm_offset_t end, int prot) 789{ 790 vm_offset_t va, sva; 791 792 va = sva = *virt; 793 while (start < end) { 794 pmap_kenter(va, start); 795 va += PAGE_SIZE; 796 start += PAGE_SIZE; 797 } 798 *virt = va; 799 return (sva); 800} 801 802/* 803 * Add a list of wired pages to the kva 804 * this routine is only used for temporary 805 * kernel mappings that do not need to have 806 * page modification or references recorded. 807 * Note that old mappings are simply written 808 * over. The page *must* be wired. 809 */ 810void 811pmap_qenter(vm_offset_t va, vm_page_t *m, int count) 812{ 813 int i; 814 vm_offset_t origva = va; 815 816 for (i = 0; i < count; i++) { 817 pmap_flush_pvcache(m[i]); 818 pmap_kenter(va, VM_PAGE_TO_PHYS(m[i])); 819 va += PAGE_SIZE; 820 } 821 822 mips_dcache_wbinv_range_index(origva, PAGE_SIZE*count); 823} 824 825/* 826 * this routine jerks page mappings from the 827 * kernel -- it is meant only for temporary mappings. 828 */ 829void 830pmap_qremove(vm_offset_t va, int count) 831{ 832 /* 833 * No need to wb/inv caches here, 834 * pmap_kremove will do it for us 835 */ 836 837 while (count-- > 0) { 838 pmap_kremove(va); 839 va += PAGE_SIZE; 840 } 841} 842 843/*************************************************** 844 * Page table page management routines..... 845 ***************************************************/ 846 847/* Revision 1.507 848 * 849 * Simplify the reference counting of page table pages. Specifically, use 850 * the page table page's wired count rather than its hold count to contain 851 * the reference count. 852 */ 853 854/* 855 * This routine unholds page table pages, and if the hold count 856 * drops to zero, then it decrements the wire count. 857 */ 858static int 859_pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m) 860{ 861 vm_offset_t pteva; 862 863 /* 864 * unmap the page table page 865 */ 866 pteva = (vm_offset_t)pmap->pm_segtab[m->pindex]; 867 if (pteva >= VM_MIN_KERNEL_ADDRESS) { 868 pmap_kremove(pteva); 869 kmem_free(kernel_map, pteva, PAGE_SIZE); 870 } else { 871 KASSERT(MIPS_IS_KSEG0_ADDR(pteva), 872 ("_pmap_unwire_pte_hold: 0x%0lx is not in kseg0", 873 (long)pteva)); 874 } 875 876 pmap->pm_segtab[m->pindex] = 0; 877 --pmap->pm_stats.resident_count; 878 879 if (pmap->pm_ptphint == m) 880 pmap->pm_ptphint = NULL; 881 882 /* 883 * If the page is finally unwired, simply free it. 884 */ 885 vm_page_free_zero(m); 886 atomic_subtract_int(&cnt.v_wire_count, 1); 887 return (1); 888} 889 890static PMAP_INLINE int 891pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m) 892{ 893 --m->wire_count; 894 if (m->wire_count == 0) 895 return (_pmap_unwire_pte_hold(pmap, m)); 896 else 897 return (0); 898} 899 900/* 901 * After removing a page table entry, this routine is used to 902 * conditionally free the page, and manage the hold/wire counts. 903 */ 904static int 905pmap_unuse_pt(pmap_t pmap, vm_offset_t va, vm_page_t mpte) 906{ 907 unsigned ptepindex; 908 pd_entry_t pteva; 909 910 if (va >= VM_MAXUSER_ADDRESS) 911 return (0); 912 913 if (mpte == NULL) { 914 ptepindex = (va >> SEGSHIFT); 915 if (pmap->pm_ptphint && 916 (pmap->pm_ptphint->pindex == ptepindex)) { 917 mpte = pmap->pm_ptphint; 918 } else { 919 pteva = *pmap_pde(pmap, va); 920 mpte = PHYS_TO_VM_PAGE(vtophys(pteva)); 921 pmap->pm_ptphint = mpte; 922 } 923 } 924 return pmap_unwire_pte_hold(pmap, mpte); 925} 926 927void 928pmap_pinit0(pmap_t pmap) 929{ 930 int i; 931 932 PMAP_LOCK_INIT(pmap); 933 pmap->pm_segtab = kernel_segmap; 934 pmap->pm_active = 0; 935 pmap->pm_ptphint = NULL; 936 for (i = 0; i < MAXCPU; i++) { 937 pmap->pm_asid[i].asid = PMAP_ASID_RESERVED; 938 pmap->pm_asid[i].gen = 0; 939 } 940 PCPU_SET(curpmap, pmap); 941 TAILQ_INIT(&pmap->pm_pvlist); 942 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 943} 944 945/* 946 * Initialize a preallocated and zeroed pmap structure, 947 * such as one in a vmspace structure. 948 */ 949int 950pmap_pinit(pmap_t pmap) 951{ 952 vm_offset_t ptdva; 953 vm_paddr_t ptdpa; 954 vm_page_t ptdpg; 955 int i; 956 int req; 957 958 PMAP_LOCK_INIT(pmap); 959 960 req = VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL | VM_ALLOC_WIRED | 961 VM_ALLOC_ZERO; 962 963 /* 964 * allocate the page directory page 965 */ 966 while ((ptdpg = vm_page_alloc(NULL, NUSERPGTBLS, req)) == NULL) 967 VM_WAIT; 968 969 ptdpg->valid = VM_PAGE_BITS_ALL; 970 971 ptdpa = VM_PAGE_TO_PHYS(ptdpg); 972 if (ptdpa < MIPS_KSEG0_LARGEST_PHYS) { 973 ptdva = MIPS_PHYS_TO_KSEG0(ptdpa); 974 } else { 975 ptdva = kmem_alloc_nofault(kernel_map, PAGE_SIZE); 976 if (ptdva == 0) 977 panic("pmap_pinit: unable to allocate kva"); 978 pmap_kenter(ptdva, ptdpa); 979 } 980 981 pmap->pm_segtab = (pd_entry_t *)ptdva; 982 if ((ptdpg->flags & PG_ZERO) == 0) 983 bzero(pmap->pm_segtab, PAGE_SIZE); 984 985 pmap->pm_active = 0; 986 pmap->pm_ptphint = NULL; 987 for (i = 0; i < MAXCPU; i++) { 988 pmap->pm_asid[i].asid = PMAP_ASID_RESERVED; 989 pmap->pm_asid[i].gen = 0; 990 } 991 TAILQ_INIT(&pmap->pm_pvlist); 992 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 993 994 return (1); 995} 996 997/* 998 * this routine is called if the page table page is not 999 * mapped correctly. 1000 */ 1001static vm_page_t 1002_pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags) 1003{ 1004 vm_offset_t pteva, ptepa; 1005 vm_page_t m; 1006 int req; 1007 1008 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1009 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1010 ("_pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1011 1012 req = VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ; 1013 /* 1014 * Find or fabricate a new pagetable page 1015 */ 1016 if ((m = vm_page_alloc(NULL, ptepindex, req)) == NULL) { 1017 if (flags & M_WAITOK) { 1018 PMAP_UNLOCK(pmap); 1019 vm_page_unlock_queues(); 1020 VM_WAIT; 1021 vm_page_lock_queues(); 1022 PMAP_LOCK(pmap); 1023 } 1024 /* 1025 * Indicate the need to retry. While waiting, the page 1026 * table page may have been allocated. 1027 */ 1028 return (NULL); 1029 } 1030 if ((m->flags & PG_ZERO) == 0) 1031 pmap_zero_page(m); 1032 1033 KASSERT(m->queue == PQ_NONE, 1034 ("_pmap_allocpte: %p->queue != PQ_NONE", m)); 1035 1036 /* 1037 * Map the pagetable page into the process address space, if it 1038 * isn't already there. 1039 */ 1040 1041 pmap->pm_stats.resident_count++; 1042 1043 ptepa = VM_PAGE_TO_PHYS(m); 1044 if (ptepa < MIPS_KSEG0_LARGEST_PHYS) { 1045 pteva = MIPS_PHYS_TO_KSEG0(ptepa); 1046 } else { 1047 pteva = kmem_alloc_nofault(kernel_map, PAGE_SIZE); 1048 if (pteva == 0) 1049 panic("_pmap_allocpte: unable to allocate kva"); 1050 pmap_kenter(pteva, ptepa); 1051 } 1052 1053 pmap->pm_segtab[ptepindex] = (pd_entry_t)pteva; 1054 1055 /* 1056 * Set the page table hint 1057 */ 1058 pmap->pm_ptphint = m; 1059 1060 /* 1061 * Kernel page tables are allocated in pmap_bootstrap() or 1062 * pmap_growkernel(). 1063 */ 1064 if (is_kernel_pmap(pmap)) 1065 panic("_pmap_allocpte() called for kernel pmap\n"); 1066 1067 m->valid = VM_PAGE_BITS_ALL; 1068 vm_page_flag_clear(m, PG_ZERO); 1069 1070 return (m); 1071} 1072 1073static vm_page_t 1074pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags) 1075{ 1076 unsigned ptepindex; 1077 vm_offset_t pteva; 1078 vm_page_t m; 1079 1080 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1081 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1082 ("pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1083 1084 /* 1085 * Calculate pagetable page index 1086 */ 1087 ptepindex = va >> SEGSHIFT; 1088retry: 1089 /* 1090 * Get the page directory entry 1091 */ 1092 pteva = (vm_offset_t)pmap->pm_segtab[ptepindex]; 1093 1094 /* 1095 * If the page table page is mapped, we just increment the hold 1096 * count, and activate it. 1097 */ 1098 if (pteva) { 1099 /* 1100 * In order to get the page table page, try the hint first. 1101 */ 1102 if (pmap->pm_ptphint && 1103 (pmap->pm_ptphint->pindex == ptepindex)) { 1104 m = pmap->pm_ptphint; 1105 } else { 1106 m = PHYS_TO_VM_PAGE(vtophys(pteva)); 1107 pmap->pm_ptphint = m; 1108 } 1109 m->wire_count++; 1110 } else { 1111 /* 1112 * Here if the pte page isn't mapped, or if it has been 1113 * deallocated. 1114 */ 1115 m = _pmap_allocpte(pmap, ptepindex, flags); 1116 if (m == NULL && (flags & M_WAITOK)) 1117 goto retry; 1118 } 1119 return m; 1120} 1121 1122 1123/*************************************************** 1124* Pmap allocation/deallocation routines. 1125 ***************************************************/ 1126/* 1127 * Revision 1.397 1128 * - Merged pmap_release and pmap_release_free_page. When pmap_release is 1129 * called only the page directory page(s) can be left in the pmap pte 1130 * object, since all page table pages will have been freed by 1131 * pmap_remove_pages and pmap_remove. In addition, there can only be one 1132 * reference to the pmap and the page directory is wired, so the page(s) 1133 * can never be busy. So all there is to do is clear the magic mappings 1134 * from the page directory and free the page(s). 1135 */ 1136 1137 1138/* 1139 * Release any resources held by the given physical map. 1140 * Called when a pmap initialized by pmap_pinit is being released. 1141 * Should only be called if the map contains no valid mappings. 1142 */ 1143void 1144pmap_release(pmap_t pmap) 1145{ 1146 vm_offset_t ptdva; 1147 vm_page_t ptdpg; 1148 1149 KASSERT(pmap->pm_stats.resident_count == 0, 1150 ("pmap_release: pmap resident count %ld != 0", 1151 pmap->pm_stats.resident_count)); 1152 1153 ptdva = (vm_offset_t)pmap->pm_segtab; 1154 ptdpg = PHYS_TO_VM_PAGE(vtophys(ptdva)); 1155 1156 if (ptdva >= VM_MIN_KERNEL_ADDRESS) { 1157 pmap_kremove(ptdva); 1158 kmem_free(kernel_map, ptdva, PAGE_SIZE); 1159 } else { 1160 KASSERT(MIPS_IS_KSEG0_ADDR(ptdva), 1161 ("pmap_release: 0x%0lx is not in kseg0", (long)ptdva)); 1162 } 1163 1164 ptdpg->wire_count--; 1165 atomic_subtract_int(&cnt.v_wire_count, 1); 1166 vm_page_free_zero(ptdpg); 1167 PMAP_LOCK_DESTROY(pmap); 1168} 1169 1170/* 1171 * grow the number of kernel page table entries, if needed 1172 */ 1173void 1174pmap_growkernel(vm_offset_t addr) 1175{ 1176 vm_offset_t ptppaddr; 1177 vm_page_t nkpg; 1178 pt_entry_t *pte; 1179 int i, req; 1180 1181 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 1182 if (kernel_vm_end == 0) { 1183 kernel_vm_end = VM_MIN_KERNEL_ADDRESS; 1184 nkpt = 0; 1185 while (segtab_pde(kernel_segmap, kernel_vm_end)) { 1186 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & 1187 ~(PAGE_SIZE * NPTEPG - 1); 1188 nkpt++; 1189 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1190 kernel_vm_end = kernel_map->max_offset; 1191 break; 1192 } 1193 } 1194 } 1195 addr = (addr + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1196 if (addr - 1 >= kernel_map->max_offset) 1197 addr = kernel_map->max_offset; 1198 while (kernel_vm_end < addr) { 1199 if (segtab_pde(kernel_segmap, kernel_vm_end)) { 1200 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & 1201 ~(PAGE_SIZE * NPTEPG - 1); 1202 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1203 kernel_vm_end = kernel_map->max_offset; 1204 break; 1205 } 1206 continue; 1207 } 1208 /* 1209 * This index is bogus, but out of the way 1210 */ 1211 req = VM_ALLOC_INTERRUPT | VM_ALLOC_WIRED | VM_ALLOC_NOOBJ; 1212 nkpg = vm_page_alloc(NULL, nkpt, req); 1213 if (!nkpg) 1214 panic("pmap_growkernel: no memory to grow kernel"); 1215 1216 nkpt++; 1217 1218 ptppaddr = VM_PAGE_TO_PHYS(nkpg); 1219 if (ptppaddr >= MIPS_KSEG0_LARGEST_PHYS) { 1220 /* 1221 * We need to do something here, but I am not sure 1222 * what. We can access anything in the 0 - 512Meg 1223 * region, but if we get a page to go in the kernel 1224 * segmap that is outside of of that we really need 1225 * to have another mapping beyond the temporary ones 1226 * I have. Not sure how to do this yet. FIXME FIXME. 1227 */ 1228 panic("Gak, can't handle a k-page table outside of lower 512Meg"); 1229 } 1230 pte = (pt_entry_t *)MIPS_PHYS_TO_KSEG0(ptppaddr); 1231 segtab_pde(kernel_segmap, kernel_vm_end) = (pd_entry_t)pte; 1232 1233 /* 1234 * The R[4-7]?00 stores only one copy of the Global bit in 1235 * the translation lookaside buffer for each 2 page entry. 1236 * Thus invalid entrys must have the Global bit set so when 1237 * Entry LO and Entry HI G bits are anded together they will 1238 * produce a global bit to store in the tlb. 1239 */ 1240 for (i = 0; i < NPTEPG; i++, pte++) 1241 *pte = PTE_G; 1242 1243 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & 1244 ~(PAGE_SIZE * NPTEPG - 1); 1245 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1246 kernel_vm_end = kernel_map->max_offset; 1247 break; 1248 } 1249 } 1250} 1251 1252/*************************************************** 1253* page management routines. 1254 ***************************************************/ 1255 1256/* 1257 * free the pv_entry back to the free list 1258 */ 1259static PMAP_INLINE void 1260free_pv_entry(pv_entry_t pv) 1261{ 1262 1263 pv_entry_count--; 1264 uma_zfree(pvzone, pv); 1265} 1266 1267/* 1268 * get a new pv_entry, allocating a block from the system 1269 * when needed. 1270 * the memory allocation is performed bypassing the malloc code 1271 * because of the possibility of allocations at interrupt time. 1272 */ 1273static pv_entry_t 1274get_pv_entry(pmap_t locked_pmap) 1275{ 1276 static const struct timeval printinterval = { 60, 0 }; 1277 static struct timeval lastprint; 1278 struct vpgqueues *vpq; 1279 pt_entry_t *pte, oldpte; 1280 pmap_t pmap; 1281 pv_entry_t allocated_pv, next_pv, pv; 1282 vm_offset_t va; 1283 vm_page_t m; 1284 1285 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED); 1286 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1287 allocated_pv = uma_zalloc(pvzone, M_NOWAIT); 1288 if (allocated_pv != NULL) { 1289 pv_entry_count++; 1290 if (pv_entry_count > pv_entry_high_water) 1291 pagedaemon_wakeup(); 1292 else 1293 return (allocated_pv); 1294 } 1295 /* 1296 * Reclaim pv entries: At first, destroy mappings to inactive 1297 * pages. After that, if a pv entry is still needed, destroy 1298 * mappings to active pages. 1299 */ 1300 if (ratecheck(&lastprint, &printinterval)) 1301 printf("Approaching the limit on PV entries, " 1302 "increase the vm.pmap.shpgperproc tunable.\n"); 1303 vpq = &vm_page_queues[PQ_INACTIVE]; 1304retry: 1305 TAILQ_FOREACH(m, &vpq->pl, pageq) { 1306 if (m->hold_count || m->busy) 1307 continue; 1308 TAILQ_FOREACH_SAFE(pv, &m->md.pv_list, pv_list, next_pv) { 1309 va = pv->pv_va; 1310 pmap = pv->pv_pmap; 1311 /* Avoid deadlock and lock recursion. */ 1312 if (pmap > locked_pmap) 1313 PMAP_LOCK(pmap); 1314 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) 1315 continue; 1316 pmap->pm_stats.resident_count--; 1317 pte = pmap_pte(pmap, va); 1318 KASSERT(pte != NULL, ("pte")); 1319 oldpte = loadandclear((u_int *)pte); 1320 if (is_kernel_pmap(pmap)) 1321 *pte = PTE_G; 1322 KASSERT((oldpte & PTE_W) == 0, 1323 ("wired pte for unwired page")); 1324 if (m->md.pv_flags & PV_TABLE_REF) 1325 vm_page_flag_set(m, PG_REFERENCED); 1326 if (oldpte & PTE_M) 1327 vm_page_dirty(m); 1328 pmap_invalidate_page(pmap, va); 1329 TAILQ_REMOVE(&pmap->pm_pvlist, pv, pv_plist); 1330 m->md.pv_list_count--; 1331 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 1332 if (TAILQ_EMPTY(&m->md.pv_list)) { 1333 vm_page_flag_clear(m, PG_WRITEABLE); 1334 m->md.pv_flags &= ~(PV_TABLE_REF | PV_TABLE_MOD); 1335 } 1336 pmap_unuse_pt(pmap, va, pv->pv_ptem); 1337 if (pmap != locked_pmap) 1338 PMAP_UNLOCK(pmap); 1339 if (allocated_pv == NULL) 1340 allocated_pv = pv; 1341 else 1342 free_pv_entry(pv); 1343 } 1344 } 1345 if (allocated_pv == NULL) { 1346 if (vpq == &vm_page_queues[PQ_INACTIVE]) { 1347 vpq = &vm_page_queues[PQ_ACTIVE]; 1348 goto retry; 1349 } 1350 panic("get_pv_entry: increase the vm.pmap.shpgperproc tunable"); 1351 } 1352 return (allocated_pv); 1353} 1354 1355/* 1356 * Revision 1.370 1357 * 1358 * Move pmap_collect() out of the machine-dependent code, rename it 1359 * to reflect its new location, and add page queue and flag locking. 1360 * 1361 * Notes: (1) alpha, i386, and ia64 had identical implementations 1362 * of pmap_collect() in terms of machine-independent interfaces; 1363 * (2) sparc64 doesn't require it; (3) powerpc had it as a TODO. 1364 * 1365 * MIPS implementation was identical to alpha [Junos 8.2] 1366 */ 1367 1368/* 1369 * If it is the first entry on the list, it is actually 1370 * in the header and we must copy the following entry up 1371 * to the header. Otherwise we must search the list for 1372 * the entry. In either case we free the now unused entry. 1373 */ 1374 1375static void 1376pmap_remove_entry(struct pmap *pmap, vm_page_t m, vm_offset_t va) 1377{ 1378 pv_entry_t pv; 1379 1380 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1381 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1382 if (m->md.pv_list_count < pmap->pm_stats.resident_count) { 1383 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 1384 if (pmap == pv->pv_pmap && va == pv->pv_va) 1385 break; 1386 } 1387 } else { 1388 TAILQ_FOREACH(pv, &pmap->pm_pvlist, pv_plist) { 1389 if (va == pv->pv_va) 1390 break; 1391 } 1392 } 1393 1394 KASSERT(pv != NULL, ("pmap_remove_entry: pv not found")); 1395 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 1396 m->md.pv_list_count--; 1397 if (TAILQ_FIRST(&m->md.pv_list) == NULL) 1398 vm_page_flag_clear(m, PG_WRITEABLE); 1399 1400 TAILQ_REMOVE(&pmap->pm_pvlist, pv, pv_plist); 1401 free_pv_entry(pv); 1402} 1403 1404/* 1405 * Create a pv entry for page at pa for 1406 * (pmap, va). 1407 */ 1408static void 1409pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t mpte, vm_page_t m, 1410 boolean_t wired) 1411{ 1412 pv_entry_t pv; 1413 1414 pv = get_pv_entry(pmap); 1415 pv->pv_va = va; 1416 pv->pv_pmap = pmap; 1417 pv->pv_ptem = mpte; 1418 pv->pv_wired = wired; 1419 1420 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1421 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1422 TAILQ_INSERT_TAIL(&pmap->pm_pvlist, pv, pv_plist); 1423 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 1424 m->md.pv_list_count++; 1425} 1426 1427/* 1428 * Conditionally create a pv entry. 1429 */ 1430static boolean_t 1431pmap_try_insert_pv_entry(pmap_t pmap, vm_page_t mpte, vm_offset_t va, 1432 vm_page_t m) 1433{ 1434 pv_entry_t pv; 1435 1436 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1437 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1438 if (pv_entry_count < pv_entry_high_water && 1439 (pv = uma_zalloc(pvzone, M_NOWAIT)) != NULL) { 1440 pv_entry_count++; 1441 pv->pv_va = va; 1442 pv->pv_pmap = pmap; 1443 pv->pv_ptem = mpte; 1444 pv->pv_wired = FALSE; 1445 TAILQ_INSERT_TAIL(&pmap->pm_pvlist, pv, pv_plist); 1446 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 1447 m->md.pv_list_count++; 1448 return (TRUE); 1449 } else 1450 return (FALSE); 1451} 1452 1453/* 1454 * pmap_remove_pte: do the things to unmap a page in a process 1455 */ 1456static int 1457pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va) 1458{ 1459 pt_entry_t oldpte; 1460 vm_page_t m; 1461 vm_offset_t pa; 1462 1463 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1464 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1465 1466 oldpte = loadandclear((u_int *)ptq); 1467 if (is_kernel_pmap(pmap)) 1468 *ptq = PTE_G; 1469 1470 if (oldpte & PTE_W) 1471 pmap->pm_stats.wired_count -= 1; 1472 1473 pmap->pm_stats.resident_count -= 1; 1474 pa = mips_tlbpfn_to_paddr(oldpte); 1475 1476 if (page_is_managed(pa)) { 1477 m = PHYS_TO_VM_PAGE(pa); 1478 if (oldpte & PTE_M) { 1479#if defined(PMAP_DIAGNOSTIC) 1480 if (pmap_nw_modified(oldpte)) { 1481 printf( 1482 "pmap_remove: modified page not writable: va: 0x%x, pte: 0x%x\n", 1483 va, oldpte); 1484 } 1485#endif 1486 vm_page_dirty(m); 1487 } 1488 if (m->md.pv_flags & PV_TABLE_REF) 1489 vm_page_flag_set(m, PG_REFERENCED); 1490 m->md.pv_flags &= ~(PV_TABLE_REF | PV_TABLE_MOD); 1491 1492 pmap_remove_entry(pmap, m, va); 1493 } 1494 return pmap_unuse_pt(pmap, va, NULL); 1495} 1496 1497/* 1498 * Remove a single page from a process address space 1499 */ 1500static void 1501pmap_remove_page(struct pmap *pmap, vm_offset_t va) 1502{ 1503 register pt_entry_t *ptq; 1504 1505 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1506 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1507 ptq = pmap_pte(pmap, va); 1508 1509 /* 1510 * if there is no pte for this address, just skip it!!! 1511 */ 1512 if (!ptq || !pmap_pte_v(ptq)) { 1513 return; 1514 } 1515 1516 /* 1517 * Write back all caches from the page being destroyed 1518 */ 1519 mips_dcache_wbinv_range_index(va, NBPG); 1520 1521 /* 1522 * get a local va for mappings for this pmap. 1523 */ 1524 (void)pmap_remove_pte(pmap, ptq, va); 1525 pmap_invalidate_page(pmap, va); 1526 1527 return; 1528} 1529 1530/* 1531 * Remove the given range of addresses from the specified map. 1532 * 1533 * It is assumed that the start and end are properly 1534 * rounded to the page size. 1535 */ 1536void 1537pmap_remove(struct pmap *pmap, vm_offset_t sva, vm_offset_t eva) 1538{ 1539 vm_offset_t va, nva; 1540 1541 if (pmap == NULL) 1542 return; 1543 1544 if (pmap->pm_stats.resident_count == 0) 1545 return; 1546 1547 vm_page_lock_queues(); 1548 PMAP_LOCK(pmap); 1549 1550 /* 1551 * special handling of removing one page. a very common operation 1552 * and easy to short circuit some code. 1553 */ 1554 if ((sva + PAGE_SIZE) == eva) { 1555 pmap_remove_page(pmap, sva); 1556 goto out; 1557 } 1558 for (va = sva; va < eva; va = nva) { 1559 if (!*pmap_pde(pmap, va)) { 1560 nva = mips_segtrunc(va + MIPS_SEGSIZE); 1561 continue; 1562 } 1563 pmap_remove_page(pmap, va); 1564 nva = va + PAGE_SIZE; 1565 } 1566 1567out: 1568 vm_page_unlock_queues(); 1569 PMAP_UNLOCK(pmap); 1570} 1571 1572/* 1573 * Routine: pmap_remove_all 1574 * Function: 1575 * Removes this physical page from 1576 * all physical maps in which it resides. 1577 * Reflects back modify bits to the pager. 1578 * 1579 * Notes: 1580 * Original versions of this routine were very 1581 * inefficient because they iteratively called 1582 * pmap_remove (slow...) 1583 */ 1584 1585void 1586pmap_remove_all(vm_page_t m) 1587{ 1588 register pv_entry_t pv; 1589 register pt_entry_t *pte, tpte; 1590 1591 KASSERT((m->flags & PG_FICTITIOUS) == 0, 1592 ("pmap_remove_all: page %p is fictitious", m)); 1593 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1594 1595 if (m->md.pv_flags & PV_TABLE_REF) 1596 vm_page_flag_set(m, PG_REFERENCED); 1597 1598 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 1599 PMAP_LOCK(pv->pv_pmap); 1600 1601 /* 1602 * If it's last mapping writeback all caches from 1603 * the page being destroyed 1604 */ 1605 if (m->md.pv_list_count == 1) 1606 mips_dcache_wbinv_range_index(pv->pv_va, NBPG); 1607 1608 pv->pv_pmap->pm_stats.resident_count--; 1609 1610 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 1611 1612 tpte = loadandclear((u_int *)pte); 1613 if (is_kernel_pmap(pv->pv_pmap)) 1614 *pte = PTE_G; 1615 1616 if (tpte & PTE_W) 1617 pv->pv_pmap->pm_stats.wired_count--; 1618 1619 /* 1620 * Update the vm_page_t clean and reference bits. 1621 */ 1622 if (tpte & PTE_M) { 1623#if defined(PMAP_DIAGNOSTIC) 1624 if (pmap_nw_modified(tpte)) { 1625 printf( 1626 "pmap_remove_all: modified page not writable: va: 0x%x, pte: 0x%x\n", 1627 pv->pv_va, tpte); 1628 } 1629#endif 1630 vm_page_dirty(m); 1631 } 1632 pmap_invalidate_page(pv->pv_pmap, pv->pv_va); 1633 1634 TAILQ_REMOVE(&pv->pv_pmap->pm_pvlist, pv, pv_plist); 1635 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 1636 m->md.pv_list_count--; 1637 pmap_unuse_pt(pv->pv_pmap, pv->pv_va, pv->pv_ptem); 1638 PMAP_UNLOCK(pv->pv_pmap); 1639 free_pv_entry(pv); 1640 } 1641 1642 vm_page_flag_clear(m, PG_WRITEABLE); 1643 m->md.pv_flags &= ~(PV_TABLE_REF | PV_TABLE_MOD); 1644} 1645 1646/* 1647 * Set the physical protection on the 1648 * specified range of this map as requested. 1649 */ 1650void 1651pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 1652{ 1653 pt_entry_t *pte; 1654 1655 if (pmap == NULL) 1656 return; 1657 1658 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1659 pmap_remove(pmap, sva, eva); 1660 return; 1661 } 1662 if (prot & VM_PROT_WRITE) 1663 return; 1664 1665 vm_page_lock_queues(); 1666 PMAP_LOCK(pmap); 1667 while (sva < eva) { 1668 pt_entry_t pbits, obits; 1669 vm_page_t m; 1670 vm_offset_t pa; 1671 1672 /* 1673 * If segment table entry is empty, skip this segment. 1674 */ 1675 if (!*pmap_pde(pmap, sva)) { 1676 sva = mips_segtrunc(sva + MIPS_SEGSIZE); 1677 continue; 1678 } 1679 /* 1680 * If pte is invalid, skip this page 1681 */ 1682 pte = pmap_pte(pmap, sva); 1683 if (!pmap_pte_v(pte)) { 1684 sva += PAGE_SIZE; 1685 continue; 1686 } 1687retry: 1688 obits = pbits = *pte; 1689 pa = mips_tlbpfn_to_paddr(pbits); 1690 1691 if (page_is_managed(pa)) { 1692 m = PHYS_TO_VM_PAGE(pa); 1693 if (m->md.pv_flags & PV_TABLE_REF) { 1694 vm_page_flag_set(m, PG_REFERENCED); 1695 m->md.pv_flags &= ~PV_TABLE_REF; 1696 } 1697 if (pbits & PTE_M) { 1698 vm_page_dirty(m); 1699 m->md.pv_flags &= ~PV_TABLE_MOD; 1700 } 1701 } 1702 pbits = (pbits & ~PTE_M) | PTE_RO; 1703 1704 if (pbits != *pte) { 1705 if (!atomic_cmpset_int((u_int *)pte, obits, pbits)) 1706 goto retry; 1707 pmap_update_page(pmap, sva, pbits); 1708 } 1709 sva += PAGE_SIZE; 1710 } 1711 vm_page_unlock_queues(); 1712 PMAP_UNLOCK(pmap); 1713} 1714 1715/* 1716 * Insert the given physical page (p) at 1717 * the specified virtual address (v) in the 1718 * target physical map with the protection requested. 1719 * 1720 * If specified, the page will be wired down, meaning 1721 * that the related pte can not be reclaimed. 1722 * 1723 * NB: This is the only routine which MAY NOT lazy-evaluate 1724 * or lose information. That is, this routine must actually 1725 * insert this page into the given map NOW. 1726 */ 1727void 1728pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m, 1729 vm_prot_t prot, boolean_t wired) 1730{ 1731 vm_offset_t pa, opa; 1732 register pt_entry_t *pte; 1733 pt_entry_t origpte, newpte; 1734 vm_page_t mpte, om; 1735 int rw = 0; 1736 1737 if (pmap == NULL) 1738 return; 1739 1740 va &= ~PAGE_MASK; 1741#ifdef PMAP_DIAGNOSTIC 1742 if (va > VM_MAX_KERNEL_ADDRESS) 1743 panic("pmap_enter: toobig"); 1744#endif 1745 1746 mpte = NULL; 1747 1748 vm_page_lock_queues(); 1749 PMAP_LOCK(pmap); 1750 1751 /* 1752 * In the case that a page table page is not resident, we are 1753 * creating it here. 1754 */ 1755 if (va < VM_MAXUSER_ADDRESS) { 1756 mpte = pmap_allocpte(pmap, va, M_WAITOK); 1757 } 1758 pte = pmap_pte(pmap, va); 1759 1760 /* 1761 * Page Directory table entry not valid, we need a new PT page 1762 */ 1763 if (pte == NULL) { 1764 panic("pmap_enter: invalid page directory, pdir=%p, va=%p\n", 1765 (void *)pmap->pm_segtab, (void *)va); 1766 } 1767 pa = VM_PAGE_TO_PHYS(m); 1768 om = NULL; 1769 origpte = *pte; 1770 opa = mips_tlbpfn_to_paddr(origpte); 1771 1772 /* 1773 * Mapping has not changed, must be protection or wiring change. 1774 */ 1775 if ((origpte & PTE_V) && (opa == pa)) { 1776 /* 1777 * Wiring change, just update stats. We don't worry about 1778 * wiring PT pages as they remain resident as long as there 1779 * are valid mappings in them. Hence, if a user page is 1780 * wired, the PT page will be also. 1781 */ 1782 if (wired && ((origpte & PTE_W) == 0)) 1783 pmap->pm_stats.wired_count++; 1784 else if (!wired && (origpte & PTE_W)) 1785 pmap->pm_stats.wired_count--; 1786 1787#if defined(PMAP_DIAGNOSTIC) 1788 if (pmap_nw_modified(origpte)) { 1789 printf( 1790 "pmap_enter: modified page not writable: va: 0x%x, pte: 0x%x\n", 1791 va, origpte); 1792 } 1793#endif 1794 1795 /* 1796 * Remove extra pte reference 1797 */ 1798 if (mpte) 1799 mpte->wire_count--; 1800 1801 /* 1802 * We might be turning off write access to the page, so we 1803 * go ahead and sense modify status. 1804 */ 1805 if (page_is_managed(opa)) { 1806 om = m; 1807 } 1808 goto validate; 1809 } 1810 /* 1811 * Mapping has changed, invalidate old range and fall through to 1812 * handle validating new mapping. 1813 */ 1814 if (opa) { 1815 if (origpte & PTE_W) 1816 pmap->pm_stats.wired_count--; 1817 1818 if (page_is_managed(opa)) { 1819 om = PHYS_TO_VM_PAGE(opa); 1820 pmap_remove_entry(pmap, om, va); 1821 } 1822 if (mpte != NULL) { 1823 mpte->wire_count--; 1824 KASSERT(mpte->wire_count > 0, 1825 ("pmap_enter: missing reference to page table page," 1826 " va: %p", (void *)va)); 1827 } 1828 } else 1829 pmap->pm_stats.resident_count++; 1830 1831 /* 1832 * Enter on the PV list if part of our managed memory. Note that we 1833 * raise IPL while manipulating pv_table since pmap_enter can be 1834 * called at interrupt time. 1835 */ 1836 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) { 1837 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva, 1838 ("pmap_enter: managed mapping within the clean submap")); 1839 pmap_insert_entry(pmap, va, mpte, m, wired); 1840 } 1841 /* 1842 * Increment counters 1843 */ 1844 if (wired) 1845 pmap->pm_stats.wired_count++; 1846 1847validate: 1848 if ((access & VM_PROT_WRITE) != 0) 1849 m->md.pv_flags |= PV_TABLE_MOD | PV_TABLE_REF; 1850 rw = init_pte_prot(va, m, prot); 1851 1852#ifdef PMAP_DEBUG 1853 printf("pmap_enter: va: 0x%08x -> pa: 0x%08x\n", va, pa); 1854#endif 1855 /* 1856 * Now validate mapping with desired protection/wiring. 1857 */ 1858 newpte = mips_paddr_to_tlbpfn(pa) | rw | PTE_V; 1859 1860 if (is_cacheable_mem(pa)) 1861 newpte |= PTE_CACHE; 1862 else 1863 newpte |= PTE_UNCACHED; 1864 1865 if (wired) 1866 newpte |= PTE_W; 1867 1868 if (is_kernel_pmap(pmap)) { 1869 newpte |= PTE_G; 1870 } 1871 1872 /* 1873 * if the mapping or permission bits are different, we need to 1874 * update the pte. 1875 */ 1876 if (origpte != newpte) { 1877 if (origpte & PTE_V) { 1878 *pte = newpte; 1879 if (page_is_managed(opa) && (opa != pa)) { 1880 if (om->md.pv_flags & PV_TABLE_REF) 1881 vm_page_flag_set(om, PG_REFERENCED); 1882 om->md.pv_flags &= 1883 ~(PV_TABLE_REF | PV_TABLE_MOD); 1884 } 1885 if (origpte & PTE_M) { 1886 KASSERT((origpte & PTE_RW), 1887 ("pmap_enter: modified page not writable:" 1888 " va: %p, pte: 0x%lx", (void *)va, origpte)); 1889 if (page_is_managed(opa)) 1890 vm_page_dirty(om); 1891 } 1892 } else { 1893 *pte = newpte; 1894 } 1895 } 1896 pmap_update_page(pmap, va, newpte); 1897 1898 /* 1899 * Sync I & D caches for executable pages. Do this only if the the 1900 * target pmap belongs to the current process. Otherwise, an 1901 * unresolvable TLB miss may occur. 1902 */ 1903 if (!is_kernel_pmap(pmap) && (pmap == &curproc->p_vmspace->vm_pmap) && 1904 (prot & VM_PROT_EXECUTE)) { 1905 mips_icache_sync_range(va, NBPG); 1906 mips_dcache_wbinv_range(va, NBPG); 1907 } 1908 vm_page_unlock_queues(); 1909 PMAP_UNLOCK(pmap); 1910} 1911 1912/* 1913 * this code makes some *MAJOR* assumptions: 1914 * 1. Current pmap & pmap exists. 1915 * 2. Not wired. 1916 * 3. Read access. 1917 * 4. No page table pages. 1918 * but is *MUCH* faster than pmap_enter... 1919 */ 1920 1921void 1922pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 1923{ 1924 1925 PMAP_LOCK(pmap); 1926 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL); 1927 PMAP_UNLOCK(pmap); 1928} 1929 1930static vm_page_t 1931pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, 1932 vm_prot_t prot, vm_page_t mpte) 1933{ 1934 pt_entry_t *pte; 1935 vm_offset_t pa; 1936 1937 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva || 1938 (m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0, 1939 ("pmap_enter_quick_locked: managed mapping within the clean submap")); 1940 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1941 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1942 1943 /* 1944 * In the case that a page table page is not resident, we are 1945 * creating it here. 1946 */ 1947 if (va < VM_MAXUSER_ADDRESS) { 1948 unsigned ptepindex; 1949 vm_offset_t pteva; 1950 1951 /* 1952 * Calculate pagetable page index 1953 */ 1954 ptepindex = va >> SEGSHIFT; 1955 if (mpte && (mpte->pindex == ptepindex)) { 1956 mpte->wire_count++; 1957 } else { 1958 /* 1959 * Get the page directory entry 1960 */ 1961 pteva = (vm_offset_t)pmap->pm_segtab[ptepindex]; 1962 1963 /* 1964 * If the page table page is mapped, we just 1965 * increment the hold count, and activate it. 1966 */ 1967 if (pteva) { 1968 if (pmap->pm_ptphint && 1969 (pmap->pm_ptphint->pindex == ptepindex)) { 1970 mpte = pmap->pm_ptphint; 1971 } else { 1972 mpte = PHYS_TO_VM_PAGE(vtophys(pteva)); 1973 pmap->pm_ptphint = mpte; 1974 } 1975 mpte->wire_count++; 1976 } else { 1977 mpte = _pmap_allocpte(pmap, ptepindex, 1978 M_NOWAIT); 1979 if (mpte == NULL) 1980 return (mpte); 1981 } 1982 } 1983 } else { 1984 mpte = NULL; 1985 } 1986 1987 pte = pmap_pte(pmap, va); 1988 if (pmap_pte_v(pte)) { 1989 if (mpte != NULL) { 1990 mpte->wire_count--; 1991 mpte = NULL; 1992 } 1993 return (mpte); 1994 } 1995 1996 /* 1997 * Enter on the PV list if part of our managed memory. 1998 */ 1999 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0 && 2000 !pmap_try_insert_pv_entry(pmap, mpte, va, m)) { 2001 if (mpte != NULL) { 2002 pmap_unwire_pte_hold(pmap, mpte); 2003 mpte = NULL; 2004 } 2005 return (mpte); 2006 } 2007 2008 /* 2009 * Increment counters 2010 */ 2011 pmap->pm_stats.resident_count++; 2012 2013 pa = VM_PAGE_TO_PHYS(m); 2014 2015 /* 2016 * Now validate mapping with RO protection 2017 */ 2018 *pte = mips_paddr_to_tlbpfn(pa) | PTE_V; 2019 2020 if (is_cacheable_mem(pa)) 2021 *pte |= PTE_CACHE; 2022 else 2023 *pte |= PTE_UNCACHED; 2024 2025 if (is_kernel_pmap(pmap)) 2026 *pte |= PTE_G; 2027 else { 2028 *pte |= PTE_RO; 2029 /* 2030 * Sync I & D caches. Do this only if the the target pmap 2031 * belongs to the current process. Otherwise, an 2032 * unresolvable TLB miss may occur. */ 2033 if (pmap == &curproc->p_vmspace->vm_pmap) { 2034 va &= ~PAGE_MASK; 2035 mips_icache_sync_range(va, NBPG); 2036 mips_dcache_wbinv_range(va, NBPG); 2037 } 2038 } 2039 return (mpte); 2040} 2041 2042/* 2043 * Make a temporary mapping for a physical address. This is only intended 2044 * to be used for panic dumps. 2045 */ 2046void * 2047pmap_kenter_temporary(vm_paddr_t pa, int i) 2048{ 2049 vm_offset_t va; 2050 register_t intr; 2051 if (i != 0) 2052 printf("%s: ERROR!!! More than one page of virtual address mapping not supported\n", 2053 __func__); 2054 2055 if (pa < MIPS_KSEG0_LARGEST_PHYS) { 2056 va = MIPS_PHYS_TO_KSEG0(pa); 2057 } else { 2058 int cpu; 2059 struct local_sysmaps *sysm; 2060 pt_entry_t *pte, npte; 2061 2062 /* If this is used other than for dumps, we may need to leave 2063 * interrupts disasbled on return. If crash dumps don't work when 2064 * we get to this point, we might want to consider this (leaving things 2065 * disabled as a starting point ;-) 2066 */ 2067 intr = intr_disable(); 2068 cpu = PCPU_GET(cpuid); 2069 sysm = &sysmap_lmem[cpu]; 2070 /* Since this is for the debugger, no locks or any other fun */ 2071 npte = mips_paddr_to_tlbpfn(pa) | PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; 2072 pte = pmap_pte(kernel_pmap, sysm->base); 2073 *pte = npte; 2074 sysm->valid1 = 1; 2075 pmap_update_page(kernel_pmap, sysm->base, npte); 2076 va = sysm->base; 2077 intr_restore(intr); 2078 } 2079 return ((void *)va); 2080} 2081 2082void 2083pmap_kenter_temporary_free(vm_paddr_t pa) 2084{ 2085 int cpu; 2086 register_t intr; 2087 struct local_sysmaps *sysm; 2088 2089 if (pa < MIPS_KSEG0_LARGEST_PHYS) { 2090 /* nothing to do for this case */ 2091 return; 2092 } 2093 cpu = PCPU_GET(cpuid); 2094 sysm = &sysmap_lmem[cpu]; 2095 if (sysm->valid1) { 2096 pt_entry_t *pte; 2097 2098 intr = intr_disable(); 2099 pte = pmap_pte(kernel_pmap, sysm->base); 2100 *pte = PTE_G; 2101 pmap_invalidate_page(kernel_pmap, sysm->base); 2102 intr_restore(intr); 2103 sysm->valid1 = 0; 2104 } 2105} 2106 2107/* 2108 * Moved the code to Machine Independent 2109 * vm_map_pmap_enter() 2110 */ 2111 2112/* 2113 * Maps a sequence of resident pages belonging to the same object. 2114 * The sequence begins with the given page m_start. This page is 2115 * mapped at the given virtual address start. Each subsequent page is 2116 * mapped at a virtual address that is offset from start by the same 2117 * amount as the page is offset from m_start within the object. The 2118 * last page in the sequence is the page with the largest offset from 2119 * m_start that can be mapped at a virtual address less than the given 2120 * virtual address end. Not every virtual page between start and end 2121 * is mapped; only those for which a resident page exists with the 2122 * corresponding offset from m_start are mapped. 2123 */ 2124void 2125pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 2126 vm_page_t m_start, vm_prot_t prot) 2127{ 2128 vm_page_t m, mpte; 2129 vm_pindex_t diff, psize; 2130 2131 VM_OBJECT_LOCK_ASSERT(m_start->object, MA_OWNED); 2132 psize = atop(end - start); 2133 mpte = NULL; 2134 m = m_start; 2135 PMAP_LOCK(pmap); 2136 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 2137 mpte = pmap_enter_quick_locked(pmap, start + ptoa(diff), m, 2138 prot, mpte); 2139 m = TAILQ_NEXT(m, listq); 2140 } 2141 PMAP_UNLOCK(pmap); 2142} 2143 2144/* 2145 * pmap_object_init_pt preloads the ptes for a given object 2146 * into the specified pmap. This eliminates the blast of soft 2147 * faults on process startup and immediately after an mmap. 2148 */ 2149void 2150pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, 2151 vm_object_t object, vm_pindex_t pindex, vm_size_t size) 2152{ 2153 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 2154 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 2155 ("pmap_object_init_pt: non-device object")); 2156} 2157 2158/* 2159 * Routine: pmap_change_wiring 2160 * Function: Change the wiring attribute for a map/virtual-address 2161 * pair. 2162 * In/out conditions: 2163 * The mapping must already exist in the pmap. 2164 */ 2165void 2166pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 2167{ 2168 register pt_entry_t *pte; 2169 2170 if (pmap == NULL) 2171 return; 2172 2173 PMAP_LOCK(pmap); 2174 pte = pmap_pte(pmap, va); 2175 2176 if (wired && !pmap_pte_w(pte)) 2177 pmap->pm_stats.wired_count++; 2178 else if (!wired && pmap_pte_w(pte)) 2179 pmap->pm_stats.wired_count--; 2180 2181 /* 2182 * Wiring is not a hardware characteristic so there is no need to 2183 * invalidate TLB. 2184 */ 2185 pmap_pte_set_w(pte, wired); 2186 PMAP_UNLOCK(pmap); 2187} 2188 2189/* 2190 * Copy the range specified by src_addr/len 2191 * from the source map to the range dst_addr/len 2192 * in the destination map. 2193 * 2194 * This routine is only advisory and need not do anything. 2195 */ 2196 2197void 2198pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, 2199 vm_size_t len, vm_offset_t src_addr) 2200{ 2201} 2202 2203/* 2204 * pmap_zero_page zeros the specified hardware page by mapping 2205 * the page into KVM and using bzero to clear its contents. 2206 */ 2207void 2208pmap_zero_page(vm_page_t m) 2209{ 2210 vm_offset_t va; 2211 vm_paddr_t phys = VM_PAGE_TO_PHYS(m); 2212 register_t intr; 2213 2214 if (phys < MIPS_KSEG0_LARGEST_PHYS) { 2215 va = MIPS_PHYS_TO_KSEG0(phys); 2216 2217 bzero((caddr_t)va, PAGE_SIZE); 2218 mips_dcache_wbinv_range(va, PAGE_SIZE); 2219 } else { 2220 PMAP_LMEM_MAP1(va, phys); 2221 2222 bzero((caddr_t)va, PAGE_SIZE); 2223 mips_dcache_wbinv_range(va, PAGE_SIZE); 2224 2225 PMAP_LMEM_UNMAP(); 2226 } 2227} 2228 2229/* 2230 * pmap_zero_page_area zeros the specified hardware page by mapping 2231 * the page into KVM and using bzero to clear its contents. 2232 * 2233 * off and size may not cover an area beyond a single hardware page. 2234 */ 2235void 2236pmap_zero_page_area(vm_page_t m, int off, int size) 2237{ 2238 vm_offset_t va; 2239 vm_paddr_t phys = VM_PAGE_TO_PHYS(m); 2240 register_t intr; 2241 2242 if (phys < MIPS_KSEG0_LARGEST_PHYS) { 2243 va = MIPS_PHYS_TO_KSEG0(phys); 2244 bzero((char *)(caddr_t)va + off, size); 2245 mips_dcache_wbinv_range(va + off, size); 2246 } else { 2247 PMAP_LMEM_MAP1(va, phys); 2248 2249 bzero((char *)va + off, size); 2250 mips_dcache_wbinv_range(va + off, size); 2251 2252 PMAP_LMEM_UNMAP(); 2253 } 2254} 2255 2256void 2257pmap_zero_page_idle(vm_page_t m) 2258{ 2259 vm_offset_t va; 2260 vm_paddr_t phys = VM_PAGE_TO_PHYS(m); 2261 register_t intr; 2262 2263 if (phys < MIPS_KSEG0_LARGEST_PHYS) { 2264 va = MIPS_PHYS_TO_KSEG0(phys); 2265 bzero((caddr_t)va, PAGE_SIZE); 2266 mips_dcache_wbinv_range(va, PAGE_SIZE); 2267 } else { 2268 PMAP_LMEM_MAP1(va, phys); 2269 2270 bzero((caddr_t)va, PAGE_SIZE); 2271 mips_dcache_wbinv_range(va, PAGE_SIZE); 2272 2273 PMAP_LMEM_UNMAP(); 2274 } 2275} 2276 2277/* 2278 * pmap_copy_page copies the specified (machine independent) 2279 * page by mapping the page into virtual memory and using 2280 * bcopy to copy the page, one machine dependent page at a 2281 * time. 2282 */ 2283void 2284pmap_copy_page(vm_page_t src, vm_page_t dst) 2285{ 2286 vm_offset_t va_src, va_dst; 2287 vm_paddr_t phy_src = VM_PAGE_TO_PHYS(src); 2288 vm_paddr_t phy_dst = VM_PAGE_TO_PHYS(dst); 2289 register_t intr; 2290 2291 if ((phy_src < MIPS_KSEG0_LARGEST_PHYS) && (phy_dst < MIPS_KSEG0_LARGEST_PHYS)) { 2292 /* easy case, all can be accessed via KSEG0 */ 2293 /* 2294 * Flush all caches for VA that are mapped to this page 2295 * to make sure that data in SDRAM is up to date 2296 */ 2297 pmap_flush_pvcache(src); 2298 mips_dcache_wbinv_range_index( 2299 MIPS_PHYS_TO_KSEG0(phy_dst), PAGE_SIZE); 2300 va_src = MIPS_PHYS_TO_KSEG0(phy_src); 2301 va_dst = MIPS_PHYS_TO_KSEG0(phy_dst); 2302 bcopy((caddr_t)va_src, (caddr_t)va_dst, PAGE_SIZE); 2303 mips_dcache_wbinv_range(va_dst, PAGE_SIZE); 2304 } else { 2305 PMAP_LMEM_MAP2(va_src, phy_src, va_dst, phy_dst); 2306 2307 bcopy((void *)va_src, (void *)va_dst, PAGE_SIZE); 2308 mips_dcache_wbinv_range(va_dst, PAGE_SIZE); 2309 2310 PMAP_LMEM_UNMAP(); 2311 } 2312} 2313 2314/* 2315 * Returns true if the pmap's pv is one of the first 2316 * 16 pvs linked to from this page. This count may 2317 * be changed upwards or downwards in the future; it 2318 * is only necessary that true be returned for a small 2319 * subset of pmaps for proper page aging. 2320 */ 2321boolean_t 2322pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 2323{ 2324 pv_entry_t pv; 2325 int loops = 0; 2326 2327 if (m->flags & PG_FICTITIOUS) 2328 return FALSE; 2329 2330 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2331 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2332 if (pv->pv_pmap == pmap) { 2333 return TRUE; 2334 } 2335 loops++; 2336 if (loops >= 16) 2337 break; 2338 } 2339 return (FALSE); 2340} 2341 2342/* 2343 * Remove all pages from specified address space 2344 * this aids process exit speeds. Also, this code 2345 * is special cased for current process only, but 2346 * can have the more generic (and slightly slower) 2347 * mode enabled. This is much faster than pmap_remove 2348 * in the case of running down an entire address space. 2349 */ 2350void 2351pmap_remove_pages(pmap_t pmap) 2352{ 2353 pt_entry_t *pte, tpte; 2354 pv_entry_t pv, npv; 2355 vm_page_t m; 2356 2357 if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) { 2358 printf("warning: pmap_remove_pages called with non-current pmap\n"); 2359 return; 2360 } 2361 vm_page_lock_queues(); 2362 PMAP_LOCK(pmap); 2363 sched_pin(); 2364 //XXX need to be TAILQ_FOREACH_SAFE ? 2365 for (pv = TAILQ_FIRST(&pmap->pm_pvlist); pv; pv = npv) { 2366 2367 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 2368 if (!pmap_pte_v(pte)) 2369 panic("pmap_remove_pages: page on pm_pvlist has no pte\n"); 2370 tpte = *pte; 2371 2372/* 2373 * We cannot remove wired pages from a process' mapping at this time 2374 */ 2375 if (tpte & PTE_W) { 2376 npv = TAILQ_NEXT(pv, pv_plist); 2377 continue; 2378 } 2379 *pte = is_kernel_pmap(pmap) ? PTE_G : 0; 2380 2381 m = PHYS_TO_VM_PAGE(mips_tlbpfn_to_paddr(tpte)); 2382 2383 KASSERT(m < &vm_page_array[vm_page_array_size], 2384 ("pmap_remove_pages: bad tpte %lx", tpte)); 2385 2386 pv->pv_pmap->pm_stats.resident_count--; 2387 2388 /* 2389 * Update the vm_page_t clean and reference bits. 2390 */ 2391 if (tpte & PTE_M) { 2392 vm_page_dirty(m); 2393 } 2394 npv = TAILQ_NEXT(pv, pv_plist); 2395 TAILQ_REMOVE(&pv->pv_pmap->pm_pvlist, pv, pv_plist); 2396 2397 m->md.pv_list_count--; 2398 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2399 if (TAILQ_FIRST(&m->md.pv_list) == NULL) { 2400 vm_page_flag_clear(m, PG_WRITEABLE); 2401 } 2402 pmap_unuse_pt(pv->pv_pmap, pv->pv_va, pv->pv_ptem); 2403 free_pv_entry(pv); 2404 } 2405 sched_unpin(); 2406 pmap_invalidate_all(pmap); 2407 PMAP_UNLOCK(pmap); 2408 vm_page_unlock_queues(); 2409} 2410 2411/* 2412 * pmap_testbit tests bits in pte's 2413 * note that the testbit/changebit routines are inline, 2414 * and a lot of things compile-time evaluate. 2415 */ 2416static boolean_t 2417pmap_testbit(vm_page_t m, int bit) 2418{ 2419 pv_entry_t pv; 2420 pt_entry_t *pte; 2421 boolean_t rv = FALSE; 2422 2423 if (m->flags & PG_FICTITIOUS) 2424 return rv; 2425 2426 if (TAILQ_FIRST(&m->md.pv_list) == NULL) 2427 return rv; 2428 2429 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2430 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2431#if defined(PMAP_DIAGNOSTIC) 2432 if (!pv->pv_pmap) { 2433 printf("Null pmap (tb) at va: 0x%x\n", pv->pv_va); 2434 continue; 2435 } 2436#endif 2437 PMAP_LOCK(pv->pv_pmap); 2438 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 2439 rv = (*pte & bit) != 0; 2440 PMAP_UNLOCK(pv->pv_pmap); 2441 if (rv) 2442 break; 2443 } 2444 return (rv); 2445} 2446 2447/* 2448 * this routine is used to modify bits in ptes 2449 */ 2450static __inline void 2451pmap_changebit(vm_page_t m, int bit, boolean_t setem) 2452{ 2453 register pv_entry_t pv; 2454 register pt_entry_t *pte; 2455 2456 if (m->flags & PG_FICTITIOUS) 2457 return; 2458 2459 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2460 /* 2461 * Loop over all current mappings setting/clearing as appropos If 2462 * setting RO do we need to clear the VAC? 2463 */ 2464 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2465#if defined(PMAP_DIAGNOSTIC) 2466 if (!pv->pv_pmap) { 2467 printf("Null pmap (cb) at va: 0x%x\n", pv->pv_va); 2468 continue; 2469 } 2470#endif 2471 2472 PMAP_LOCK(pv->pv_pmap); 2473 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 2474 2475 if (setem) { 2476 *(int *)pte |= bit; 2477 pmap_update_page(pv->pv_pmap, pv->pv_va, *pte); 2478 } else { 2479 vm_offset_t pbits = *(vm_offset_t *)pte; 2480 2481 if (pbits & bit) { 2482 if (bit == PTE_RW) { 2483 if (pbits & PTE_M) { 2484 vm_page_dirty(m); 2485 } 2486 *(int *)pte = (pbits & ~(PTE_M | PTE_RW)) | 2487 PTE_RO; 2488 } else { 2489 *(int *)pte = pbits & ~bit; 2490 } 2491 pmap_update_page(pv->pv_pmap, pv->pv_va, *pte); 2492 } 2493 } 2494 PMAP_UNLOCK(pv->pv_pmap); 2495 } 2496 if (!setem && bit == PTE_RW) 2497 vm_page_flag_clear(m, PG_WRITEABLE); 2498} 2499 2500/* 2501 * pmap_page_wired_mappings: 2502 * 2503 * Return the number of managed mappings to the given physical page 2504 * that are wired. 2505 */ 2506int 2507pmap_page_wired_mappings(vm_page_t m) 2508{ 2509 pv_entry_t pv; 2510 int count; 2511 2512 count = 0; 2513 if ((m->flags & PG_FICTITIOUS) != 0) 2514 return (count); 2515 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2516 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) 2517 if (pv->pv_wired) 2518 count++; 2519 return (count); 2520} 2521 2522/* 2523 * Clear the write and modified bits in each of the given page's mappings. 2524 */ 2525void 2526pmap_remove_write(vm_page_t m) 2527{ 2528 pv_entry_t pv, npv; 2529 vm_offset_t va; 2530 pt_entry_t *pte; 2531 2532 if ((m->flags & PG_WRITEABLE) == 0) 2533 return; 2534 2535 /* 2536 * Loop over all current mappings setting/clearing as appropos. 2537 */ 2538 for (pv = TAILQ_FIRST(&m->md.pv_list); pv; pv = npv) { 2539 npv = TAILQ_NEXT(pv, pv_plist); 2540 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 2541 2542 if ((pte == NULL) || !mips_pg_v(*pte)) 2543 panic("page on pm_pvlist has no pte\n"); 2544 2545 va = pv->pv_va; 2546 pmap_protect(pv->pv_pmap, va, va + PAGE_SIZE, 2547 VM_PROT_READ | VM_PROT_EXECUTE); 2548 } 2549 vm_page_flag_clear(m, PG_WRITEABLE); 2550} 2551 2552/* 2553 * pmap_ts_referenced: 2554 * 2555 * Return the count of reference bits for a page, clearing all of them. 2556 */ 2557int 2558pmap_ts_referenced(vm_page_t m) 2559{ 2560 if (m->flags & PG_FICTITIOUS) 2561 return (0); 2562 2563 if (m->md.pv_flags & PV_TABLE_REF) { 2564 m->md.pv_flags &= ~PV_TABLE_REF; 2565 return 1; 2566 } 2567 return 0; 2568} 2569 2570/* 2571 * pmap_is_modified: 2572 * 2573 * Return whether or not the specified physical page was modified 2574 * in any physical maps. 2575 */ 2576boolean_t 2577pmap_is_modified(vm_page_t m) 2578{ 2579 if (m->flags & PG_FICTITIOUS) 2580 return FALSE; 2581 2582 if (m->md.pv_flags & PV_TABLE_MOD) 2583 return TRUE; 2584 else 2585 return pmap_testbit(m, PTE_M); 2586} 2587 2588/* N/C */ 2589 2590/* 2591 * pmap_is_prefaultable: 2592 * 2593 * Return whether or not the specified virtual address is elgible 2594 * for prefault. 2595 */ 2596boolean_t 2597pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 2598{ 2599 pt_entry_t *pte; 2600 boolean_t rv; 2601 2602 rv = FALSE; 2603 PMAP_LOCK(pmap); 2604 if (*pmap_pde(pmap, addr)) { 2605 pte = pmap_pte(pmap, addr); 2606 rv = (*pte == 0); 2607 } 2608 PMAP_UNLOCK(pmap); 2609 return (rv); 2610} 2611 2612/* 2613 * Clear the modify bits on the specified physical page. 2614 */ 2615void 2616pmap_clear_modify(vm_page_t m) 2617{ 2618 if (m->flags & PG_FICTITIOUS) 2619 return; 2620 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2621 if (m->md.pv_flags & PV_TABLE_MOD) { 2622 pmap_changebit(m, PTE_M, FALSE); 2623 m->md.pv_flags &= ~PV_TABLE_MOD; 2624 } 2625} 2626 2627/* 2628 * pmap_clear_reference: 2629 * 2630 * Clear the reference bit on the specified physical page. 2631 */ 2632void 2633pmap_clear_reference(vm_page_t m) 2634{ 2635 if (m->flags & PG_FICTITIOUS) 2636 return; 2637 2638 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2639 if (m->md.pv_flags & PV_TABLE_REF) { 2640 m->md.pv_flags &= ~PV_TABLE_REF; 2641 } 2642} 2643 2644/* 2645 * Miscellaneous support routines follow 2646 */ 2647 2648/* 2649 * Map a set of physical memory pages into the kernel virtual 2650 * address space. Return a pointer to where it is mapped. This 2651 * routine is intended to be used for mapping device memory, 2652 * NOT real memory. 2653 */ 2654 2655/* 2656 * Map a set of physical memory pages into the kernel virtual 2657 * address space. Return a pointer to where it is mapped. This 2658 * routine is intended to be used for mapping device memory, 2659 * NOT real memory. 2660 */ 2661void * 2662pmap_mapdev(vm_offset_t pa, vm_size_t size) 2663{ 2664 vm_offset_t va, tmpva, offset; 2665 2666 /* 2667 * KSEG1 maps only first 512M of phys address space. For 2668 * pa > 0x20000000 we should make proper mapping * using pmap_kenter. 2669 */ 2670 if ((pa + size - 1) < MIPS_KSEG0_LARGEST_PHYS) 2671 return (void *)MIPS_PHYS_TO_KSEG1(pa); 2672 else { 2673 offset = pa & PAGE_MASK; 2674 size = roundup(size + offset, PAGE_SIZE); 2675 2676 va = kmem_alloc_nofault(kernel_map, size); 2677 if (!va) 2678 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 2679 pa = trunc_page(pa); 2680 for (tmpva = va; size > 0;) { 2681 pmap_kenter(tmpva, pa); 2682 size -= PAGE_SIZE; 2683 tmpva += PAGE_SIZE; 2684 pa += PAGE_SIZE; 2685 } 2686 } 2687 2688 return ((void *)(va + offset)); 2689} 2690 2691void 2692pmap_unmapdev(vm_offset_t va, vm_size_t size) 2693{ 2694 vm_offset_t base, offset, tmpva; 2695 2696 /* If the address is within KSEG1 then there is nothing to do */ 2697 if (va >= MIPS_KSEG1_START && va <= MIPS_KSEG1_END) 2698 return; 2699 2700 base = trunc_page(va); 2701 offset = va & PAGE_MASK; 2702 size = roundup(size + offset, PAGE_SIZE); 2703 for (tmpva = base; tmpva < base + size; tmpva += PAGE_SIZE) 2704 pmap_kremove(tmpva); 2705 kmem_free(kernel_map, base, size); 2706} 2707 2708/* 2709 * perform the pmap work for mincore 2710 */ 2711int 2712pmap_mincore(pmap_t pmap, vm_offset_t addr) 2713{ 2714 2715 pt_entry_t *ptep, pte; 2716 vm_page_t m; 2717 int val = 0; 2718 2719 PMAP_LOCK(pmap); 2720 ptep = pmap_pte(pmap, addr); 2721 pte = (ptep != NULL) ? *ptep : 0; 2722 PMAP_UNLOCK(pmap); 2723 2724 if (mips_pg_v(pte)) { 2725 vm_offset_t pa; 2726 2727 val = MINCORE_INCORE; 2728 pa = mips_tlbpfn_to_paddr(pte); 2729 if (!page_is_managed(pa)) 2730 return val; 2731 2732 m = PHYS_TO_VM_PAGE(pa); 2733 2734 /* 2735 * Modified by us 2736 */ 2737 if (pte & PTE_M) 2738 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 2739 /* 2740 * Modified by someone 2741 */ 2742 else { 2743 vm_page_lock_queues(); 2744 if (m->dirty || pmap_is_modified(m)) 2745 val |= MINCORE_MODIFIED_OTHER; 2746 vm_page_unlock_queues(); 2747 } 2748 /* 2749 * Referenced by us or someone 2750 */ 2751 vm_page_lock_queues(); 2752 if ((m->flags & PG_REFERENCED) || pmap_ts_referenced(m)) { 2753 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 2754 vm_page_flag_set(m, PG_REFERENCED); 2755 } 2756 vm_page_unlock_queues(); 2757 } 2758 return val; 2759} 2760 2761void 2762pmap_activate(struct thread *td) 2763{ 2764 pmap_t pmap, oldpmap; 2765 struct proc *p = td->td_proc; 2766 2767 critical_enter(); 2768 2769 pmap = vmspace_pmap(p->p_vmspace); 2770 oldpmap = PCPU_GET(curpmap); 2771 2772 if (oldpmap) 2773 atomic_clear_32(&oldpmap->pm_active, PCPU_GET(cpumask)); 2774 atomic_set_32(&pmap->pm_active, PCPU_GET(cpumask)); 2775 pmap_asid_alloc(pmap); 2776 if (td == curthread) { 2777 PCPU_SET(segbase, pmap->pm_segtab); 2778 MachSetPID(pmap->pm_asid[PCPU_GET(cpuid)].asid); 2779 } 2780 2781 PCPU_SET(curpmap, pmap); 2782 critical_exit(); 2783} 2784 2785void 2786pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 2787{ 2788} 2789 2790/* 2791 * Increase the starting virtual address of the given mapping if a 2792 * different alignment might result in more superpage mappings. 2793 */ 2794void 2795pmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 2796 vm_offset_t *addr, vm_size_t size) 2797{ 2798 vm_offset_t superpage_offset; 2799 2800 if (size < NBSEG) 2801 return; 2802 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 2803 offset += ptoa(object->pg_color); 2804 superpage_offset = offset & SEGOFSET; 2805 if (size - ((NBSEG - superpage_offset) & SEGOFSET) < NBSEG || 2806 (*addr & SEGOFSET) == superpage_offset) 2807 return; 2808 if ((*addr & SEGOFSET) < superpage_offset) 2809 *addr = (*addr & ~SEGOFSET) + superpage_offset; 2810 else 2811 *addr = ((*addr + SEGOFSET) & ~SEGOFSET) + superpage_offset; 2812} 2813 2814int pmap_pid_dump(int pid); 2815 2816int 2817pmap_pid_dump(int pid) 2818{ 2819 pmap_t pmap; 2820 struct proc *p; 2821 int npte = 0; 2822 int index; 2823 2824 sx_slock(&allproc_lock); 2825 LIST_FOREACH(p, &allproc, p_list) { 2826 if (p->p_pid != pid) 2827 continue; 2828 2829 if (p->p_vmspace) { 2830 int i, j; 2831 2832 printf("vmspace is %p\n", 2833 p->p_vmspace); 2834 index = 0; 2835 pmap = vmspace_pmap(p->p_vmspace); 2836 printf("pmap asid:%x generation:%x\n", 2837 pmap->pm_asid[0].asid, 2838 pmap->pm_asid[0].gen); 2839 for (i = 0; i < NUSERPGTBLS; i++) { 2840 pd_entry_t *pde; 2841 pt_entry_t *pte; 2842 unsigned base = i << SEGSHIFT; 2843 2844 pde = &pmap->pm_segtab[i]; 2845 if (pde && pmap_pde_v(pde)) { 2846 for (j = 0; j < 1024; j++) { 2847 vm_offset_t va = base + 2848 (j << PAGE_SHIFT); 2849 2850 pte = pmap_pte(pmap, va); 2851 if (pte && pmap_pte_v(pte)) { 2852 vm_offset_t pa; 2853 vm_page_t m; 2854 2855 pa = mips_tlbpfn_to_paddr(*pte); 2856 m = PHYS_TO_VM_PAGE(pa); 2857 printf("va: %p, pt: %p, h: %d, w: %d, f: 0x%x", 2858 (void *)va, 2859 (void *)pa, 2860 m->hold_count, 2861 m->wire_count, 2862 m->flags); 2863 npte++; 2864 index++; 2865 if (index >= 2) { 2866 index = 0; 2867 printf("\n"); 2868 } else { 2869 printf(" "); 2870 } 2871 } 2872 } 2873 } 2874 } 2875 } else { 2876 printf("Process pid:%d has no vm_space\n", pid); 2877 } 2878 break; 2879 } 2880 sx_sunlock(&allproc_lock); 2881 return npte; 2882} 2883 2884 2885#if defined(DEBUG) 2886 2887static void pads(pmap_t pm); 2888void pmap_pvdump(vm_offset_t pa); 2889 2890/* print address space of pmap*/ 2891static void 2892pads(pmap_t pm) 2893{ 2894 unsigned va, i, j; 2895 pt_entry_t *ptep; 2896 2897 if (pm == kernel_pmap) 2898 return; 2899 for (i = 0; i < NPTEPG; i++) 2900 if (pm->pm_segtab[i]) 2901 for (j = 0; j < NPTEPG; j++) { 2902 va = (i << SEGSHIFT) + (j << PAGE_SHIFT); 2903 if (pm == kernel_pmap && va < KERNBASE) 2904 continue; 2905 if (pm != kernel_pmap && 2906 va >= VM_MAXUSER_ADDRESS) 2907 continue; 2908 ptep = pmap_pte(pm, va); 2909 if (pmap_pte_v(ptep)) 2910 printf("%x:%x ", va, *(int *)ptep); 2911 } 2912 2913} 2914 2915void 2916pmap_pvdump(vm_offset_t pa) 2917{ 2918 register pv_entry_t pv; 2919 vm_page_t m; 2920 2921 printf("pa %x", pa); 2922 m = PHYS_TO_VM_PAGE(pa); 2923 for (pv = TAILQ_FIRST(&m->md.pv_list); pv; 2924 pv = TAILQ_NEXT(pv, pv_list)) { 2925 printf(" -> pmap %p, va %x", (void *)pv->pv_pmap, pv->pv_va); 2926 pads(pv->pv_pmap); 2927 } 2928 printf(" "); 2929} 2930 2931/* N/C */ 2932#endif 2933 2934 2935/* 2936 * Allocate TLB address space tag (called ASID or TLBPID) and return it. 2937 * It takes almost as much or more time to search the TLB for a 2938 * specific ASID and flush those entries as it does to flush the entire TLB. 2939 * Therefore, when we allocate a new ASID, we just take the next number. When 2940 * we run out of numbers, we flush the TLB, increment the generation count 2941 * and start over. ASID zero is reserved for kernel use. 2942 */ 2943static void 2944pmap_asid_alloc(pmap) 2945 pmap_t pmap; 2946{ 2947 if (pmap->pm_asid[PCPU_GET(cpuid)].asid != PMAP_ASID_RESERVED && 2948 pmap->pm_asid[PCPU_GET(cpuid)].gen == PCPU_GET(asid_generation)); 2949 else { 2950 if (PCPU_GET(next_asid) == pmap_max_asid) { 2951 MIPS_TBIAP(); 2952 PCPU_SET(asid_generation, 2953 (PCPU_GET(asid_generation) + 1) & ASIDGEN_MASK); 2954 if (PCPU_GET(asid_generation) == 0) { 2955 PCPU_SET(asid_generation, 1); 2956 } 2957 PCPU_SET(next_asid, 1); /* 0 means invalid */ 2958 } 2959 pmap->pm_asid[PCPU_GET(cpuid)].asid = PCPU_GET(next_asid); 2960 pmap->pm_asid[PCPU_GET(cpuid)].gen = PCPU_GET(asid_generation); 2961 PCPU_SET(next_asid, PCPU_GET(next_asid) + 1); 2962 } 2963} 2964 2965int 2966page_is_managed(vm_offset_t pa) 2967{ 2968 vm_offset_t pgnum = mips_btop(pa); 2969 2970 if (pgnum >= first_page && (pgnum < (first_page + vm_page_array_size))) { 2971 vm_page_t m; 2972 2973 m = PHYS_TO_VM_PAGE(pa); 2974 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) 2975 return 1; 2976 } 2977 return 0; 2978} 2979 2980static int 2981init_pte_prot(vm_offset_t va, vm_page_t m, vm_prot_t prot) 2982{ 2983 int rw = 0; 2984 2985 if (!(prot & VM_PROT_WRITE)) 2986 rw = PTE_ROPAGE; 2987 else { 2988 if (va >= VM_MIN_KERNEL_ADDRESS) { 2989 /* 2990 * Don't bother to trap on kernel writes, just 2991 * record page as dirty. 2992 */ 2993 rw = PTE_RWPAGE; 2994 vm_page_dirty(m); 2995 } else if ((m->md.pv_flags & PV_TABLE_MOD) || 2996 m->dirty == VM_PAGE_BITS_ALL) 2997 rw = PTE_RWPAGE; 2998 else 2999 rw = PTE_CWPAGE; 3000 vm_page_flag_set(m, PG_WRITEABLE); 3001 } 3002 return rw; 3003} 3004 3005/* 3006 * pmap_page_is_free: 3007 * 3008 * Called when a page is freed to allow pmap to clean up 3009 * any extra state associated with the page. In this case 3010 * clear modified/referenced bits. 3011 */ 3012void 3013pmap_page_is_free(vm_page_t m) 3014{ 3015 3016 m->md.pv_flags = 0; 3017} 3018 3019/* 3020 * pmap_set_modified: 3021 * 3022 * Sets the page modified and reference bits for the specified page. 3023 */ 3024void 3025pmap_set_modified(vm_offset_t pa) 3026{ 3027 3028 PHYS_TO_VM_PAGE(pa)->md.pv_flags |= (PV_TABLE_REF | PV_TABLE_MOD); 3029} 3030 3031/* 3032 * Routine: pmap_kextract 3033 * Function: 3034 * Extract the physical page address associated 3035 * virtual address. 3036 */ 3037 /* PMAP_INLINE */ vm_offset_t 3038pmap_kextract(vm_offset_t va) 3039{ 3040 vm_offset_t pa = 0; 3041 3042 if (va < MIPS_KSEG0_START) { 3043 /* user virtual address */ 3044 pt_entry_t *ptep; 3045 3046 if (curproc && curproc->p_vmspace) { 3047 ptep = pmap_pte(&curproc->p_vmspace->vm_pmap, va); 3048 if (ptep) 3049 pa = mips_tlbpfn_to_paddr(*ptep) | 3050 (va & PAGE_MASK); 3051 } 3052 } else if (va >= MIPS_KSEG0_START && 3053 va < MIPS_KSEG1_START) 3054 pa = MIPS_KSEG0_TO_PHYS(va); 3055 else if (va >= MIPS_KSEG1_START && 3056 va < MIPS_KSEG2_START) 3057 pa = MIPS_KSEG1_TO_PHYS(va); 3058 else if (va >= MIPS_KSEG2_START && va < VM_MAX_KERNEL_ADDRESS) { 3059 pt_entry_t *ptep; 3060 3061 /* Is the kernel pmap initialized? */ 3062 if (kernel_pmap->pm_active) { 3063 /* Its inside the virtual address range */ 3064 ptep = pmap_pte(kernel_pmap, va); 3065 if (ptep) 3066 pa = mips_tlbpfn_to_paddr(*ptep) | 3067 (va & PAGE_MASK); 3068 } 3069 } 3070 return pa; 3071} 3072 3073void 3074pmap_flush_pvcache(vm_page_t m) 3075{ 3076 pv_entry_t pv; 3077 3078 if (m != NULL) { 3079 for (pv = TAILQ_FIRST(&m->md.pv_list); pv; 3080 pv = TAILQ_NEXT(pv, pv_list)) { 3081 mips_dcache_wbinv_range_index(pv->pv_va, NBPG); 3082 } 3083 } 3084} 3085 3086void 3087pmap_save_tlb(void) 3088{ 3089 int tlbno, cpu; 3090 3091 cpu = PCPU_GET(cpuid); 3092 3093 for (tlbno = 0; tlbno < num_tlbentries; ++tlbno) 3094 MachTLBRead(tlbno, &tlbstash[cpu][tlbno]); 3095} 3096 3097#ifdef DDB 3098#include <ddb/ddb.h> 3099 3100DB_SHOW_COMMAND(tlb, ddb_dump_tlb) 3101{ 3102 int cpu, tlbno; 3103 struct tlb *tlb; 3104 3105 if (have_addr) 3106 cpu = ((addr >> 4) % 16) * 10 + (addr % 16); 3107 else 3108 cpu = PCPU_GET(cpuid); 3109 3110 if (cpu < 0 || cpu >= mp_ncpus) { 3111 db_printf("Invalid CPU %d\n", cpu); 3112 return; 3113 } else 3114 db_printf("CPU %d:\n", cpu); 3115 3116 if (cpu == PCPU_GET(cpuid)) 3117 pmap_save_tlb(); 3118 3119 for (tlbno = 0; tlbno < num_tlbentries; ++tlbno) { 3120 tlb = &tlbstash[cpu][tlbno]; 3121 if (tlb->tlb_lo0 & PTE_V || tlb->tlb_lo1 & PTE_V) { 3122 printf("TLB %2d vad 0x%0lx ", 3123 tlbno, (long)(tlb->tlb_hi & 0xffffff00)); 3124 } else { 3125 printf("TLB*%2d vad 0x%0lx ", 3126 tlbno, (long)(tlb->tlb_hi & 0xffffff00)); 3127 } 3128 printf("0=0x%0lx ", pfn_to_vad((long)tlb->tlb_lo0)); 3129 printf("%c", tlb->tlb_lo0 & PTE_V ? 'V' : '-'); 3130 printf("%c", tlb->tlb_lo0 & PTE_M ? 'M' : '-'); 3131 printf("%c", tlb->tlb_lo0 & PTE_G ? 'G' : '-'); 3132 printf(" atr %x ", (tlb->tlb_lo0 >> 3) & 7); 3133 printf("1=0x%0lx ", pfn_to_vad((long)tlb->tlb_lo1)); 3134 printf("%c", tlb->tlb_lo1 & PTE_V ? 'V' : '-'); 3135 printf("%c", tlb->tlb_lo1 & PTE_M ? 'M' : '-'); 3136 printf("%c", tlb->tlb_lo1 & PTE_G ? 'G' : '-'); 3137 printf(" atr %x ", (tlb->tlb_lo1 >> 3) & 7); 3138 printf(" sz=%x pid=%x\n", tlb->tlb_mask, 3139 (tlb->tlb_hi & 0x000000ff)); 3140 } 3141} 3142#endif /* DDB */ 3143