pmap.c revision 205360
1/* 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * Copyright (c) 1994 John S. Dyson 5 * All rights reserved. 6 * Copyright (c) 1994 David Greenman 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * the Systems Programming Group of the University of Utah Computer 11 * Science Department and William Jolitz of UUNET Technologies Inc. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 38 * from: src/sys/i386/i386/pmap.c,v 1.250.2.8 2000/11/21 00:09:14 ps 39 * JNPR: pmap.c,v 1.11.2.1 2007/08/16 11:51:06 girish 40 */ 41 42/* 43 * Manages physical address maps. 44 * 45 * In addition to hardware address maps, this 46 * module is called upon to provide software-use-only 47 * maps which may or may not be stored in the same 48 * form as hardware maps. These pseudo-maps are 49 * used to store intermediate results from copy 50 * operations to and from address spaces. 51 * 52 * Since the information managed by this module is 53 * also stored by the logical address mapping module, 54 * this module may throw away valid virtual-to-physical 55 * mappings at almost any time. However, invalidations 56 * of virtual-to-physical mappings must be done as 57 * requested. 58 * 59 * In order to cope with hardware architectures which 60 * make virtual-to-physical map invalidates expensive, 61 * this module may delay invalidate or reduced protection 62 * operations until such time as they are actually 63 * necessary. This module is given full information as 64 * to which processors are currently using which maps, 65 * and to when physical maps must be made correct. 66 */ 67 68#include <sys/cdefs.h> 69__FBSDID("$FreeBSD: head/sys/mips/mips/pmap.c 205360 2010-03-20 05:07:15Z neel $"); 70 71#include "opt_ddb.h" 72#include "opt_msgbuf.h" 73#include <sys/param.h> 74#include <sys/systm.h> 75#include <sys/proc.h> 76#include <sys/msgbuf.h> 77#include <sys/vmmeter.h> 78#include <sys/mman.h> 79#include <sys/smp.h> 80 81#include <vm/vm.h> 82#include <vm/vm_param.h> 83#include <sys/lock.h> 84#include <sys/mutex.h> 85#include <vm/vm_kern.h> 86#include <vm/vm_page.h> 87#include <vm/vm_map.h> 88#include <vm/vm_object.h> 89#include <vm/vm_extern.h> 90#include <vm/vm_pageout.h> 91#include <vm/vm_pager.h> 92#include <vm/uma.h> 93#include <sys/pcpu.h> 94#include <sys/sched.h> 95#ifdef SMP 96#include <sys/smp.h> 97#endif 98 99#include <machine/cache.h> 100#include <machine/md_var.h> 101 102#if defined(DIAGNOSTIC) 103#define PMAP_DIAGNOSTIC 104#endif 105 106#undef PMAP_DEBUG 107 108#ifndef PMAP_SHPGPERPROC 109#define PMAP_SHPGPERPROC 200 110#endif 111 112#if !defined(PMAP_DIAGNOSTIC) 113#define PMAP_INLINE __inline 114#else 115#define PMAP_INLINE 116#endif 117 118/* 119 * Get PDEs and PTEs for user/kernel address space 120 */ 121#define pmap_pde(m, v) (&((m)->pm_segtab[(vm_offset_t)(v) >> SEGSHIFT])) 122#define segtab_pde(m, v) (m[(vm_offset_t)(v) >> SEGSHIFT]) 123 124#define pmap_pte_w(pte) ((*(int *)pte & PTE_W) != 0) 125#define pmap_pde_v(pte) ((*(int *)pte) != 0) 126#define pmap_pte_m(pte) ((*(int *)pte & PTE_M) != 0) 127#define pmap_pte_v(pte) ((*(int *)pte & PTE_V) != 0) 128 129#define pmap_pte_set_w(pte, v) ((v)?(*(int *)pte |= PTE_W):(*(int *)pte &= ~PTE_W)) 130#define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v))) 131 132#define MIPS_SEGSIZE (1L << SEGSHIFT) 133#define mips_segtrunc(va) ((va) & ~(MIPS_SEGSIZE-1)) 134#define pmap_TLB_invalidate_all() MIPS_TBIAP() 135#define pmap_va_asid(pmap, va) ((va) | ((pmap)->pm_asid[PCPU_GET(cpuid)].asid << VMTLB_PID_SHIFT)) 136#define is_kernel_pmap(x) ((x) == kernel_pmap) 137 138struct pmap kernel_pmap_store; 139pd_entry_t *kernel_segmap; 140 141vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 142vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 143 144static int nkpt; 145unsigned pmap_max_asid; /* max ASID supported by the system */ 146 147 148#define PMAP_ASID_RESERVED 0 149 150 151vm_offset_t kernel_vm_end; 152 153static struct tlb tlbstash[MAXCPU][MIPS_MAX_TLB_ENTRIES]; 154 155static void pmap_asid_alloc(pmap_t pmap); 156 157/* 158 * Data for the pv entry allocation mechanism 159 */ 160static uma_zone_t pvzone; 161static struct vm_object pvzone_obj; 162static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 163 164struct fpage fpages_shared[FPAGES_SHARED]; 165 166struct sysmaps sysmaps_pcpu[MAXCPU]; 167 168static PMAP_INLINE void free_pv_entry(pv_entry_t pv); 169static pv_entry_t get_pv_entry(pmap_t locked_pmap); 170static __inline void pmap_changebit(vm_page_t m, int bit, boolean_t setem); 171 172static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, 173 vm_page_t m, vm_prot_t prot, vm_page_t mpte); 174static int pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va); 175static void pmap_remove_page(struct pmap *pmap, vm_offset_t va); 176static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, vm_offset_t va); 177static boolean_t pmap_testbit(vm_page_t m, int bit); 178static void 179pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t mpte, 180 vm_page_t m, boolean_t wired); 181static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_page_t mpte, 182 vm_offset_t va, vm_page_t m); 183 184static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags); 185 186static vm_page_t _pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags); 187static int pmap_unuse_pt(pmap_t, vm_offset_t, vm_page_t); 188static int init_pte_prot(vm_offset_t va, vm_page_t m, vm_prot_t prot); 189static void pmap_TLB_invalidate_kernel(vm_offset_t); 190static void pmap_TLB_update_kernel(vm_offset_t, pt_entry_t); 191static void pmap_init_fpage(void); 192 193#ifdef SMP 194static void pmap_invalidate_page_action(void *arg); 195static void pmap_invalidate_all_action(void *arg); 196static void pmap_update_page_action(void *arg); 197 198#endif 199 200struct local_sysmaps { 201 struct mtx lock; 202 pt_entry_t CMAP1; 203 pt_entry_t CMAP2; 204 caddr_t CADDR1; 205 caddr_t CADDR2; 206 uint16_t valid1, valid2; 207}; 208 209/* This structure is for large memory 210 * above 512Meg. We can't (in 32 bit mode) 211 * just use the direct mapped MIPS_KSEG0_TO_PHYS() 212 * macros since we can't see the memory and must 213 * map it in when we need to access it. In 64 214 * bit mode this goes away. 215 */ 216static struct local_sysmaps sysmap_lmem[MAXCPU]; 217caddr_t virtual_sys_start = (caddr_t)0; 218 219pd_entry_t 220pmap_segmap(pmap_t pmap, vm_offset_t va) 221{ 222 if (pmap->pm_segtab) 223 return (pmap->pm_segtab[((vm_offset_t)(va) >> SEGSHIFT)]); 224 else 225 return ((pd_entry_t)0); 226} 227 228/* 229 * Routine: pmap_pte 230 * Function: 231 * Extract the page table entry associated 232 * with the given map/virtual_address pair. 233 */ 234pt_entry_t * 235pmap_pte(pmap_t pmap, vm_offset_t va) 236{ 237 pt_entry_t *pdeaddr; 238 239 if (pmap) { 240 pdeaddr = (pt_entry_t *)pmap_segmap(pmap, va); 241 if (pdeaddr) { 242 return pdeaddr + vad_to_pte_offset(va); 243 } 244 } 245 return ((pt_entry_t *)0); 246} 247 248 249vm_offset_t 250pmap_steal_memory(vm_size_t size) 251{ 252 vm_size_t bank_size; 253 vm_offset_t pa, va; 254 255 size = round_page(size); 256 257 bank_size = phys_avail[1] - phys_avail[0]; 258 while (size > bank_size) { 259 int i; 260 261 for (i = 0; phys_avail[i + 2]; i += 2) { 262 phys_avail[i] = phys_avail[i + 2]; 263 phys_avail[i + 1] = phys_avail[i + 3]; 264 } 265 phys_avail[i] = 0; 266 phys_avail[i + 1] = 0; 267 if (!phys_avail[0]) 268 panic("pmap_steal_memory: out of memory"); 269 bank_size = phys_avail[1] - phys_avail[0]; 270 } 271 272 pa = phys_avail[0]; 273 phys_avail[0] += size; 274 if (pa >= MIPS_KSEG0_LARGEST_PHYS) { 275 panic("Out of memory below 512Meg?"); 276 } 277 va = MIPS_PHYS_TO_KSEG0(pa); 278 bzero((caddr_t)va, size); 279 return va; 280} 281 282/* 283 * Bootstrap the system enough to run with virtual memory. This 284 * assumes that the phys_avail array has been initialized. 285 */ 286void 287pmap_bootstrap(void) 288{ 289 pt_entry_t *pgtab; 290 pt_entry_t *pte; 291 int i, j; 292 int memory_larger_than_512meg = 0; 293 294 /* Sort. */ 295again: 296 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 297 /* 298 * Keep the memory aligned on page boundary. 299 */ 300 phys_avail[i] = round_page(phys_avail[i]); 301 phys_avail[i + 1] = trunc_page(phys_avail[i + 1]); 302 303 if (phys_avail[i + 1] >= MIPS_KSEG0_LARGEST_PHYS) 304 memory_larger_than_512meg++; 305 if (i < 2) 306 continue; 307 if (phys_avail[i - 2] > phys_avail[i]) { 308 vm_paddr_t ptemp[2]; 309 310 311 ptemp[0] = phys_avail[i + 0]; 312 ptemp[1] = phys_avail[i + 1]; 313 314 phys_avail[i + 0] = phys_avail[i - 2]; 315 phys_avail[i + 1] = phys_avail[i - 1]; 316 317 phys_avail[i - 2] = ptemp[0]; 318 phys_avail[i - 1] = ptemp[1]; 319 goto again; 320 } 321 } 322 323 /* 324 * Copy the phys_avail[] array before we start stealing memory from it. 325 */ 326 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 327 physmem_desc[i] = phys_avail[i]; 328 physmem_desc[i + 1] = phys_avail[i + 1]; 329 } 330 331 Maxmem = atop(phys_avail[i - 1]); 332 333 if (bootverbose) { 334 printf("Physical memory chunk(s):\n"); 335 for (i = 0; phys_avail[i + 1] != 0; i += 2) { 336 vm_paddr_t size; 337 338 size = phys_avail[i + 1] - phys_avail[i]; 339 printf("%#08jx - %#08jx, %ju bytes (%ju pages)\n", 340 (uintmax_t) phys_avail[i], 341 (uintmax_t) phys_avail[i + 1] - 1, 342 (uintmax_t) size, (uintmax_t) size / PAGE_SIZE); 343 } 344 printf("Maxmem is 0x%0lx\n", ptoa(Maxmem)); 345 } 346 /* 347 * Steal the message buffer from the beginning of memory. 348 */ 349 msgbufp = (struct msgbuf *)pmap_steal_memory(MSGBUF_SIZE); 350 msgbufinit(msgbufp, MSGBUF_SIZE); 351 352 /* 353 * Steal thread0 kstack. 354 */ 355 kstack0 = pmap_steal_memory(KSTACK_PAGES << PAGE_SHIFT); 356 357 358 virtual_avail = VM_MIN_KERNEL_ADDRESS + VM_KERNEL_ALLOC_OFFSET; 359 virtual_end = VM_MAX_KERNEL_ADDRESS; 360 361#ifdef SMP 362 /* 363 * Steal some virtual address space to map the pcpu area. 364 */ 365 virtual_avail = roundup2(virtual_avail, PAGE_SIZE * 2); 366 pcpup = (struct pcpu *)virtual_avail; 367 virtual_avail += PAGE_SIZE * 2; 368 369 /* 370 * Initialize the wired TLB entry mapping the pcpu region for 371 * the BSP at 'pcpup'. Up until this point we were operating 372 * with the 'pcpup' for the BSP pointing to a virtual address 373 * in KSEG0 so there was no need for a TLB mapping. 374 */ 375 mips_pcpu_tlb_init(PCPU_ADDR(0)); 376 377 if (bootverbose) 378 printf("pcpu is available at virtual address %p.\n", pcpup); 379#endif 380 381 /* 382 * Steal some virtual space that will not be in kernel_segmap. This 383 * va memory space will be used to map in kernel pages that are 384 * outside the 512Meg region. Note that we only do this steal when 385 * we do have memory in this region, that way for systems with 386 * smaller memory we don't "steal" any va ranges :-) 387 */ 388 if (memory_larger_than_512meg) { 389 for (i = 0; i < MAXCPU; i++) { 390 sysmap_lmem[i].CMAP1 = PTE_G; 391 sysmap_lmem[i].CMAP2 = PTE_G; 392 sysmap_lmem[i].CADDR1 = (caddr_t)virtual_avail; 393 virtual_avail += PAGE_SIZE; 394 sysmap_lmem[i].CADDR2 = (caddr_t)virtual_avail; 395 virtual_avail += PAGE_SIZE; 396 sysmap_lmem[i].valid1 = sysmap_lmem[i].valid2 = 0; 397 PMAP_LGMEM_LOCK_INIT(&sysmap_lmem[i]); 398 } 399 } 400 virtual_sys_start = (caddr_t)virtual_avail; 401 /* 402 * Allocate segment table for the kernel 403 */ 404 kernel_segmap = (pd_entry_t *)pmap_steal_memory(PAGE_SIZE); 405 406 /* 407 * Allocate second level page tables for the kernel 408 */ 409 nkpt = NKPT; 410 if (memory_larger_than_512meg) { 411 /* 412 * If we have a large memory system we CANNOT afford to hit 413 * pmap_growkernel() and allocate memory. Since we MAY end 414 * up with a page that is NOT mappable. For that reason we 415 * up front grab more. Normall NKPT is 120 (YMMV see pmap.h) 416 * this gives us 480meg of kernel virtual addresses at the 417 * cost of 120 pages (each page gets us 4 Meg). Since the 418 * kernel starts at virtual_avail, we can use this to 419 * calculate how many entris are left from there to the end 420 * of the segmap, we want to allocate all of it, which would 421 * be somewhere above 0xC0000000 - 0xFFFFFFFF which results 422 * in about 256 entries or so instead of the 120. 423 */ 424 nkpt = (PAGE_SIZE / sizeof(pd_entry_t)) - (virtual_avail >> SEGSHIFT); 425 } 426 pgtab = (pt_entry_t *)pmap_steal_memory(PAGE_SIZE * nkpt); 427 428 /* 429 * The R[4-7]?00 stores only one copy of the Global bit in the 430 * translation lookaside buffer for each 2 page entry. Thus invalid 431 * entrys must have the Global bit set so when Entry LO and Entry HI 432 * G bits are anded together they will produce a global bit to store 433 * in the tlb. 434 */ 435 for (i = 0, pte = pgtab; i < (nkpt * NPTEPG); i++, pte++) 436 *pte = PTE_G; 437 438 /* 439 * The segment table contains the KVA of the pages in the second 440 * level page table. 441 */ 442 for (i = 0, j = (virtual_avail >> SEGSHIFT); i < nkpt; i++, j++) 443 kernel_segmap[j] = (pd_entry_t)(pgtab + (i * NPTEPG)); 444 445 /* 446 * The kernel's pmap is statically allocated so we don't have to use 447 * pmap_create, which is unlikely to work correctly at this part of 448 * the boot sequence (XXX and which no longer exists). 449 */ 450 PMAP_LOCK_INIT(kernel_pmap); 451 kernel_pmap->pm_segtab = kernel_segmap; 452 kernel_pmap->pm_active = ~0; 453 TAILQ_INIT(&kernel_pmap->pm_pvlist); 454 kernel_pmap->pm_asid[0].asid = PMAP_ASID_RESERVED; 455 kernel_pmap->pm_asid[0].gen = 0; 456 pmap_max_asid = VMNUM_PIDS; 457 MachSetPID(0); 458} 459 460/* 461 * Initialize a vm_page's machine-dependent fields. 462 */ 463void 464pmap_page_init(vm_page_t m) 465{ 466 467 TAILQ_INIT(&m->md.pv_list); 468 m->md.pv_list_count = 0; 469 m->md.pv_flags = 0; 470} 471 472/* 473 * Initialize the pmap module. 474 * Called by vm_init, to initialize any structures that the pmap 475 * system needs to map virtual memory. 476 * pmap_init has been enhanced to support in a fairly consistant 477 * way, discontiguous physical memory. 478 */ 479void 480pmap_init(void) 481{ 482 483 if (need_wired_tlb_page_pool) 484 pmap_init_fpage(); 485 /* 486 * Initialize the address space (zone) for the pv entries. Set a 487 * high water mark so that the system can recover from excessive 488 * numbers of pv entries. 489 */ 490 pvzone = uma_zcreate("PV ENTRY", sizeof(struct pv_entry), NULL, NULL, 491 NULL, NULL, UMA_ALIGN_PTR, UMA_ZONE_VM | UMA_ZONE_NOFREE); 492 pv_entry_max = PMAP_SHPGPERPROC * maxproc + cnt.v_page_count; 493 pv_entry_high_water = 9 * (pv_entry_max / 10); 494 uma_zone_set_obj(pvzone, &pvzone_obj, pv_entry_max); 495} 496 497/*************************************************** 498 * Low level helper routines..... 499 ***************************************************/ 500 501#if defined(PMAP_DIAGNOSTIC) 502 503/* 504 * This code checks for non-writeable/modified pages. 505 * This should be an invalid condition. 506 */ 507static int 508pmap_nw_modified(pt_entry_t pte) 509{ 510 if ((pte & (PTE_M | PTE_RO)) == (PTE_M | PTE_RO)) 511 return (1); 512 else 513 return (0); 514} 515 516#endif 517 518static void 519pmap_invalidate_all(pmap_t pmap) 520{ 521#ifdef SMP 522 smp_rendezvous(0, pmap_invalidate_all_action, 0, (void *)pmap); 523} 524 525static void 526pmap_invalidate_all_action(void *arg) 527{ 528 pmap_t pmap = (pmap_t)arg; 529 530#endif 531 532 if (pmap->pm_active & PCPU_GET(cpumask)) { 533 pmap_TLB_invalidate_all(); 534 } else 535 pmap->pm_asid[PCPU_GET(cpuid)].gen = 0; 536} 537 538struct pmap_invalidate_page_arg { 539 pmap_t pmap; 540 vm_offset_t va; 541}; 542 543static __inline void 544pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 545{ 546#ifdef SMP 547 struct pmap_invalidate_page_arg arg; 548 549 arg.pmap = pmap; 550 arg.va = va; 551 552 smp_rendezvous(0, pmap_invalidate_page_action, 0, (void *)&arg); 553} 554 555static void 556pmap_invalidate_page_action(void *arg) 557{ 558 pmap_t pmap = ((struct pmap_invalidate_page_arg *)arg)->pmap; 559 vm_offset_t va = ((struct pmap_invalidate_page_arg *)arg)->va; 560 561#endif 562 563 if (is_kernel_pmap(pmap)) { 564 pmap_TLB_invalidate_kernel(va); 565 return; 566 } 567 if (pmap->pm_asid[PCPU_GET(cpuid)].gen != PCPU_GET(asid_generation)) 568 return; 569 else if (!(pmap->pm_active & PCPU_GET(cpumask))) { 570 pmap->pm_asid[PCPU_GET(cpuid)].gen = 0; 571 return; 572 } 573 va = pmap_va_asid(pmap, (va & ~PGOFSET)); 574 mips_TBIS(va); 575} 576 577static void 578pmap_TLB_invalidate_kernel(vm_offset_t va) 579{ 580 u_int32_t pid; 581 582 MachTLBGetPID(pid); 583 va = va | (pid << VMTLB_PID_SHIFT); 584 mips_TBIS(va); 585} 586 587struct pmap_update_page_arg { 588 pmap_t pmap; 589 vm_offset_t va; 590 pt_entry_t pte; 591}; 592 593void 594pmap_update_page(pmap_t pmap, vm_offset_t va, pt_entry_t pte) 595{ 596#ifdef SMP 597 struct pmap_update_page_arg arg; 598 599 arg.pmap = pmap; 600 arg.va = va; 601 arg.pte = pte; 602 603 smp_rendezvous(0, pmap_update_page_action, 0, (void *)&arg); 604} 605 606static void 607pmap_update_page_action(void *arg) 608{ 609 pmap_t pmap = ((struct pmap_update_page_arg *)arg)->pmap; 610 vm_offset_t va = ((struct pmap_update_page_arg *)arg)->va; 611 pt_entry_t pte = ((struct pmap_update_page_arg *)arg)->pte; 612 613#endif 614 if (is_kernel_pmap(pmap)) { 615 pmap_TLB_update_kernel(va, pte); 616 return; 617 } 618 if (pmap->pm_asid[PCPU_GET(cpuid)].gen != PCPU_GET(asid_generation)) 619 return; 620 else if (!(pmap->pm_active & PCPU_GET(cpumask))) { 621 pmap->pm_asid[PCPU_GET(cpuid)].gen = 0; 622 return; 623 } 624 va = pmap_va_asid(pmap, va); 625 MachTLBUpdate(va, pte); 626} 627 628static void 629pmap_TLB_update_kernel(vm_offset_t va, pt_entry_t pte) 630{ 631 u_int32_t pid; 632 633 MachTLBGetPID(pid); 634 va = va | (pid << VMTLB_PID_SHIFT); 635 636 MachTLBUpdate(va, pte); 637} 638 639/* 640 * Routine: pmap_extract 641 * Function: 642 * Extract the physical page address associated 643 * with the given map/virtual_address pair. 644 */ 645vm_paddr_t 646pmap_extract(pmap_t pmap, vm_offset_t va) 647{ 648 pt_entry_t *pte; 649 vm_offset_t retval = 0; 650 651 PMAP_LOCK(pmap); 652 pte = pmap_pte(pmap, va); 653 if (pte) { 654 retval = mips_tlbpfn_to_paddr(*pte) | (va & PAGE_MASK); 655 } 656 PMAP_UNLOCK(pmap); 657 return retval; 658} 659 660/* 661 * Routine: pmap_extract_and_hold 662 * Function: 663 * Atomically extract and hold the physical page 664 * with the given pmap and virtual address pair 665 * if that mapping permits the given protection. 666 */ 667vm_page_t 668pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 669{ 670 pt_entry_t pte; 671 vm_page_t m; 672 673 m = NULL; 674 vm_page_lock_queues(); 675 PMAP_LOCK(pmap); 676 677 pte = *pmap_pte(pmap, va); 678 if (pte != 0 && pmap_pte_v(&pte) && 679 ((pte & PTE_RW) || (prot & VM_PROT_WRITE) == 0)) { 680 m = PHYS_TO_VM_PAGE(mips_tlbpfn_to_paddr(pte)); 681 vm_page_hold(m); 682 } 683 vm_page_unlock_queues(); 684 PMAP_UNLOCK(pmap); 685 return (m); 686} 687 688/*************************************************** 689 * Low level mapping routines..... 690 ***************************************************/ 691 692/* 693 * add a wired page to the kva 694 */ 695 /* PMAP_INLINE */ void 696pmap_kenter(vm_offset_t va, vm_paddr_t pa) 697{ 698 register pt_entry_t *pte; 699 pt_entry_t npte, opte; 700 701#ifdef PMAP_DEBUG 702 printf("pmap_kenter: va: 0x%08x -> pa: 0x%08x\n", va, pa); 703#endif 704 npte = mips_paddr_to_tlbpfn(pa) | PTE_RW | PTE_V | PTE_G | PTE_W; 705 706 if (is_cacheable_mem(pa)) 707 npte |= PTE_CACHE; 708 else 709 npte |= PTE_UNCACHED; 710 711 pte = pmap_pte(kernel_pmap, va); 712 opte = *pte; 713 *pte = npte; 714 715 pmap_update_page(kernel_pmap, va, npte); 716} 717 718/* 719 * remove a page from the kernel pagetables 720 */ 721 /* PMAP_INLINE */ void 722pmap_kremove(vm_offset_t va) 723{ 724 register pt_entry_t *pte; 725 726 /* 727 * Write back all caches from the page being destroyed 728 */ 729 mips_dcache_wbinv_range_index(va, NBPG); 730 731 pte = pmap_pte(kernel_pmap, va); 732 *pte = PTE_G; 733 pmap_invalidate_page(kernel_pmap, va); 734} 735 736/* 737 * Used to map a range of physical addresses into kernel 738 * virtual address space. 739 * 740 * The value passed in '*virt' is a suggested virtual address for 741 * the mapping. Architectures which can support a direct-mapped 742 * physical to virtual region can return the appropriate address 743 * within that region, leaving '*virt' unchanged. Other 744 * architectures should map the pages starting at '*virt' and 745 * update '*virt' with the first usable address after the mapped 746 * region. 747 */ 748vm_offset_t 749pmap_map(vm_offset_t *virt, vm_offset_t start, vm_offset_t end, int prot) 750{ 751 vm_offset_t va, sva; 752 753 va = sva = *virt; 754 while (start < end) { 755 pmap_kenter(va, start); 756 va += PAGE_SIZE; 757 start += PAGE_SIZE; 758 } 759 *virt = va; 760 return (sva); 761} 762 763/* 764 * Add a list of wired pages to the kva 765 * this routine is only used for temporary 766 * kernel mappings that do not need to have 767 * page modification or references recorded. 768 * Note that old mappings are simply written 769 * over. The page *must* be wired. 770 */ 771void 772pmap_qenter(vm_offset_t va, vm_page_t *m, int count) 773{ 774 int i; 775 vm_offset_t origva = va; 776 777 for (i = 0; i < count; i++) { 778 pmap_flush_pvcache(m[i]); 779 pmap_kenter(va, VM_PAGE_TO_PHYS(m[i])); 780 va += PAGE_SIZE; 781 } 782 783 mips_dcache_wbinv_range_index(origva, PAGE_SIZE*count); 784} 785 786/* 787 * this routine jerks page mappings from the 788 * kernel -- it is meant only for temporary mappings. 789 */ 790void 791pmap_qremove(vm_offset_t va, int count) 792{ 793 /* 794 * No need to wb/inv caches here, 795 * pmap_kremove will do it for us 796 */ 797 798 while (count-- > 0) { 799 pmap_kremove(va); 800 va += PAGE_SIZE; 801 } 802} 803 804/*************************************************** 805 * Page table page management routines..... 806 ***************************************************/ 807 808/* 809 * floating pages (FPAGES) management routines 810 * 811 * FPAGES are the reserved virtual memory areas which can be 812 * mapped to any physical memory. This gets used typically 813 * in the following functions: 814 * 815 * pmap_zero_page 816 * pmap_copy_page 817 */ 818 819/* 820 * Create the floating pages, aka FPAGES! 821 */ 822static void 823pmap_init_fpage() 824{ 825 vm_offset_t kva; 826 int i, j; 827 struct sysmaps *sysmaps; 828 829 /* 830 * We allocate a total of (FPAGES*MAXCPU + FPAGES_SHARED + 1) pages 831 * at first. FPAGES & FPAGES_SHARED should be EVEN Then we'll adjust 832 * 'kva' to be even-page aligned so that the fpage area can be wired 833 * in the TLB with a single TLB entry. 834 */ 835 kva = kmem_alloc_nofault(kernel_map, 836 (FPAGES * MAXCPU + 1 + FPAGES_SHARED) * PAGE_SIZE); 837 if ((void *)kva == NULL) 838 panic("pmap_init_fpage: fpage allocation failed"); 839 840 /* 841 * Make up start at an even page number so we can wire down the 842 * fpage area in the tlb with a single tlb entry. 843 */ 844 if ((((vm_offset_t)kva) >> PGSHIFT) & 1) { 845 /* 846 * 'kva' is not even-page aligned. Adjust it and free the 847 * first page which is unused. 848 */ 849 kmem_free(kernel_map, (vm_offset_t)kva, NBPG); 850 kva = ((vm_offset_t)kva) + NBPG; 851 } else { 852 /* 853 * 'kva' is even page aligned. We don't need the last page, 854 * free it. 855 */ 856 kmem_free(kernel_map, ((vm_offset_t)kva) + FSPACE, NBPG); 857 } 858 859 for (i = 0; i < MAXCPU; i++) { 860 sysmaps = &sysmaps_pcpu[i]; 861 mtx_init(&sysmaps->lock, "SYSMAPS", NULL, MTX_DEF); 862 863 /* Assign FPAGES pages to the CPU */ 864 for (j = 0; j < FPAGES; j++) 865 sysmaps->fp[j].kva = kva + (j) * PAGE_SIZE; 866 kva = ((vm_offset_t)kva) + (FPAGES * PAGE_SIZE); 867 } 868 869 /* 870 * An additional 2 pages are needed, one for pmap_zero_page_idle() 871 * and one for coredump. These pages are shared by all cpu's 872 */ 873 fpages_shared[PMAP_FPAGE3].kva = kva; 874 fpages_shared[PMAP_FPAGE_KENTER_TEMP].kva = kva + PAGE_SIZE; 875} 876 877/* 878 * Map the page to the fpage virtual address as specified thru' fpage id 879 */ 880vm_offset_t 881pmap_map_fpage(vm_paddr_t pa, struct fpage *fp, boolean_t check_unmaped) 882{ 883 vm_offset_t kva; 884 register pt_entry_t *pte; 885 pt_entry_t npte; 886 887 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 888 /* 889 * Check if the fpage is free 890 */ 891 if (fp->state) { 892 if (check_unmaped == TRUE) 893 pmap_unmap_fpage(pa, fp); 894 else 895 panic("pmap_map_fpage: fpage is busy"); 896 } 897 fp->state = TRUE; 898 kva = fp->kva; 899 900 npte = mips_paddr_to_tlbpfn(pa) | PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; 901 pte = pmap_pte(kernel_pmap, kva); 902 *pte = npte; 903 904 pmap_TLB_update_kernel(kva, npte); 905 906 return (kva); 907} 908 909/* 910 * Unmap the page from the fpage virtual address as specified thru' fpage id 911 */ 912void 913pmap_unmap_fpage(vm_paddr_t pa, struct fpage *fp) 914{ 915 vm_offset_t kva; 916 register pt_entry_t *pte; 917 918 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 919 /* 920 * Check if the fpage is busy 921 */ 922 if (!(fp->state)) { 923 panic("pmap_unmap_fpage: fpage is free"); 924 } 925 kva = fp->kva; 926 927 pte = pmap_pte(kernel_pmap, kva); 928 *pte = PTE_G; 929 pmap_TLB_invalidate_kernel(kva); 930 931 fp->state = FALSE; 932 933 /* 934 * Should there be any flush operation at the end? 935 */ 936} 937 938/* Revision 1.507 939 * 940 * Simplify the reference counting of page table pages. Specifically, use 941 * the page table page's wired count rather than its hold count to contain 942 * the reference count. 943 */ 944 945/* 946 * This routine unholds page table pages, and if the hold count 947 * drops to zero, then it decrements the wire count. 948 */ 949static int 950_pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m) 951{ 952 vm_offset_t pteva; 953 954 /* 955 * unmap the page table page 956 */ 957 pteva = (vm_offset_t)pmap->pm_segtab[m->pindex]; 958 if (pteva >= VM_MIN_KERNEL_ADDRESS) { 959 pmap_kremove(pteva); 960 kmem_free(kernel_map, pteva, PAGE_SIZE); 961 } else { 962 KASSERT(MIPS_IS_KSEG0_ADDR(pteva), 963 ("_pmap_unwire_pte_hold: 0x%0lx is not in kseg0", 964 (long)pteva)); 965 } 966 967 pmap->pm_segtab[m->pindex] = 0; 968 --pmap->pm_stats.resident_count; 969 970 if (pmap->pm_ptphint == m) 971 pmap->pm_ptphint = NULL; 972 973 /* 974 * If the page is finally unwired, simply free it. 975 */ 976 vm_page_free_zero(m); 977 atomic_subtract_int(&cnt.v_wire_count, 1); 978 return (1); 979} 980 981static PMAP_INLINE int 982pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m) 983{ 984 --m->wire_count; 985 if (m->wire_count == 0) 986 return (_pmap_unwire_pte_hold(pmap, m)); 987 else 988 return (0); 989} 990 991/* 992 * After removing a page table entry, this routine is used to 993 * conditionally free the page, and manage the hold/wire counts. 994 */ 995static int 996pmap_unuse_pt(pmap_t pmap, vm_offset_t va, vm_page_t mpte) 997{ 998 unsigned ptepindex; 999 pd_entry_t pteva; 1000 1001 if (va >= VM_MAXUSER_ADDRESS) 1002 return (0); 1003 1004 if (mpte == NULL) { 1005 ptepindex = (va >> SEGSHIFT); 1006 if (pmap->pm_ptphint && 1007 (pmap->pm_ptphint->pindex == ptepindex)) { 1008 mpte = pmap->pm_ptphint; 1009 } else { 1010 pteva = *pmap_pde(pmap, va); 1011 mpte = PHYS_TO_VM_PAGE(vtophys(pteva)); 1012 pmap->pm_ptphint = mpte; 1013 } 1014 } 1015 return pmap_unwire_pte_hold(pmap, mpte); 1016} 1017 1018void 1019pmap_pinit0(pmap_t pmap) 1020{ 1021 int i; 1022 1023 PMAP_LOCK_INIT(pmap); 1024 pmap->pm_segtab = kernel_segmap; 1025 pmap->pm_active = 0; 1026 pmap->pm_ptphint = NULL; 1027 for (i = 0; i < MAXCPU; i++) { 1028 pmap->pm_asid[i].asid = PMAP_ASID_RESERVED; 1029 pmap->pm_asid[i].gen = 0; 1030 } 1031 PCPU_SET(curpmap, pmap); 1032 TAILQ_INIT(&pmap->pm_pvlist); 1033 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1034} 1035 1036/* 1037 * Initialize a preallocated and zeroed pmap structure, 1038 * such as one in a vmspace structure. 1039 */ 1040int 1041pmap_pinit(pmap_t pmap) 1042{ 1043 vm_offset_t ptdva; 1044 vm_paddr_t ptdpa; 1045 vm_page_t ptdpg; 1046 int i; 1047 int req; 1048 1049 PMAP_LOCK_INIT(pmap); 1050 1051 req = VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL | VM_ALLOC_WIRED | 1052 VM_ALLOC_ZERO; 1053 1054#ifdef VM_ALLOC_WIRED_TLB_PG_POOL 1055 if (need_wired_tlb_page_pool) 1056 req |= VM_ALLOC_WIRED_TLB_PG_POOL; 1057#endif 1058 /* 1059 * allocate the page directory page 1060 */ 1061 while ((ptdpg = vm_page_alloc(NULL, NUSERPGTBLS, req)) == NULL) 1062 VM_WAIT; 1063 1064 ptdpg->valid = VM_PAGE_BITS_ALL; 1065 1066 ptdpa = VM_PAGE_TO_PHYS(ptdpg); 1067 if (ptdpa < MIPS_KSEG0_LARGEST_PHYS) { 1068 ptdva = MIPS_PHYS_TO_KSEG0(ptdpa); 1069 } else { 1070 ptdva = kmem_alloc_nofault(kernel_map, PAGE_SIZE); 1071 if (ptdva == 0) 1072 panic("pmap_pinit: unable to allocate kva"); 1073 pmap_kenter(ptdva, ptdpa); 1074 } 1075 1076 pmap->pm_segtab = (pd_entry_t *)ptdva; 1077 if ((ptdpg->flags & PG_ZERO) == 0) 1078 bzero(pmap->pm_segtab, PAGE_SIZE); 1079 1080 pmap->pm_active = 0; 1081 pmap->pm_ptphint = NULL; 1082 for (i = 0; i < MAXCPU; i++) { 1083 pmap->pm_asid[i].asid = PMAP_ASID_RESERVED; 1084 pmap->pm_asid[i].gen = 0; 1085 } 1086 TAILQ_INIT(&pmap->pm_pvlist); 1087 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1088 1089 return (1); 1090} 1091 1092/* 1093 * this routine is called if the page table page is not 1094 * mapped correctly. 1095 */ 1096static vm_page_t 1097_pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags) 1098{ 1099 vm_offset_t pteva, ptepa; 1100 vm_page_t m; 1101 int req; 1102 1103 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1104 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1105 ("_pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1106 1107 req = VM_ALLOC_WIRED | VM_ALLOC_ZERO | VM_ALLOC_NOOBJ; 1108#ifdef VM_ALLOC_WIRED_TLB_PG_POOL 1109 if (need_wired_tlb_page_pool) 1110 req |= VM_ALLOC_WIRED_TLB_PG_POOL; 1111#endif 1112 /* 1113 * Find or fabricate a new pagetable page 1114 */ 1115 if ((m = vm_page_alloc(NULL, ptepindex, req)) == NULL) { 1116 if (flags & M_WAITOK) { 1117 PMAP_UNLOCK(pmap); 1118 vm_page_unlock_queues(); 1119 VM_WAIT; 1120 vm_page_lock_queues(); 1121 PMAP_LOCK(pmap); 1122 } 1123 /* 1124 * Indicate the need to retry. While waiting, the page 1125 * table page may have been allocated. 1126 */ 1127 return (NULL); 1128 } 1129 if ((m->flags & PG_ZERO) == 0) 1130 pmap_zero_page(m); 1131 1132 KASSERT(m->queue == PQ_NONE, 1133 ("_pmap_allocpte: %p->queue != PQ_NONE", m)); 1134 1135 /* 1136 * Map the pagetable page into the process address space, if it 1137 * isn't already there. 1138 */ 1139 1140 pmap->pm_stats.resident_count++; 1141 1142 ptepa = VM_PAGE_TO_PHYS(m); 1143 if (ptepa < MIPS_KSEG0_LARGEST_PHYS) { 1144 pteva = MIPS_PHYS_TO_KSEG0(ptepa); 1145 } else { 1146 pteva = kmem_alloc_nofault(kernel_map, PAGE_SIZE); 1147 if (pteva == 0) 1148 panic("_pmap_allocpte: unable to allocate kva"); 1149 pmap_kenter(pteva, ptepa); 1150 } 1151 1152 pmap->pm_segtab[ptepindex] = (pd_entry_t)pteva; 1153 1154 /* 1155 * Set the page table hint 1156 */ 1157 pmap->pm_ptphint = m; 1158 1159 /* 1160 * Kernel page tables are allocated in pmap_bootstrap() or 1161 * pmap_growkernel(). 1162 */ 1163 if (is_kernel_pmap(pmap)) 1164 panic("_pmap_allocpte() called for kernel pmap\n"); 1165 1166 m->valid = VM_PAGE_BITS_ALL; 1167 vm_page_flag_clear(m, PG_ZERO); 1168 1169 return (m); 1170} 1171 1172static vm_page_t 1173pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags) 1174{ 1175 unsigned ptepindex; 1176 vm_offset_t pteva; 1177 vm_page_t m; 1178 1179 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1180 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1181 ("pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1182 1183 /* 1184 * Calculate pagetable page index 1185 */ 1186 ptepindex = va >> SEGSHIFT; 1187retry: 1188 /* 1189 * Get the page directory entry 1190 */ 1191 pteva = (vm_offset_t)pmap->pm_segtab[ptepindex]; 1192 1193 /* 1194 * If the page table page is mapped, we just increment the hold 1195 * count, and activate it. 1196 */ 1197 if (pteva) { 1198 /* 1199 * In order to get the page table page, try the hint first. 1200 */ 1201 if (pmap->pm_ptphint && 1202 (pmap->pm_ptphint->pindex == ptepindex)) { 1203 m = pmap->pm_ptphint; 1204 } else { 1205 m = PHYS_TO_VM_PAGE(vtophys(pteva)); 1206 pmap->pm_ptphint = m; 1207 } 1208 m->wire_count++; 1209 } else { 1210 /* 1211 * Here if the pte page isn't mapped, or if it has been 1212 * deallocated. 1213 */ 1214 m = _pmap_allocpte(pmap, ptepindex, flags); 1215 if (m == NULL && (flags & M_WAITOK)) 1216 goto retry; 1217 } 1218 return m; 1219} 1220 1221 1222/*************************************************** 1223* Pmap allocation/deallocation routines. 1224 ***************************************************/ 1225/* 1226 * Revision 1.397 1227 * - Merged pmap_release and pmap_release_free_page. When pmap_release is 1228 * called only the page directory page(s) can be left in the pmap pte 1229 * object, since all page table pages will have been freed by 1230 * pmap_remove_pages and pmap_remove. In addition, there can only be one 1231 * reference to the pmap and the page directory is wired, so the page(s) 1232 * can never be busy. So all there is to do is clear the magic mappings 1233 * from the page directory and free the page(s). 1234 */ 1235 1236 1237/* 1238 * Release any resources held by the given physical map. 1239 * Called when a pmap initialized by pmap_pinit is being released. 1240 * Should only be called if the map contains no valid mappings. 1241 */ 1242void 1243pmap_release(pmap_t pmap) 1244{ 1245 vm_offset_t ptdva; 1246 vm_page_t ptdpg; 1247 1248 KASSERT(pmap->pm_stats.resident_count == 0, 1249 ("pmap_release: pmap resident count %ld != 0", 1250 pmap->pm_stats.resident_count)); 1251 1252 ptdva = (vm_offset_t)pmap->pm_segtab; 1253 ptdpg = PHYS_TO_VM_PAGE(vtophys(ptdva)); 1254 1255 if (ptdva >= VM_MIN_KERNEL_ADDRESS) { 1256 pmap_kremove(ptdva); 1257 kmem_free(kernel_map, ptdva, PAGE_SIZE); 1258 } else { 1259 KASSERT(MIPS_IS_KSEG0_ADDR(ptdva), 1260 ("pmap_release: 0x%0lx is not in kseg0", (long)ptdva)); 1261 } 1262 1263 ptdpg->wire_count--; 1264 atomic_subtract_int(&cnt.v_wire_count, 1); 1265 vm_page_free_zero(ptdpg); 1266} 1267 1268/* 1269 * grow the number of kernel page table entries, if needed 1270 */ 1271void 1272pmap_growkernel(vm_offset_t addr) 1273{ 1274 vm_offset_t ptppaddr; 1275 vm_page_t nkpg; 1276 pt_entry_t *pte; 1277 int i, req; 1278 1279 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 1280 if (kernel_vm_end == 0) { 1281 kernel_vm_end = VM_MIN_KERNEL_ADDRESS + VM_KERNEL_ALLOC_OFFSET; 1282 nkpt = 0; 1283 while (segtab_pde(kernel_segmap, kernel_vm_end)) { 1284 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & 1285 ~(PAGE_SIZE * NPTEPG - 1); 1286 nkpt++; 1287 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1288 kernel_vm_end = kernel_map->max_offset; 1289 break; 1290 } 1291 } 1292 } 1293 addr = (addr + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1); 1294 if (addr - 1 >= kernel_map->max_offset) 1295 addr = kernel_map->max_offset; 1296 while (kernel_vm_end < addr) { 1297 if (segtab_pde(kernel_segmap, kernel_vm_end)) { 1298 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & 1299 ~(PAGE_SIZE * NPTEPG - 1); 1300 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1301 kernel_vm_end = kernel_map->max_offset; 1302 break; 1303 } 1304 continue; 1305 } 1306 /* 1307 * This index is bogus, but out of the way 1308 */ 1309 req = VM_ALLOC_INTERRUPT | VM_ALLOC_WIRED | VM_ALLOC_NOOBJ; 1310#ifdef VM_ALLOC_WIRED_TLB_PG_POOL 1311 if (need_wired_tlb_page_pool) 1312 req |= VM_ALLOC_WIRED_TLB_PG_POOL; 1313#endif 1314 nkpg = vm_page_alloc(NULL, nkpt, req); 1315 if (!nkpg) 1316 panic("pmap_growkernel: no memory to grow kernel"); 1317 1318 nkpt++; 1319 1320 ptppaddr = VM_PAGE_TO_PHYS(nkpg); 1321 if (ptppaddr >= MIPS_KSEG0_LARGEST_PHYS) { 1322 /* 1323 * We need to do something here, but I am not sure 1324 * what. We can access anything in the 0 - 512Meg 1325 * region, but if we get a page to go in the kernel 1326 * segmap that is outside of of that we really need 1327 * to have another mapping beyond the temporary ones 1328 * I have. Not sure how to do this yet. FIXME FIXME. 1329 */ 1330 panic("Gak, can't handle a k-page table outside of lower 512Meg"); 1331 } 1332 pte = (pt_entry_t *)MIPS_PHYS_TO_KSEG0(ptppaddr); 1333 segtab_pde(kernel_segmap, kernel_vm_end) = (pd_entry_t)pte; 1334 1335 /* 1336 * The R[4-7]?00 stores only one copy of the Global bit in 1337 * the translation lookaside buffer for each 2 page entry. 1338 * Thus invalid entrys must have the Global bit set so when 1339 * Entry LO and Entry HI G bits are anded together they will 1340 * produce a global bit to store in the tlb. 1341 */ 1342 for (i = 0; i < NPTEPG; i++, pte++) 1343 *pte = PTE_G; 1344 1345 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & 1346 ~(PAGE_SIZE * NPTEPG - 1); 1347 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 1348 kernel_vm_end = kernel_map->max_offset; 1349 break; 1350 } 1351 } 1352} 1353 1354/*************************************************** 1355* page management routines. 1356 ***************************************************/ 1357 1358/* 1359 * free the pv_entry back to the free list 1360 */ 1361static PMAP_INLINE void 1362free_pv_entry(pv_entry_t pv) 1363{ 1364 1365 pv_entry_count--; 1366 uma_zfree(pvzone, pv); 1367} 1368 1369/* 1370 * get a new pv_entry, allocating a block from the system 1371 * when needed. 1372 * the memory allocation is performed bypassing the malloc code 1373 * because of the possibility of allocations at interrupt time. 1374 */ 1375static pv_entry_t 1376get_pv_entry(pmap_t locked_pmap) 1377{ 1378 static const struct timeval printinterval = { 60, 0 }; 1379 static struct timeval lastprint; 1380 struct vpgqueues *vpq; 1381 pt_entry_t *pte, oldpte; 1382 pmap_t pmap; 1383 pv_entry_t allocated_pv, next_pv, pv; 1384 vm_offset_t va; 1385 vm_page_t m; 1386 1387 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED); 1388 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1389 allocated_pv = uma_zalloc(pvzone, M_NOWAIT); 1390 if (allocated_pv != NULL) { 1391 pv_entry_count++; 1392 if (pv_entry_count > pv_entry_high_water) 1393 pagedaemon_wakeup(); 1394 else 1395 return (allocated_pv); 1396 } 1397 /* 1398 * Reclaim pv entries: At first, destroy mappings to inactive 1399 * pages. After that, if a pv entry is still needed, destroy 1400 * mappings to active pages. 1401 */ 1402 if (ratecheck(&lastprint, &printinterval)) 1403 printf("Approaching the limit on PV entries, " 1404 "increase the vm.pmap.shpgperproc tunable.\n"); 1405 vpq = &vm_page_queues[PQ_INACTIVE]; 1406retry: 1407 TAILQ_FOREACH(m, &vpq->pl, pageq) { 1408 if (m->hold_count || m->busy) 1409 continue; 1410 TAILQ_FOREACH_SAFE(pv, &m->md.pv_list, pv_list, next_pv) { 1411 va = pv->pv_va; 1412 pmap = pv->pv_pmap; 1413 /* Avoid deadlock and lock recursion. */ 1414 if (pmap > locked_pmap) 1415 PMAP_LOCK(pmap); 1416 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) 1417 continue; 1418 pmap->pm_stats.resident_count--; 1419 pte = pmap_pte(pmap, va); 1420 KASSERT(pte != NULL, ("pte")); 1421 oldpte = loadandclear((u_int *)pte); 1422 if (is_kernel_pmap(pmap)) 1423 *pte = PTE_G; 1424 KASSERT((oldpte & PTE_W) == 0, 1425 ("wired pte for unwired page")); 1426 if (m->md.pv_flags & PV_TABLE_REF) 1427 vm_page_flag_set(m, PG_REFERENCED); 1428 if (oldpte & PTE_M) 1429 vm_page_dirty(m); 1430 pmap_invalidate_page(pmap, va); 1431 TAILQ_REMOVE(&pmap->pm_pvlist, pv, pv_plist); 1432 m->md.pv_list_count--; 1433 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 1434 if (TAILQ_EMPTY(&m->md.pv_list)) { 1435 vm_page_flag_clear(m, PG_WRITEABLE); 1436 m->md.pv_flags &= ~(PV_TABLE_REF | PV_TABLE_MOD); 1437 } 1438 pmap_unuse_pt(pmap, va, pv->pv_ptem); 1439 if (pmap != locked_pmap) 1440 PMAP_UNLOCK(pmap); 1441 if (allocated_pv == NULL) 1442 allocated_pv = pv; 1443 else 1444 free_pv_entry(pv); 1445 } 1446 } 1447 if (allocated_pv == NULL) { 1448 if (vpq == &vm_page_queues[PQ_INACTIVE]) { 1449 vpq = &vm_page_queues[PQ_ACTIVE]; 1450 goto retry; 1451 } 1452 panic("get_pv_entry: increase the vm.pmap.shpgperproc tunable"); 1453 } 1454 return (allocated_pv); 1455} 1456 1457/* 1458 * Revision 1.370 1459 * 1460 * Move pmap_collect() out of the machine-dependent code, rename it 1461 * to reflect its new location, and add page queue and flag locking. 1462 * 1463 * Notes: (1) alpha, i386, and ia64 had identical implementations 1464 * of pmap_collect() in terms of machine-independent interfaces; 1465 * (2) sparc64 doesn't require it; (3) powerpc had it as a TODO. 1466 * 1467 * MIPS implementation was identical to alpha [Junos 8.2] 1468 */ 1469 1470/* 1471 * If it is the first entry on the list, it is actually 1472 * in the header and we must copy the following entry up 1473 * to the header. Otherwise we must search the list for 1474 * the entry. In either case we free the now unused entry. 1475 */ 1476 1477static void 1478pmap_remove_entry(struct pmap *pmap, vm_page_t m, vm_offset_t va) 1479{ 1480 pv_entry_t pv; 1481 1482 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1483 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1484 if (m->md.pv_list_count < pmap->pm_stats.resident_count) { 1485 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 1486 if (pmap == pv->pv_pmap && va == pv->pv_va) 1487 break; 1488 } 1489 } else { 1490 TAILQ_FOREACH(pv, &pmap->pm_pvlist, pv_plist) { 1491 if (va == pv->pv_va) 1492 break; 1493 } 1494 } 1495 1496 KASSERT(pv != NULL, ("pmap_remove_entry: pv not found")); 1497 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 1498 m->md.pv_list_count--; 1499 if (TAILQ_FIRST(&m->md.pv_list) == NULL) 1500 vm_page_flag_clear(m, PG_WRITEABLE); 1501 1502 TAILQ_REMOVE(&pmap->pm_pvlist, pv, pv_plist); 1503 free_pv_entry(pv); 1504} 1505 1506/* 1507 * Create a pv entry for page at pa for 1508 * (pmap, va). 1509 */ 1510static void 1511pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t mpte, vm_page_t m, 1512 boolean_t wired) 1513{ 1514 pv_entry_t pv; 1515 1516 pv = get_pv_entry(pmap); 1517 pv->pv_va = va; 1518 pv->pv_pmap = pmap; 1519 pv->pv_ptem = mpte; 1520 pv->pv_wired = wired; 1521 1522 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1523 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1524 TAILQ_INSERT_TAIL(&pmap->pm_pvlist, pv, pv_plist); 1525 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 1526 m->md.pv_list_count++; 1527} 1528 1529/* 1530 * Conditionally create a pv entry. 1531 */ 1532static boolean_t 1533pmap_try_insert_pv_entry(pmap_t pmap, vm_page_t mpte, vm_offset_t va, 1534 vm_page_t m) 1535{ 1536 pv_entry_t pv; 1537 1538 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1539 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1540 if (pv_entry_count < pv_entry_high_water && 1541 (pv = uma_zalloc(pvzone, M_NOWAIT)) != NULL) { 1542 pv_entry_count++; 1543 pv->pv_va = va; 1544 pv->pv_pmap = pmap; 1545 pv->pv_ptem = mpte; 1546 pv->pv_wired = FALSE; 1547 TAILQ_INSERT_TAIL(&pmap->pm_pvlist, pv, pv_plist); 1548 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list); 1549 m->md.pv_list_count++; 1550 return (TRUE); 1551 } else 1552 return (FALSE); 1553} 1554 1555/* 1556 * pmap_remove_pte: do the things to unmap a page in a process 1557 */ 1558static int 1559pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va) 1560{ 1561 pt_entry_t oldpte; 1562 vm_page_t m; 1563 vm_offset_t pa; 1564 1565 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1566 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1567 1568 oldpte = loadandclear((u_int *)ptq); 1569 if (is_kernel_pmap(pmap)) 1570 *ptq = PTE_G; 1571 1572 if (oldpte & PTE_W) 1573 pmap->pm_stats.wired_count -= 1; 1574 1575 pmap->pm_stats.resident_count -= 1; 1576 pa = mips_tlbpfn_to_paddr(oldpte); 1577 1578 if (page_is_managed(pa)) { 1579 m = PHYS_TO_VM_PAGE(pa); 1580 if (oldpte & PTE_M) { 1581#if defined(PMAP_DIAGNOSTIC) 1582 if (pmap_nw_modified(oldpte)) { 1583 printf( 1584 "pmap_remove: modified page not writable: va: 0x%x, pte: 0x%x\n", 1585 va, oldpte); 1586 } 1587#endif 1588 vm_page_dirty(m); 1589 } 1590 if (m->md.pv_flags & PV_TABLE_REF) 1591 vm_page_flag_set(m, PG_REFERENCED); 1592 m->md.pv_flags &= ~(PV_TABLE_REF | PV_TABLE_MOD); 1593 1594 pmap_remove_entry(pmap, m, va); 1595 } 1596 return pmap_unuse_pt(pmap, va, NULL); 1597} 1598 1599/* 1600 * Remove a single page from a process address space 1601 */ 1602static void 1603pmap_remove_page(struct pmap *pmap, vm_offset_t va) 1604{ 1605 register pt_entry_t *ptq; 1606 1607 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1608 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1609 ptq = pmap_pte(pmap, va); 1610 1611 /* 1612 * if there is no pte for this address, just skip it!!! 1613 */ 1614 if (!ptq || !pmap_pte_v(ptq)) { 1615 return; 1616 } 1617 1618 /* 1619 * Write back all caches from the page being destroyed 1620 */ 1621 mips_dcache_wbinv_range_index(va, NBPG); 1622 1623 /* 1624 * get a local va for mappings for this pmap. 1625 */ 1626 (void)pmap_remove_pte(pmap, ptq, va); 1627 pmap_invalidate_page(pmap, va); 1628 1629 return; 1630} 1631 1632/* 1633 * Remove the given range of addresses from the specified map. 1634 * 1635 * It is assumed that the start and end are properly 1636 * rounded to the page size. 1637 */ 1638void 1639pmap_remove(struct pmap *pmap, vm_offset_t sva, vm_offset_t eva) 1640{ 1641 vm_offset_t va, nva; 1642 1643 if (pmap == NULL) 1644 return; 1645 1646 if (pmap->pm_stats.resident_count == 0) 1647 return; 1648 1649 vm_page_lock_queues(); 1650 PMAP_LOCK(pmap); 1651 1652 /* 1653 * special handling of removing one page. a very common operation 1654 * and easy to short circuit some code. 1655 */ 1656 if ((sva + PAGE_SIZE) == eva) { 1657 pmap_remove_page(pmap, sva); 1658 goto out; 1659 } 1660 for (va = sva; va < eva; va = nva) { 1661 if (!*pmap_pde(pmap, va)) { 1662 nva = mips_segtrunc(va + MIPS_SEGSIZE); 1663 continue; 1664 } 1665 pmap_remove_page(pmap, va); 1666 nva = va + PAGE_SIZE; 1667 } 1668 1669out: 1670 vm_page_unlock_queues(); 1671 PMAP_UNLOCK(pmap); 1672} 1673 1674/* 1675 * Routine: pmap_remove_all 1676 * Function: 1677 * Removes this physical page from 1678 * all physical maps in which it resides. 1679 * Reflects back modify bits to the pager. 1680 * 1681 * Notes: 1682 * Original versions of this routine were very 1683 * inefficient because they iteratively called 1684 * pmap_remove (slow...) 1685 */ 1686 1687void 1688pmap_remove_all(vm_page_t m) 1689{ 1690 register pv_entry_t pv; 1691 register pt_entry_t *pte, tpte; 1692 1693 KASSERT((m->flags & PG_FICTITIOUS) == 0, 1694 ("pmap_remove_all: page %p is fictitious", m)); 1695 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 1696 1697 if (m->md.pv_flags & PV_TABLE_REF) 1698 vm_page_flag_set(m, PG_REFERENCED); 1699 1700 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 1701 PMAP_LOCK(pv->pv_pmap); 1702 1703 /* 1704 * If it's last mapping writeback all caches from 1705 * the page being destroyed 1706 */ 1707 if (m->md.pv_list_count == 1) 1708 mips_dcache_wbinv_range_index(pv->pv_va, NBPG); 1709 1710 pv->pv_pmap->pm_stats.resident_count--; 1711 1712 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 1713 1714 tpte = loadandclear((u_int *)pte); 1715 if (is_kernel_pmap(pv->pv_pmap)) 1716 *pte = PTE_G; 1717 1718 if (tpte & PTE_W) 1719 pv->pv_pmap->pm_stats.wired_count--; 1720 1721 /* 1722 * Update the vm_page_t clean and reference bits. 1723 */ 1724 if (tpte & PTE_M) { 1725#if defined(PMAP_DIAGNOSTIC) 1726 if (pmap_nw_modified(tpte)) { 1727 printf( 1728 "pmap_remove_all: modified page not writable: va: 0x%x, pte: 0x%x\n", 1729 pv->pv_va, tpte); 1730 } 1731#endif 1732 vm_page_dirty(m); 1733 } 1734 pmap_invalidate_page(pv->pv_pmap, pv->pv_va); 1735 1736 TAILQ_REMOVE(&pv->pv_pmap->pm_pvlist, pv, pv_plist); 1737 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 1738 m->md.pv_list_count--; 1739 pmap_unuse_pt(pv->pv_pmap, pv->pv_va, pv->pv_ptem); 1740 PMAP_UNLOCK(pv->pv_pmap); 1741 free_pv_entry(pv); 1742 } 1743 1744 vm_page_flag_clear(m, PG_WRITEABLE); 1745 m->md.pv_flags &= ~(PV_TABLE_REF | PV_TABLE_MOD); 1746} 1747 1748/* 1749 * Set the physical protection on the 1750 * specified range of this map as requested. 1751 */ 1752void 1753pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 1754{ 1755 pt_entry_t *pte; 1756 1757 if (pmap == NULL) 1758 return; 1759 1760 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 1761 pmap_remove(pmap, sva, eva); 1762 return; 1763 } 1764 if (prot & VM_PROT_WRITE) 1765 return; 1766 1767 vm_page_lock_queues(); 1768 PMAP_LOCK(pmap); 1769 while (sva < eva) { 1770 pt_entry_t pbits, obits; 1771 vm_page_t m; 1772 vm_offset_t pa; 1773 1774 /* 1775 * If segment table entry is empty, skip this segment. 1776 */ 1777 if (!*pmap_pde(pmap, sva)) { 1778 sva = mips_segtrunc(sva + MIPS_SEGSIZE); 1779 continue; 1780 } 1781 /* 1782 * If pte is invalid, skip this page 1783 */ 1784 pte = pmap_pte(pmap, sva); 1785 if (!pmap_pte_v(pte)) { 1786 sva += PAGE_SIZE; 1787 continue; 1788 } 1789retry: 1790 obits = pbits = *pte; 1791 pa = mips_tlbpfn_to_paddr(pbits); 1792 1793 if (page_is_managed(pa)) { 1794 m = PHYS_TO_VM_PAGE(pa); 1795 if (m->md.pv_flags & PV_TABLE_REF) { 1796 vm_page_flag_set(m, PG_REFERENCED); 1797 m->md.pv_flags &= ~PV_TABLE_REF; 1798 } 1799 if (pbits & PTE_M) { 1800 vm_page_dirty(m); 1801 m->md.pv_flags &= ~PV_TABLE_MOD; 1802 } 1803 } 1804 pbits = (pbits & ~PTE_M) | PTE_RO; 1805 1806 if (pbits != *pte) { 1807 if (!atomic_cmpset_int((u_int *)pte, obits, pbits)) 1808 goto retry; 1809 pmap_update_page(pmap, sva, pbits); 1810 } 1811 sva += PAGE_SIZE; 1812 } 1813 vm_page_unlock_queues(); 1814 PMAP_UNLOCK(pmap); 1815} 1816 1817/* 1818 * Insert the given physical page (p) at 1819 * the specified virtual address (v) in the 1820 * target physical map with the protection requested. 1821 * 1822 * If specified, the page will be wired down, meaning 1823 * that the related pte can not be reclaimed. 1824 * 1825 * NB: This is the only routine which MAY NOT lazy-evaluate 1826 * or lose information. That is, this routine must actually 1827 * insert this page into the given map NOW. 1828 */ 1829void 1830pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m, 1831 vm_prot_t prot, boolean_t wired) 1832{ 1833 vm_offset_t pa, opa; 1834 register pt_entry_t *pte; 1835 pt_entry_t origpte, newpte; 1836 vm_page_t mpte, om; 1837 int rw = 0; 1838 1839 if (pmap == NULL) 1840 return; 1841 1842 va &= ~PAGE_MASK; 1843#ifdef PMAP_DIAGNOSTIC 1844 if (va > VM_MAX_KERNEL_ADDRESS) 1845 panic("pmap_enter: toobig"); 1846#endif 1847 1848 mpte = NULL; 1849 1850 vm_page_lock_queues(); 1851 PMAP_LOCK(pmap); 1852 1853 /* 1854 * In the case that a page table page is not resident, we are 1855 * creating it here. 1856 */ 1857 if (va < VM_MAXUSER_ADDRESS) { 1858 mpte = pmap_allocpte(pmap, va, M_WAITOK); 1859 } 1860 pte = pmap_pte(pmap, va); 1861 1862 /* 1863 * Page Directory table entry not valid, we need a new PT page 1864 */ 1865 if (pte == NULL) { 1866 panic("pmap_enter: invalid page directory, pdir=%p, va=%p\n", 1867 (void *)pmap->pm_segtab, (void *)va); 1868 } 1869 pa = VM_PAGE_TO_PHYS(m); 1870 om = NULL; 1871 origpte = *pte; 1872 opa = mips_tlbpfn_to_paddr(origpte); 1873 1874 /* 1875 * Mapping has not changed, must be protection or wiring change. 1876 */ 1877 if ((origpte & PTE_V) && (opa == pa)) { 1878 /* 1879 * Wiring change, just update stats. We don't worry about 1880 * wiring PT pages as they remain resident as long as there 1881 * are valid mappings in them. Hence, if a user page is 1882 * wired, the PT page will be also. 1883 */ 1884 if (wired && ((origpte & PTE_W) == 0)) 1885 pmap->pm_stats.wired_count++; 1886 else if (!wired && (origpte & PTE_W)) 1887 pmap->pm_stats.wired_count--; 1888 1889#if defined(PMAP_DIAGNOSTIC) 1890 if (pmap_nw_modified(origpte)) { 1891 printf( 1892 "pmap_enter: modified page not writable: va: 0x%x, pte: 0x%x\n", 1893 va, origpte); 1894 } 1895#endif 1896 1897 /* 1898 * Remove extra pte reference 1899 */ 1900 if (mpte) 1901 mpte->wire_count--; 1902 1903 /* 1904 * We might be turning off write access to the page, so we 1905 * go ahead and sense modify status. 1906 */ 1907 if (page_is_managed(opa)) { 1908 om = m; 1909 } 1910 goto validate; 1911 } 1912 /* 1913 * Mapping has changed, invalidate old range and fall through to 1914 * handle validating new mapping. 1915 */ 1916 if (opa) { 1917 if (origpte & PTE_W) 1918 pmap->pm_stats.wired_count--; 1919 1920 if (page_is_managed(opa)) { 1921 om = PHYS_TO_VM_PAGE(opa); 1922 pmap_remove_entry(pmap, om, va); 1923 } 1924 if (mpte != NULL) { 1925 mpte->wire_count--; 1926 KASSERT(mpte->wire_count > 0, 1927 ("pmap_enter: missing reference to page table page," 1928 " va: %p", (void *)va)); 1929 } 1930 } else 1931 pmap->pm_stats.resident_count++; 1932 1933 /* 1934 * Enter on the PV list if part of our managed memory. Note that we 1935 * raise IPL while manipulating pv_table since pmap_enter can be 1936 * called at interrupt time. 1937 */ 1938 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) { 1939 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva, 1940 ("pmap_enter: managed mapping within the clean submap")); 1941 pmap_insert_entry(pmap, va, mpte, m, wired); 1942 } 1943 /* 1944 * Increment counters 1945 */ 1946 if (wired) 1947 pmap->pm_stats.wired_count++; 1948 1949validate: 1950 if ((access & VM_PROT_WRITE) != 0) 1951 m->md.pv_flags |= PV_TABLE_MOD | PV_TABLE_REF; 1952 rw = init_pte_prot(va, m, prot); 1953 1954#ifdef PMAP_DEBUG 1955 printf("pmap_enter: va: 0x%08x -> pa: 0x%08x\n", va, pa); 1956#endif 1957 /* 1958 * Now validate mapping with desired protection/wiring. 1959 */ 1960 newpte = mips_paddr_to_tlbpfn(pa) | rw | PTE_V; 1961 1962 if (is_cacheable_mem(pa)) 1963 newpte |= PTE_CACHE; 1964 else 1965 newpte |= PTE_UNCACHED; 1966 1967 if (wired) 1968 newpte |= PTE_W; 1969 1970 if (is_kernel_pmap(pmap)) { 1971 newpte |= PTE_G; 1972 } 1973 1974 /* 1975 * if the mapping or permission bits are different, we need to 1976 * update the pte. 1977 */ 1978 if (origpte != newpte) { 1979 if (origpte & PTE_V) { 1980 *pte = newpte; 1981 if (page_is_managed(opa) && (opa != pa)) { 1982 if (om->md.pv_flags & PV_TABLE_REF) 1983 vm_page_flag_set(om, PG_REFERENCED); 1984 om->md.pv_flags &= 1985 ~(PV_TABLE_REF | PV_TABLE_MOD); 1986 } 1987 if (origpte & PTE_M) { 1988 KASSERT((origpte & PTE_RW), 1989 ("pmap_enter: modified page not writable:" 1990 " va: %p, pte: 0x%lx", (void *)va, origpte)); 1991 if (page_is_managed(opa)) 1992 vm_page_dirty(om); 1993 } 1994 } else { 1995 *pte = newpte; 1996 } 1997 } 1998 pmap_update_page(pmap, va, newpte); 1999 2000 /* 2001 * Sync I & D caches for executable pages. Do this only if the the 2002 * target pmap belongs to the current process. Otherwise, an 2003 * unresolvable TLB miss may occur. 2004 */ 2005 if (!is_kernel_pmap(pmap) && (pmap == &curproc->p_vmspace->vm_pmap) && 2006 (prot & VM_PROT_EXECUTE)) { 2007 mips_icache_sync_range(va, NBPG); 2008 mips_dcache_wbinv_range(va, NBPG); 2009 } 2010 vm_page_unlock_queues(); 2011 PMAP_UNLOCK(pmap); 2012} 2013 2014/* 2015 * this code makes some *MAJOR* assumptions: 2016 * 1. Current pmap & pmap exists. 2017 * 2. Not wired. 2018 * 3. Read access. 2019 * 4. No page table pages. 2020 * but is *MUCH* faster than pmap_enter... 2021 */ 2022 2023void 2024pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 2025{ 2026 2027 PMAP_LOCK(pmap); 2028 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL); 2029 PMAP_UNLOCK(pmap); 2030} 2031 2032static vm_page_t 2033pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, 2034 vm_prot_t prot, vm_page_t mpte) 2035{ 2036 pt_entry_t *pte; 2037 vm_offset_t pa; 2038 2039 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva || 2040 (m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0, 2041 ("pmap_enter_quick_locked: managed mapping within the clean submap")); 2042 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2043 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2044 2045 /* 2046 * In the case that a page table page is not resident, we are 2047 * creating it here. 2048 */ 2049 if (va < VM_MAXUSER_ADDRESS) { 2050 unsigned ptepindex; 2051 vm_offset_t pteva; 2052 2053 /* 2054 * Calculate pagetable page index 2055 */ 2056 ptepindex = va >> SEGSHIFT; 2057 if (mpte && (mpte->pindex == ptepindex)) { 2058 mpte->wire_count++; 2059 } else { 2060 /* 2061 * Get the page directory entry 2062 */ 2063 pteva = (vm_offset_t)pmap->pm_segtab[ptepindex]; 2064 2065 /* 2066 * If the page table page is mapped, we just 2067 * increment the hold count, and activate it. 2068 */ 2069 if (pteva) { 2070 if (pmap->pm_ptphint && 2071 (pmap->pm_ptphint->pindex == ptepindex)) { 2072 mpte = pmap->pm_ptphint; 2073 } else { 2074 mpte = PHYS_TO_VM_PAGE(vtophys(pteva)); 2075 pmap->pm_ptphint = mpte; 2076 } 2077 mpte->wire_count++; 2078 } else { 2079 mpte = _pmap_allocpte(pmap, ptepindex, 2080 M_NOWAIT); 2081 if (mpte == NULL) 2082 return (mpte); 2083 } 2084 } 2085 } else { 2086 mpte = NULL; 2087 } 2088 2089 pte = pmap_pte(pmap, va); 2090 if (pmap_pte_v(pte)) { 2091 if (mpte != NULL) { 2092 mpte->wire_count--; 2093 mpte = NULL; 2094 } 2095 return (mpte); 2096 } 2097 2098 /* 2099 * Enter on the PV list if part of our managed memory. 2100 */ 2101 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0 && 2102 !pmap_try_insert_pv_entry(pmap, mpte, va, m)) { 2103 if (mpte != NULL) { 2104 pmap_unwire_pte_hold(pmap, mpte); 2105 mpte = NULL; 2106 } 2107 return (mpte); 2108 } 2109 2110 /* 2111 * Increment counters 2112 */ 2113 pmap->pm_stats.resident_count++; 2114 2115 pa = VM_PAGE_TO_PHYS(m); 2116 2117 /* 2118 * Now validate mapping with RO protection 2119 */ 2120 *pte = mips_paddr_to_tlbpfn(pa) | PTE_V; 2121 2122 if (is_cacheable_mem(pa)) 2123 *pte |= PTE_CACHE; 2124 else 2125 *pte |= PTE_UNCACHED; 2126 2127 if (is_kernel_pmap(pmap)) 2128 *pte |= PTE_G; 2129 else { 2130 *pte |= PTE_RO; 2131 /* 2132 * Sync I & D caches. Do this only if the the target pmap 2133 * belongs to the current process. Otherwise, an 2134 * unresolvable TLB miss may occur. */ 2135 if (pmap == &curproc->p_vmspace->vm_pmap) { 2136 va &= ~PAGE_MASK; 2137 mips_icache_sync_range(va, NBPG); 2138 mips_dcache_wbinv_range(va, NBPG); 2139 } 2140 } 2141 return (mpte); 2142} 2143 2144/* 2145 * Make a temporary mapping for a physical address. This is only intended 2146 * to be used for panic dumps. 2147 */ 2148void * 2149pmap_kenter_temporary(vm_paddr_t pa, int i) 2150{ 2151 vm_offset_t va; 2152 int int_level; 2153 if (i != 0) 2154 printf("%s: ERROR!!! More than one page of virtual address mapping not supported\n", 2155 __func__); 2156 2157#ifdef VM_ALLOC_WIRED_TLB_PG_POOL 2158 if (need_wired_tlb_page_pool) { 2159 va = pmap_map_fpage(pa, &fpages_shared[PMAP_FPAGE_KENTER_TEMP], 2160 TRUE); 2161 } else 2162#endif 2163 if (pa < MIPS_KSEG0_LARGEST_PHYS) { 2164 va = MIPS_PHYS_TO_KSEG0(pa); 2165 } else { 2166 int cpu; 2167 struct local_sysmaps *sysm; 2168 /* If this is used other than for dumps, we may need to leave 2169 * interrupts disasbled on return. If crash dumps don't work when 2170 * we get to this point, we might want to consider this (leaving things 2171 * disabled as a starting point ;-) 2172 */ 2173 int_level = disableintr(); 2174 cpu = PCPU_GET(cpuid); 2175 sysm = &sysmap_lmem[cpu]; 2176 /* Since this is for the debugger, no locks or any other fun */ 2177 sysm->CMAP1 = mips_paddr_to_tlbpfn(pa) | PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; 2178 sysm->valid1 = 1; 2179 pmap_TLB_update_kernel((vm_offset_t)sysm->CADDR1, sysm->CMAP1); 2180 va = (vm_offset_t)sysm->CADDR1; 2181 restoreintr(int_level); 2182 } 2183 return ((void *)va); 2184} 2185 2186void 2187pmap_kenter_temporary_free(vm_paddr_t pa) 2188{ 2189 int cpu; 2190 int int_level; 2191 struct local_sysmaps *sysm; 2192 2193 if (pa < MIPS_KSEG0_LARGEST_PHYS) { 2194 /* nothing to do for this case */ 2195 return; 2196 } 2197 cpu = PCPU_GET(cpuid); 2198 sysm = &sysmap_lmem[cpu]; 2199 if (sysm->valid1) { 2200 int_level = disableintr(); 2201 pmap_TLB_invalidate_kernel((vm_offset_t)sysm->CADDR1); 2202 restoreintr(int_level); 2203 sysm->CMAP1 = 0; 2204 sysm->valid1 = 0; 2205 } 2206} 2207 2208/* 2209 * Moved the code to Machine Independent 2210 * vm_map_pmap_enter() 2211 */ 2212 2213/* 2214 * Maps a sequence of resident pages belonging to the same object. 2215 * The sequence begins with the given page m_start. This page is 2216 * mapped at the given virtual address start. Each subsequent page is 2217 * mapped at a virtual address that is offset from start by the same 2218 * amount as the page is offset from m_start within the object. The 2219 * last page in the sequence is the page with the largest offset from 2220 * m_start that can be mapped at a virtual address less than the given 2221 * virtual address end. Not every virtual page between start and end 2222 * is mapped; only those for which a resident page exists with the 2223 * corresponding offset from m_start are mapped. 2224 */ 2225void 2226pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 2227 vm_page_t m_start, vm_prot_t prot) 2228{ 2229 vm_page_t m, mpte; 2230 vm_pindex_t diff, psize; 2231 2232 VM_OBJECT_LOCK_ASSERT(m_start->object, MA_OWNED); 2233 psize = atop(end - start); 2234 mpte = NULL; 2235 m = m_start; 2236 PMAP_LOCK(pmap); 2237 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 2238 mpte = pmap_enter_quick_locked(pmap, start + ptoa(diff), m, 2239 prot, mpte); 2240 m = TAILQ_NEXT(m, listq); 2241 } 2242 PMAP_UNLOCK(pmap); 2243} 2244 2245/* 2246 * pmap_object_init_pt preloads the ptes for a given object 2247 * into the specified pmap. This eliminates the blast of soft 2248 * faults on process startup and immediately after an mmap. 2249 */ 2250void 2251pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, 2252 vm_object_t object, vm_pindex_t pindex, vm_size_t size) 2253{ 2254 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED); 2255 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 2256 ("pmap_object_init_pt: non-device object")); 2257} 2258 2259/* 2260 * Routine: pmap_change_wiring 2261 * Function: Change the wiring attribute for a map/virtual-address 2262 * pair. 2263 * In/out conditions: 2264 * The mapping must already exist in the pmap. 2265 */ 2266void 2267pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 2268{ 2269 register pt_entry_t *pte; 2270 2271 if (pmap == NULL) 2272 return; 2273 2274 PMAP_LOCK(pmap); 2275 pte = pmap_pte(pmap, va); 2276 2277 if (wired && !pmap_pte_w(pte)) 2278 pmap->pm_stats.wired_count++; 2279 else if (!wired && pmap_pte_w(pte)) 2280 pmap->pm_stats.wired_count--; 2281 2282 /* 2283 * Wiring is not a hardware characteristic so there is no need to 2284 * invalidate TLB. 2285 */ 2286 pmap_pte_set_w(pte, wired); 2287 PMAP_UNLOCK(pmap); 2288} 2289 2290/* 2291 * Copy the range specified by src_addr/len 2292 * from the source map to the range dst_addr/len 2293 * in the destination map. 2294 * 2295 * This routine is only advisory and need not do anything. 2296 */ 2297 2298void 2299pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, 2300 vm_size_t len, vm_offset_t src_addr) 2301{ 2302} 2303 2304/* 2305 * pmap_zero_page zeros the specified hardware page by mapping 2306 * the page into KVM and using bzero to clear its contents. 2307 */ 2308void 2309pmap_zero_page(vm_page_t m) 2310{ 2311 vm_offset_t va; 2312 vm_paddr_t phys = VM_PAGE_TO_PHYS(m); 2313 int int_level; 2314#ifdef VM_ALLOC_WIRED_TLB_PG_POOL 2315 if (need_wired_tlb_page_pool) { 2316 struct fpage *fp1; 2317 struct sysmaps *sysmaps; 2318 2319 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 2320 mtx_lock(&sysmaps->lock); 2321 sched_pin(); 2322 2323 fp1 = &sysmaps->fp[PMAP_FPAGE1]; 2324 va = pmap_map_fpage(phys, fp1, FALSE); 2325 bzero((caddr_t)va, PAGE_SIZE); 2326 pmap_unmap_fpage(phys, fp1); 2327 sched_unpin(); 2328 mtx_unlock(&sysmaps->lock); 2329 /* 2330 * Should you do cache flush? 2331 */ 2332 } else 2333#endif 2334 if (phys < MIPS_KSEG0_LARGEST_PHYS) { 2335 2336 va = MIPS_PHYS_TO_KSEG0(phys); 2337 2338 bzero((caddr_t)va, PAGE_SIZE); 2339 mips_dcache_wbinv_range(va, PAGE_SIZE); 2340 } else { 2341 int cpu; 2342 struct local_sysmaps *sysm; 2343 2344 cpu = PCPU_GET(cpuid); 2345 sysm = &sysmap_lmem[cpu]; 2346 PMAP_LGMEM_LOCK(sysm); 2347 sched_pin(); 2348 int_level = disableintr(); 2349 sysm->CMAP1 = mips_paddr_to_tlbpfn(phys) | PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; 2350 sysm->valid1 = 1; 2351 pmap_TLB_update_kernel((vm_offset_t)sysm->CADDR1, sysm->CMAP1); 2352 bzero(sysm->CADDR1, PAGE_SIZE); 2353 pmap_TLB_invalidate_kernel((vm_offset_t)sysm->CADDR1); 2354 restoreintr(int_level); 2355 sysm->CMAP1 = 0; 2356 sysm->valid1 = 0; 2357 sched_unpin(); 2358 PMAP_LGMEM_UNLOCK(sysm); 2359 } 2360 2361} 2362 2363/* 2364 * pmap_zero_page_area zeros the specified hardware page by mapping 2365 * the page into KVM and using bzero to clear its contents. 2366 * 2367 * off and size may not cover an area beyond a single hardware page. 2368 */ 2369void 2370pmap_zero_page_area(vm_page_t m, int off, int size) 2371{ 2372 vm_offset_t va; 2373 vm_paddr_t phys = VM_PAGE_TO_PHYS(m); 2374 int int_level; 2375#ifdef VM_ALLOC_WIRED_TLB_PG_POOL 2376 if (need_wired_tlb_page_pool) { 2377 struct fpage *fp1; 2378 struct sysmaps *sysmaps; 2379 2380 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 2381 mtx_lock(&sysmaps->lock); 2382 sched_pin(); 2383 2384 fp1 = &sysmaps->fp[PMAP_FPAGE1]; 2385 va = pmap_map_fpage(phys, fp1, FALSE); 2386 bzero((caddr_t)va + off, size); 2387 pmap_unmap_fpage(phys, fp1); 2388 2389 sched_unpin(); 2390 mtx_unlock(&sysmaps->lock); 2391 } else 2392#endif 2393 if (phys < MIPS_KSEG0_LARGEST_PHYS) { 2394 va = MIPS_PHYS_TO_KSEG0(phys); 2395 bzero((char *)(caddr_t)va + off, size); 2396 mips_dcache_wbinv_range(va + off, size); 2397 } else { 2398 int cpu; 2399 struct local_sysmaps *sysm; 2400 2401 cpu = PCPU_GET(cpuid); 2402 sysm = &sysmap_lmem[cpu]; 2403 PMAP_LGMEM_LOCK(sysm); 2404 int_level = disableintr(); 2405 sched_pin(); 2406 sysm->CMAP1 = mips_paddr_to_tlbpfn(phys) | PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; 2407 sysm->valid1 = 1; 2408 pmap_TLB_update_kernel((vm_offset_t)sysm->CADDR1, sysm->CMAP1); 2409 bzero((char *)sysm->CADDR1 + off, size); 2410 pmap_TLB_invalidate_kernel((vm_offset_t)sysm->CADDR1); 2411 restoreintr(int_level); 2412 sysm->CMAP1 = 0; 2413 sysm->valid1 = 0; 2414 sched_unpin(); 2415 PMAP_LGMEM_UNLOCK(sysm); 2416 } 2417} 2418 2419void 2420pmap_zero_page_idle(vm_page_t m) 2421{ 2422 vm_offset_t va; 2423 vm_paddr_t phys = VM_PAGE_TO_PHYS(m); 2424 int int_level; 2425#ifdef VM_ALLOC_WIRED_TLB_PG_POOL 2426 if (need_wired_tlb_page_pool) { 2427 sched_pin(); 2428 va = pmap_map_fpage(phys, &fpages_shared[PMAP_FPAGE3], FALSE); 2429 bzero((caddr_t)va, PAGE_SIZE); 2430 pmap_unmap_fpage(phys, &fpages_shared[PMAP_FPAGE3]); 2431 sched_unpin(); 2432 } else 2433#endif 2434 if (phys < MIPS_KSEG0_LARGEST_PHYS) { 2435 va = MIPS_PHYS_TO_KSEG0(phys); 2436 bzero((caddr_t)va, PAGE_SIZE); 2437 mips_dcache_wbinv_range(va, PAGE_SIZE); 2438 } else { 2439 int cpu; 2440 struct local_sysmaps *sysm; 2441 2442 cpu = PCPU_GET(cpuid); 2443 sysm = &sysmap_lmem[cpu]; 2444 PMAP_LGMEM_LOCK(sysm); 2445 int_level = disableintr(); 2446 sched_pin(); 2447 sysm->CMAP1 = mips_paddr_to_tlbpfn(phys) | PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; 2448 sysm->valid1 = 1; 2449 pmap_TLB_update_kernel((vm_offset_t)sysm->CADDR1, sysm->CMAP1); 2450 bzero(sysm->CADDR1, PAGE_SIZE); 2451 pmap_TLB_invalidate_kernel((vm_offset_t)sysm->CADDR1); 2452 restoreintr(int_level); 2453 sysm->CMAP1 = 0; 2454 sysm->valid1 = 0; 2455 sched_unpin(); 2456 PMAP_LGMEM_UNLOCK(sysm); 2457 } 2458 2459} 2460 2461/* 2462 * pmap_copy_page copies the specified (machine independent) 2463 * page by mapping the page into virtual memory and using 2464 * bcopy to copy the page, one machine dependent page at a 2465 * time. 2466 */ 2467void 2468pmap_copy_page(vm_page_t src, vm_page_t dst) 2469{ 2470 vm_offset_t va_src, va_dst; 2471 vm_paddr_t phy_src = VM_PAGE_TO_PHYS(src); 2472 vm_paddr_t phy_dst = VM_PAGE_TO_PHYS(dst); 2473 int int_level; 2474#ifdef VM_ALLOC_WIRED_TLB_PG_POOL 2475 if (need_wired_tlb_page_pool) { 2476 struct fpage *fp1, *fp2; 2477 struct sysmaps *sysmaps; 2478 2479 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 2480 mtx_lock(&sysmaps->lock); 2481 sched_pin(); 2482 2483 fp1 = &sysmaps->fp[PMAP_FPAGE1]; 2484 fp2 = &sysmaps->fp[PMAP_FPAGE2]; 2485 2486 va_src = pmap_map_fpage(phy_src, fp1, FALSE); 2487 va_dst = pmap_map_fpage(phy_dst, fp2, FALSE); 2488 2489 bcopy((caddr_t)va_src, (caddr_t)va_dst, PAGE_SIZE); 2490 2491 pmap_unmap_fpage(phy_src, fp1); 2492 pmap_unmap_fpage(phy_dst, fp2); 2493 sched_unpin(); 2494 mtx_unlock(&sysmaps->lock); 2495 2496 /* 2497 * Should you flush the cache? 2498 */ 2499 } else 2500#endif 2501 { 2502 if ((phy_src < MIPS_KSEG0_LARGEST_PHYS) && (phy_dst < MIPS_KSEG0_LARGEST_PHYS)) { 2503 /* easy case, all can be accessed via KSEG0 */ 2504 /* 2505 * Flush all caches for VA that are mapped to this page 2506 * to make sure that data in SDRAM is up to date 2507 */ 2508 pmap_flush_pvcache(src); 2509 mips_dcache_wbinv_range_index( 2510 MIPS_PHYS_TO_KSEG0(phy_dst), NBPG); 2511 va_src = MIPS_PHYS_TO_KSEG0(phy_src); 2512 va_dst = MIPS_PHYS_TO_KSEG0(phy_dst); 2513 bcopy((caddr_t)va_src, (caddr_t)va_dst, PAGE_SIZE); 2514 mips_dcache_wbinv_range(va_dst, PAGE_SIZE); 2515 } else { 2516 int cpu; 2517 struct local_sysmaps *sysm; 2518 2519 cpu = PCPU_GET(cpuid); 2520 sysm = &sysmap_lmem[cpu]; 2521 PMAP_LGMEM_LOCK(sysm); 2522 sched_pin(); 2523 int_level = disableintr(); 2524 if (phy_src < MIPS_KSEG0_LARGEST_PHYS) { 2525 /* one side needs mapping - dest */ 2526 va_src = MIPS_PHYS_TO_KSEG0(phy_src); 2527 sysm->CMAP2 = mips_paddr_to_tlbpfn(phy_dst) | PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; 2528 pmap_TLB_update_kernel((vm_offset_t)sysm->CADDR2, sysm->CMAP2); 2529 sysm->valid2 = 1; 2530 va_dst = (vm_offset_t)sysm->CADDR2; 2531 } else if (phy_dst < MIPS_KSEG0_LARGEST_PHYS) { 2532 /* one side needs mapping - src */ 2533 va_dst = MIPS_PHYS_TO_KSEG0(phy_dst); 2534 sysm->CMAP1 = mips_paddr_to_tlbpfn(phy_src) | PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; 2535 pmap_TLB_update_kernel((vm_offset_t)sysm->CADDR1, sysm->CMAP1); 2536 va_src = (vm_offset_t)sysm->CADDR1; 2537 sysm->valid1 = 1; 2538 } else { 2539 /* all need mapping */ 2540 sysm->CMAP1 = mips_paddr_to_tlbpfn(phy_src) | PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; 2541 sysm->CMAP2 = mips_paddr_to_tlbpfn(phy_dst) | PTE_RW | PTE_V | PTE_G | PTE_W | PTE_CACHE; 2542 pmap_TLB_update_kernel((vm_offset_t)sysm->CADDR1, sysm->CMAP1); 2543 pmap_TLB_update_kernel((vm_offset_t)sysm->CADDR2, sysm->CMAP2); 2544 sysm->valid1 = sysm->valid2 = 1; 2545 va_src = (vm_offset_t)sysm->CADDR1; 2546 va_dst = (vm_offset_t)sysm->CADDR2; 2547 } 2548 bcopy((void *)va_src, (void *)va_dst, PAGE_SIZE); 2549 if (sysm->valid1) { 2550 pmap_TLB_invalidate_kernel((vm_offset_t)sysm->CADDR1); 2551 sysm->CMAP1 = 0; 2552 sysm->valid1 = 0; 2553 } 2554 if (sysm->valid2) { 2555 pmap_TLB_invalidate_kernel((vm_offset_t)sysm->CADDR2); 2556 sysm->CMAP2 = 0; 2557 sysm->valid2 = 0; 2558 } 2559 restoreintr(int_level); 2560 sched_unpin(); 2561 PMAP_LGMEM_UNLOCK(sysm); 2562 } 2563 } 2564} 2565 2566/* 2567 * Returns true if the pmap's pv is one of the first 2568 * 16 pvs linked to from this page. This count may 2569 * be changed upwards or downwards in the future; it 2570 * is only necessary that true be returned for a small 2571 * subset of pmaps for proper page aging. 2572 */ 2573boolean_t 2574pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 2575{ 2576 pv_entry_t pv; 2577 int loops = 0; 2578 2579 if (m->flags & PG_FICTITIOUS) 2580 return FALSE; 2581 2582 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2583 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2584 if (pv->pv_pmap == pmap) { 2585 return TRUE; 2586 } 2587 loops++; 2588 if (loops >= 16) 2589 break; 2590 } 2591 return (FALSE); 2592} 2593 2594/* 2595 * Remove all pages from specified address space 2596 * this aids process exit speeds. Also, this code 2597 * is special cased for current process only, but 2598 * can have the more generic (and slightly slower) 2599 * mode enabled. This is much faster than pmap_remove 2600 * in the case of running down an entire address space. 2601 */ 2602void 2603pmap_remove_pages(pmap_t pmap) 2604{ 2605 pt_entry_t *pte, tpte; 2606 pv_entry_t pv, npv; 2607 vm_page_t m; 2608 2609 if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) { 2610 printf("warning: pmap_remove_pages called with non-current pmap\n"); 2611 return; 2612 } 2613 vm_page_lock_queues(); 2614 PMAP_LOCK(pmap); 2615 sched_pin(); 2616 //XXX need to be TAILQ_FOREACH_SAFE ? 2617 for (pv = TAILQ_FIRST(&pmap->pm_pvlist); pv; pv = npv) { 2618 2619 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 2620 if (!pmap_pte_v(pte)) 2621 panic("pmap_remove_pages: page on pm_pvlist has no pte\n"); 2622 tpte = *pte; 2623 2624/* 2625 * We cannot remove wired pages from a process' mapping at this time 2626 */ 2627 if (tpte & PTE_W) { 2628 npv = TAILQ_NEXT(pv, pv_plist); 2629 continue; 2630 } 2631 *pte = is_kernel_pmap(pmap) ? PTE_G : 0; 2632 2633 m = PHYS_TO_VM_PAGE(mips_tlbpfn_to_paddr(tpte)); 2634 2635 KASSERT(m < &vm_page_array[vm_page_array_size], 2636 ("pmap_remove_pages: bad tpte %lx", tpte)); 2637 2638 pv->pv_pmap->pm_stats.resident_count--; 2639 2640 /* 2641 * Update the vm_page_t clean and reference bits. 2642 */ 2643 if (tpte & PTE_M) { 2644 vm_page_dirty(m); 2645 } 2646 npv = TAILQ_NEXT(pv, pv_plist); 2647 TAILQ_REMOVE(&pv->pv_pmap->pm_pvlist, pv, pv_plist); 2648 2649 m->md.pv_list_count--; 2650 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list); 2651 if (TAILQ_FIRST(&m->md.pv_list) == NULL) { 2652 vm_page_flag_clear(m, PG_WRITEABLE); 2653 } 2654 pmap_unuse_pt(pv->pv_pmap, pv->pv_va, pv->pv_ptem); 2655 free_pv_entry(pv); 2656 } 2657 sched_unpin(); 2658 pmap_invalidate_all(pmap); 2659 PMAP_UNLOCK(pmap); 2660 vm_page_unlock_queues(); 2661} 2662 2663/* 2664 * pmap_testbit tests bits in pte's 2665 * note that the testbit/changebit routines are inline, 2666 * and a lot of things compile-time evaluate. 2667 */ 2668static boolean_t 2669pmap_testbit(vm_page_t m, int bit) 2670{ 2671 pv_entry_t pv; 2672 pt_entry_t *pte; 2673 boolean_t rv = FALSE; 2674 2675 if (m->flags & PG_FICTITIOUS) 2676 return rv; 2677 2678 if (TAILQ_FIRST(&m->md.pv_list) == NULL) 2679 return rv; 2680 2681 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2682 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2683#if defined(PMAP_DIAGNOSTIC) 2684 if (!pv->pv_pmap) { 2685 printf("Null pmap (tb) at va: 0x%x\n", pv->pv_va); 2686 continue; 2687 } 2688#endif 2689 PMAP_LOCK(pv->pv_pmap); 2690 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 2691 rv = (*pte & bit) != 0; 2692 PMAP_UNLOCK(pv->pv_pmap); 2693 if (rv) 2694 break; 2695 } 2696 return (rv); 2697} 2698 2699/* 2700 * this routine is used to modify bits in ptes 2701 */ 2702static __inline void 2703pmap_changebit(vm_page_t m, int bit, boolean_t setem) 2704{ 2705 register pv_entry_t pv; 2706 register pt_entry_t *pte; 2707 2708 if (m->flags & PG_FICTITIOUS) 2709 return; 2710 2711 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2712 /* 2713 * Loop over all current mappings setting/clearing as appropos If 2714 * setting RO do we need to clear the VAC? 2715 */ 2716 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) { 2717#if defined(PMAP_DIAGNOSTIC) 2718 if (!pv->pv_pmap) { 2719 printf("Null pmap (cb) at va: 0x%x\n", pv->pv_va); 2720 continue; 2721 } 2722#endif 2723 2724 PMAP_LOCK(pv->pv_pmap); 2725 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 2726 2727 if (setem) { 2728 *(int *)pte |= bit; 2729 pmap_update_page(pv->pv_pmap, pv->pv_va, *pte); 2730 } else { 2731 vm_offset_t pbits = *(vm_offset_t *)pte; 2732 2733 if (pbits & bit) { 2734 if (bit == PTE_RW) { 2735 if (pbits & PTE_M) { 2736 vm_page_dirty(m); 2737 } 2738 *(int *)pte = (pbits & ~(PTE_M | PTE_RW)) | 2739 PTE_RO; 2740 } else { 2741 *(int *)pte = pbits & ~bit; 2742 } 2743 pmap_update_page(pv->pv_pmap, pv->pv_va, *pte); 2744 } 2745 } 2746 PMAP_UNLOCK(pv->pv_pmap); 2747 } 2748 if (!setem && bit == PTE_RW) 2749 vm_page_flag_clear(m, PG_WRITEABLE); 2750} 2751 2752/* 2753 * pmap_page_wired_mappings: 2754 * 2755 * Return the number of managed mappings to the given physical page 2756 * that are wired. 2757 */ 2758int 2759pmap_page_wired_mappings(vm_page_t m) 2760{ 2761 pv_entry_t pv; 2762 int count; 2763 2764 count = 0; 2765 if ((m->flags & PG_FICTITIOUS) != 0) 2766 return (count); 2767 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2768 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) 2769 if (pv->pv_wired) 2770 count++; 2771 return (count); 2772} 2773 2774/* 2775 * Clear the write and modified bits in each of the given page's mappings. 2776 */ 2777void 2778pmap_remove_write(vm_page_t m) 2779{ 2780 pv_entry_t pv, npv; 2781 vm_offset_t va; 2782 pt_entry_t *pte; 2783 2784 if ((m->flags & PG_WRITEABLE) == 0) 2785 return; 2786 2787 /* 2788 * Loop over all current mappings setting/clearing as appropos. 2789 */ 2790 for (pv = TAILQ_FIRST(&m->md.pv_list); pv; pv = npv) { 2791 npv = TAILQ_NEXT(pv, pv_plist); 2792 pte = pmap_pte(pv->pv_pmap, pv->pv_va); 2793 2794 if ((pte == NULL) || !mips_pg_v(*pte)) 2795 panic("page on pm_pvlist has no pte\n"); 2796 2797 va = pv->pv_va; 2798 pmap_protect(pv->pv_pmap, va, va + PAGE_SIZE, 2799 VM_PROT_READ | VM_PROT_EXECUTE); 2800 } 2801 vm_page_flag_clear(m, PG_WRITEABLE); 2802} 2803 2804/* 2805 * pmap_ts_referenced: 2806 * 2807 * Return the count of reference bits for a page, clearing all of them. 2808 */ 2809int 2810pmap_ts_referenced(vm_page_t m) 2811{ 2812 if (m->flags & PG_FICTITIOUS) 2813 return (0); 2814 2815 if (m->md.pv_flags & PV_TABLE_REF) { 2816 m->md.pv_flags &= ~PV_TABLE_REF; 2817 return 1; 2818 } 2819 return 0; 2820} 2821 2822/* 2823 * pmap_is_modified: 2824 * 2825 * Return whether or not the specified physical page was modified 2826 * in any physical maps. 2827 */ 2828boolean_t 2829pmap_is_modified(vm_page_t m) 2830{ 2831 if (m->flags & PG_FICTITIOUS) 2832 return FALSE; 2833 2834 if (m->md.pv_flags & PV_TABLE_MOD) 2835 return TRUE; 2836 else 2837 return pmap_testbit(m, PTE_M); 2838} 2839 2840/* N/C */ 2841 2842/* 2843 * pmap_is_prefaultable: 2844 * 2845 * Return whether or not the specified virtual address is elgible 2846 * for prefault. 2847 */ 2848boolean_t 2849pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 2850{ 2851 pt_entry_t *pte; 2852 boolean_t rv; 2853 2854 rv = FALSE; 2855 PMAP_LOCK(pmap); 2856 if (*pmap_pde(pmap, addr)) { 2857 pte = pmap_pte(pmap, addr); 2858 rv = (*pte == 0); 2859 } 2860 PMAP_UNLOCK(pmap); 2861 return (rv); 2862} 2863 2864/* 2865 * Clear the modify bits on the specified physical page. 2866 */ 2867void 2868pmap_clear_modify(vm_page_t m) 2869{ 2870 if (m->flags & PG_FICTITIOUS) 2871 return; 2872 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2873 if (m->md.pv_flags & PV_TABLE_MOD) { 2874 pmap_changebit(m, PTE_M, FALSE); 2875 m->md.pv_flags &= ~PV_TABLE_MOD; 2876 } 2877} 2878 2879/* 2880 * pmap_clear_reference: 2881 * 2882 * Clear the reference bit on the specified physical page. 2883 */ 2884void 2885pmap_clear_reference(vm_page_t m) 2886{ 2887 if (m->flags & PG_FICTITIOUS) 2888 return; 2889 2890 mtx_assert(&vm_page_queue_mtx, MA_OWNED); 2891 if (m->md.pv_flags & PV_TABLE_REF) { 2892 m->md.pv_flags &= ~PV_TABLE_REF; 2893 } 2894} 2895 2896/* 2897 * Miscellaneous support routines follow 2898 */ 2899 2900/* 2901 * Map a set of physical memory pages into the kernel virtual 2902 * address space. Return a pointer to where it is mapped. This 2903 * routine is intended to be used for mapping device memory, 2904 * NOT real memory. 2905 */ 2906 2907/* 2908 * Map a set of physical memory pages into the kernel virtual 2909 * address space. Return a pointer to where it is mapped. This 2910 * routine is intended to be used for mapping device memory, 2911 * NOT real memory. 2912 */ 2913void * 2914pmap_mapdev(vm_offset_t pa, vm_size_t size) 2915{ 2916 vm_offset_t va, tmpva, offset; 2917 2918 /* 2919 * KSEG1 maps only first 512M of phys address space. For 2920 * pa > 0x20000000 we should make proper mapping * using pmap_kenter. 2921 */ 2922 if ((pa + size - 1) < MIPS_KSEG0_LARGEST_PHYS) 2923 return (void *)MIPS_PHYS_TO_KSEG1(pa); 2924 else { 2925 offset = pa & PAGE_MASK; 2926 size = roundup(size + offset, PAGE_SIZE); 2927 2928 va = kmem_alloc_nofault(kernel_map, size); 2929 if (!va) 2930 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 2931 pa = trunc_page(pa); 2932 for (tmpva = va; size > 0;) { 2933 pmap_kenter(tmpva, pa); 2934 size -= PAGE_SIZE; 2935 tmpva += PAGE_SIZE; 2936 pa += PAGE_SIZE; 2937 } 2938 } 2939 2940 return ((void *)(va + offset)); 2941} 2942 2943void 2944pmap_unmapdev(vm_offset_t va, vm_size_t size) 2945{ 2946 vm_offset_t base, offset, tmpva; 2947 2948 /* If the address is within KSEG1 then there is nothing to do */ 2949 if (va >= MIPS_KSEG1_START && va <= MIPS_KSEG1_END) 2950 return; 2951 2952 base = trunc_page(va); 2953 offset = va & PAGE_MASK; 2954 size = roundup(size + offset, PAGE_SIZE); 2955 for (tmpva = base; tmpva < base + size; tmpva += PAGE_SIZE) 2956 pmap_kremove(tmpva); 2957 kmem_free(kernel_map, base, size); 2958} 2959 2960/* 2961 * perform the pmap work for mincore 2962 */ 2963int 2964pmap_mincore(pmap_t pmap, vm_offset_t addr) 2965{ 2966 2967 pt_entry_t *ptep, pte; 2968 vm_page_t m; 2969 int val = 0; 2970 2971 PMAP_LOCK(pmap); 2972 ptep = pmap_pte(pmap, addr); 2973 pte = (ptep != NULL) ? *ptep : 0; 2974 PMAP_UNLOCK(pmap); 2975 2976 if (mips_pg_v(pte)) { 2977 vm_offset_t pa; 2978 2979 val = MINCORE_INCORE; 2980 pa = mips_tlbpfn_to_paddr(pte); 2981 if (!page_is_managed(pa)) 2982 return val; 2983 2984 m = PHYS_TO_VM_PAGE(pa); 2985 2986 /* 2987 * Modified by us 2988 */ 2989 if (pte & PTE_M) 2990 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 2991 /* 2992 * Modified by someone 2993 */ 2994 else { 2995 vm_page_lock_queues(); 2996 if (m->dirty || pmap_is_modified(m)) 2997 val |= MINCORE_MODIFIED_OTHER; 2998 vm_page_unlock_queues(); 2999 } 3000 /* 3001 * Referenced by us or someone 3002 */ 3003 vm_page_lock_queues(); 3004 if ((m->flags & PG_REFERENCED) || pmap_ts_referenced(m)) { 3005 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 3006 vm_page_flag_set(m, PG_REFERENCED); 3007 } 3008 vm_page_unlock_queues(); 3009 } 3010 return val; 3011} 3012 3013void 3014pmap_activate(struct thread *td) 3015{ 3016 pmap_t pmap, oldpmap; 3017 struct proc *p = td->td_proc; 3018 3019 critical_enter(); 3020 3021 pmap = vmspace_pmap(p->p_vmspace); 3022 oldpmap = PCPU_GET(curpmap); 3023 3024 if (oldpmap) 3025 atomic_clear_32(&oldpmap->pm_active, PCPU_GET(cpumask)); 3026 atomic_set_32(&pmap->pm_active, PCPU_GET(cpumask)); 3027 pmap_asid_alloc(pmap); 3028 if (td == curthread) { 3029 PCPU_SET(segbase, pmap->pm_segtab); 3030 MachSetPID(pmap->pm_asid[PCPU_GET(cpuid)].asid); 3031 } 3032 3033 PCPU_SET(curpmap, pmap); 3034 critical_exit(); 3035} 3036 3037void 3038pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 3039{ 3040} 3041 3042/* 3043 * Increase the starting virtual address of the given mapping if a 3044 * different alignment might result in more superpage mappings. 3045 */ 3046void 3047pmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 3048 vm_offset_t *addr, vm_size_t size) 3049{ 3050 vm_offset_t superpage_offset; 3051 3052 if (size < NBSEG) 3053 return; 3054 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 3055 offset += ptoa(object->pg_color); 3056 superpage_offset = offset & SEGOFSET; 3057 if (size - ((NBSEG - superpage_offset) & SEGOFSET) < NBSEG || 3058 (*addr & SEGOFSET) == superpage_offset) 3059 return; 3060 if ((*addr & SEGOFSET) < superpage_offset) 3061 *addr = (*addr & ~SEGOFSET) + superpage_offset; 3062 else 3063 *addr = ((*addr + SEGOFSET) & ~SEGOFSET) + superpage_offset; 3064} 3065 3066int pmap_pid_dump(int pid); 3067 3068int 3069pmap_pid_dump(int pid) 3070{ 3071 pmap_t pmap; 3072 struct proc *p; 3073 int npte = 0; 3074 int index; 3075 3076 sx_slock(&allproc_lock); 3077 LIST_FOREACH(p, &allproc, p_list) { 3078 if (p->p_pid != pid) 3079 continue; 3080 3081 if (p->p_vmspace) { 3082 int i, j; 3083 3084 printf("vmspace is %p\n", 3085 p->p_vmspace); 3086 index = 0; 3087 pmap = vmspace_pmap(p->p_vmspace); 3088 printf("pmap asid:%x generation:%x\n", 3089 pmap->pm_asid[0].asid, 3090 pmap->pm_asid[0].gen); 3091 for (i = 0; i < NUSERPGTBLS; i++) { 3092 pd_entry_t *pde; 3093 pt_entry_t *pte; 3094 unsigned base = i << SEGSHIFT; 3095 3096 pde = &pmap->pm_segtab[i]; 3097 if (pde && pmap_pde_v(pde)) { 3098 for (j = 0; j < 1024; j++) { 3099 vm_offset_t va = base + 3100 (j << PAGE_SHIFT); 3101 3102 pte = pmap_pte(pmap, va); 3103 if (pte && pmap_pte_v(pte)) { 3104 vm_offset_t pa; 3105 vm_page_t m; 3106 3107 pa = mips_tlbpfn_to_paddr(*pte); 3108 m = PHYS_TO_VM_PAGE(pa); 3109 printf("va: %p, pt: %p, h: %d, w: %d, f: 0x%x", 3110 (void *)va, 3111 (void *)pa, 3112 m->hold_count, 3113 m->wire_count, 3114 m->flags); 3115 npte++; 3116 index++; 3117 if (index >= 2) { 3118 index = 0; 3119 printf("\n"); 3120 } else { 3121 printf(" "); 3122 } 3123 } 3124 } 3125 } 3126 } 3127 } else { 3128 printf("Process pid:%d has no vm_space\n", pid); 3129 } 3130 break; 3131 } 3132 sx_sunlock(&allproc_lock); 3133 return npte; 3134} 3135 3136 3137#if defined(DEBUG) 3138 3139static void pads(pmap_t pm); 3140void pmap_pvdump(vm_offset_t pa); 3141 3142/* print address space of pmap*/ 3143static void 3144pads(pmap_t pm) 3145{ 3146 unsigned va, i, j; 3147 pt_entry_t *ptep; 3148 3149 if (pm == kernel_pmap) 3150 return; 3151 for (i = 0; i < NPTEPG; i++) 3152 if (pm->pm_segtab[i]) 3153 for (j = 0; j < NPTEPG; j++) { 3154 va = (i << SEGSHIFT) + (j << PAGE_SHIFT); 3155 if (pm == kernel_pmap && va < KERNBASE) 3156 continue; 3157 if (pm != kernel_pmap && 3158 va >= VM_MAXUSER_ADDRESS) 3159 continue; 3160 ptep = pmap_pte(pm, va); 3161 if (pmap_pte_v(ptep)) 3162 printf("%x:%x ", va, *(int *)ptep); 3163 } 3164 3165} 3166 3167void 3168pmap_pvdump(vm_offset_t pa) 3169{ 3170 register pv_entry_t pv; 3171 vm_page_t m; 3172 3173 printf("pa %x", pa); 3174 m = PHYS_TO_VM_PAGE(pa); 3175 for (pv = TAILQ_FIRST(&m->md.pv_list); pv; 3176 pv = TAILQ_NEXT(pv, pv_list)) { 3177 printf(" -> pmap %p, va %x", (void *)pv->pv_pmap, pv->pv_va); 3178 pads(pv->pv_pmap); 3179 } 3180 printf(" "); 3181} 3182 3183/* N/C */ 3184#endif 3185 3186 3187/* 3188 * Allocate TLB address space tag (called ASID or TLBPID) and return it. 3189 * It takes almost as much or more time to search the TLB for a 3190 * specific ASID and flush those entries as it does to flush the entire TLB. 3191 * Therefore, when we allocate a new ASID, we just take the next number. When 3192 * we run out of numbers, we flush the TLB, increment the generation count 3193 * and start over. ASID zero is reserved for kernel use. 3194 */ 3195static void 3196pmap_asid_alloc(pmap) 3197 pmap_t pmap; 3198{ 3199 if (pmap->pm_asid[PCPU_GET(cpuid)].asid != PMAP_ASID_RESERVED && 3200 pmap->pm_asid[PCPU_GET(cpuid)].gen == PCPU_GET(asid_generation)); 3201 else { 3202 if (PCPU_GET(next_asid) == pmap_max_asid) { 3203 MIPS_TBIAP(); 3204 PCPU_SET(asid_generation, 3205 (PCPU_GET(asid_generation) + 1) & ASIDGEN_MASK); 3206 if (PCPU_GET(asid_generation) == 0) { 3207 PCPU_SET(asid_generation, 1); 3208 } 3209 PCPU_SET(next_asid, 1); /* 0 means invalid */ 3210 } 3211 pmap->pm_asid[PCPU_GET(cpuid)].asid = PCPU_GET(next_asid); 3212 pmap->pm_asid[PCPU_GET(cpuid)].gen = PCPU_GET(asid_generation); 3213 PCPU_SET(next_asid, PCPU_GET(next_asid) + 1); 3214 } 3215} 3216 3217int 3218page_is_managed(vm_offset_t pa) 3219{ 3220 vm_offset_t pgnum = mips_btop(pa); 3221 3222 if (pgnum >= first_page && (pgnum < (first_page + vm_page_array_size))) { 3223 vm_page_t m; 3224 3225 m = PHYS_TO_VM_PAGE(pa); 3226 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) 3227 return 1; 3228 } 3229 return 0; 3230} 3231 3232static int 3233init_pte_prot(vm_offset_t va, vm_page_t m, vm_prot_t prot) 3234{ 3235 int rw = 0; 3236 3237 if (!(prot & VM_PROT_WRITE)) 3238 rw = PTE_ROPAGE; 3239 else { 3240 if (va >= VM_MIN_KERNEL_ADDRESS) { 3241 /* 3242 * Don't bother to trap on kernel writes, just 3243 * record page as dirty. 3244 */ 3245 rw = PTE_RWPAGE; 3246 vm_page_dirty(m); 3247 } else if ((m->md.pv_flags & PV_TABLE_MOD) || 3248 m->dirty == VM_PAGE_BITS_ALL) 3249 rw = PTE_RWPAGE; 3250 else 3251 rw = PTE_CWPAGE; 3252 vm_page_flag_set(m, PG_WRITEABLE); 3253 } 3254 return rw; 3255} 3256 3257/* 3258 * pmap_page_is_free: 3259 * 3260 * Called when a page is freed to allow pmap to clean up 3261 * any extra state associated with the page. In this case 3262 * clear modified/referenced bits. 3263 */ 3264void 3265pmap_page_is_free(vm_page_t m) 3266{ 3267 3268 m->md.pv_flags = 0; 3269} 3270 3271/* 3272 * pmap_set_modified: 3273 * 3274 * Sets the page modified and reference bits for the specified page. 3275 */ 3276void 3277pmap_set_modified(vm_offset_t pa) 3278{ 3279 3280 PHYS_TO_VM_PAGE(pa)->md.pv_flags |= (PV_TABLE_REF | PV_TABLE_MOD); 3281} 3282 3283/* 3284 * Routine: pmap_kextract 3285 * Function: 3286 * Extract the physical page address associated 3287 * virtual address. 3288 */ 3289 /* PMAP_INLINE */ vm_offset_t 3290pmap_kextract(vm_offset_t va) 3291{ 3292 vm_offset_t pa = 0; 3293 3294 if (va < MIPS_KSEG0_START) { 3295 /* user virtual address */ 3296 pt_entry_t *ptep; 3297 3298 if (curproc && curproc->p_vmspace) { 3299 ptep = pmap_pte(&curproc->p_vmspace->vm_pmap, va); 3300 if (ptep) 3301 pa = mips_tlbpfn_to_paddr(*ptep) | 3302 (va & PAGE_MASK); 3303 } 3304 } else if (va >= MIPS_KSEG0_START && 3305 va < MIPS_KSEG1_START) 3306 pa = MIPS_KSEG0_TO_PHYS(va); 3307 else if (va >= MIPS_KSEG1_START && 3308 va < MIPS_KSEG2_START) 3309 pa = MIPS_KSEG1_TO_PHYS(va); 3310#ifdef VM_ALLOC_WIRED_TLB_PG_POOL 3311 else if (need_wired_tlb_page_pool && ((va >= VM_MIN_KERNEL_ADDRESS) && 3312 (va < (VM_MIN_KERNEL_ADDRESS + VM_KERNEL_ALLOC_OFFSET)))) 3313 pa = MIPS_KSEG0_TO_PHYS(va); 3314#endif 3315 else if (va >= MIPS_KSEG2_START && va < VM_MAX_KERNEL_ADDRESS) { 3316 pt_entry_t *ptep; 3317 3318 /* Is the kernel pmap initialized? */ 3319 if (kernel_pmap->pm_active) { 3320 if (va >= (vm_offset_t)virtual_sys_start) { 3321 /* Its inside the virtual address range */ 3322 ptep = pmap_pte(kernel_pmap, va); 3323 if (ptep) 3324 pa = mips_tlbpfn_to_paddr(*ptep) | 3325 (va & PAGE_MASK); 3326 } else { 3327 int i; 3328 3329 /* 3330 * its inside the special mapping area, I 3331 * don't think this should happen, but if it 3332 * does I want it toa all work right :-) 3333 * Note if it does happen, we assume the 3334 * caller has the lock? FIXME, this needs to 3335 * be checked FIXEM - RRS. 3336 */ 3337 for (i = 0; i < MAXCPU; i++) { 3338 if ((sysmap_lmem[i].valid1) && ((vm_offset_t)sysmap_lmem[i].CADDR1 == va)) { 3339 pa = mips_tlbpfn_to_paddr(sysmap_lmem[i].CMAP1); 3340 break; 3341 } 3342 if ((sysmap_lmem[i].valid2) && ((vm_offset_t)sysmap_lmem[i].CADDR2 == va)) { 3343 pa = mips_tlbpfn_to_paddr(sysmap_lmem[i].CMAP2); 3344 break; 3345 } 3346 } 3347 } 3348 } 3349 } 3350 return pa; 3351} 3352 3353void 3354pmap_flush_pvcache(vm_page_t m) 3355{ 3356 pv_entry_t pv; 3357 3358 if (m != NULL) { 3359 for (pv = TAILQ_FIRST(&m->md.pv_list); pv; 3360 pv = TAILQ_NEXT(pv, pv_list)) { 3361 mips_dcache_wbinv_range_index(pv->pv_va, NBPG); 3362 } 3363 } 3364} 3365 3366void 3367pmap_save_tlb(void) 3368{ 3369 int tlbno, cpu; 3370 3371 cpu = PCPU_GET(cpuid); 3372 3373 for (tlbno = 0; tlbno < num_tlbentries; ++tlbno) 3374 MachTLBRead(tlbno, &tlbstash[cpu][tlbno]); 3375} 3376 3377#ifdef DDB 3378#include <ddb/ddb.h> 3379 3380DB_SHOW_COMMAND(tlb, ddb_dump_tlb) 3381{ 3382 int cpu, tlbno; 3383 struct tlb *tlb; 3384 3385 if (have_addr) 3386 cpu = ((addr >> 4) % 16) * 10 + (addr % 16); 3387 else 3388 cpu = PCPU_GET(cpuid); 3389 3390 if (cpu < 0 || cpu >= mp_ncpus) { 3391 db_printf("Invalid CPU %d\n", cpu); 3392 return; 3393 } else 3394 db_printf("CPU %d:\n", cpu); 3395 3396 if (cpu == PCPU_GET(cpuid)) 3397 pmap_save_tlb(); 3398 3399 for (tlbno = 0; tlbno < num_tlbentries; ++tlbno) { 3400 tlb = &tlbstash[cpu][tlbno]; 3401 if (tlb->tlb_lo0 & PTE_V || tlb->tlb_lo1 & PTE_V) { 3402 printf("TLB %2d vad 0x%0lx ", 3403 tlbno, (long)(tlb->tlb_hi & 0xffffff00)); 3404 } else { 3405 printf("TLB*%2d vad 0x%0lx ", 3406 tlbno, (long)(tlb->tlb_hi & 0xffffff00)); 3407 } 3408 printf("0=0x%0lx ", pfn_to_vad((long)tlb->tlb_lo0)); 3409 printf("%c", tlb->tlb_lo0 & PTE_V ? 'V' : '-'); 3410 printf("%c", tlb->tlb_lo0 & PTE_M ? 'M' : '-'); 3411 printf("%c", tlb->tlb_lo0 & PTE_G ? 'G' : '-'); 3412 printf(" atr %x ", (tlb->tlb_lo0 >> 3) & 7); 3413 printf("1=0x%0lx ", pfn_to_vad((long)tlb->tlb_lo1)); 3414 printf("%c", tlb->tlb_lo1 & PTE_V ? 'V' : '-'); 3415 printf("%c", tlb->tlb_lo1 & PTE_M ? 'M' : '-'); 3416 printf("%c", tlb->tlb_lo1 & PTE_G ? 'G' : '-'); 3417 printf(" atr %x ", (tlb->tlb_lo1 >> 3) & 7); 3418 printf(" sz=%x pid=%x\n", tlb->tlb_mask, 3419 (tlb->tlb_hi & 0x000000ff)); 3420 } 3421} 3422#endif /* DDB */ 3423