1/*- 2 * Copyright(c) 2002-2011 Exar Corp. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification are permitted provided the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Exar Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31/*$FreeBSD$*/ 32 33#ifndef VXGE_HAL_DEVICE_H 34#define VXGE_HAL_DEVICE_H 35 36__EXTERN_BEGIN_DECLS 37 38struct __hal_mrpcim_t; 39struct __hal_srpcim_t; 40 41/* 42 * vxge_hal_vpd_data_t 43 * 44 * Represents vpd capabilty structure 45 */ 46typedef struct vxge_hal_vpd_data_t { 47 u8 product_name[VXGE_HAL_VPD_LEN]; 48 u8 serial_num[VXGE_HAL_VPD_LEN]; 49} vxge_hal_vpd_data_t; 50 51#if defined(VXGE_TRACE_INTO_CIRCULAR_ARR) 52/* 53 * __hal_tracebuf_t 54 * 55 * HAL trace buffer object. 56 */ 57typedef struct __hal_tracebuf_t { 58 u8 *data; 59 u64 wrapped_count; 60 volatile u32 offset; 61 u32 size; 62} __hal_tracebuf_t; 63#endif 64 65/* 66 * __hal_msix_map_t 67 * 68 * HAL msix to vpath map. 69 */ 70typedef struct __hal_msix_map_t { 71 u32 vp_id; 72 u32 int_num; 73} __hal_msix_map_t; 74 75/* 76 * __hal_device_t 77 * 78 * HAL device object. Represents X3100. 79 */ 80typedef struct __hal_device_t { 81 vxge_hal_device_t header; 82 u32 host_type; 83 u32 vh_id; 84 u32 func_id; 85 u32 srpcim_id; 86 u32 access_rights; 87#define VXGE_HAL_DEVICE_ACCESS_RIGHT_VPATH 0x1 88#define VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM 0x2 89#define VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM 0x4 90 u32 ifmsg_seqno; 91 u32 manager_up; 92 vxge_hal_pci_config_t pci_config_space; 93 vxge_hal_pci_config_t pci_config_space_bios; 94 vxge_hal_pci_caps_offset_t pci_caps; 95 vxge_hal_pci_e_caps_offset_t pci_e_caps; 96 vxge_hal_pci_e_ext_caps_offset_t pci_e_ext_caps; 97 vxge_hal_legacy_reg_t *legacy_reg; 98 vxge_hal_toc_reg_t *toc_reg; 99 vxge_hal_common_reg_t *common_reg; 100 vxge_hal_memrepair_reg_t *memrepair_reg; 101 vxge_hal_pcicfgmgmt_reg_t 102 *pcicfgmgmt_reg[VXGE_HAL_TITAN_PCICFGMGMT_REG_SPACES]; 103 vxge_hal_mrpcim_reg_t *mrpcim_reg; 104 vxge_hal_srpcim_reg_t 105 *srpcim_reg[VXGE_HAL_TITAN_SRPCIM_REG_SPACES]; 106 vxge_hal_vpmgmt_reg_t 107 *vpmgmt_reg[VXGE_HAL_TITAN_VPMGMT_REG_SPACES]; 108 vxge_hal_vpath_reg_t 109 *vpath_reg[VXGE_HAL_TITAN_VPATH_REG_SPACES]; 110 u8 *kdfc; 111 u8 *usdc; 112 __hal_virtualpath_t 113 virtual_paths[VXGE_HAL_MAX_VIRTUAL_PATHS]; 114 u64 vpath_assignments; 115 u64 vpaths_deployed; 116 u32 first_vp_id; 117 u64 tim_int_mask0[4]; 118 u32 tim_int_mask1[4]; 119 __hal_msix_map_t 120 msix_map[VXGE_HAL_MAX_VIRTUAL_PATHS * VXGE_HAL_VPATH_MSIX_MAX]; 121 struct __hal_srpcim_t *srpcim; 122 struct __hal_mrpcim_t *mrpcim; 123 __hal_blockpool_t block_pool; 124 vxge_list_t pending_channel_list; 125 spinlock_t pending_channel_lock; 126 vxge_hal_device_stats_t stats; 127 volatile u32 msix_enabled; 128 volatile u32 hw_is_initialized; 129 volatile int device_resetting; 130 volatile int is_promisc; 131 int tti_enabled; 132 spinlock_t titan_post_lock; 133 u32 mtu_first_time_set; 134 char *dump_buf; 135#if defined(VXGE_TRACE_INTO_CIRCULAR_ARR) 136 __hal_tracebuf_t trace_buf; 137#endif 138 volatile u32 in_poll; 139 u32 d_err_mask; 140 u32 d_info_mask; 141 u32 d_trace_mask; 142} __hal_device_t; 143 144/* 145 * I2C device id. Used in I2C control register for accessing EEPROM device 146 * memory. 147 */ 148#define VXGE_DEV_ID 5 149 150#define VXGE_HAL_DEVICE_MANAGER_STATE_SET(hldev, wmsg) { \ 151 ((__hal_device_t *)hldev)->manager_up = \ 152 __hal_ifmsg_is_manager_up(wmsg); \ 153} 154 155#define VXGE_HAL_DEVICE_LINK_STATE_SET(hldev, ls) { \ 156 ((vxge_hal_device_t *)hldev)->link_state = ls; \ 157} 158 159#define VXGE_HAL_DEVICE_DATA_RATE_SET(hldev, dr) { \ 160 ((vxge_hal_device_t *)hldev)->data_rate = dr; \ 161} 162 163#define VXGE_HAL_DEVICE_TIM_INT_MASK_SET(hldev, i) { \ 164 if (i < 16) { \ 165 ((__hal_device_t *)hldev)->tim_int_mask0[0] |= \ 166 vBIT(0x8, (i*4), 4); \ 167 ((__hal_device_t *)hldev)->tim_int_mask0[1] |= \ 168 vBIT(0x4, (i*4), 4); \ 169 ((__hal_device_t *)hldev)->tim_int_mask0[3] |= \ 170 vBIT(0x1, (i*4), 4); \ 171 } else { \ 172 ((__hal_device_t *)hldev)->tim_int_mask1[0] = 0x80000000; \ 173 ((__hal_device_t *)hldev)->tim_int_mask1[1] = 0x40000000; \ 174 ((__hal_device_t *)hldev)->tim_int_mask1[3] = 0x10000000; \ 175 } \ 176} 177 178#define VXGE_HAL_DEVICE_TIM_INT_MASK_RESET(hldev, i) { \ 179 if (i < 16) { \ 180 ((__hal_device_t *)hldev)->tim_int_mask0[0] &= \ 181 ~vBIT(0x8, (i*4), 4); \ 182 ((__hal_device_t *)hldev)->tim_int_mask0[1] &= \ 183 ~vBIT(0x4, (i*4), 4); \ 184 ((__hal_device_t *)hldev)->tim_int_mask0[3] &= \ 185 ~vBIT(0x1, (i*4), 4); \ 186 } else { \ 187 ((__hal_device_t *)hldev)->tim_int_mask1[0] = 0; \ 188 ((__hal_device_t *)hldev)->tim_int_mask1[1] = 0; \ 189 ((__hal_device_t *)hldev)->tim_int_mask1[3] = 0; \ 190 } \ 191} 192 193/* ========================== PRIVATE API ================================= */ 194 195void 196vxge_hal_pio_mem_write32_upper(pci_dev_h pdev, 197 pci_reg_h regh, 198 u32 val, 199 void *addr); 200 201void 202vxge_hal_pio_mem_write32_lower(pci_dev_h pdev, 203 pci_reg_h regh, 204 u32 val, 205 void *addr); 206 207void 208__hal_device_event_queued(void *data, 209 u32 event_type); 210 211void 212__hal_device_pci_caps_list_process(__hal_device_t *hldev); 213 214void 215__hal_device_pci_e_init(__hal_device_t *hldev); 216 217vxge_hal_status_e 218vxge_hal_device_register_poll(pci_dev_h pdev, 219 pci_reg_h regh, 220 u64 *reg, 221 u32 op, 222 u64 mask, 223 u32 max_millis); 224 225vxge_hal_status_e 226__hal_device_register_stall(pci_dev_h pdev, 227 pci_reg_h regh, 228 u64 *reg, 229 u32 op, 230 u64 mask, 231 u32 max_millis); 232 233vxge_hal_status_e 234__hal_device_reg_addr_get(__hal_device_t *hldev); 235 236void 237__hal_device_id_get(__hal_device_t *hldev); 238 239u32 240__hal_device_access_rights_get(u32 host_type, u32 func_id); 241 242void 243__hal_device_host_info_get(__hal_device_t *hldev); 244 245vxge_hal_status_e 246__hal_device_hw_initialize(__hal_device_t *hldev); 247 248vxge_hal_status_e 249__hal_device_reset(__hal_device_t *hldev); 250 251vxge_hal_status_e 252__hal_device_handle_link_up_ind(__hal_device_t *hldev); 253 254vxge_hal_status_e 255__hal_device_handle_link_down_ind(__hal_device_t *hldev); 256 257void 258__hal_device_handle_error( 259 __hal_device_t *hldev, 260 u32 vp_id, 261 vxge_hal_event_e type); 262 263__EXTERN_END_DECLS 264 265#endif /* VXGE_HAL_DEVICE_H */ 266