1/*- 2 * Copyright (c) 2006 Sam Leffler, Errno Consulting 3 * Copyright (c) 2008-2009 Weongyo Jeong <weongyo@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 13 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 14 * redistribution must be conditioned upon including a substantially 15 * similar Disclaimer requirement for further binary redistribution. 16 * 17 * NO WARRANTY 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 21 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 22 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 23 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 26 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 * THE POSSIBILITY OF SUCH DAMAGES. 29 */ 30 31/* 32 * This driver is distantly derived from a driver of the same name 33 * by Damien Bergamini. The original copyright is included below: 34 * 35 * Copyright (c) 2006 36 * Damien Bergamini <damien.bergamini@free.fr> 37 * 38 * Permission to use, copy, modify, and distribute this software for any 39 * purpose with or without fee is hereby granted, provided that the above 40 * copyright notice and this permission notice appear in all copies. 41 * 42 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 43 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 44 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 45 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 46 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 47 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 48 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 49 */ 50 51#include <sys/cdefs.h> 52__FBSDID("$FreeBSD$"); 53 54/*- 55 * Driver for Atheros AR5523 USB parts. 56 * 57 * The driver requires firmware to be loaded into the device. This 58 * is done on device discovery from a user application (uathload) 59 * that is launched by devd when a device with suitable product ID 60 * is recognized. Once firmware has been loaded the device will 61 * reset the USB port and re-attach with the original product ID+1 62 * and this driver will be attached. The firmware is licensed for 63 * general use (royalty free) and may be incorporated in products. 64 * Note that the firmware normally packaged with the NDIS drivers 65 * for these devices does not work in this way and so does not work 66 * with this driver. 67 */ 68#include <sys/param.h> 69#include <sys/sockio.h> 70#include <sys/sysctl.h> 71#include <sys/lock.h> 72#include <sys/mutex.h> 73#include <sys/mbuf.h> 74#include <sys/kernel.h> 75#include <sys/socket.h> 76#include <sys/systm.h> 77#include <sys/malloc.h> 78#include <sys/module.h> 79#include <sys/bus.h> 80#include <sys/endian.h> 81#include <sys/kdb.h> 82 83#include <machine/bus.h> 84#include <machine/resource.h> 85#include <sys/rman.h> 86 87#include <net/bpf.h> 88#include <net/if.h> 89#include <net/if_arp.h> 90#include <net/ethernet.h> 91#include <net/if_dl.h> 92#include <net/if_media.h> 93#include <net/if_types.h> 94 95#ifdef INET 96#include <netinet/in.h> 97#include <netinet/in_systm.h> 98#include <netinet/in_var.h> 99#include <netinet/if_ether.h> 100#include <netinet/ip.h> 101#endif 102 103#include <net80211/ieee80211_var.h> 104#include <net80211/ieee80211_regdomain.h> 105#include <net80211/ieee80211_radiotap.h> 106 107#include <dev/usb/usb.h> 108#include <dev/usb/usbdi.h> 109#include "usbdevs.h" 110 111#include <dev/usb/wlan/if_uathreg.h> 112#include <dev/usb/wlan/if_uathvar.h> 113 114static SYSCTL_NODE(_hw_usb, OID_AUTO, uath, CTLFLAG_RW, 0, "USB Atheros"); 115 116static int uath_countrycode = CTRY_DEFAULT; /* country code */ 117SYSCTL_INT(_hw_usb_uath, OID_AUTO, countrycode, CTLFLAG_RW | CTLFLAG_TUN, &uath_countrycode, 118 0, "country code"); 119TUNABLE_INT("hw.usb.uath.countrycode", &uath_countrycode); 120static int uath_regdomain = 0; /* regulatory domain */ 121SYSCTL_INT(_hw_usb_uath, OID_AUTO, regdomain, CTLFLAG_RD, &uath_regdomain, 122 0, "regulatory domain"); 123 124#ifdef UATH_DEBUG 125int uath_debug = 0; 126SYSCTL_INT(_hw_usb_uath, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN, &uath_debug, 0, 127 "uath debug level"); 128TUNABLE_INT("hw.usb.uath.debug", &uath_debug); 129enum { 130 UATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 131 UATH_DEBUG_XMIT_DUMP = 0x00000002, /* xmit dump */ 132 UATH_DEBUG_RECV = 0x00000004, /* basic recv operation */ 133 UATH_DEBUG_TX_PROC = 0x00000008, /* tx ISR proc */ 134 UATH_DEBUG_RX_PROC = 0x00000010, /* rx ISR proc */ 135 UATH_DEBUG_RECV_ALL = 0x00000020, /* trace all frames (beacons) */ 136 UATH_DEBUG_INIT = 0x00000040, /* initialization of dev */ 137 UATH_DEBUG_DEVCAP = 0x00000080, /* dev caps */ 138 UATH_DEBUG_CMDS = 0x00000100, /* commands */ 139 UATH_DEBUG_CMDS_DUMP = 0x00000200, /* command buffer dump */ 140 UATH_DEBUG_RESET = 0x00000400, /* reset processing */ 141 UATH_DEBUG_STATE = 0x00000800, /* 802.11 state transitions */ 142 UATH_DEBUG_MULTICAST = 0x00001000, /* multicast */ 143 UATH_DEBUG_WME = 0x00002000, /* WME */ 144 UATH_DEBUG_CHANNEL = 0x00004000, /* channel */ 145 UATH_DEBUG_RATES = 0x00008000, /* rates */ 146 UATH_DEBUG_CRYPTO = 0x00010000, /* crypto */ 147 UATH_DEBUG_LED = 0x00020000, /* LED */ 148 UATH_DEBUG_ANY = 0xffffffff 149}; 150#define DPRINTF(sc, m, fmt, ...) do { \ 151 if (sc->sc_debug & (m)) \ 152 printf(fmt, __VA_ARGS__); \ 153} while (0) 154#else 155#define DPRINTF(sc, m, fmt, ...) do { \ 156 (void) sc; \ 157} while (0) 158#endif 159 160/* unaligned little endian access */ 161#define LE_READ_2(p) \ 162 ((u_int16_t) \ 163 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8))) 164#define LE_READ_4(p) \ 165 ((u_int32_t) \ 166 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \ 167 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24))) 168 169/* recognized device vendors/products */ 170static const STRUCT_USB_HOST_ID uath_devs[] = { 171#define UATH_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 172 UATH_DEV(ACCTON, SMCWUSBTG2), 173 UATH_DEV(ATHEROS, AR5523), 174 UATH_DEV(ATHEROS2, AR5523_1), 175 UATH_DEV(ATHEROS2, AR5523_2), 176 UATH_DEV(ATHEROS2, AR5523_3), 177 UATH_DEV(CONCEPTRONIC, AR5523_1), 178 UATH_DEV(CONCEPTRONIC, AR5523_2), 179 UATH_DEV(DLINK, DWLAG122), 180 UATH_DEV(DLINK, DWLAG132), 181 UATH_DEV(DLINK, DWLG132), 182 UATH_DEV(DLINK2, DWA120), 183 UATH_DEV(GIGASET, AR5523), 184 UATH_DEV(GIGASET, SMCWUSBTG), 185 UATH_DEV(GLOBALSUN, AR5523_1), 186 UATH_DEV(GLOBALSUN, AR5523_2), 187 UATH_DEV(NETGEAR, WG111U), 188 UATH_DEV(NETGEAR3, WG111T), 189 UATH_DEV(NETGEAR3, WPN111), 190 UATH_DEV(NETGEAR3, WPN111_2), 191 UATH_DEV(UMEDIA, TEW444UBEU), 192 UATH_DEV(UMEDIA, AR5523_2), 193 UATH_DEV(WISTRONNEWEB, AR5523_1), 194 UATH_DEV(WISTRONNEWEB, AR5523_2), 195 UATH_DEV(ZCOM, AR5523) 196#undef UATH_DEV 197}; 198 199static usb_callback_t uath_intr_rx_callback; 200static usb_callback_t uath_intr_tx_callback; 201static usb_callback_t uath_bulk_rx_callback; 202static usb_callback_t uath_bulk_tx_callback; 203 204static const struct usb_config uath_usbconfig[UATH_N_XFERS] = { 205 [UATH_INTR_RX] = { 206 .type = UE_BULK, 207 .endpoint = 0x1, 208 .direction = UE_DIR_IN, 209 .bufsize = UATH_MAX_CMDSZ, 210 .flags = { 211 .pipe_bof = 1, 212 .short_xfer_ok = 1 213 }, 214 .callback = uath_intr_rx_callback 215 }, 216 [UATH_INTR_TX] = { 217 .type = UE_BULK, 218 .endpoint = 0x1, 219 .direction = UE_DIR_OUT, 220 .bufsize = UATH_MAX_CMDSZ * UATH_CMD_LIST_COUNT, 221 .flags = { 222 .force_short_xfer = 1, 223 .pipe_bof = 1, 224 }, 225 .callback = uath_intr_tx_callback, 226 .timeout = UATH_CMD_TIMEOUT 227 }, 228 [UATH_BULK_RX] = { 229 .type = UE_BULK, 230 .endpoint = 0x2, 231 .direction = UE_DIR_IN, 232 .bufsize = MCLBYTES, 233 .flags = { 234 .ext_buffer = 1, 235 .pipe_bof = 1, 236 .short_xfer_ok = 1 237 }, 238 .callback = uath_bulk_rx_callback 239 }, 240 [UATH_BULK_TX] = { 241 .type = UE_BULK, 242 .endpoint = 0x2, 243 .direction = UE_DIR_OUT, 244 .bufsize = UATH_MAX_TXBUFSZ * UATH_TX_DATA_LIST_COUNT, 245 .flags = { 246 .force_short_xfer = 1, 247 .pipe_bof = 1 248 }, 249 .callback = uath_bulk_tx_callback, 250 .timeout = UATH_DATA_TIMEOUT 251 } 252}; 253 254static struct ieee80211vap *uath_vap_create(struct ieee80211com *, 255 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 256 const uint8_t [IEEE80211_ADDR_LEN], 257 const uint8_t [IEEE80211_ADDR_LEN]); 258static void uath_vap_delete(struct ieee80211vap *); 259static int uath_alloc_cmd_list(struct uath_softc *, struct uath_cmd []); 260static void uath_free_cmd_list(struct uath_softc *, struct uath_cmd []); 261static int uath_host_available(struct uath_softc *); 262static int uath_get_capability(struct uath_softc *, uint32_t, uint32_t *); 263static int uath_get_devcap(struct uath_softc *); 264static struct uath_cmd * 265 uath_get_cmdbuf(struct uath_softc *); 266static int uath_cmd_read(struct uath_softc *, uint32_t, const void *, 267 int, void *, int, int); 268static int uath_cmd_write(struct uath_softc *, uint32_t, const void *, 269 int, int); 270static void uath_stat(void *); 271#ifdef UATH_DEBUG 272static void uath_dump_cmd(const uint8_t *, int, char); 273static const char * 274 uath_codename(int); 275#endif 276static int uath_get_devstatus(struct uath_softc *, 277 uint8_t macaddr[IEEE80211_ADDR_LEN]); 278static int uath_get_status(struct uath_softc *, uint32_t, void *, int); 279static int uath_alloc_rx_data_list(struct uath_softc *); 280static int uath_alloc_tx_data_list(struct uath_softc *); 281static void uath_free_rx_data_list(struct uath_softc *); 282static void uath_free_tx_data_list(struct uath_softc *); 283static int uath_init_locked(void *); 284static void uath_init(void *); 285static void uath_stop_locked(struct ifnet *); 286static void uath_stop(struct ifnet *); 287static int uath_ioctl(struct ifnet *, u_long, caddr_t); 288static void uath_start(struct ifnet *); 289static int uath_raw_xmit(struct ieee80211_node *, struct mbuf *, 290 const struct ieee80211_bpf_params *); 291static void uath_scan_start(struct ieee80211com *); 292static void uath_scan_end(struct ieee80211com *); 293static void uath_set_channel(struct ieee80211com *); 294static void uath_update_mcast(struct ifnet *); 295static void uath_update_promisc(struct ifnet *); 296static int uath_config(struct uath_softc *, uint32_t, uint32_t); 297static int uath_config_multi(struct uath_softc *, uint32_t, const void *, 298 int); 299static int uath_switch_channel(struct uath_softc *, 300 struct ieee80211_channel *); 301static int uath_set_rxfilter(struct uath_softc *, uint32_t, uint32_t); 302static void uath_watchdog(void *); 303static void uath_abort_xfers(struct uath_softc *); 304static int uath_dataflush(struct uath_softc *); 305static int uath_cmdflush(struct uath_softc *); 306static int uath_flush(struct uath_softc *); 307static int uath_set_ledstate(struct uath_softc *, int); 308static int uath_set_chan(struct uath_softc *, struct ieee80211_channel *); 309static int uath_reset_tx_queues(struct uath_softc *); 310static int uath_wme_init(struct uath_softc *); 311static struct uath_data * 312 uath_getbuf(struct uath_softc *); 313static int uath_newstate(struct ieee80211vap *, enum ieee80211_state, 314 int); 315static int uath_set_key(struct uath_softc *, 316 const struct ieee80211_key *, int); 317static int uath_set_keys(struct uath_softc *, struct ieee80211vap *); 318static void uath_sysctl_node(struct uath_softc *); 319 320static int 321uath_match(device_t dev) 322{ 323 struct usb_attach_arg *uaa = device_get_ivars(dev); 324 325 if (uaa->usb_mode != USB_MODE_HOST) 326 return (ENXIO); 327 if (uaa->info.bConfigIndex != UATH_CONFIG_INDEX) 328 return (ENXIO); 329 if (uaa->info.bIfaceIndex != UATH_IFACE_INDEX) 330 return (ENXIO); 331 332 return (usbd_lookup_id_by_uaa(uath_devs, sizeof(uath_devs), uaa)); 333} 334 335static int 336uath_attach(device_t dev) 337{ 338 struct uath_softc *sc = device_get_softc(dev); 339 struct usb_attach_arg *uaa = device_get_ivars(dev); 340 struct ieee80211com *ic; 341 struct ifnet *ifp; 342 uint8_t bands, iface_index = UATH_IFACE_INDEX; /* XXX */ 343 usb_error_t error; 344 uint8_t macaddr[IEEE80211_ADDR_LEN]; 345 346 sc->sc_dev = dev; 347 sc->sc_udev = uaa->device; 348#ifdef UATH_DEBUG 349 sc->sc_debug = uath_debug; 350#endif 351 device_set_usb_desc(dev); 352 353 /* 354 * Only post-firmware devices here. 355 */ 356 mtx_init(&sc->sc_mtx, device_get_nameunit(sc->sc_dev), MTX_NETWORK_LOCK, 357 MTX_DEF); 358 callout_init(&sc->stat_ch, 0); 359 callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0); 360 361 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 362 uath_usbconfig, UATH_N_XFERS, sc, &sc->sc_mtx); 363 if (error) { 364 device_printf(dev, "could not allocate USB transfers, " 365 "err=%s\n", usbd_errstr(error)); 366 goto fail; 367 } 368 369 sc->sc_cmd_dma_buf = 370 usbd_xfer_get_frame_buffer(sc->sc_xfer[UATH_INTR_TX], 0); 371 sc->sc_tx_dma_buf = 372 usbd_xfer_get_frame_buffer(sc->sc_xfer[UATH_BULK_TX], 0); 373 374 /* 375 * Setup buffers for firmware commands. 376 */ 377 error = uath_alloc_cmd_list(sc, sc->sc_cmd); 378 if (error != 0) { 379 device_printf(sc->sc_dev, 380 "could not allocate Tx command list\n"); 381 goto fail1; 382 } 383 384 /* 385 * We're now ready to send+receive firmware commands. 386 */ 387 UATH_LOCK(sc); 388 error = uath_host_available(sc); 389 if (error != 0) { 390 device_printf(sc->sc_dev, "could not initialize adapter\n"); 391 goto fail3; 392 } 393 error = uath_get_devcap(sc); 394 if (error != 0) { 395 device_printf(sc->sc_dev, 396 "could not get device capabilities\n"); 397 goto fail3; 398 } 399 UATH_UNLOCK(sc); 400 401 /* Create device sysctl node. */ 402 uath_sysctl_node(sc); 403 404 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 405 if (ifp == NULL) { 406 device_printf(sc->sc_dev, "can not allocate ifnet\n"); 407 error = ENXIO; 408 goto fail2; 409 } 410 411 UATH_LOCK(sc); 412 error = uath_get_devstatus(sc, macaddr); 413 if (error != 0) { 414 device_printf(sc->sc_dev, "could not get device status\n"); 415 goto fail4; 416 } 417 418 /* 419 * Allocate xfers for Rx/Tx data pipes. 420 */ 421 error = uath_alloc_rx_data_list(sc); 422 if (error != 0) { 423 device_printf(sc->sc_dev, "could not allocate Rx data list\n"); 424 goto fail4; 425 } 426 error = uath_alloc_tx_data_list(sc); 427 if (error != 0) { 428 device_printf(sc->sc_dev, "could not allocate Tx data list\n"); 429 goto fail4; 430 } 431 UATH_UNLOCK(sc); 432 433 ifp->if_softc = sc; 434 if_initname(ifp, "uath", device_get_unit(sc->sc_dev)); 435 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 436 ifp->if_init = uath_init; 437 ifp->if_ioctl = uath_ioctl; 438 ifp->if_start = uath_start; 439 /* XXX UATH_TX_DATA_LIST_COUNT */ 440 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 441 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 442 IFQ_SET_READY(&ifp->if_snd); 443 444 ic = ifp->if_l2com; 445 ic->ic_ifp = ifp; 446 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 447 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ 448 449 /* set device capabilities */ 450 ic->ic_caps = 451 IEEE80211_C_STA | /* station mode */ 452 IEEE80211_C_MONITOR | /* monitor mode supported */ 453 IEEE80211_C_TXPMGT | /* tx power management */ 454 IEEE80211_C_SHPREAMBLE | /* short preamble supported */ 455 IEEE80211_C_SHSLOT | /* short slot time supported */ 456 IEEE80211_C_WPA | /* 802.11i */ 457 IEEE80211_C_BGSCAN | /* capable of bg scanning */ 458 IEEE80211_C_TXFRAG; /* handle tx frags */ 459 460 /* put a regulatory domain to reveal informations. */ 461 uath_regdomain = sc->sc_devcap.regDomain; 462 463 bands = 0; 464 setbit(&bands, IEEE80211_MODE_11B); 465 setbit(&bands, IEEE80211_MODE_11G); 466 if ((sc->sc_devcap.analog5GhzRevision & 0xf0) == 0x30) 467 setbit(&bands, IEEE80211_MODE_11A); 468 /* XXX turbo */ 469 ieee80211_init_channels(ic, NULL, &bands); 470 471 ieee80211_ifattach(ic, macaddr); 472 ic->ic_raw_xmit = uath_raw_xmit; 473 ic->ic_scan_start = uath_scan_start; 474 ic->ic_scan_end = uath_scan_end; 475 ic->ic_set_channel = uath_set_channel; 476 477 ic->ic_vap_create = uath_vap_create; 478 ic->ic_vap_delete = uath_vap_delete; 479 ic->ic_update_mcast = uath_update_mcast; 480 ic->ic_update_promisc = uath_update_promisc; 481 482 ieee80211_radiotap_attach(ic, 483 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 484 UATH_TX_RADIOTAP_PRESENT, 485 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 486 UATH_RX_RADIOTAP_PRESENT); 487 488 if (bootverbose) 489 ieee80211_announce(ic); 490 491 return (0); 492 493fail4: if_free(ifp); 494fail3: UATH_UNLOCK(sc); 495fail2: uath_free_cmd_list(sc, sc->sc_cmd); 496fail1: usbd_transfer_unsetup(sc->sc_xfer, UATH_N_XFERS); 497fail: 498 return (error); 499} 500 501static int 502uath_detach(device_t dev) 503{ 504 struct uath_softc *sc = device_get_softc(dev); 505 struct ifnet *ifp = sc->sc_ifp; 506 struct ieee80211com *ic = ifp->if_l2com; 507 unsigned int x; 508 509 /* 510 * Prevent further allocations from RX/TX/CMD 511 * data lists and ioctls 512 */ 513 UATH_LOCK(sc); 514 sc->sc_flags |= UATH_FLAG_INVALID; 515 516 STAILQ_INIT(&sc->sc_rx_active); 517 STAILQ_INIT(&sc->sc_rx_inactive); 518 519 STAILQ_INIT(&sc->sc_tx_active); 520 STAILQ_INIT(&sc->sc_tx_inactive); 521 STAILQ_INIT(&sc->sc_tx_pending); 522 523 STAILQ_INIT(&sc->sc_cmd_active); 524 STAILQ_INIT(&sc->sc_cmd_pending); 525 STAILQ_INIT(&sc->sc_cmd_waiting); 526 STAILQ_INIT(&sc->sc_cmd_inactive); 527 UATH_UNLOCK(sc); 528 529 uath_stop(ifp); 530 531 callout_drain(&sc->stat_ch); 532 callout_drain(&sc->watchdog_ch); 533 534 /* drain USB transfers */ 535 for (x = 0; x != UATH_N_XFERS; x++) 536 usbd_transfer_drain(sc->sc_xfer[x]); 537 538 /* free data buffers */ 539 UATH_LOCK(sc); 540 uath_free_rx_data_list(sc); 541 uath_free_tx_data_list(sc); 542 uath_free_cmd_list(sc, sc->sc_cmd); 543 UATH_UNLOCK(sc); 544 545 /* free USB transfers and some data buffers */ 546 usbd_transfer_unsetup(sc->sc_xfer, UATH_N_XFERS); 547 548 ieee80211_ifdetach(ic); 549 if_free(ifp); 550 mtx_destroy(&sc->sc_mtx); 551 return (0); 552} 553 554static void 555uath_free_cmd_list(struct uath_softc *sc, struct uath_cmd cmds[]) 556{ 557 int i; 558 559 for (i = 0; i != UATH_CMD_LIST_COUNT; i++) 560 cmds[i].buf = NULL; 561} 562 563static int 564uath_alloc_cmd_list(struct uath_softc *sc, struct uath_cmd cmds[]) 565{ 566 int i; 567 568 STAILQ_INIT(&sc->sc_cmd_active); 569 STAILQ_INIT(&sc->sc_cmd_pending); 570 STAILQ_INIT(&sc->sc_cmd_waiting); 571 STAILQ_INIT(&sc->sc_cmd_inactive); 572 573 for (i = 0; i != UATH_CMD_LIST_COUNT; i++) { 574 struct uath_cmd *cmd = &cmds[i]; 575 576 cmd->sc = sc; /* backpointer for callbacks */ 577 cmd->msgid = i; 578 cmd->buf = ((uint8_t *)sc->sc_cmd_dma_buf) + 579 (i * UATH_MAX_CMDSZ); 580 STAILQ_INSERT_TAIL(&sc->sc_cmd_inactive, cmd, next); 581 UATH_STAT_INC(sc, st_cmd_inactive); 582 } 583 return (0); 584} 585 586static int 587uath_host_available(struct uath_softc *sc) 588{ 589 struct uath_cmd_host_available setup; 590 591 UATH_ASSERT_LOCKED(sc); 592 593 /* inform target the host is available */ 594 setup.sw_ver_major = htobe32(ATH_SW_VER_MAJOR); 595 setup.sw_ver_minor = htobe32(ATH_SW_VER_MINOR); 596 setup.sw_ver_patch = htobe32(ATH_SW_VER_PATCH); 597 setup.sw_ver_build = htobe32(ATH_SW_VER_BUILD); 598 return uath_cmd_read(sc, WDCMSG_HOST_AVAILABLE, 599 &setup, sizeof setup, NULL, 0, 0); 600} 601 602#ifdef UATH_DEBUG 603static void 604uath_dump_cmd(const uint8_t *buf, int len, char prefix) 605{ 606 const char *sep = ""; 607 int i; 608 609 for (i = 0; i < len; i++) { 610 if ((i % 16) == 0) { 611 printf("%s%c ", sep, prefix); 612 sep = "\n"; 613 } 614 else if ((i % 4) == 0) 615 printf(" "); 616 printf("%02x", buf[i]); 617 } 618 printf("\n"); 619} 620 621static const char * 622uath_codename(int code) 623{ 624#define N(a) (sizeof(a)/sizeof(a[0])) 625 static const char *names[] = { 626 "0x00", 627 "HOST_AVAILABLE", 628 "BIND", 629 "TARGET_RESET", 630 "TARGET_GET_CAPABILITY", 631 "TARGET_SET_CONFIG", 632 "TARGET_GET_STATUS", 633 "TARGET_GET_STATS", 634 "TARGET_START", 635 "TARGET_STOP", 636 "TARGET_ENABLE", 637 "TARGET_DISABLE", 638 "CREATE_CONNECTION", 639 "UPDATE_CONNECT_ATTR", 640 "DELETE_CONNECT", 641 "SEND", 642 "FLUSH", 643 "STATS_UPDATE", 644 "BMISS", 645 "DEVICE_AVAIL", 646 "SEND_COMPLETE", 647 "DATA_AVAIL", 648 "SET_PWR_MODE", 649 "BMISS_ACK", 650 "SET_LED_STEADY", 651 "SET_LED_BLINK", 652 "SETUP_BEACON_DESC", 653 "BEACON_INIT", 654 "RESET_KEY_CACHE", 655 "RESET_KEY_CACHE_ENTRY", 656 "SET_KEY_CACHE_ENTRY", 657 "SET_DECOMP_MASK", 658 "SET_REGULATORY_DOMAIN", 659 "SET_LED_STATE", 660 "WRITE_ASSOCID", 661 "SET_STA_BEACON_TIMERS", 662 "GET_TSF", 663 "RESET_TSF", 664 "SET_ADHOC_MODE", 665 "SET_BASIC_RATE", 666 "MIB_CONTROL", 667 "GET_CHANNEL_DATA", 668 "GET_CUR_RSSI", 669 "SET_ANTENNA_SWITCH", 670 "0x2c", "0x2d", "0x2e", 671 "USE_SHORT_SLOT_TIME", 672 "SET_POWER_MODE", 673 "SETUP_PSPOLL_DESC", 674 "SET_RX_MULTICAST_FILTER", 675 "RX_FILTER", 676 "PER_CALIBRATION", 677 "RESET", 678 "DISABLE", 679 "PHY_DISABLE", 680 "SET_TX_POWER_LIMIT", 681 "SET_TX_QUEUE_PARAMS", 682 "SETUP_TX_QUEUE", 683 "RELEASE_TX_QUEUE", 684 }; 685 static char buf[8]; 686 687 if (code < N(names)) 688 return names[code]; 689 if (code == WDCMSG_SET_DEFAULT_KEY) 690 return "SET_DEFAULT_KEY"; 691 snprintf(buf, sizeof(buf), "0x%02x", code); 692 return buf; 693#undef N 694} 695#endif 696 697/* 698 * Low-level function to send read or write commands to the firmware. 699 */ 700static int 701uath_cmdsend(struct uath_softc *sc, uint32_t code, const void *idata, int ilen, 702 void *odata, int olen, int flags) 703{ 704 struct uath_cmd_hdr *hdr; 705 struct uath_cmd *cmd; 706 int error; 707 708 UATH_ASSERT_LOCKED(sc); 709 710 /* grab a xfer */ 711 cmd = uath_get_cmdbuf(sc); 712 if (cmd == NULL) { 713 device_printf(sc->sc_dev, "%s: empty inactive queue\n", 714 __func__); 715 return (ENOBUFS); 716 } 717 cmd->flags = flags; 718 /* always bulk-out a multiple of 4 bytes */ 719 cmd->buflen = roundup2(sizeof(struct uath_cmd_hdr) + ilen, 4); 720 721 hdr = (struct uath_cmd_hdr *)cmd->buf; 722 memset(hdr, 0, sizeof(struct uath_cmd_hdr)); 723 hdr->len = htobe32(cmd->buflen); 724 hdr->code = htobe32(code); 725 hdr->msgid = cmd->msgid; /* don't care about endianness */ 726 hdr->magic = htobe32((cmd->flags & UATH_CMD_FLAG_MAGIC) ? 1 << 24 : 0); 727 memcpy((uint8_t *)(hdr + 1), idata, ilen); 728 729#ifdef UATH_DEBUG 730 if (sc->sc_debug & UATH_DEBUG_CMDS) { 731 printf("%s: send %s [flags 0x%x] olen %d\n", 732 __func__, uath_codename(code), cmd->flags, olen); 733 if (sc->sc_debug & UATH_DEBUG_CMDS_DUMP) 734 uath_dump_cmd(cmd->buf, cmd->buflen, '+'); 735 } 736#endif 737 cmd->odata = odata; 738 KASSERT(odata == NULL || 739 olen < UATH_MAX_CMDSZ - sizeof(*hdr) + sizeof(uint32_t), 740 ("odata %p olen %u", odata, olen)); 741 cmd->olen = olen; 742 743 STAILQ_INSERT_TAIL(&sc->sc_cmd_pending, cmd, next); 744 UATH_STAT_INC(sc, st_cmd_pending); 745 usbd_transfer_start(sc->sc_xfer[UATH_INTR_TX]); 746 747 if (cmd->flags & UATH_CMD_FLAG_READ) { 748 usbd_transfer_start(sc->sc_xfer[UATH_INTR_RX]); 749 750 /* wait at most two seconds for command reply */ 751 error = mtx_sleep(cmd, &sc->sc_mtx, 0, "uathcmd", 2 * hz); 752 cmd->odata = NULL; /* in case reply comes too late */ 753 if (error != 0) { 754 device_printf(sc->sc_dev, "timeout waiting for reply " 755 "to cmd 0x%x (%u)\n", code, code); 756 } else if (cmd->olen != olen) { 757 device_printf(sc->sc_dev, "unexpected reply data count " 758 "to cmd 0x%x (%u), got %u, expected %u\n", 759 code, code, cmd->olen, olen); 760 error = EINVAL; 761 } 762 return (error); 763 } 764 return (0); 765} 766 767static int 768uath_cmd_read(struct uath_softc *sc, uint32_t code, const void *idata, 769 int ilen, void *odata, int olen, int flags) 770{ 771 772 flags |= UATH_CMD_FLAG_READ; 773 return uath_cmdsend(sc, code, idata, ilen, odata, olen, flags); 774} 775 776static int 777uath_cmd_write(struct uath_softc *sc, uint32_t code, const void *data, int len, 778 int flags) 779{ 780 781 flags &= ~UATH_CMD_FLAG_READ; 782 return uath_cmdsend(sc, code, data, len, NULL, 0, flags); 783} 784 785static struct uath_cmd * 786uath_get_cmdbuf(struct uath_softc *sc) 787{ 788 struct uath_cmd *uc; 789 790 UATH_ASSERT_LOCKED(sc); 791 792 uc = STAILQ_FIRST(&sc->sc_cmd_inactive); 793 if (uc != NULL) { 794 STAILQ_REMOVE_HEAD(&sc->sc_cmd_inactive, next); 795 UATH_STAT_DEC(sc, st_cmd_inactive); 796 } else 797 uc = NULL; 798 if (uc == NULL) 799 DPRINTF(sc, UATH_DEBUG_XMIT, "%s: %s\n", __func__, 800 "out of command xmit buffers"); 801 return (uc); 802} 803 804/* 805 * This function is called periodically (every second) when associated to 806 * query device statistics. 807 */ 808static void 809uath_stat(void *arg) 810{ 811 struct uath_softc *sc = arg; 812 int error; 813 814 UATH_LOCK(sc); 815 /* 816 * Send request for statistics asynchronously. The timer will be 817 * restarted when we'll get the stats notification. 818 */ 819 error = uath_cmd_write(sc, WDCMSG_TARGET_GET_STATS, NULL, 0, 820 UATH_CMD_FLAG_ASYNC); 821 if (error != 0) { 822 device_printf(sc->sc_dev, 823 "could not query stats, error %d\n", error); 824 } 825 UATH_UNLOCK(sc); 826} 827 828static int 829uath_get_capability(struct uath_softc *sc, uint32_t cap, uint32_t *val) 830{ 831 int error; 832 833 cap = htobe32(cap); 834 error = uath_cmd_read(sc, WDCMSG_TARGET_GET_CAPABILITY, 835 &cap, sizeof cap, val, sizeof(uint32_t), UATH_CMD_FLAG_MAGIC); 836 if (error != 0) { 837 device_printf(sc->sc_dev, "could not read capability %u\n", 838 be32toh(cap)); 839 return (error); 840 } 841 *val = be32toh(*val); 842 return (error); 843} 844 845static int 846uath_get_devcap(struct uath_softc *sc) 847{ 848#define GETCAP(x, v) do { \ 849 error = uath_get_capability(sc, x, &v); \ 850 if (error != 0) \ 851 return (error); \ 852 DPRINTF(sc, UATH_DEBUG_DEVCAP, \ 853 "%s: %s=0x%08x\n", __func__, #x, v); \ 854} while (0) 855 struct uath_devcap *cap = &sc->sc_devcap; 856 int error; 857 858 /* collect device capabilities */ 859 GETCAP(CAP_TARGET_VERSION, cap->targetVersion); 860 GETCAP(CAP_TARGET_REVISION, cap->targetRevision); 861 GETCAP(CAP_MAC_VERSION, cap->macVersion); 862 GETCAP(CAP_MAC_REVISION, cap->macRevision); 863 GETCAP(CAP_PHY_REVISION, cap->phyRevision); 864 GETCAP(CAP_ANALOG_5GHz_REVISION, cap->analog5GhzRevision); 865 GETCAP(CAP_ANALOG_2GHz_REVISION, cap->analog2GhzRevision); 866 867 GETCAP(CAP_REG_DOMAIN, cap->regDomain); 868 GETCAP(CAP_REG_CAP_BITS, cap->regCapBits); 869#if 0 870 /* NB: not supported in rev 1.5 */ 871 GETCAP(CAP_COUNTRY_CODE, cap->countryCode); 872#endif 873 GETCAP(CAP_WIRELESS_MODES, cap->wirelessModes); 874 GETCAP(CAP_CHAN_SPREAD_SUPPORT, cap->chanSpreadSupport); 875 GETCAP(CAP_COMPRESS_SUPPORT, cap->compressSupport); 876 GETCAP(CAP_BURST_SUPPORT, cap->burstSupport); 877 GETCAP(CAP_FAST_FRAMES_SUPPORT, cap->fastFramesSupport); 878 GETCAP(CAP_CHAP_TUNING_SUPPORT, cap->chapTuningSupport); 879 GETCAP(CAP_TURBOG_SUPPORT, cap->turboGSupport); 880 GETCAP(CAP_TURBO_PRIME_SUPPORT, cap->turboPrimeSupport); 881 GETCAP(CAP_DEVICE_TYPE, cap->deviceType); 882 GETCAP(CAP_WME_SUPPORT, cap->wmeSupport); 883 GETCAP(CAP_TOTAL_QUEUES, cap->numTxQueues); 884 GETCAP(CAP_CONNECTION_ID_MAX, cap->connectionIdMax); 885 886 GETCAP(CAP_LOW_5GHZ_CHAN, cap->low5GhzChan); 887 GETCAP(CAP_HIGH_5GHZ_CHAN, cap->high5GhzChan); 888 GETCAP(CAP_LOW_2GHZ_CHAN, cap->low2GhzChan); 889 GETCAP(CAP_HIGH_2GHZ_CHAN, cap->high2GhzChan); 890 GETCAP(CAP_TWICE_ANTENNAGAIN_5G, cap->twiceAntennaGain5G); 891 GETCAP(CAP_TWICE_ANTENNAGAIN_2G, cap->twiceAntennaGain2G); 892 893 GETCAP(CAP_CIPHER_AES_CCM, cap->supportCipherAES_CCM); 894 GETCAP(CAP_CIPHER_TKIP, cap->supportCipherTKIP); 895 GETCAP(CAP_MIC_TKIP, cap->supportMicTKIP); 896 897 cap->supportCipherWEP = 1; /* NB: always available */ 898 899 return (0); 900} 901 902static int 903uath_get_devstatus(struct uath_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) 904{ 905 int error; 906 907 /* retrieve MAC address */ 908 error = uath_get_status(sc, ST_MAC_ADDR, macaddr, IEEE80211_ADDR_LEN); 909 if (error != 0) { 910 device_printf(sc->sc_dev, "could not read MAC address\n"); 911 return (error); 912 } 913 914 error = uath_get_status(sc, ST_SERIAL_NUMBER, 915 &sc->sc_serial[0], sizeof(sc->sc_serial)); 916 if (error != 0) { 917 device_printf(sc->sc_dev, 918 "could not read device serial number\n"); 919 return (error); 920 } 921 return (0); 922} 923 924static int 925uath_get_status(struct uath_softc *sc, uint32_t which, void *odata, int olen) 926{ 927 int error; 928 929 which = htobe32(which); 930 error = uath_cmd_read(sc, WDCMSG_TARGET_GET_STATUS, 931 &which, sizeof(which), odata, olen, UATH_CMD_FLAG_MAGIC); 932 if (error != 0) 933 device_printf(sc->sc_dev, 934 "could not read EEPROM offset 0x%02x\n", be32toh(which)); 935 return (error); 936} 937 938static void 939uath_free_data_list(struct uath_softc *sc, struct uath_data data[], int ndata, 940 int fillmbuf) 941{ 942 int i; 943 944 for (i = 0; i < ndata; i++) { 945 struct uath_data *dp = &data[i]; 946 947 if (fillmbuf == 1) { 948 if (dp->m != NULL) { 949 m_freem(dp->m); 950 dp->m = NULL; 951 dp->buf = NULL; 952 } 953 } else { 954 dp->buf = NULL; 955 } 956 if (dp->ni != NULL) { 957 ieee80211_free_node(dp->ni); 958 dp->ni = NULL; 959 } 960 } 961} 962 963static int 964uath_alloc_data_list(struct uath_softc *sc, struct uath_data data[], 965 int ndata, int maxsz, void *dma_buf) 966{ 967 int i, error; 968 969 for (i = 0; i < ndata; i++) { 970 struct uath_data *dp = &data[i]; 971 972 dp->sc = sc; 973 if (dma_buf == NULL) { 974 /* XXX check maxsz */ 975 dp->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 976 if (dp->m == NULL) { 977 device_printf(sc->sc_dev, 978 "could not allocate rx mbuf\n"); 979 error = ENOMEM; 980 goto fail; 981 } 982 dp->buf = mtod(dp->m, uint8_t *); 983 } else { 984 dp->m = NULL; 985 dp->buf = ((uint8_t *)dma_buf) + (i * maxsz); 986 } 987 dp->ni = NULL; 988 } 989 990 return (0); 991 992fail: uath_free_data_list(sc, data, ndata, 1 /* free mbufs */); 993 return (error); 994} 995 996static int 997uath_alloc_rx_data_list(struct uath_softc *sc) 998{ 999 int error, i; 1000 1001 /* XXX is it enough to store the RX packet with MCLBYTES bytes? */ 1002 error = uath_alloc_data_list(sc, 1003 sc->sc_rx, UATH_RX_DATA_LIST_COUNT, MCLBYTES, 1004 NULL /* setup mbufs */); 1005 if (error != 0) 1006 return (error); 1007 1008 STAILQ_INIT(&sc->sc_rx_active); 1009 STAILQ_INIT(&sc->sc_rx_inactive); 1010 1011 for (i = 0; i < UATH_RX_DATA_LIST_COUNT; i++) { 1012 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], 1013 next); 1014 UATH_STAT_INC(sc, st_rx_inactive); 1015 } 1016 1017 return (0); 1018} 1019 1020static int 1021uath_alloc_tx_data_list(struct uath_softc *sc) 1022{ 1023 int error, i; 1024 1025 error = uath_alloc_data_list(sc, 1026 sc->sc_tx, UATH_TX_DATA_LIST_COUNT, UATH_MAX_TXBUFSZ, 1027 sc->sc_tx_dma_buf); 1028 if (error != 0) 1029 return (error); 1030 1031 STAILQ_INIT(&sc->sc_tx_active); 1032 STAILQ_INIT(&sc->sc_tx_inactive); 1033 STAILQ_INIT(&sc->sc_tx_pending); 1034 1035 for (i = 0; i < UATH_TX_DATA_LIST_COUNT; i++) { 1036 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i], 1037 next); 1038 UATH_STAT_INC(sc, st_tx_inactive); 1039 } 1040 1041 return (0); 1042} 1043 1044static void 1045uath_free_rx_data_list(struct uath_softc *sc) 1046{ 1047 uath_free_data_list(sc, sc->sc_rx, UATH_RX_DATA_LIST_COUNT, 1048 1 /* free mbufs */); 1049} 1050 1051static void 1052uath_free_tx_data_list(struct uath_softc *sc) 1053{ 1054 uath_free_data_list(sc, sc->sc_tx, UATH_TX_DATA_LIST_COUNT, 1055 0 /* no mbufs */); 1056} 1057 1058static struct ieee80211vap * 1059uath_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 1060 enum ieee80211_opmode opmode, int flags, 1061 const uint8_t bssid[IEEE80211_ADDR_LEN], 1062 const uint8_t mac[IEEE80211_ADDR_LEN]) 1063{ 1064 struct uath_vap *uvp; 1065 struct ieee80211vap *vap; 1066 1067 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 1068 return (NULL); 1069 uvp = (struct uath_vap *) malloc(sizeof(struct uath_vap), 1070 M_80211_VAP, M_NOWAIT | M_ZERO); 1071 if (uvp == NULL) 1072 return (NULL); 1073 vap = &uvp->vap; 1074 /* enable s/w bmiss handling for sta mode */ 1075 ieee80211_vap_setup(ic, vap, name, unit, opmode, 1076 flags | IEEE80211_CLONE_NOBEACONS, bssid, mac); 1077 1078 /* override state transition machine */ 1079 uvp->newstate = vap->iv_newstate; 1080 vap->iv_newstate = uath_newstate; 1081 1082 /* complete setup */ 1083 ieee80211_vap_attach(vap, ieee80211_media_change, 1084 ieee80211_media_status); 1085 ic->ic_opmode = opmode; 1086 return (vap); 1087} 1088 1089static void 1090uath_vap_delete(struct ieee80211vap *vap) 1091{ 1092 struct uath_vap *uvp = UATH_VAP(vap); 1093 1094 ieee80211_vap_detach(vap); 1095 free(uvp, M_80211_VAP); 1096} 1097 1098static int 1099uath_init_locked(void *arg) 1100{ 1101 struct uath_softc *sc = arg; 1102 struct ifnet *ifp = sc->sc_ifp; 1103 struct ieee80211com *ic = ifp->if_l2com; 1104 uint32_t val; 1105 int error; 1106 1107 UATH_ASSERT_LOCKED(sc); 1108 1109 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1110 uath_stop_locked(ifp); 1111 1112 /* reset variables */ 1113 sc->sc_intrx_nextnum = sc->sc_msgid = 0; 1114 1115 val = htobe32(0); 1116 uath_cmd_write(sc, WDCMSG_BIND, &val, sizeof val, 0); 1117 1118 /* set MAC address */ 1119 uath_config_multi(sc, CFG_MAC_ADDR, IF_LLADDR(ifp), IEEE80211_ADDR_LEN); 1120 1121 /* XXX honor net80211 state */ 1122 uath_config(sc, CFG_RATE_CONTROL_ENABLE, 0x00000001); 1123 uath_config(sc, CFG_DIVERSITY_CTL, 0x00000001); 1124 uath_config(sc, CFG_ABOLT, 0x0000003f); 1125 uath_config(sc, CFG_WME_ENABLED, 0x00000001); 1126 1127 uath_config(sc, CFG_SERVICE_TYPE, 1); 1128 uath_config(sc, CFG_TP_SCALE, 0x00000000); 1129 uath_config(sc, CFG_TPC_HALF_DBM5, 0x0000003c); 1130 uath_config(sc, CFG_TPC_HALF_DBM2, 0x0000003c); 1131 uath_config(sc, CFG_OVERRD_TX_POWER, 0x00000000); 1132 uath_config(sc, CFG_GMODE_PROTECTION, 0x00000000); 1133 uath_config(sc, CFG_GMODE_PROTECT_RATE_INDEX, 0x00000003); 1134 uath_config(sc, CFG_PROTECTION_TYPE, 0x00000000); 1135 uath_config(sc, CFG_MODE_CTS, 0x00000002); 1136 1137 error = uath_cmd_read(sc, WDCMSG_TARGET_START, NULL, 0, 1138 &val, sizeof(val), UATH_CMD_FLAG_MAGIC); 1139 if (error) { 1140 device_printf(sc->sc_dev, 1141 "could not start target, error %d\n", error); 1142 goto fail; 1143 } 1144 DPRINTF(sc, UATH_DEBUG_INIT, "%s returns handle: 0x%x\n", 1145 uath_codename(WDCMSG_TARGET_START), be32toh(val)); 1146 1147 /* set default channel */ 1148 error = uath_switch_channel(sc, ic->ic_curchan); 1149 if (error) { 1150 device_printf(sc->sc_dev, 1151 "could not switch channel, error %d\n", error); 1152 goto fail; 1153 } 1154 1155 val = htobe32(TARGET_DEVICE_AWAKE); 1156 uath_cmd_write(sc, WDCMSG_SET_PWR_MODE, &val, sizeof val, 0); 1157 /* XXX? check */ 1158 uath_cmd_write(sc, WDCMSG_RESET_KEY_CACHE, NULL, 0, 0); 1159 1160 usbd_transfer_start(sc->sc_xfer[UATH_BULK_RX]); 1161 /* enable Rx */ 1162 uath_set_rxfilter(sc, 0x0, UATH_FILTER_OP_INIT); 1163 uath_set_rxfilter(sc, 1164 UATH_FILTER_RX_UCAST | UATH_FILTER_RX_MCAST | 1165 UATH_FILTER_RX_BCAST | UATH_FILTER_RX_BEACON, 1166 UATH_FILTER_OP_SET); 1167 1168 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1169 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1170 sc->sc_flags |= UATH_FLAG_INITDONE; 1171 1172 callout_reset(&sc->watchdog_ch, hz, uath_watchdog, sc); 1173 1174 return (0); 1175 1176fail: 1177 uath_stop_locked(ifp); 1178 return (error); 1179} 1180 1181static void 1182uath_init(void *arg) 1183{ 1184 struct uath_softc *sc = arg; 1185 1186 UATH_LOCK(sc); 1187 (void)uath_init_locked(sc); 1188 UATH_UNLOCK(sc); 1189} 1190 1191static void 1192uath_stop_locked(struct ifnet *ifp) 1193{ 1194 struct uath_softc *sc = ifp->if_softc; 1195 1196 UATH_ASSERT_LOCKED(sc); 1197 1198 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1199 sc->sc_flags &= ~UATH_FLAG_INITDONE; 1200 1201 callout_stop(&sc->stat_ch); 1202 callout_stop(&sc->watchdog_ch); 1203 sc->sc_tx_timer = 0; 1204 /* abort pending transmits */ 1205 uath_abort_xfers(sc); 1206 /* flush data & control requests into the target */ 1207 (void)uath_flush(sc); 1208 /* set a LED status to the disconnected. */ 1209 uath_set_ledstate(sc, 0); 1210 /* stop the target */ 1211 uath_cmd_write(sc, WDCMSG_TARGET_STOP, NULL, 0, 0); 1212} 1213 1214static void 1215uath_stop(struct ifnet *ifp) 1216{ 1217 struct uath_softc *sc = ifp->if_softc; 1218 1219 UATH_LOCK(sc); 1220 uath_stop_locked(ifp); 1221 UATH_UNLOCK(sc); 1222} 1223 1224static int 1225uath_config(struct uath_softc *sc, uint32_t reg, uint32_t val) 1226{ 1227 struct uath_write_mac write; 1228 int error; 1229 1230 write.reg = htobe32(reg); 1231 write.len = htobe32(0); /* 0 = single write */ 1232 *(uint32_t *)write.data = htobe32(val); 1233 1234 error = uath_cmd_write(sc, WDCMSG_TARGET_SET_CONFIG, &write, 1235 3 * sizeof (uint32_t), 0); 1236 if (error != 0) { 1237 device_printf(sc->sc_dev, "could not write register 0x%02x\n", 1238 reg); 1239 } 1240 return (error); 1241} 1242 1243static int 1244uath_config_multi(struct uath_softc *sc, uint32_t reg, const void *data, 1245 int len) 1246{ 1247 struct uath_write_mac write; 1248 int error; 1249 1250 write.reg = htobe32(reg); 1251 write.len = htobe32(len); 1252 bcopy(data, write.data, len); 1253 1254 /* properly handle the case where len is zero (reset) */ 1255 error = uath_cmd_write(sc, WDCMSG_TARGET_SET_CONFIG, &write, 1256 (len == 0) ? sizeof (uint32_t) : 2 * sizeof (uint32_t) + len, 0); 1257 if (error != 0) { 1258 device_printf(sc->sc_dev, 1259 "could not write %d bytes to register 0x%02x\n", len, reg); 1260 } 1261 return (error); 1262} 1263 1264static int 1265uath_switch_channel(struct uath_softc *sc, struct ieee80211_channel *c) 1266{ 1267 int error; 1268 1269 UATH_ASSERT_LOCKED(sc); 1270 1271 /* set radio frequency */ 1272 error = uath_set_chan(sc, c); 1273 if (error) { 1274 device_printf(sc->sc_dev, 1275 "could not set channel, error %d\n", error); 1276 goto failed; 1277 } 1278 /* reset Tx rings */ 1279 error = uath_reset_tx_queues(sc); 1280 if (error) { 1281 device_printf(sc->sc_dev, 1282 "could not reset Tx queues, error %d\n", error); 1283 goto failed; 1284 } 1285 /* set Tx rings WME properties */ 1286 error = uath_wme_init(sc); 1287 if (error) { 1288 device_printf(sc->sc_dev, 1289 "could not init Tx queues, error %d\n", error); 1290 goto failed; 1291 } 1292 error = uath_set_ledstate(sc, 0); 1293 if (error) { 1294 device_printf(sc->sc_dev, 1295 "could not set led state, error %d\n", error); 1296 goto failed; 1297 } 1298 error = uath_flush(sc); 1299 if (error) { 1300 device_printf(sc->sc_dev, 1301 "could not flush pipes, error %d\n", error); 1302 goto failed; 1303 } 1304failed: 1305 return (error); 1306} 1307 1308static int 1309uath_set_rxfilter(struct uath_softc *sc, uint32_t bits, uint32_t op) 1310{ 1311 struct uath_cmd_rx_filter rxfilter; 1312 1313 rxfilter.bits = htobe32(bits); 1314 rxfilter.op = htobe32(op); 1315 1316 DPRINTF(sc, UATH_DEBUG_RECV | UATH_DEBUG_RECV_ALL, 1317 "setting Rx filter=0x%x flags=0x%x\n", bits, op); 1318 return uath_cmd_write(sc, WDCMSG_RX_FILTER, &rxfilter, 1319 sizeof rxfilter, 0); 1320} 1321 1322static void 1323uath_watchdog(void *arg) 1324{ 1325 struct uath_softc *sc = arg; 1326 struct ifnet *ifp = sc->sc_ifp; 1327 1328 if (sc->sc_tx_timer > 0) { 1329 if (--sc->sc_tx_timer == 0) { 1330 device_printf(sc->sc_dev, "device timeout\n"); 1331 /*uath_init(ifp); XXX needs a process context! */ 1332 ifp->if_oerrors++; 1333 return; 1334 } 1335 callout_reset(&sc->watchdog_ch, hz, uath_watchdog, sc); 1336 } 1337} 1338 1339static void 1340uath_abort_xfers(struct uath_softc *sc) 1341{ 1342 int i; 1343 1344 UATH_ASSERT_LOCKED(sc); 1345 /* abort any pending transfers */ 1346 for (i = 0; i < UATH_N_XFERS; i++) 1347 usbd_transfer_stop(sc->sc_xfer[i]); 1348} 1349 1350static int 1351uath_flush(struct uath_softc *sc) 1352{ 1353 int error; 1354 1355 error = uath_dataflush(sc); 1356 if (error != 0) 1357 goto failed; 1358 1359 error = uath_cmdflush(sc); 1360 if (error != 0) 1361 goto failed; 1362 1363failed: 1364 return (error); 1365} 1366 1367static int 1368uath_cmdflush(struct uath_softc *sc) 1369{ 1370 1371 return uath_cmd_write(sc, WDCMSG_FLUSH, NULL, 0, 0); 1372} 1373 1374static int 1375uath_dataflush(struct uath_softc *sc) 1376{ 1377 struct uath_data *data; 1378 struct uath_chunk *chunk; 1379 struct uath_tx_desc *desc; 1380 1381 UATH_ASSERT_LOCKED(sc); 1382 1383 data = uath_getbuf(sc); 1384 if (data == NULL) 1385 return (ENOBUFS); 1386 data->buflen = sizeof(struct uath_chunk) + sizeof(struct uath_tx_desc); 1387 data->m = NULL; 1388 data->ni = NULL; 1389 chunk = (struct uath_chunk *)data->buf; 1390 desc = (struct uath_tx_desc *)(chunk + 1); 1391 1392 /* one chunk only */ 1393 chunk->seqnum = 0; 1394 chunk->flags = UATH_CFLAGS_FINAL; 1395 chunk->length = htobe16(sizeof (struct uath_tx_desc)); 1396 1397 memset(desc, 0, sizeof(struct uath_tx_desc)); 1398 desc->msglen = htobe32(sizeof(struct uath_tx_desc)); 1399 desc->msgid = (sc->sc_msgid++) + 1; /* don't care about endianness */ 1400 desc->type = htobe32(WDCMSG_FLUSH); 1401 desc->txqid = htobe32(0); 1402 desc->connid = htobe32(0); 1403 desc->flags = htobe32(0); 1404 1405#ifdef UATH_DEBUG 1406 if (sc->sc_debug & UATH_DEBUG_CMDS) { 1407 DPRINTF(sc, UATH_DEBUG_RESET, "send flush ix %d\n", 1408 desc->msgid); 1409 if (sc->sc_debug & UATH_DEBUG_CMDS_DUMP) 1410 uath_dump_cmd(data->buf, data->buflen, '+'); 1411 } 1412#endif 1413 1414 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 1415 UATH_STAT_INC(sc, st_tx_pending); 1416 sc->sc_tx_timer = 5; 1417 usbd_transfer_start(sc->sc_xfer[UATH_BULK_TX]); 1418 1419 return (0); 1420} 1421 1422static struct uath_data * 1423_uath_getbuf(struct uath_softc *sc) 1424{ 1425 struct uath_data *bf; 1426 1427 bf = STAILQ_FIRST(&sc->sc_tx_inactive); 1428 if (bf != NULL) { 1429 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next); 1430 UATH_STAT_DEC(sc, st_tx_inactive); 1431 } else 1432 bf = NULL; 1433 if (bf == NULL) 1434 DPRINTF(sc, UATH_DEBUG_XMIT, "%s: %s\n", __func__, 1435 "out of xmit buffers"); 1436 return (bf); 1437} 1438 1439static struct uath_data * 1440uath_getbuf(struct uath_softc *sc) 1441{ 1442 struct uath_data *bf; 1443 1444 UATH_ASSERT_LOCKED(sc); 1445 1446 bf = _uath_getbuf(sc); 1447 if (bf == NULL) { 1448 struct ifnet *ifp = sc->sc_ifp; 1449 1450 DPRINTF(sc, UATH_DEBUG_XMIT, "%s: stop queue\n", __func__); 1451 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1452 } 1453 return (bf); 1454} 1455 1456static int 1457uath_set_ledstate(struct uath_softc *sc, int connected) 1458{ 1459 1460 DPRINTF(sc, UATH_DEBUG_LED, 1461 "set led state %sconnected\n", connected ? "" : "!"); 1462 connected = htobe32(connected); 1463 return uath_cmd_write(sc, WDCMSG_SET_LED_STATE, 1464 &connected, sizeof connected, 0); 1465} 1466 1467static int 1468uath_set_chan(struct uath_softc *sc, struct ieee80211_channel *c) 1469{ 1470#ifdef UATH_DEBUG 1471 struct ifnet *ifp = sc->sc_ifp; 1472 struct ieee80211com *ic = ifp->if_l2com; 1473#endif 1474 struct uath_cmd_reset reset; 1475 1476 memset(&reset, 0, sizeof(reset)); 1477 if (IEEE80211_IS_CHAN_2GHZ(c)) 1478 reset.flags |= htobe32(UATH_CHAN_2GHZ); 1479 if (IEEE80211_IS_CHAN_5GHZ(c)) 1480 reset.flags |= htobe32(UATH_CHAN_5GHZ); 1481 /* NB: 11g =>'s 11b so don't specify both OFDM and CCK */ 1482 if (IEEE80211_IS_CHAN_OFDM(c)) 1483 reset.flags |= htobe32(UATH_CHAN_OFDM); 1484 else if (IEEE80211_IS_CHAN_CCK(c)) 1485 reset.flags |= htobe32(UATH_CHAN_CCK); 1486 /* turbo can be used in either 2GHz or 5GHz */ 1487 if (c->ic_flags & IEEE80211_CHAN_TURBO) 1488 reset.flags |= htobe32(UATH_CHAN_TURBO); 1489 reset.freq = htobe32(c->ic_freq); 1490 reset.maxrdpower = htobe32(50); /* XXX */ 1491 reset.channelchange = htobe32(1); 1492 reset.keeprccontent = htobe32(0); 1493 1494 DPRINTF(sc, UATH_DEBUG_CHANNEL, "set channel %d, flags 0x%x freq %u\n", 1495 ieee80211_chan2ieee(ic, c), 1496 be32toh(reset.flags), be32toh(reset.freq)); 1497 return uath_cmd_write(sc, WDCMSG_RESET, &reset, sizeof reset, 0); 1498} 1499 1500static int 1501uath_reset_tx_queues(struct uath_softc *sc) 1502{ 1503 int ac, error; 1504 1505 DPRINTF(sc, UATH_DEBUG_RESET, "%s: reset Tx queues\n", __func__); 1506 for (ac = 0; ac < 4; ac++) { 1507 const uint32_t qid = htobe32(ac); 1508 1509 error = uath_cmd_write(sc, WDCMSG_RELEASE_TX_QUEUE, &qid, 1510 sizeof qid, 0); 1511 if (error != 0) 1512 break; 1513 } 1514 return (error); 1515} 1516 1517static int 1518uath_wme_init(struct uath_softc *sc) 1519{ 1520 /* XXX get from net80211 */ 1521 static const struct uath_wme_settings uath_wme_11g[4] = { 1522 { 7, 4, 10, 0, 0 }, /* Background */ 1523 { 3, 4, 10, 0, 0 }, /* Best-Effort */ 1524 { 3, 3, 4, 26, 0 }, /* Video */ 1525 { 2, 2, 3, 47, 0 } /* Voice */ 1526 }; 1527 struct uath_cmd_txq_setup qinfo; 1528 int ac, error; 1529 1530 DPRINTF(sc, UATH_DEBUG_WME, "%s: setup Tx queues\n", __func__); 1531 for (ac = 0; ac < 4; ac++) { 1532 qinfo.qid = htobe32(ac); 1533 qinfo.len = htobe32(sizeof(qinfo.attr)); 1534 qinfo.attr.priority = htobe32(ac); /* XXX */ 1535 qinfo.attr.aifs = htobe32(uath_wme_11g[ac].aifsn); 1536 qinfo.attr.logcwmin = htobe32(uath_wme_11g[ac].logcwmin); 1537 qinfo.attr.logcwmax = htobe32(uath_wme_11g[ac].logcwmax); 1538 qinfo.attr.bursttime = htobe32(UATH_TXOP_TO_US( 1539 uath_wme_11g[ac].txop)); 1540 qinfo.attr.mode = htobe32(uath_wme_11g[ac].acm);/*XXX? */ 1541 qinfo.attr.qflags = htobe32(1); /* XXX? */ 1542 1543 error = uath_cmd_write(sc, WDCMSG_SETUP_TX_QUEUE, &qinfo, 1544 sizeof qinfo, 0); 1545 if (error != 0) 1546 break; 1547 } 1548 return (error); 1549} 1550 1551static int 1552uath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1553{ 1554 struct ieee80211com *ic = ifp->if_l2com; 1555 struct ifreq *ifr = (struct ifreq *) data; 1556 struct uath_softc *sc = ifp->if_softc; 1557 int error; 1558 int startall = 0; 1559 1560 UATH_LOCK(sc); 1561 error = (sc->sc_flags & UATH_FLAG_INVALID) ? ENXIO : 0; 1562 UATH_UNLOCK(sc); 1563 if (error) 1564 return (error); 1565 1566 switch (cmd) { 1567 case SIOCSIFFLAGS: 1568 if (ifp->if_flags & IFF_UP) { 1569 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1570 uath_init(ifp->if_softc); 1571 startall = 1; 1572 } 1573 } else { 1574 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1575 uath_stop(ifp); 1576 } 1577 if (startall) 1578 ieee80211_start_all(ic); 1579 break; 1580 case SIOCGIFMEDIA: 1581 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 1582 break; 1583 case SIOCGIFADDR: 1584 error = ether_ioctl(ifp, cmd, data); 1585 break; 1586 default: 1587 error = EINVAL; 1588 break; 1589 } 1590 1591 return (error); 1592} 1593 1594static int 1595uath_tx_start(struct uath_softc *sc, struct mbuf *m0, struct ieee80211_node *ni, 1596 struct uath_data *data) 1597{ 1598 struct ieee80211vap *vap = ni->ni_vap; 1599 struct uath_chunk *chunk; 1600 struct uath_tx_desc *desc; 1601 const struct ieee80211_frame *wh; 1602 struct ieee80211_key *k; 1603 int framelen, msglen; 1604 1605 UATH_ASSERT_LOCKED(sc); 1606 1607 data->ni = ni; 1608 data->m = m0; 1609 chunk = (struct uath_chunk *)data->buf; 1610 desc = (struct uath_tx_desc *)(chunk + 1); 1611 1612 if (ieee80211_radiotap_active_vap(vap)) { 1613 struct uath_tx_radiotap_header *tap = &sc->sc_txtap; 1614 1615 tap->wt_flags = 0; 1616 if (m0->m_flags & M_FRAG) 1617 tap->wt_flags |= IEEE80211_RADIOTAP_F_FRAG; 1618 1619 ieee80211_radiotap_tx(vap, m0); 1620 } 1621 1622 wh = mtod(m0, struct ieee80211_frame *); 1623 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1624 k = ieee80211_crypto_encap(ni, m0); 1625 if (k == NULL) { 1626 m_freem(m0); 1627 return (ENOBUFS); 1628 } 1629 1630 /* packet header may have moved, reset our local pointer */ 1631 wh = mtod(m0, struct ieee80211_frame *); 1632 } 1633 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)(desc + 1)); 1634 1635 framelen = m0->m_pkthdr.len + IEEE80211_CRC_LEN; 1636 msglen = framelen + sizeof (struct uath_tx_desc); 1637 data->buflen = msglen + sizeof (struct uath_chunk); 1638 1639 /* one chunk only for now */ 1640 chunk->seqnum = sc->sc_seqnum++; 1641 chunk->flags = (m0->m_flags & M_FRAG) ? 0 : UATH_CFLAGS_FINAL; 1642 if (m0->m_flags & M_LASTFRAG) 1643 chunk->flags |= UATH_CFLAGS_FINAL; 1644 chunk->flags = UATH_CFLAGS_FINAL; 1645 chunk->length = htobe16(msglen); 1646 1647 /* fill Tx descriptor */ 1648 desc->msglen = htobe32(msglen); 1649 /* NB: to get UATH_TX_NOTIFY reply, `msgid' must be larger than 0 */ 1650 desc->msgid = (sc->sc_msgid++) + 1; /* don't care about endianness */ 1651 desc->type = htobe32(WDCMSG_SEND); 1652 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 1653 case IEEE80211_FC0_TYPE_CTL: 1654 case IEEE80211_FC0_TYPE_MGT: 1655 /* NB: force all management frames to highest queue */ 1656 if (ni->ni_flags & IEEE80211_NODE_QOS) { 1657 /* NB: force all management frames to highest queue */ 1658 desc->txqid = htobe32(WME_AC_VO | UATH_TXQID_MINRATE); 1659 } else 1660 desc->txqid = htobe32(WME_AC_BE | UATH_TXQID_MINRATE); 1661 break; 1662 case IEEE80211_FC0_TYPE_DATA: 1663 /* XXX multicast frames should honor mcastrate */ 1664 desc->txqid = htobe32(M_WME_GETAC(m0)); 1665 break; 1666 default: 1667 device_printf(sc->sc_dev, "bogus frame type 0x%x (%s)\n", 1668 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__); 1669 m_freem(m0); 1670 return (EIO); 1671 } 1672 if (vap->iv_state == IEEE80211_S_AUTH || 1673 vap->iv_state == IEEE80211_S_ASSOC || 1674 vap->iv_state == IEEE80211_S_RUN) 1675 desc->connid = htobe32(UATH_ID_BSS); 1676 else 1677 desc->connid = htobe32(UATH_ID_INVALID); 1678 desc->flags = htobe32(0 /* no UATH_TX_NOTIFY */); 1679 desc->buflen = htobe32(m0->m_pkthdr.len); 1680 1681#ifdef UATH_DEBUG 1682 DPRINTF(sc, UATH_DEBUG_XMIT, 1683 "send frame ix %u framelen %d msglen %d connid 0x%x txqid 0x%x\n", 1684 desc->msgid, framelen, msglen, be32toh(desc->connid), 1685 be32toh(desc->txqid)); 1686 if (sc->sc_debug & UATH_DEBUG_XMIT_DUMP) 1687 uath_dump_cmd(data->buf, data->buflen, '+'); 1688#endif 1689 1690 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next); 1691 UATH_STAT_INC(sc, st_tx_pending); 1692 usbd_transfer_start(sc->sc_xfer[UATH_BULK_TX]); 1693 1694 return (0); 1695} 1696 1697/* 1698 * Cleanup driver resources when we run out of buffers while processing 1699 * fragments; return the tx buffers allocated and drop node references. 1700 */ 1701static void 1702uath_txfrag_cleanup(struct uath_softc *sc, 1703 uath_datahead *frags, struct ieee80211_node *ni) 1704{ 1705 struct uath_data *bf, *next; 1706 1707 UATH_ASSERT_LOCKED(sc); 1708 1709 STAILQ_FOREACH_SAFE(bf, frags, next, next) { 1710 /* NB: bf assumed clean */ 1711 STAILQ_REMOVE_HEAD(frags, next); 1712 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 1713 UATH_STAT_INC(sc, st_tx_inactive); 1714 ieee80211_node_decref(ni); 1715 } 1716} 1717 1718/* 1719 * Setup xmit of a fragmented frame. Allocate a buffer for each frag and bump 1720 * the node reference count to reflect the held reference to be setup by 1721 * uath_tx_start. 1722 */ 1723static int 1724uath_txfrag_setup(struct uath_softc *sc, uath_datahead *frags, 1725 struct mbuf *m0, struct ieee80211_node *ni) 1726{ 1727 struct mbuf *m; 1728 struct uath_data *bf; 1729 1730 UATH_ASSERT_LOCKED(sc); 1731 for (m = m0->m_nextpkt; m != NULL; m = m->m_nextpkt) { 1732 bf = uath_getbuf(sc); 1733 if (bf == NULL) { /* out of buffers, cleanup */ 1734 uath_txfrag_cleanup(sc, frags, ni); 1735 break; 1736 } 1737 ieee80211_node_incref(ni); 1738 STAILQ_INSERT_TAIL(frags, bf, next); 1739 } 1740 1741 return !STAILQ_EMPTY(frags); 1742} 1743 1744/* 1745 * Reclaim mbuf resources. For fragmented frames we need to claim each frag 1746 * chained with m_nextpkt. 1747 */ 1748static void 1749uath_freetx(struct mbuf *m) 1750{ 1751 struct mbuf *next; 1752 1753 do { 1754 next = m->m_nextpkt; 1755 m->m_nextpkt = NULL; 1756 m_freem(m); 1757 } while ((m = next) != NULL); 1758} 1759 1760static void 1761uath_start(struct ifnet *ifp) 1762{ 1763 struct uath_data *bf; 1764 struct uath_softc *sc = ifp->if_softc; 1765 struct ieee80211_node *ni; 1766 struct mbuf *m, *next; 1767 uath_datahead frags; 1768 1769 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || 1770 (sc->sc_flags & UATH_FLAG_INVALID)) 1771 return; 1772 1773 UATH_LOCK(sc); 1774 for (;;) { 1775 bf = uath_getbuf(sc); 1776 if (bf == NULL) 1777 break; 1778 1779 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1780 if (m == NULL) { 1781 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 1782 UATH_STAT_INC(sc, st_tx_inactive); 1783 break; 1784 } 1785 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif; 1786 m->m_pkthdr.rcvif = NULL; 1787 1788 /* 1789 * Check for fragmentation. If this frame has been broken up 1790 * verify we have enough buffers to send all the fragments 1791 * so all go out or none... 1792 */ 1793 STAILQ_INIT(&frags); 1794 if ((m->m_flags & M_FRAG) && 1795 !uath_txfrag_setup(sc, &frags, m, ni)) { 1796 DPRINTF(sc, UATH_DEBUG_XMIT, 1797 "%s: out of txfrag buffers\n", __func__); 1798 uath_freetx(m); 1799 goto bad; 1800 } 1801 sc->sc_seqnum = 0; 1802 nextfrag: 1803 /* 1804 * Pass the frame to the h/w for transmission. 1805 * Fragmented frames have each frag chained together 1806 * with m_nextpkt. We know there are sufficient uath_data's 1807 * to send all the frags because of work done by 1808 * uath_txfrag_setup. 1809 */ 1810 next = m->m_nextpkt; 1811 if (uath_tx_start(sc, m, ni, bf) != 0) { 1812 bad: 1813 ifp->if_oerrors++; 1814 reclaim: 1815 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 1816 UATH_STAT_INC(sc, st_tx_inactive); 1817 uath_txfrag_cleanup(sc, &frags, ni); 1818 ieee80211_free_node(ni); 1819 continue; 1820 } 1821 1822 if (next != NULL) { 1823 /* 1824 * Beware of state changing between frags. 1825 XXX check sta power-save state? 1826 */ 1827 if (ni->ni_vap->iv_state != IEEE80211_S_RUN) { 1828 DPRINTF(sc, UATH_DEBUG_XMIT, 1829 "%s: flush fragmented packet, state %s\n", 1830 __func__, 1831 ieee80211_state_name[ni->ni_vap->iv_state]); 1832 uath_freetx(next); 1833 goto reclaim; 1834 } 1835 m = next; 1836 bf = STAILQ_FIRST(&frags); 1837 KASSERT(bf != NULL, ("no buf for txfrag")); 1838 STAILQ_REMOVE_HEAD(&frags, next); 1839 goto nextfrag; 1840 } 1841 1842 sc->sc_tx_timer = 5; 1843 } 1844 UATH_UNLOCK(sc); 1845} 1846 1847static int 1848uath_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1849 const struct ieee80211_bpf_params *params) 1850{ 1851 struct ieee80211com *ic = ni->ni_ic; 1852 struct ifnet *ifp = ic->ic_ifp; 1853 struct uath_data *bf; 1854 struct uath_softc *sc = ifp->if_softc; 1855 1856 /* prevent management frames from being sent if we're not ready */ 1857 if ((sc->sc_flags & UATH_FLAG_INVALID) || 1858 !(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1859 m_freem(m); 1860 ieee80211_free_node(ni); 1861 return (ENETDOWN); 1862 } 1863 1864 UATH_LOCK(sc); 1865 /* grab a TX buffer */ 1866 bf = uath_getbuf(sc); 1867 if (bf == NULL) { 1868 ieee80211_free_node(ni); 1869 m_freem(m); 1870 UATH_UNLOCK(sc); 1871 return (ENOBUFS); 1872 } 1873 1874 sc->sc_seqnum = 0; 1875 if (uath_tx_start(sc, m, ni, bf) != 0) { 1876 ieee80211_free_node(ni); 1877 ifp->if_oerrors++; 1878 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next); 1879 UATH_STAT_INC(sc, st_tx_inactive); 1880 UATH_UNLOCK(sc); 1881 return (EIO); 1882 } 1883 UATH_UNLOCK(sc); 1884 1885 sc->sc_tx_timer = 5; 1886 return (0); 1887} 1888 1889static void 1890uath_scan_start(struct ieee80211com *ic) 1891{ 1892 /* do nothing */ 1893} 1894 1895static void 1896uath_scan_end(struct ieee80211com *ic) 1897{ 1898 /* do nothing */ 1899} 1900 1901static void 1902uath_set_channel(struct ieee80211com *ic) 1903{ 1904 struct ifnet *ifp = ic->ic_ifp; 1905 struct uath_softc *sc = ifp->if_softc; 1906 1907 UATH_LOCK(sc); 1908 if ((sc->sc_flags & UATH_FLAG_INVALID) || 1909 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1910 UATH_UNLOCK(sc); 1911 return; 1912 } 1913 (void)uath_switch_channel(sc, ic->ic_curchan); 1914 UATH_UNLOCK(sc); 1915} 1916 1917static int 1918uath_set_rxmulti_filter(struct uath_softc *sc) 1919{ 1920 /* XXX broken */ 1921 return (0); 1922} 1923static void 1924uath_update_mcast(struct ifnet *ifp) 1925{ 1926 struct uath_softc *sc = ifp->if_softc; 1927 1928 UATH_LOCK(sc); 1929 if ((sc->sc_flags & UATH_FLAG_INVALID) || 1930 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1931 UATH_UNLOCK(sc); 1932 return; 1933 } 1934 /* 1935 * this is for avoiding the race condition when we're try to 1936 * connect to the AP with WPA. 1937 */ 1938 if (sc->sc_flags & UATH_FLAG_INITDONE) 1939 (void)uath_set_rxmulti_filter(sc); 1940 UATH_UNLOCK(sc); 1941} 1942 1943static void 1944uath_update_promisc(struct ifnet *ifp) 1945{ 1946 struct uath_softc *sc = ifp->if_softc; 1947 1948 UATH_LOCK(sc); 1949 if ((sc->sc_flags & UATH_FLAG_INVALID) || 1950 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1951 UATH_UNLOCK(sc); 1952 return; 1953 } 1954 if (sc->sc_flags & UATH_FLAG_INITDONE) { 1955 uath_set_rxfilter(sc, 1956 UATH_FILTER_RX_UCAST | UATH_FILTER_RX_MCAST | 1957 UATH_FILTER_RX_BCAST | UATH_FILTER_RX_BEACON | 1958 UATH_FILTER_RX_PROM, UATH_FILTER_OP_SET); 1959 } 1960 UATH_UNLOCK(sc); 1961} 1962 1963static int 1964uath_create_connection(struct uath_softc *sc, uint32_t connid) 1965{ 1966 const struct ieee80211_rateset *rs; 1967 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 1968 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1969 struct ieee80211_node *ni; 1970 struct uath_cmd_create_connection create; 1971 1972 ni = ieee80211_ref_node(vap->iv_bss); 1973 memset(&create, 0, sizeof(create)); 1974 create.connid = htobe32(connid); 1975 create.bssid = htobe32(0); 1976 /* XXX packed or not? */ 1977 create.size = htobe32(sizeof(struct uath_cmd_rateset)); 1978 1979 rs = &ni->ni_rates; 1980 create.connattr.rateset.length = rs->rs_nrates; 1981 bcopy(rs->rs_rates, &create.connattr.rateset.set[0], 1982 rs->rs_nrates); 1983 1984 /* XXX turbo */ 1985 if (IEEE80211_IS_CHAN_A(ni->ni_chan)) 1986 create.connattr.wlanmode = htobe32(WLAN_MODE_11a); 1987 else if (IEEE80211_IS_CHAN_ANYG(ni->ni_chan)) 1988 create.connattr.wlanmode = htobe32(WLAN_MODE_11g); 1989 else 1990 create.connattr.wlanmode = htobe32(WLAN_MODE_11b); 1991 ieee80211_free_node(ni); 1992 1993 return uath_cmd_write(sc, WDCMSG_CREATE_CONNECTION, &create, 1994 sizeof create, 0); 1995} 1996 1997static int 1998uath_set_rates(struct uath_softc *sc, const struct ieee80211_rateset *rs) 1999{ 2000 struct uath_cmd_rates rates; 2001 2002 memset(&rates, 0, sizeof(rates)); 2003 rates.connid = htobe32(UATH_ID_BSS); /* XXX */ 2004 rates.size = htobe32(sizeof(struct uath_cmd_rateset)); 2005 /* XXX bounds check rs->rs_nrates */ 2006 rates.rateset.length = rs->rs_nrates; 2007 bcopy(rs->rs_rates, &rates.rateset.set[0], rs->rs_nrates); 2008 2009 DPRINTF(sc, UATH_DEBUG_RATES, 2010 "setting supported rates nrates=%d\n", rs->rs_nrates); 2011 return uath_cmd_write(sc, WDCMSG_SET_BASIC_RATE, 2012 &rates, sizeof rates, 0); 2013} 2014 2015static int 2016uath_write_associd(struct uath_softc *sc) 2017{ 2018 struct ieee80211com *ic = sc->sc_ifp->if_l2com; 2019 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2020 struct ieee80211_node *ni; 2021 struct uath_cmd_set_associd associd; 2022 2023 ni = ieee80211_ref_node(vap->iv_bss); 2024 memset(&associd, 0, sizeof(associd)); 2025 associd.defaultrateix = htobe32(1); /* XXX */ 2026 associd.associd = htobe32(ni->ni_associd); 2027 associd.timoffset = htobe32(0x3b); /* XXX */ 2028 IEEE80211_ADDR_COPY(associd.bssid, ni->ni_bssid); 2029 ieee80211_free_node(ni); 2030 return uath_cmd_write(sc, WDCMSG_WRITE_ASSOCID, &associd, 2031 sizeof associd, 0); 2032} 2033 2034static int 2035uath_set_ledsteady(struct uath_softc *sc, int lednum, int ledmode) 2036{ 2037 struct uath_cmd_ledsteady led; 2038 2039 led.lednum = htobe32(lednum); 2040 led.ledmode = htobe32(ledmode); 2041 2042 DPRINTF(sc, UATH_DEBUG_LED, "set %s led %s (steady)\n", 2043 (lednum == UATH_LED_LINK) ? "link" : "activity", 2044 ledmode ? "on" : "off"); 2045 return uath_cmd_write(sc, WDCMSG_SET_LED_STEADY, &led, sizeof led, 0); 2046} 2047 2048static int 2049uath_set_ledblink(struct uath_softc *sc, int lednum, int ledmode, 2050 int blinkrate, int slowmode) 2051{ 2052 struct uath_cmd_ledblink led; 2053 2054 led.lednum = htobe32(lednum); 2055 led.ledmode = htobe32(ledmode); 2056 led.blinkrate = htobe32(blinkrate); 2057 led.slowmode = htobe32(slowmode); 2058 2059 DPRINTF(sc, UATH_DEBUG_LED, "set %s led %s (blink)\n", 2060 (lednum == UATH_LED_LINK) ? "link" : "activity", 2061 ledmode ? "on" : "off"); 2062 return uath_cmd_write(sc, WDCMSG_SET_LED_BLINK, &led, sizeof led, 0); 2063} 2064 2065static int 2066uath_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 2067{ 2068 enum ieee80211_state ostate = vap->iv_state; 2069 int error; 2070 struct ieee80211_node *ni; 2071 struct ieee80211com *ic = vap->iv_ic; 2072 struct uath_softc *sc = ic->ic_ifp->if_softc; 2073 struct uath_vap *uvp = UATH_VAP(vap); 2074 2075 DPRINTF(sc, UATH_DEBUG_STATE, 2076 "%s: %s -> %s\n", __func__, ieee80211_state_name[vap->iv_state], 2077 ieee80211_state_name[nstate]); 2078 2079 IEEE80211_UNLOCK(ic); 2080 UATH_LOCK(sc); 2081 callout_stop(&sc->stat_ch); 2082 callout_stop(&sc->watchdog_ch); 2083 ni = ieee80211_ref_node(vap->iv_bss); 2084 2085 switch (nstate) { 2086 case IEEE80211_S_INIT: 2087 if (ostate == IEEE80211_S_RUN) { 2088 /* turn link and activity LEDs off */ 2089 uath_set_ledstate(sc, 0); 2090 } 2091 break; 2092 2093 case IEEE80211_S_SCAN: 2094 break; 2095 2096 case IEEE80211_S_AUTH: 2097 /* XXX good place? set RTS threshold */ 2098 uath_config(sc, CFG_USER_RTS_THRESHOLD, vap->iv_rtsthreshold); 2099 /* XXX bad place */ 2100 error = uath_set_keys(sc, vap); 2101 if (error != 0) { 2102 device_printf(sc->sc_dev, 2103 "could not set crypto keys, error %d\n", error); 2104 break; 2105 } 2106 if (uath_switch_channel(sc, ni->ni_chan) != 0) { 2107 device_printf(sc->sc_dev, "could not switch channel\n"); 2108 break; 2109 } 2110 if (uath_create_connection(sc, UATH_ID_BSS) != 0) { 2111 device_printf(sc->sc_dev, 2112 "could not create connection\n"); 2113 break; 2114 } 2115 break; 2116 2117 case IEEE80211_S_ASSOC: 2118 if (uath_set_rates(sc, &ni->ni_rates) != 0) { 2119 device_printf(sc->sc_dev, 2120 "could not set negotiated rate set\n"); 2121 break; 2122 } 2123 break; 2124 2125 case IEEE80211_S_RUN: 2126 /* XXX monitor mode doesn't be tested */ 2127 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 2128 uath_set_ledstate(sc, 1); 2129 break; 2130 } 2131 2132 /* 2133 * Tx rate is controlled by firmware, report the maximum 2134 * negotiated rate in ifconfig output. 2135 */ 2136 ni->ni_txrate = ni->ni_rates.rs_rates[ni->ni_rates.rs_nrates-1]; 2137 2138 if (uath_write_associd(sc) != 0) { 2139 device_printf(sc->sc_dev, 2140 "could not write association id\n"); 2141 break; 2142 } 2143 /* turn link LED on */ 2144 uath_set_ledsteady(sc, UATH_LED_LINK, UATH_LED_ON); 2145 /* make activity LED blink */ 2146 uath_set_ledblink(sc, UATH_LED_ACTIVITY, UATH_LED_ON, 1, 2); 2147 /* set state to associated */ 2148 uath_set_ledstate(sc, 1); 2149 2150 /* start statistics timer */ 2151 callout_reset(&sc->stat_ch, hz, uath_stat, sc); 2152 break; 2153 default: 2154 break; 2155 } 2156 ieee80211_free_node(ni); 2157 UATH_UNLOCK(sc); 2158 IEEE80211_LOCK(ic); 2159 return (uvp->newstate(vap, nstate, arg)); 2160} 2161 2162static int 2163uath_set_key(struct uath_softc *sc, const struct ieee80211_key *wk, 2164 int index) 2165{ 2166#if 0 2167 struct uath_cmd_crypto crypto; 2168 int i; 2169 2170 memset(&crypto, 0, sizeof(crypto)); 2171 crypto.keyidx = htobe32(index); 2172 crypto.magic1 = htobe32(1); 2173 crypto.size = htobe32(368); 2174 crypto.mask = htobe32(0xffff); 2175 crypto.flags = htobe32(0x80000068); 2176 if (index != UATH_DEFAULT_KEY) 2177 crypto.flags |= htobe32(index << 16); 2178 memset(crypto.magic2, 0xff, sizeof(crypto.magic2)); 2179 2180 /* 2181 * Each byte of the key must be XOR'ed with 10101010 before being 2182 * transmitted to the firmware. 2183 */ 2184 for (i = 0; i < wk->wk_keylen; i++) 2185 crypto.key[i] = wk->wk_key[i] ^ 0xaa; 2186 2187 DPRINTF(sc, UATH_DEBUG_CRYPTO, 2188 "setting crypto key index=%d len=%d\n", index, wk->wk_keylen); 2189 return uath_cmd_write(sc, WDCMSG_SET_KEY_CACHE_ENTRY, &crypto, 2190 sizeof crypto, 0); 2191#else 2192 /* XXX support H/W cryto */ 2193 return (0); 2194#endif 2195} 2196 2197static int 2198uath_set_keys(struct uath_softc *sc, struct ieee80211vap *vap) 2199{ 2200 int i, error; 2201 2202 error = 0; 2203 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 2204 const struct ieee80211_key *wk = &vap->iv_nw_keys[i]; 2205 2206 if (wk->wk_flags & (IEEE80211_KEY_XMIT|IEEE80211_KEY_RECV)) { 2207 error = uath_set_key(sc, wk, i); 2208 if (error) 2209 return (error); 2210 } 2211 } 2212 if (vap->iv_def_txkey != IEEE80211_KEYIX_NONE) { 2213 error = uath_set_key(sc, &vap->iv_nw_keys[vap->iv_def_txkey], 2214 UATH_DEFAULT_KEY); 2215 } 2216 return (error); 2217} 2218 2219#define UATH_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 2220 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 2221 2222static void 2223uath_sysctl_node(struct uath_softc *sc) 2224{ 2225 struct sysctl_ctx_list *ctx; 2226 struct sysctl_oid_list *child; 2227 struct sysctl_oid *tree; 2228 struct uath_stat *stats; 2229 2230 stats = &sc->sc_stat; 2231 ctx = device_get_sysctl_ctx(sc->sc_dev); 2232 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->sc_dev)); 2233 2234 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 2235 NULL, "UATH statistics"); 2236 child = SYSCTL_CHILDREN(tree); 2237 UATH_SYSCTL_STAT_ADD32(ctx, child, "badchunkseqnum", 2238 &stats->st_badchunkseqnum, "Bad chunk sequence numbers"); 2239 UATH_SYSCTL_STAT_ADD32(ctx, child, "invalidlen", &stats->st_invalidlen, 2240 "Invalid length"); 2241 UATH_SYSCTL_STAT_ADD32(ctx, child, "multichunk", &stats->st_multichunk, 2242 "Multi chunks"); 2243 UATH_SYSCTL_STAT_ADD32(ctx, child, "toobigrxpkt", 2244 &stats->st_toobigrxpkt, "Too big rx packets"); 2245 UATH_SYSCTL_STAT_ADD32(ctx, child, "stopinprogress", 2246 &stats->st_stopinprogress, "Stop in progress"); 2247 UATH_SYSCTL_STAT_ADD32(ctx, child, "crcerrs", &stats->st_crcerr, 2248 "CRC errors"); 2249 UATH_SYSCTL_STAT_ADD32(ctx, child, "phyerr", &stats->st_phyerr, 2250 "PHY errors"); 2251 UATH_SYSCTL_STAT_ADD32(ctx, child, "decrypt_crcerr", 2252 &stats->st_decrypt_crcerr, "Decryption CRC errors"); 2253 UATH_SYSCTL_STAT_ADD32(ctx, child, "decrypt_micerr", 2254 &stats->st_decrypt_micerr, "Decryption Misc errors"); 2255 UATH_SYSCTL_STAT_ADD32(ctx, child, "decomperr", &stats->st_decomperr, 2256 "Decomp errors"); 2257 UATH_SYSCTL_STAT_ADD32(ctx, child, "keyerr", &stats->st_keyerr, 2258 "Key errors"); 2259 UATH_SYSCTL_STAT_ADD32(ctx, child, "err", &stats->st_err, 2260 "Unknown errors"); 2261 2262 UATH_SYSCTL_STAT_ADD32(ctx, child, "cmd_active", 2263 &stats->st_cmd_active, "Active numbers in Command queue"); 2264 UATH_SYSCTL_STAT_ADD32(ctx, child, "cmd_inactive", 2265 &stats->st_cmd_inactive, "Inactive numbers in Command queue"); 2266 UATH_SYSCTL_STAT_ADD32(ctx, child, "cmd_pending", 2267 &stats->st_cmd_pending, "Pending numbers in Command queue"); 2268 UATH_SYSCTL_STAT_ADD32(ctx, child, "cmd_waiting", 2269 &stats->st_cmd_waiting, "Waiting numbers in Command queue"); 2270 UATH_SYSCTL_STAT_ADD32(ctx, child, "rx_active", 2271 &stats->st_rx_active, "Active numbers in RX queue"); 2272 UATH_SYSCTL_STAT_ADD32(ctx, child, "rx_inactive", 2273 &stats->st_rx_inactive, "Inactive numbers in RX queue"); 2274 UATH_SYSCTL_STAT_ADD32(ctx, child, "tx_active", 2275 &stats->st_tx_active, "Active numbers in TX queue"); 2276 UATH_SYSCTL_STAT_ADD32(ctx, child, "tx_inactive", 2277 &stats->st_tx_inactive, "Inactive numbers in TX queue"); 2278 UATH_SYSCTL_STAT_ADD32(ctx, child, "tx_pending", 2279 &stats->st_tx_pending, "Pending numbers in TX queue"); 2280} 2281 2282#undef UATH_SYSCTL_STAT_ADD32 2283 2284static void 2285uath_cmdeof(struct uath_softc *sc, struct uath_cmd *cmd) 2286{ 2287 struct uath_cmd_hdr *hdr; 2288 int dlen; 2289 2290 hdr = (struct uath_cmd_hdr *)cmd->buf; 2291 /* NB: msgid is passed thru w/o byte swapping */ 2292#ifdef UATH_DEBUG 2293 if (sc->sc_debug & UATH_DEBUG_CMDS) { 2294 int len = be32toh(hdr->len); 2295 printf("%s: %s [ix %u] len %u status %u\n", 2296 __func__, uath_codename(be32toh(hdr->code)), 2297 hdr->msgid, len, be32toh(hdr->magic)); 2298 if (sc->sc_debug & UATH_DEBUG_CMDS_DUMP) 2299 uath_dump_cmd(cmd->buf, 2300 len > UATH_MAX_CMDSZ ? sizeof(*hdr) : len, '-'); 2301 } 2302#endif 2303 hdr->code = be32toh(hdr->code); 2304 hdr->len = be32toh(hdr->len); 2305 hdr->magic = be32toh(hdr->magic); /* target status on return */ 2306 2307 switch (hdr->code & 0xff) { 2308 /* reply to a read command */ 2309 default: 2310 dlen = hdr->len - sizeof(*hdr); 2311 if (dlen < 0) { 2312 device_printf(sc->sc_dev, 2313 "Invalid header length %d\n", dlen); 2314 return; 2315 } 2316 DPRINTF(sc, UATH_DEBUG_RX_PROC | UATH_DEBUG_RECV_ALL, 2317 "%s: code %d data len %u\n", 2318 __func__, hdr->code & 0xff, dlen); 2319 /* 2320 * The first response from the target after the 2321 * HOST_AVAILABLE has an invalid msgid so we must 2322 * treat it specially. 2323 */ 2324 if (hdr->msgid < UATH_CMD_LIST_COUNT) { 2325 uint32_t *rp = (uint32_t *)(hdr+1); 2326 u_int olen; 2327 2328 if (!(sizeof(*hdr) <= hdr->len && 2329 hdr->len < UATH_MAX_CMDSZ)) { 2330 device_printf(sc->sc_dev, 2331 "%s: invalid WDC msg length %u; " 2332 "msg ignored\n", __func__, hdr->len); 2333 return; 2334 } 2335 /* 2336 * Calculate return/receive payload size; the 2337 * first word, if present, always gives the 2338 * number of bytes--unless it's 0 in which 2339 * case a single 32-bit word should be present. 2340 */ 2341 if (dlen >= (int)sizeof(uint32_t)) { 2342 olen = be32toh(rp[0]); 2343 dlen -= sizeof(uint32_t); 2344 if (olen == 0) { 2345 /* convention is 0 =>'s one word */ 2346 olen = sizeof(uint32_t); 2347 /* XXX KASSERT(olen == dlen ) */ 2348 } 2349 } else 2350 olen = 0; 2351 if (cmd->odata != NULL) { 2352 /* NB: cmd->olen validated in uath_cmd */ 2353 if (olen > (u_int)cmd->olen) { 2354 /* XXX complain? */ 2355 device_printf(sc->sc_dev, 2356 "%s: cmd 0x%x olen %u cmd olen %u\n", 2357 __func__, hdr->code, olen, 2358 cmd->olen); 2359 olen = cmd->olen; 2360 } 2361 if (olen > (u_int)dlen) { 2362 /* XXX complain, shouldn't happen */ 2363 device_printf(sc->sc_dev, 2364 "%s: cmd 0x%x olen %u dlen %u\n", 2365 __func__, hdr->code, olen, dlen); 2366 olen = dlen; 2367 } 2368 /* XXX have submitter do this */ 2369 /* copy answer into caller's supplied buffer */ 2370 bcopy(&rp[1], cmd->odata, olen); 2371 cmd->olen = olen; 2372 } 2373 } 2374 wakeup_one(cmd); /* wake up caller */ 2375 break; 2376 2377 case WDCMSG_TARGET_START: 2378 if (hdr->msgid >= UATH_CMD_LIST_COUNT) { 2379 /* XXX */ 2380 return; 2381 } 2382 dlen = hdr->len - sizeof(*hdr); 2383 if (dlen != (int)sizeof(uint32_t)) { 2384 /* XXX something wrong */ 2385 return; 2386 } 2387 /* XXX have submitter do this */ 2388 /* copy answer into caller's supplied buffer */ 2389 bcopy(hdr+1, cmd->odata, sizeof(uint32_t)); 2390 cmd->olen = sizeof(uint32_t); 2391 wakeup_one(cmd); /* wake up caller */ 2392 break; 2393 2394 case WDCMSG_SEND_COMPLETE: 2395 /* this notification is sent when UATH_TX_NOTIFY is set */ 2396 DPRINTF(sc, UATH_DEBUG_RX_PROC | UATH_DEBUG_RECV_ALL, 2397 "%s: received Tx notification\n", __func__); 2398 break; 2399 2400 case WDCMSG_TARGET_GET_STATS: 2401 DPRINTF(sc, UATH_DEBUG_RX_PROC | UATH_DEBUG_RECV_ALL, 2402 "%s: received device statistics\n", __func__); 2403 callout_reset(&sc->stat_ch, hz, uath_stat, sc); 2404 break; 2405 } 2406} 2407 2408static void 2409uath_intr_rx_callback(struct usb_xfer *xfer, usb_error_t error) 2410{ 2411 struct uath_softc *sc = usbd_xfer_softc(xfer); 2412 struct uath_cmd *cmd; 2413 struct usb_page_cache *pc; 2414 int actlen; 2415 2416 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 2417 2418 UATH_ASSERT_LOCKED(sc); 2419 2420 switch (USB_GET_STATE(xfer)) { 2421 case USB_ST_TRANSFERRED: 2422 cmd = STAILQ_FIRST(&sc->sc_cmd_waiting); 2423 if (cmd == NULL) 2424 goto setup; 2425 STAILQ_REMOVE_HEAD(&sc->sc_cmd_waiting, next); 2426 UATH_STAT_DEC(sc, st_cmd_waiting); 2427 STAILQ_INSERT_TAIL(&sc->sc_cmd_inactive, cmd, next); 2428 UATH_STAT_INC(sc, st_cmd_inactive); 2429 2430 KASSERT(actlen >= (int)sizeof(struct uath_cmd_hdr), 2431 ("short xfer error")); 2432 pc = usbd_xfer_get_frame(xfer, 0); 2433 usbd_copy_out(pc, 0, cmd->buf, actlen); 2434 uath_cmdeof(sc, cmd); 2435 case USB_ST_SETUP: 2436setup: 2437 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 2438 usbd_transfer_submit(xfer); 2439 break; 2440 default: 2441 if (error != USB_ERR_CANCELLED) { 2442 usbd_xfer_set_stall(xfer); 2443 goto setup; 2444 } 2445 break; 2446 } 2447} 2448 2449static void 2450uath_intr_tx_callback(struct usb_xfer *xfer, usb_error_t error) 2451{ 2452 struct uath_softc *sc = usbd_xfer_softc(xfer); 2453 struct uath_cmd *cmd; 2454 2455 UATH_ASSERT_LOCKED(sc); 2456 2457 cmd = STAILQ_FIRST(&sc->sc_cmd_active); 2458 if (cmd != NULL && USB_GET_STATE(xfer) != USB_ST_SETUP) { 2459 STAILQ_REMOVE_HEAD(&sc->sc_cmd_active, next); 2460 UATH_STAT_DEC(sc, st_cmd_active); 2461 STAILQ_INSERT_TAIL((cmd->flags & UATH_CMD_FLAG_READ) ? 2462 &sc->sc_cmd_waiting : &sc->sc_cmd_inactive, cmd, next); 2463 if (cmd->flags & UATH_CMD_FLAG_READ) 2464 UATH_STAT_INC(sc, st_cmd_waiting); 2465 else 2466 UATH_STAT_INC(sc, st_cmd_inactive); 2467 } 2468 2469 switch (USB_GET_STATE(xfer)) { 2470 case USB_ST_TRANSFERRED: 2471 case USB_ST_SETUP: 2472setup: 2473 cmd = STAILQ_FIRST(&sc->sc_cmd_pending); 2474 if (cmd == NULL) { 2475 DPRINTF(sc, UATH_DEBUG_XMIT, "%s: empty pending queue\n", 2476 __func__); 2477 return; 2478 } 2479 STAILQ_REMOVE_HEAD(&sc->sc_cmd_pending, next); 2480 UATH_STAT_DEC(sc, st_cmd_pending); 2481 STAILQ_INSERT_TAIL((cmd->flags & UATH_CMD_FLAG_ASYNC) ? 2482 &sc->sc_cmd_inactive : &sc->sc_cmd_active, cmd, next); 2483 if (cmd->flags & UATH_CMD_FLAG_ASYNC) 2484 UATH_STAT_INC(sc, st_cmd_inactive); 2485 else 2486 UATH_STAT_INC(sc, st_cmd_active); 2487 2488 usbd_xfer_set_frame_data(xfer, 0, cmd->buf, cmd->buflen); 2489 usbd_transfer_submit(xfer); 2490 break; 2491 default: 2492 if (error != USB_ERR_CANCELLED) { 2493 usbd_xfer_set_stall(xfer); 2494 goto setup; 2495 } 2496 break; 2497 } 2498} 2499 2500static void 2501uath_update_rxstat(struct uath_softc *sc, uint32_t status) 2502{ 2503 2504 switch (status) { 2505 case UATH_STATUS_STOP_IN_PROGRESS: 2506 UATH_STAT_INC(sc, st_stopinprogress); 2507 break; 2508 case UATH_STATUS_CRC_ERR: 2509 UATH_STAT_INC(sc, st_crcerr); 2510 break; 2511 case UATH_STATUS_PHY_ERR: 2512 UATH_STAT_INC(sc, st_phyerr); 2513 break; 2514 case UATH_STATUS_DECRYPT_CRC_ERR: 2515 UATH_STAT_INC(sc, st_decrypt_crcerr); 2516 break; 2517 case UATH_STATUS_DECRYPT_MIC_ERR: 2518 UATH_STAT_INC(sc, st_decrypt_micerr); 2519 break; 2520 case UATH_STATUS_DECOMP_ERR: 2521 UATH_STAT_INC(sc, st_decomperr); 2522 break; 2523 case UATH_STATUS_KEY_ERR: 2524 UATH_STAT_INC(sc, st_keyerr); 2525 break; 2526 case UATH_STATUS_ERR: 2527 UATH_STAT_INC(sc, st_err); 2528 break; 2529 default: 2530 break; 2531 } 2532} 2533 2534static struct mbuf * 2535uath_data_rxeof(struct usb_xfer *xfer, struct uath_data *data, 2536 struct uath_rx_desc **pdesc) 2537{ 2538 struct uath_softc *sc = usbd_xfer_softc(xfer); 2539 struct ifnet *ifp = sc->sc_ifp; 2540 struct ieee80211com *ic = ifp->if_l2com; 2541 struct uath_chunk *chunk; 2542 struct uath_rx_desc *desc; 2543 struct mbuf *m = data->m, *mnew, *mp; 2544 uint16_t chunklen; 2545 int actlen; 2546 2547 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 2548 2549 if (actlen < (int)UATH_MIN_RXBUFSZ) { 2550 DPRINTF(sc, UATH_DEBUG_RECV | UATH_DEBUG_RECV_ALL, 2551 "%s: wrong xfer size (len=%d)\n", __func__, actlen); 2552 ifp->if_ierrors++; 2553 return (NULL); 2554 } 2555 2556 chunk = (struct uath_chunk *)data->buf; 2557 if (chunk->seqnum == 0 && chunk->flags == 0 && chunk->length == 0) { 2558 device_printf(sc->sc_dev, "%s: strange response\n", __func__); 2559 ifp->if_ierrors++; 2560 UATH_RESET_INTRX(sc); 2561 return (NULL); 2562 } 2563 2564 if (chunk->seqnum != sc->sc_intrx_nextnum) { 2565 DPRINTF(sc, UATH_DEBUG_XMIT, "invalid seqnum %d, expected %d\n", 2566 chunk->seqnum, sc->sc_intrx_nextnum); 2567 UATH_STAT_INC(sc, st_badchunkseqnum); 2568 if (sc->sc_intrx_head != NULL) 2569 m_freem(sc->sc_intrx_head); 2570 UATH_RESET_INTRX(sc); 2571 return (NULL); 2572 } 2573 2574 /* check multi-chunk frames */ 2575 if ((chunk->seqnum == 0 && !(chunk->flags & UATH_CFLAGS_FINAL)) || 2576 (chunk->seqnum != 0 && (chunk->flags & UATH_CFLAGS_FINAL)) || 2577 chunk->flags & UATH_CFLAGS_RXMSG) 2578 UATH_STAT_INC(sc, st_multichunk); 2579 2580 chunklen = be16toh(chunk->length); 2581 if (chunk->flags & UATH_CFLAGS_FINAL) 2582 chunklen -= sizeof(struct uath_rx_desc); 2583 2584 if (chunklen > 0 && 2585 (!(chunk->flags & UATH_CFLAGS_FINAL) || !(chunk->seqnum == 0))) { 2586 /* we should use intermediate RX buffer */ 2587 if (chunk->seqnum == 0) 2588 UATH_RESET_INTRX(sc); 2589 if ((sc->sc_intrx_len + sizeof(struct uath_rx_desc) + 2590 chunklen) > UATH_MAX_INTRX_SIZE) { 2591 UATH_STAT_INC(sc, st_invalidlen); 2592 ifp->if_iqdrops++; 2593 if (sc->sc_intrx_head != NULL) 2594 m_freem(sc->sc_intrx_head); 2595 UATH_RESET_INTRX(sc); 2596 return (NULL); 2597 } 2598 2599 m->m_len = chunklen; 2600 m->m_data += sizeof(struct uath_chunk); 2601 2602 if (sc->sc_intrx_head == NULL) { 2603 sc->sc_intrx_head = m; 2604 sc->sc_intrx_tail = m; 2605 } else { 2606 m->m_flags &= ~M_PKTHDR; 2607 sc->sc_intrx_tail->m_next = m; 2608 sc->sc_intrx_tail = m; 2609 } 2610 } 2611 sc->sc_intrx_len += chunklen; 2612 2613 mnew = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 2614 if (mnew == NULL) { 2615 DPRINTF(sc, UATH_DEBUG_RECV | UATH_DEBUG_RECV_ALL, 2616 "%s: can't get new mbuf, drop frame\n", __func__); 2617 ifp->if_ierrors++; 2618 if (sc->sc_intrx_head != NULL) 2619 m_freem(sc->sc_intrx_head); 2620 UATH_RESET_INTRX(sc); 2621 return (NULL); 2622 } 2623 2624 data->m = mnew; 2625 data->buf = mtod(mnew, uint8_t *); 2626 2627 /* if the frame is not final continue the transfer */ 2628 if (!(chunk->flags & UATH_CFLAGS_FINAL)) { 2629 sc->sc_intrx_nextnum++; 2630 UATH_RESET_INTRX(sc); 2631 return (NULL); 2632 } 2633 2634 /* 2635 * if the frame is not set UATH_CFLAGS_RXMSG, then rx descriptor is 2636 * located at the end, 32-bit aligned 2637 */ 2638 desc = (chunk->flags & UATH_CFLAGS_RXMSG) ? 2639 (struct uath_rx_desc *)(chunk + 1) : 2640 (struct uath_rx_desc *)(((uint8_t *)chunk) + 2641 sizeof(struct uath_chunk) + be16toh(chunk->length) - 2642 sizeof(struct uath_rx_desc)); 2643 *pdesc = desc; 2644 2645 DPRINTF(sc, UATH_DEBUG_RECV | UATH_DEBUG_RECV_ALL, 2646 "%s: frame len %u code %u status %u rate %u antenna %u " 2647 "rssi %d channel %u phyerror %u connix %u decrypterror %u " 2648 "keycachemiss %u\n", __func__, be32toh(desc->framelen) 2649 , be32toh(desc->code), be32toh(desc->status), be32toh(desc->rate) 2650 , be32toh(desc->antenna), be32toh(desc->rssi), be32toh(desc->channel) 2651 , be32toh(desc->phyerror), be32toh(desc->connix) 2652 , be32toh(desc->decrypterror), be32toh(desc->keycachemiss)); 2653 2654 if (be32toh(desc->len) > MCLBYTES) { 2655 DPRINTF(sc, UATH_DEBUG_RECV | UATH_DEBUG_RECV_ALL, 2656 "%s: bad descriptor (len=%d)\n", __func__, 2657 be32toh(desc->len)); 2658 ifp->if_iqdrops++; 2659 UATH_STAT_INC(sc, st_toobigrxpkt); 2660 if (sc->sc_intrx_head != NULL) 2661 m_freem(sc->sc_intrx_head); 2662 UATH_RESET_INTRX(sc); 2663 return (NULL); 2664 } 2665 2666 uath_update_rxstat(sc, be32toh(desc->status)); 2667 2668 /* finalize mbuf */ 2669 if (sc->sc_intrx_head == NULL) { 2670 m->m_pkthdr.rcvif = ifp; 2671 m->m_pkthdr.len = m->m_len = 2672 be32toh(desc->framelen) - UATH_RX_DUMMYSIZE; 2673 m->m_data += sizeof(struct uath_chunk); 2674 } else { 2675 mp = sc->sc_intrx_head; 2676 mp->m_pkthdr.rcvif = ifp; 2677 mp->m_flags |= M_PKTHDR; 2678 mp->m_pkthdr.len = sc->sc_intrx_len; 2679 m = mp; 2680 } 2681 2682 /* there are a lot more fields in the RX descriptor */ 2683 if ((sc->sc_flags & UATH_FLAG_INVALID) == 0 && 2684 ieee80211_radiotap_active(ic)) { 2685 struct uath_rx_radiotap_header *tap = &sc->sc_rxtap; 2686 uint32_t tsf_hi = be32toh(desc->tstamp_high); 2687 uint32_t tsf_lo = be32toh(desc->tstamp_low); 2688 2689 /* XXX only get low order 24bits of tsf from h/w */ 2690 tap->wr_tsf = htole64(((uint64_t)tsf_hi << 32) | tsf_lo); 2691 tap->wr_flags = 0; 2692 if (be32toh(desc->status) == UATH_STATUS_CRC_ERR) 2693 tap->wr_flags |= IEEE80211_RADIOTAP_F_BADFCS; 2694 /* XXX map other status to BADFCS? */ 2695 /* XXX ath h/w rate code, need to map */ 2696 tap->wr_rate = be32toh(desc->rate); 2697 tap->wr_antenna = be32toh(desc->antenna); 2698 tap->wr_antsignal = -95 + be32toh(desc->rssi); 2699 tap->wr_antnoise = -95; 2700 } 2701 2702 ifp->if_ipackets++; 2703 UATH_RESET_INTRX(sc); 2704 2705 return (m); 2706} 2707 2708static void 2709uath_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error) 2710{ 2711 struct uath_softc *sc = usbd_xfer_softc(xfer); 2712 struct ifnet *ifp = sc->sc_ifp; 2713 struct ieee80211com *ic = ifp->if_l2com; 2714 struct ieee80211_frame *wh; 2715 struct ieee80211_node *ni; 2716 struct mbuf *m = NULL; 2717 struct uath_data *data; 2718 struct uath_rx_desc *desc = NULL; 2719 int8_t nf; 2720 2721 UATH_ASSERT_LOCKED(sc); 2722 2723 switch (USB_GET_STATE(xfer)) { 2724 case USB_ST_TRANSFERRED: 2725 data = STAILQ_FIRST(&sc->sc_rx_active); 2726 if (data == NULL) 2727 goto setup; 2728 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 2729 UATH_STAT_DEC(sc, st_rx_active); 2730 m = uath_data_rxeof(xfer, data, &desc); 2731 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 2732 UATH_STAT_INC(sc, st_rx_inactive); 2733 /* FALLTHROUGH */ 2734 case USB_ST_SETUP: 2735setup: 2736 data = STAILQ_FIRST(&sc->sc_rx_inactive); 2737 if (data == NULL) 2738 return; 2739 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next); 2740 UATH_STAT_DEC(sc, st_rx_inactive); 2741 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next); 2742 UATH_STAT_INC(sc, st_rx_active); 2743 usbd_xfer_set_frame_data(xfer, 0, data->buf, MCLBYTES); 2744 usbd_transfer_submit(xfer); 2745 2746 /* 2747 * To avoid LOR we should unlock our private mutex here to call 2748 * ieee80211_input() because here is at the end of a USB 2749 * callback and safe to unlock. 2750 */ 2751 if (sc->sc_flags & UATH_FLAG_INVALID) { 2752 if (m != NULL) 2753 m_freem(m); 2754 return; 2755 } 2756 UATH_UNLOCK(sc); 2757 if (m != NULL && desc != NULL) { 2758 wh = mtod(m, struct ieee80211_frame *); 2759 ni = ieee80211_find_rxnode(ic, 2760 (struct ieee80211_frame_min *)wh); 2761 nf = -95; /* XXX */ 2762 if (ni != NULL) { 2763 (void) ieee80211_input(ni, m, 2764 (int)be32toh(desc->rssi), nf); 2765 /* node is no longer needed */ 2766 ieee80211_free_node(ni); 2767 } else 2768 (void) ieee80211_input_all(ic, m, 2769 (int)be32toh(desc->rssi), nf); 2770 m = NULL; 2771 desc = NULL; 2772 } 2773 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0 && 2774 !IFQ_IS_EMPTY(&ifp->if_snd)) 2775 uath_start(ifp); 2776 UATH_LOCK(sc); 2777 break; 2778 default: 2779 /* needs it to the inactive queue due to a error. */ 2780 data = STAILQ_FIRST(&sc->sc_rx_active); 2781 if (data != NULL) { 2782 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next); 2783 UATH_STAT_DEC(sc, st_rx_active); 2784 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next); 2785 UATH_STAT_INC(sc, st_rx_inactive); 2786 } 2787 if (error != USB_ERR_CANCELLED) { 2788 usbd_xfer_set_stall(xfer); 2789 ifp->if_ierrors++; 2790 goto setup; 2791 } 2792 break; 2793 } 2794} 2795 2796static void 2797uath_data_txeof(struct usb_xfer *xfer, struct uath_data *data) 2798{ 2799 struct uath_softc *sc = usbd_xfer_softc(xfer); 2800 struct ifnet *ifp = sc->sc_ifp; 2801 struct mbuf *m; 2802 2803 UATH_ASSERT_LOCKED(sc); 2804 2805 /* 2806 * Do any tx complete callback. Note this must be done before releasing 2807 * the node reference. 2808 */ 2809 if (data->m) { 2810 m = data->m; 2811 if (m->m_flags & M_TXCB && 2812 (sc->sc_flags & UATH_FLAG_INVALID) == 0) { 2813 /* XXX status? */ 2814 ieee80211_process_callback(data->ni, m, 0); 2815 } 2816 m_freem(m); 2817 data->m = NULL; 2818 } 2819 if (data->ni) { 2820 if ((sc->sc_flags & UATH_FLAG_INVALID) == 0) 2821 ieee80211_free_node(data->ni); 2822 data->ni = NULL; 2823 } 2824 sc->sc_tx_timer = 0; 2825 ifp->if_opackets++; 2826 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2827} 2828 2829static void 2830uath_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error) 2831{ 2832 struct uath_softc *sc = usbd_xfer_softc(xfer); 2833 struct ifnet *ifp = sc->sc_ifp; 2834 struct uath_data *data; 2835 2836 UATH_ASSERT_LOCKED(sc); 2837 2838 switch (USB_GET_STATE(xfer)) { 2839 case USB_ST_TRANSFERRED: 2840 data = STAILQ_FIRST(&sc->sc_tx_active); 2841 if (data == NULL) 2842 goto setup; 2843 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next); 2844 UATH_STAT_DEC(sc, st_tx_active); 2845 uath_data_txeof(xfer, data); 2846 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next); 2847 UATH_STAT_INC(sc, st_tx_inactive); 2848 /* FALLTHROUGH */ 2849 case USB_ST_SETUP: 2850setup: 2851 data = STAILQ_FIRST(&sc->sc_tx_pending); 2852 if (data == NULL) { 2853 DPRINTF(sc, UATH_DEBUG_XMIT, "%s: empty pending queue\n", 2854 __func__); 2855 return; 2856 } 2857 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next); 2858 UATH_STAT_DEC(sc, st_tx_pending); 2859 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next); 2860 UATH_STAT_INC(sc, st_tx_active); 2861 2862 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen); 2863 usbd_transfer_submit(xfer); 2864 2865 UATH_UNLOCK(sc); 2866 uath_start(ifp); 2867 UATH_LOCK(sc); 2868 break; 2869 default: 2870 data = STAILQ_FIRST(&sc->sc_tx_active); 2871 if (data == NULL) 2872 goto setup; 2873 if (data->ni != NULL) { 2874 if ((sc->sc_flags & UATH_FLAG_INVALID) == 0) 2875 ieee80211_free_node(data->ni); 2876 data->ni = NULL; 2877 ifp->if_oerrors++; 2878 } 2879 if (error != USB_ERR_CANCELLED) { 2880 usbd_xfer_set_stall(xfer); 2881 goto setup; 2882 } 2883 break; 2884 } 2885} 2886 2887static device_method_t uath_methods[] = { 2888 DEVMETHOD(device_probe, uath_match), 2889 DEVMETHOD(device_attach, uath_attach), 2890 DEVMETHOD(device_detach, uath_detach), 2891 DEVMETHOD_END 2892}; 2893static driver_t uath_driver = { 2894 .name = "uath", 2895 .methods = uath_methods, 2896 .size = sizeof(struct uath_softc) 2897}; 2898static devclass_t uath_devclass; 2899 2900DRIVER_MODULE(uath, uhub, uath_driver, uath_devclass, NULL, 0); 2901MODULE_DEPEND(uath, wlan, 1, 1, 1); 2902MODULE_DEPEND(uath, usb, 1, 1, 1); 2903MODULE_VERSION(uath, 1); 2904