1/*- 2 * Copyright (c) 2012 Semihalf. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD$"); 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/kernel.h> 33#include <sys/bus.h> 34#include <machine/bus.h> 35 36#include <dev/uart/uart.h> 37#include <dev/uart/uart_cpu.h> 38#include <dev/uart/uart_bus.h> 39#include "uart_if.h" 40 41#include <sys/kdb.h> 42 43/* PL011 UART registers and masks*/ 44#define UART_DR 0x00 /* Data register */ 45#define DR_FE (1 << 8) /* Framing error */ 46#define DR_PE (1 << 9) /* Parity error */ 47#define DR_BE (1 << 10) /* Break error */ 48#define DR_OE (1 << 11) /* Overrun error */ 49 50#define UART_FR 0x06 /* Flag register */ 51#define FR_RXFF (1 << 6) /* Receive FIFO/reg full */ 52#define FR_TXFE (1 << 7) /* Transmit FIFO/reg empty */ 53 54#define UART_IBRD 0x09 /* Integer baud rate register */ 55#define IBRD_BDIVINT 0xffff /* Significant part of int. divisor value */ 56 57#define UART_FBRD 0x0a /* Fractional baud rate register */ 58#define FBRD_BDIVFRAC 0x3f /* Significant part of frac. divisor value */ 59 60#define UART_LCR_H 0x0b /* Line control register */ 61#define LCR_H_WLEN8 (0x3 << 5) 62#define LCR_H_WLEN7 (0x2 << 5) 63#define LCR_H_WLEN6 (0x1 << 5) 64#define LCR_H_FEN (1 << 4) /* FIFO mode enable */ 65#define LCR_H_STP2 (1 << 3) /* 2 stop frames at the end */ 66#define LCR_H_EPS (1 << 2) /* Even parity select */ 67#define LCR_H_PEN (1 << 1) /* Parity enable */ 68 69#define UART_CR 0x0c /* Control register */ 70#define CR_RXE (1 << 9) /* Receive enable */ 71#define CR_TXE (1 << 8) /* Transmit enable */ 72#define CR_UARTEN (1 << 0) /* UART enable */ 73 74#define UART_IMSC 0x0e /* Interrupt mask set/clear register */ 75#define IMSC_MASK_ALL 0x7ff /* Mask all interrupts */ 76 77#define UART_RIS 0x0f /* Raw interrupt status register */ 78#define UART_RXREADY (1 << 4) /* RX buffer full */ 79#define UART_TXEMPTY (1 << 5) /* TX buffer empty */ 80#define RIS_FE (1 << 7) /* Framing error interrupt status */ 81#define RIS_PE (1 << 8) /* Parity error interrupt status */ 82#define RIS_BE (1 << 9) /* Break error interrupt status */ 83#define RIS_OE (1 << 10) /* Overrun interrupt status */ 84 85#define UART_MIS 0x10 /* Masked interrupt status register */ 86#define UART_ICR 0x11 /* Interrupt clear register */ 87 88/* 89 * FIXME: actual register size is SoC-dependent, we need to handle it 90 */ 91#define __uart_getreg(bas, reg) \ 92 bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg)) 93#define __uart_setreg(bas, reg, value) \ 94 bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value) 95 96/* 97 * Low-level UART interface. 98 */ 99static int uart_pl011_probe(struct uart_bas *bas); 100static void uart_pl011_init(struct uart_bas *bas, int, int, int, int); 101static void uart_pl011_term(struct uart_bas *bas); 102static void uart_pl011_putc(struct uart_bas *bas, int); 103static int uart_pl011_rxready(struct uart_bas *bas); 104static int uart_pl011_getc(struct uart_bas *bas, struct mtx *); 105 106static struct uart_ops uart_pl011_ops = { 107 .probe = uart_pl011_probe, 108 .init = uart_pl011_init, 109 .term = uart_pl011_term, 110 .putc = uart_pl011_putc, 111 .rxready = uart_pl011_rxready, 112 .getc = uart_pl011_getc, 113}; 114 115static int 116uart_pl011_probe(struct uart_bas *bas) 117{ 118 119 return (0); 120} 121 122static void 123uart_pl011_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 124 int parity) 125{ 126 uint32_t ctrl, line; 127 uint32_t baud; 128 129 /* 130 * Zero all settings to make sure 131 * UART is disabled and not configured 132 */ 133 ctrl = line = 0x0; 134 __uart_setreg(bas, UART_CR, ctrl); 135 136 /* As we know UART is disabled we may setup the line */ 137 switch (databits) { 138 case 7: 139 line |= LCR_H_WLEN7; 140 break; 141 case 6: 142 line |= LCR_H_WLEN6; 143 break; 144 case 8: 145 default: 146 line |= LCR_H_WLEN8; 147 break; 148 } 149 150 /* TODO: Calculate divisors */ 151 baud = (0x1 << 16) | 0x28; 152 153 if (stopbits == 2) 154 line |= LCR_H_STP2; 155 else 156 line &= ~LCR_H_STP2; 157 158 if (parity) 159 line |= LCR_H_PEN; 160 else 161 line &= ~LCR_H_PEN; 162 163 /* Configure the rest */ 164 line &= ~LCR_H_FEN; 165 ctrl |= (CR_RXE | CR_TXE | CR_UARTEN); 166 167 __uart_setreg(bas, UART_IBRD, ((uint32_t)(baud >> 16)) & IBRD_BDIVINT); 168 __uart_setreg(bas, UART_FBRD, (uint32_t)(baud) & FBRD_BDIVFRAC); 169 170 /* Add config. to line before reenabling UART */ 171 __uart_setreg(bas, UART_LCR_H, (__uart_getreg(bas, UART_LCR_H) & 172 ~0xff) | line); 173 174 __uart_setreg(bas, UART_CR, ctrl); 175} 176 177static void 178uart_pl011_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 179 int parity) 180{ 181 /* Mask all interrupts */ 182 __uart_setreg(bas, UART_IMSC, __uart_getreg(bas, UART_IMSC) & 183 ~IMSC_MASK_ALL); 184 185 uart_pl011_param(bas, baudrate, databits, stopbits, parity); 186} 187 188static void 189uart_pl011_term(struct uart_bas *bas) 190{ 191} 192 193static void 194uart_pl011_putc(struct uart_bas *bas, int c) 195{ 196 197 while (!(__uart_getreg(bas, UART_FR) & FR_TXFE)) 198 ; 199 __uart_setreg(bas, UART_DR, c & 0xff); 200} 201 202static int 203uart_pl011_rxready(struct uart_bas *bas) 204{ 205 206 return (__uart_getreg(bas, UART_FR) & FR_RXFF); 207} 208 209static int 210uart_pl011_getc(struct uart_bas *bas, struct mtx *hwmtx) 211{ 212 int c; 213 214 while (!uart_pl011_rxready(bas)) 215 ; 216 c = __uart_getreg(bas, UART_DR) & 0xff; 217 218 return (c); 219} 220 221/* 222 * High-level UART interface. 223 */ 224struct uart_pl011_softc { 225 struct uart_softc base; 226 uint8_t fcr; 227 uint8_t ier; 228 uint8_t mcr; 229 230 uint8_t ier_mask; 231 uint8_t ier_rxbits; 232}; 233 234static int uart_pl011_bus_attach(struct uart_softc *); 235static int uart_pl011_bus_detach(struct uart_softc *); 236static int uart_pl011_bus_flush(struct uart_softc *, int); 237static int uart_pl011_bus_getsig(struct uart_softc *); 238static int uart_pl011_bus_ioctl(struct uart_softc *, int, intptr_t); 239static int uart_pl011_bus_ipend(struct uart_softc *); 240static int uart_pl011_bus_param(struct uart_softc *, int, int, int, int); 241static int uart_pl011_bus_probe(struct uart_softc *); 242static int uart_pl011_bus_receive(struct uart_softc *); 243static int uart_pl011_bus_setsig(struct uart_softc *, int); 244static int uart_pl011_bus_transmit(struct uart_softc *); 245 246static kobj_method_t uart_pl011_methods[] = { 247 KOBJMETHOD(uart_attach, uart_pl011_bus_attach), 248 KOBJMETHOD(uart_detach, uart_pl011_bus_detach), 249 KOBJMETHOD(uart_flush, uart_pl011_bus_flush), 250 KOBJMETHOD(uart_getsig, uart_pl011_bus_getsig), 251 KOBJMETHOD(uart_ioctl, uart_pl011_bus_ioctl), 252 KOBJMETHOD(uart_ipend, uart_pl011_bus_ipend), 253 KOBJMETHOD(uart_param, uart_pl011_bus_param), 254 KOBJMETHOD(uart_probe, uart_pl011_bus_probe), 255 KOBJMETHOD(uart_receive, uart_pl011_bus_receive), 256 KOBJMETHOD(uart_setsig, uart_pl011_bus_setsig), 257 KOBJMETHOD(uart_transmit, uart_pl011_bus_transmit), 258 { 0, 0 } 259}; 260 261struct uart_class uart_pl011_class = { 262 "uart_pl011", 263 uart_pl011_methods, 264 sizeof(struct uart_pl011_softc), 265 .uc_ops = &uart_pl011_ops, 266 .uc_range = 0x48, 267 .uc_rclk = 0 268}; 269 270static int 271uart_pl011_bus_attach(struct uart_softc *sc) 272{ 273 struct uart_bas *bas; 274 275 bas = &sc->sc_bas; 276 /* Enable RX & TX interrupts */ 277 __uart_setreg(bas, UART_IMSC, (UART_RXREADY | UART_TXEMPTY)); 278 /* Clear RX & TX interrupts */ 279 __uart_setreg(bas, UART_ICR, IMSC_MASK_ALL); 280 281 return (0); 282} 283 284static int 285uart_pl011_bus_detach(struct uart_softc *sc) 286{ 287 288 return (0); 289} 290 291static int 292uart_pl011_bus_flush(struct uart_softc *sc, int what) 293{ 294 295 return (0); 296} 297 298static int 299uart_pl011_bus_getsig(struct uart_softc *sc) 300{ 301 302 return (0); 303} 304 305static int 306uart_pl011_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 307{ 308 struct uart_bas *bas; 309 int error; 310 311 bas = &sc->sc_bas; 312 error = 0; 313 uart_lock(sc->sc_hwmtx); 314 switch (request) { 315 case UART_IOCTL_BREAK: 316 break; 317 case UART_IOCTL_BAUD: 318 *(int*)data = 115200; 319 break; 320 default: 321 error = EINVAL; 322 break; 323 } 324 uart_unlock(sc->sc_hwmtx); 325 326 return (error); 327} 328 329static int 330uart_pl011_bus_ipend(struct uart_softc *sc) 331{ 332 struct uart_bas *bas; 333 int ipend; 334 uint32_t ints; 335 336 bas = &sc->sc_bas; 337 uart_lock(sc->sc_hwmtx); 338 ints = __uart_getreg(bas, UART_MIS); 339 ipend = 0; 340 341 if (ints & UART_RXREADY) 342 ipend |= SER_INT_RXREADY; 343 if (ints & RIS_BE) 344 ipend |= SER_INT_BREAK; 345 if (ints & RIS_OE) 346 ipend |= SER_INT_OVERRUN; 347 if (ints & UART_TXEMPTY) { 348 if (sc->sc_txbusy) 349 ipend |= SER_INT_TXIDLE; 350 351 __uart_setreg(bas, UART_IMSC, UART_RXREADY); 352 } 353 354 uart_unlock(sc->sc_hwmtx); 355 356 return (ipend); 357} 358 359static int 360uart_pl011_bus_param(struct uart_softc *sc, int baudrate, int databits, 361 int stopbits, int parity) 362{ 363 364 uart_lock(sc->sc_hwmtx); 365 uart_pl011_param(&sc->sc_bas, baudrate, databits, stopbits, parity); 366 uart_unlock(sc->sc_hwmtx); 367 368 return (0); 369} 370 371static int 372uart_pl011_bus_probe(struct uart_softc *sc) 373{ 374 375 device_set_desc(sc->sc_dev, "PrimeCell UART (PL011)"); 376 377 sc->sc_rxfifosz = 1; 378 sc->sc_txfifosz = 1; 379 380 return (0); 381} 382 383static int 384uart_pl011_bus_receive(struct uart_softc *sc) 385{ 386 struct uart_bas *bas; 387 int rx; 388 uint32_t ints, xc; 389 390 bas = &sc->sc_bas; 391 uart_lock(sc->sc_hwmtx); 392 393 ints = __uart_getreg(bas, UART_MIS); 394 while (ints & UART_RXREADY) { 395 if (uart_rx_full(sc)) { 396 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 397 break; 398 } 399 xc = __uart_getreg(bas, UART_DR); 400 rx = xc & 0xff; 401 402 if (xc & DR_FE) 403 rx |= UART_STAT_FRAMERR; 404 if (xc & DR_PE) 405 rx |= UART_STAT_PARERR; 406 407 __uart_setreg(bas, UART_ICR, UART_RXREADY); 408 409 uart_rx_put(sc, rx); 410 ints = __uart_getreg(bas, UART_MIS); 411 } 412 413 uart_unlock(sc->sc_hwmtx); 414 415 return (0); 416} 417 418static int 419uart_pl011_bus_setsig(struct uart_softc *sc, int sig) 420{ 421 422 return (0); 423} 424 425static int 426uart_pl011_bus_transmit(struct uart_softc *sc) 427{ 428 struct uart_bas *bas; 429 int i; 430 431 bas = &sc->sc_bas; 432 uart_lock(sc->sc_hwmtx); 433 434 for (i = 0; i < sc->sc_txdatasz; i++) { 435 __uart_setreg(bas, UART_DR, sc->sc_txbuf[i]); 436 uart_barrier(bas); 437 } 438 sc->sc_txbusy = 1; 439 __uart_setreg(bas, UART_IMSC, (UART_RXREADY | UART_TXEMPTY)); 440 uart_unlock(sc->sc_hwmtx); 441 442 return (0); 443} 444