1223927Sray/*- 2223927Sray * Copyright (c) 2009, Aleksandr Rybalko 3223927Sray * All rights reserved. 4223927Sray * 5223927Sray * Redistribution and use in source and binary forms, with or without 6223927Sray * modification, are permitted provided that the following conditions 7223927Sray * are met: 8223927Sray * 1. Redistributions of source code must retain the above copyright 9223927Sray * notice unmodified, this list of conditions, and the following 10223927Sray * disclaimer. 11223927Sray * 2. Redistributions in binary form must reproduce the above copyright 12223927Sray * notice, this list of conditions and the following disclaimer in the 13223927Sray * documentation and/or other materials provided with the distribution. 14223927Sray * 15223927Sray * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16223927Sray * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17223927Sray * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18223927Sray * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19223927Sray * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20223927Sray * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21223927Sray * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22223927Sray * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23223927Sray * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24223927Sray * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25223927Sray * SUCH DAMAGE. 26223927Sray * 27223927Sray * $FreeBSD$ 28223927Sray */ 29223927Sray 30223927Sray#ifndef _IF_RTREG_H_ 31223927Sray#define _IF_RTREG_H_ 32223927Sray 33223927Sray#define RT_READ(sc, reg) \ 34223927Sray bus_space_read_4((sc)->bst, (sc)->bsh, reg) 35223927Sray 36223927Sray#define RT_WRITE(sc, reg, val) \ 37223927Sray bus_space_write_4((sc)->bst, (sc)->bsh, reg, val) 38223927Sray 39223927Sray#define GE_PORT_BASE 0x0000 40223927Sray 41223927Sray#define MDIO_ACCESS 0x00 42223927Sray#define MDIO_CMD_ONGO (1<<31) 43223927Sray#define MDIO_CMD_WR (1<<30) 44223927Sray#define MDIO_PHY_ADDR_MASK 0x1f000000 45223927Sray#define MDIO_PHY_ADDR_SHIFT 24 46223927Sray#define MDIO_PHYREG_ADDR_MASK 0x001f0000 47223927Sray#define MDIO_PHYREG_ADDR_SHIFT 16 48223927Sray#define MDIO_PHY_DATA_MASK 0x0000ffff 49223927Sray#define MDIO_PHY_DATA_SHIFT 0 50223927Sray 51223927Sray#define FE_GLO_CFG 0x08 /*Frame Engine Global Configuration */ 52223927Sray#define EXT_VLAN_TYPE_MASK 0xffff0000 53223927Sray#define EXT_VLAN_TYPE_SHIFT 16 54223927Sray#define EXT_VLAN_TYPE_DFLT 0x81000000 55223927Sray#define US_CYC_CNT_MASK 0x0000ff00 56223927Sray#define US_CYC_CNT_SHIFT 8 57223927Sray#define US_CYC_CNT_DFLT (132<<8) /* sys clocks per 1uS */ 58223927Sray#define L2_SPACE (8<<4) /* L2 space. Unit is 8 bytes */ 59223927Sray 60223927Sray#define FE_RST_GLO 0x0C /*Frame Engine Global Reset*/ 61223927Sray#define FC_DROP_CNT_MASK 0xffff0000 /*Flow cntrl drop count */ 62223927Sray#define FC_DROP_CNT_SHIFT 16 63223927Sray#define PSE_RESET (1<<0) 64223927Sray 65223927Sray#define FE_INT_STATUS 0x10 66223927Sray#define CNT_PPE_AF (1<<31) 67223927Sray#define CNT_GDM_AF (1<<29) 68223927Sray#define PSE_P2_FC (1<<26) 69223927Sray#define GDM_CRC_DROP (1<<25) 70223927Sray#define PSE_BUF_DROP (1<<24) 71223927Sray#define GDM_OTHER_DROP (1<<23) 72223927Sray#define PSE_P1_FC (1<<22) 73223927Sray#define PSE_P0_FC (1<<21) 74223927Sray#define PSE_FQ_EMPTY (1<<20) 75223927Sray#define INT_TX_COHERENT (1<<17) 76223927Sray#define INT_RX_COHERENT (1<<16) 77223927Sray#define INT_TXQ3_DONE (1<<11) 78223927Sray#define INT_TXQ2_DONE (1<<10) 79223927Sray#define INT_TXQ1_DONE (1<<9) 80223927Sray#define INT_TXQ0_DONE (1<<8) 81223927Sray#define INT_RX_DONE (1<<2) 82223927Sray#define TX_DLY_INT (1<<1) /* TXQ[0|1]_DONE with delay */ 83223927Sray#define RX_DLY_INT (1<<0) /* RX_DONE with delay */ 84223927Sray#define FE_INT_ENABLE 0x14 85223927Sray#define MDIO_CFG2 0x18 86223927Sray#define FOE_TS_T 0x1c 87223927Sray#define PSE_FQ_PCNT_MASK 0xff000000 88223927Sray#define PSE_FQ_PCNT_SHIFT 24 89223927Sray#define FOE_TS_TIMESTAMP_MASK 0x0000ffff 90223927Sray#define FOE_TS_TIMESTAMP_SHIFT 0 91223927Sray 92223927Sray#define GDMA1_BASE 0x0020 93223927Sray#define GDMA2_BASE 0x0060 94223927Sray#define CDMA_BASE 0x0080 95223927Sray 96223927Sray#define GDMA_FWD_CFG 0x00 /* Only GDMA */ 97223927Sray#define GDM_DROP_256B (1<<23) 98223927Sray#define GDM_ICS_EN (1<<22) 99223927Sray#define GDM_TCS_EN (1<<21) 100223927Sray#define GDM_UCS_EN (1<<20) 101223927Sray#define GDM_DISPAD (1<<18) 102223927Sray#define GDM_DISCRC (1<<17) 103223927Sray#define GDM_STRPCRC (1<<16) 104223927Sray#define GDM_UFRC_P_SHIFT 12 105223927Sray#define GDM_BFRC_P_SHIFT 8 106223927Sray#define GDM_MFRC_P_SHIFT 4 107223927Sray#define GDM_OFRC_P_SHIFT 0 108223927Sray#define GDM_XFRC_P_MASK 0x07 109223927Sray#define GDM_DST_PORT_CPU 0 110223927Sray#define GDM_DST_PORT_GDMA1 1 111223927Sray#define GDM_DST_PORT_GDMA2 2 112223927Sray#define GDM_DST_PORT_PPE 6 113223927Sray#define GDM_DST_PORT_DISCARD 7 114223927Sray 115223927Sray#define CDMA_CSG_CFG 0x00 /* Only CDMA */ 116223927Sray#define INS_VLAN_TAG (0x8100<<16) 117223927Sray#define ICS_GEN_EN (1<<2) 118223927Sray#define TCS_GEN_EN (1<<1) 119223927Sray#define UCS_GEN_EN (1<<0) 120223927Sray 121223927Sray#define GDMA_SCH_CFG 0x04 122223927Sray#define GDM1_SCH_MOD_MASK 0x03000000 123223927Sray#define GDM1_SCH_MOD_SHIFT 24 124223927Sray#define GDM1_SCH_MOD_WRR 0 125223927Sray#define GDM1_SCH_MOD_STRICT 1 126223927Sray#define GDM1_SCH_MOD_MIXED 2 127223927Sray#define GDM1_WT_1 0 128223927Sray#define GDM1_WT_2 1 129223927Sray#define GDM1_WT_4 2 130223927Sray#define GDM1_WT_8 3 131223927Sray#define GDM1_WT_16 4 132223927Sray#define GDM1_WT_Q3_SHIFT 12 133223927Sray#define GDM1_WT_Q2_SHIFT 8 134223927Sray#define GDM1_WT_Q1_SHIFT 4 135223927Sray#define GDM1_WT_Q0_SHIFT 0 136223927Sray 137223927Sray#define GDMA_SHPR_CFG 0x08 138223927Sray#define GDM1_SHPR_EN (1<<24) 139223927Sray#define GDM1_BK_SIZE_MASK 0x00ff0000 /* Bucket size 1kB units */ 140223927Sray#define GDM1_BK_SIZE_SHIFT 16 141223927Sray#define GDM1_TK_RATE_MASK 0x00003fff /* Shaper token rate 8B/ms units */ 142223927Sray#define GDM1_TK_RATE_SHIFT 0 143223927Sray 144223927Sray#define GDMA_MAC_ADRL 0x0C 145223927Sray#define GDMA_MAC_ADRH 0x10 146223927Sray 147223927Sray#define PPPOE_SID_0001 0x08 /* 0..15 SID0, 15..31 SID1 */ 148223927Sray#define PPPOE_SID_0203 0x0c 149223927Sray#define PPPOE_SID_0405 0x10 150223927Sray#define PPPOE_SID_0607 0x14 151223927Sray#define PPPOE_SID_0809 0x18 152223927Sray#define PPPOE_SID_1011 0x1c 153223927Sray#define PPPOE_SID_1213 0x20 154223927Sray#define PPPOE_SID_1415 0x24 155223927Sray#define VLAN_ID_0001 0x28 /* 0..11 VID0, 15..26 VID1 */ 156223927Sray#define VLAN_ID_0203 0x2c 157223927Sray#define VLAN_ID_0405 0x30 158223927Sray#define VLAN_ID_0607 0x34 159223927Sray#define VLAN_ID_0809 0x38 160223927Sray#define VLAN_ID_1011 0x3c 161223927Sray#define VLAN_ID_1213 0x40 162223927Sray#define VLAN_ID_1415 0x44 163223927Sray 164223927Sray#define PSE_BASE 0x0040 165223927Sray#define PSE_FQFC_CFG 0x00 166223927Sray#define FQ_MAX_PCNT_MASK 0xff000000 167223927Sray#define FQ_MAX_PCNT_SHIFT 24 168223927Sray#define FQ_FC_RLS_MASK 0x00ff0000 169223927Sray#define FQ_FC_RLS_SHIFT 16 170223927Sray#define FQ_FC_ASRT_MASK 0x0000ff00 171223927Sray#define FQ_FC_ASRT_SHIFT 8 172223927Sray#define FQ_FC_DROP_MASK 0x000000ff 173223927Sray#define FQ_FC_DROP_SHIFT 0 174223927Sray 175223927Sray#define CDMA_FC_CFG 0x04 176223927Sray#define GDMA1_FC_CFG 0x08 177223927Sray#define GDMA2_FC_CFG 0x0C 178223927Sray#define P_SHARING (1<<28) 179223927Sray#define P_HQ_DEF_MASK 0x0f000000 180223927Sray#define P_HQ_DEF_SHIFT 24 181223927Sray#define P_HQ_RESV_MASK 0x00ff0000 182223927Sray#define P_HQ_RESV_SHIFT 16 183223927Sray#define P_LQ_RESV_MASK 0x0000ff00 184223927Sray#define P_LQ_RESV_SHIFT 8 185223927Sray#define P_IQ_ASRT_MASK 0x000000ff 186223927Sray#define P_IQ_ASRT_SHIFT 0 187223927Sray 188223927Sray#define CDMA_OQ_STA 0x10 189223927Sray#define GDMA1_OQ_STA 0x14 190223927Sray#define GDMA2_OQ_STA 0x18 191223927Sray#define P_OQ3_PCNT_MASK 0xff000000 192223927Sray#define P_OQ3_PCNT_SHIFT 24 193223927Sray#define P_OQ2_PCNT_MASK 0x00ff0000 194223927Sray#define P_OQ2_PCNT_SHIFT 16 195223927Sray#define P_OQ1_PCNT_MASK 0x0000ff00 196223927Sray#define P_OQ1_PCNT_SHIFT 8 197223927Sray#define P_OQ0_PCNT_MASK 0x000000ff 198223927Sray#define P_OQ0_PCNT_SHIFT 0 199223927Sray 200223927Sray#define PSE_IQ_STA 0x1C 201223927Sray#define P6_OQ0_PCNT_MASK 0xff000000 202223927Sray#define P6_OQ0_PCNT_SHIFT 24 203223927Sray#define P2_IQ_PCNT_MASK 0x00ff0000 204223927Sray#define P2_IQ_PCNT_SHIFT 16 205223927Sray#define P1_IQ_PCNT_MASK 0x0000ff00 206223927Sray#define P1_IQ_PCNT_SHIFT 8 207223927Sray#define P0_IQ_PCNT_MASK 0x000000ff 208223927Sray#define P0_IQ_PCNT_SHIFT 0 209223927Sray 210223927Sray#define PDMA_BASE 0x0100 211223927Sray#define PDMA_GLO_CFG 0x00 212223927Sray#define FE_TX_WB_DDONE (1<<6) 213223927Sray#define FE_DMA_BT_SIZE4 (0<<4) 214223927Sray#define FE_DMA_BT_SIZE8 (1<<4) 215223927Sray#define FE_DMA_BT_SIZE16 (2<<4) 216223927Sray#define FE_RX_DMA_BUSY (1<<3) 217223927Sray#define FE_RX_DMA_EN (1<<2) 218223927Sray#define FE_TX_DMA_BUSY (1<<1) 219223927Sray#define FE_TX_DMA_EN (1<<0) 220223927Sray#define PDMA_RST_IDX 0x04 221223927Sray#define FE_RST_DRX_IDX0 (1<<16) 222223927Sray#define FE_RST_DTX_IDX3 (1<<3) 223223927Sray#define FE_RST_DTX_IDX2 (1<<2) 224223927Sray#define FE_RST_DTX_IDX1 (1<<1) 225223927Sray#define FE_RST_DTX_IDX0 (1<<0) 226223927Sray 227223927Sray#define PDMA_SCH_CFG 0x08 228223927Sray#define DELAY_INT_CFG 0x0C 229223927Sray#define TXDLY_INT_EN (1<<31) 230223927Sray#define TXMAX_PINT_SHIFT 24 231223927Sray#define TXMAX_PTIME_SHIFT 16 232223927Sray#define RXDLY_INT_EN (1<<15) 233223927Sray#define RXMAX_PINT_SHIFT 8 234223927Sray#define RXMAX_PTIME_SHIFT 0 235223927Sray 236223927Sray#define TX_BASE_PTR0 0x10 237223927Sray#define TX_MAX_CNT0 0x14 238223927Sray#define TX_CTX_IDX0 0x18 239223927Sray#define TX_DTX_IDX0 0x1C 240223927Sray 241223927Sray#define TX_BASE_PTR1 0x20 242223927Sray#define TX_MAX_CNT1 0x24 243223927Sray#define TX_CTX_IDX1 0x28 244223927Sray#define TX_DTX_IDX1 0x2C 245223927Sray 246223927Sray#define RX_BASE_PTR0 0x30 247223927Sray#define RX_MAX_CNT0 0x34 248223927Sray#define RX_CALC_IDX0 0x38 249223927Sray#define RX_DRX_IDX0 0x3C 250223927Sray 251223927Sray#define TX_BASE_PTR2 0x40 252223927Sray#define TX_MAX_CNT2 0x44 253223927Sray#define TX_CTX_IDX2 0x48 254223927Sray#define TX_DTX_IDX2 0x4C 255223927Sray 256223927Sray#define TX_BASE_PTR3 0x50 257223927Sray#define TX_MAX_CNT3 0x54 258223927Sray#define TX_CTX_IDX3 0x58 259223927Sray#define TX_DTX_IDX3 0x5C 260223927Sray 261223927Sray#define TX_BASE_PTR(qid) (((qid>1)?(0x20):(0x10)) + (qid) * 16) 262223927Sray#define TX_MAX_CNT(qid) (((qid>1)?(0x24):(0x14)) + (qid) * 16) 263223927Sray#define TX_CTX_IDX(qid) (((qid>1)?(0x28):(0x18)) + (qid) * 16) 264223927Sray#define TX_DTX_IDX(qid) (((qid>1)?(0x2c):(0x1c)) + (qid) * 16) 265223927Sray 266223927Sray#define PPE_BASE 0x0200 267223927Sray 268223927Sray#define CNTR_BASE 0x0400 269223927Sray#define PPE_AC_BCNT0 0x000 270223927Sray#define PPE_AC_PCNT0 0x004 271223927Sray#define PPE_AC_BCNT63 0x1F8 272223927Sray#define PPE_AC_PCNT63 0x1FC 273223927Sray#define PPE_MTR_CNT0 0x200 274223927Sray#define PPE_MTR_CNT63 0x2FC 275223927Sray#define GDMA_TX_GBCNT0 0x300 276223927Sray#define GDMA_TX_GPCNT0 0x304 277223927Sray#define GDMA_TX_SKIPCNT0 0x308 278223927Sray#define GDMA_TX_COLCNT0 0x30C 279223927Sray#define GDMA_RX_GBCNT0 0x320 280223927Sray#define GDMA_RX_GPCNT0 0x324 281223927Sray#define GDMA_RX_OERCNT0 0x328 282223927Sray#define GDMA_RX_FERCNT0 0x32C 283223927Sray#define GDMA_RX_SHORT_ERCNT0 0x330 284223927Sray#define GDMA_RX_LONG_ERCNT0 0x334 285223927Sray#define GDMA_RX_CSUM_ERCNT0 0x338 286223927Sray 287223927Sray#define POLICYTABLE_BASE 0x1000 288223927Sray 289223927Sray#endif /* _IF_RTREG_H_ */ 290