1/*- 2 * Copyright (c) 2009, Aleksandr Rybalko 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30#ifndef _IF_RTREG_H_ 31#define _IF_RTREG_H_ 32 33#define RT_READ(sc, reg) \ 34 bus_space_read_4((sc)->bst, (sc)->bsh, reg) 35 36#define RT_WRITE(sc, reg, val) \ 37 bus_space_write_4((sc)->bst, (sc)->bsh, reg, val) 38 39#define GE_PORT_BASE 0x0000 40 41#define MDIO_ACCESS 0x00 42#define MDIO_CMD_ONGO (1<<31) 43#define MDIO_CMD_WR (1<<30) 44#define MDIO_PHY_ADDR_MASK 0x1f000000 45#define MDIO_PHY_ADDR_SHIFT 24 46#define MDIO_PHYREG_ADDR_MASK 0x001f0000 47#define MDIO_PHYREG_ADDR_SHIFT 16 48#define MDIO_PHY_DATA_MASK 0x0000ffff 49#define MDIO_PHY_DATA_SHIFT 0 50 51#define FE_GLO_CFG 0x08 /*Frame Engine Global Configuration */ 52#define EXT_VLAN_TYPE_MASK 0xffff0000 53#define EXT_VLAN_TYPE_SHIFT 16 54#define EXT_VLAN_TYPE_DFLT 0x81000000 55#define US_CYC_CNT_MASK 0x0000ff00 56#define US_CYC_CNT_SHIFT 8 57#define US_CYC_CNT_DFLT (132<<8) /* sys clocks per 1uS */ 58#define L2_SPACE (8<<4) /* L2 space. Unit is 8 bytes */ 59 60#define FE_RST_GLO 0x0C /*Frame Engine Global Reset*/ 61#define FC_DROP_CNT_MASK 0xffff0000 /*Flow cntrl drop count */ 62#define FC_DROP_CNT_SHIFT 16 63#define PSE_RESET (1<<0) 64 65#define FE_INT_STATUS 0x10 66#define CNT_PPE_AF (1<<31) 67#define CNT_GDM_AF (1<<29) 68#define PSE_P2_FC (1<<26) 69#define GDM_CRC_DROP (1<<25) 70#define PSE_BUF_DROP (1<<24) 71#define GDM_OTHER_DROP (1<<23) 72#define PSE_P1_FC (1<<22) 73#define PSE_P0_FC (1<<21) 74#define PSE_FQ_EMPTY (1<<20) 75#define INT_TX_COHERENT (1<<17) 76#define INT_RX_COHERENT (1<<16) 77#define INT_TXQ3_DONE (1<<11) 78#define INT_TXQ2_DONE (1<<10) 79#define INT_TXQ1_DONE (1<<9) 80#define INT_TXQ0_DONE (1<<8) 81#define INT_RX_DONE (1<<2) 82#define TX_DLY_INT (1<<1) /* TXQ[0|1]_DONE with delay */ 83#define RX_DLY_INT (1<<0) /* RX_DONE with delay */ 84#define FE_INT_ENABLE 0x14 85#define MDIO_CFG2 0x18 86#define FOE_TS_T 0x1c 87#define PSE_FQ_PCNT_MASK 0xff000000 88#define PSE_FQ_PCNT_SHIFT 24 89#define FOE_TS_TIMESTAMP_MASK 0x0000ffff 90#define FOE_TS_TIMESTAMP_SHIFT 0 91 92#define GDMA1_BASE 0x0020 93#define GDMA2_BASE 0x0060 94#define CDMA_BASE 0x0080 95 96#define GDMA_FWD_CFG 0x00 /* Only GDMA */ 97#define GDM_DROP_256B (1<<23) 98#define GDM_ICS_EN (1<<22) 99#define GDM_TCS_EN (1<<21) 100#define GDM_UCS_EN (1<<20) 101#define GDM_DISPAD (1<<18) 102#define GDM_DISCRC (1<<17) 103#define GDM_STRPCRC (1<<16) 104#define GDM_UFRC_P_SHIFT 12 105#define GDM_BFRC_P_SHIFT 8 106#define GDM_MFRC_P_SHIFT 4 107#define GDM_OFRC_P_SHIFT 0 108#define GDM_XFRC_P_MASK 0x07 109#define GDM_DST_PORT_CPU 0 110#define GDM_DST_PORT_GDMA1 1 111#define GDM_DST_PORT_GDMA2 2 112#define GDM_DST_PORT_PPE 6 113#define GDM_DST_PORT_DISCARD 7 114 115#define CDMA_CSG_CFG 0x00 /* Only CDMA */ 116#define INS_VLAN_TAG (0x8100<<16) 117#define ICS_GEN_EN (1<<2) 118#define TCS_GEN_EN (1<<1) 119#define UCS_GEN_EN (1<<0) 120 121#define GDMA_SCH_CFG 0x04 122#define GDM1_SCH_MOD_MASK 0x03000000 123#define GDM1_SCH_MOD_SHIFT 24 124#define GDM1_SCH_MOD_WRR 0 125#define GDM1_SCH_MOD_STRICT 1 126#define GDM1_SCH_MOD_MIXED 2 127#define GDM1_WT_1 0 128#define GDM1_WT_2 1 129#define GDM1_WT_4 2 130#define GDM1_WT_8 3 131#define GDM1_WT_16 4 132#define GDM1_WT_Q3_SHIFT 12 133#define GDM1_WT_Q2_SHIFT 8 134#define GDM1_WT_Q1_SHIFT 4 135#define GDM1_WT_Q0_SHIFT 0 136 137#define GDMA_SHPR_CFG 0x08 138#define GDM1_SHPR_EN (1<<24) 139#define GDM1_BK_SIZE_MASK 0x00ff0000 /* Bucket size 1kB units */ 140#define GDM1_BK_SIZE_SHIFT 16 141#define GDM1_TK_RATE_MASK 0x00003fff /* Shaper token rate 8B/ms units */ 142#define GDM1_TK_RATE_SHIFT 0 143 144#define GDMA_MAC_ADRL 0x0C 145#define GDMA_MAC_ADRH 0x10 146 147#define PPPOE_SID_0001 0x08 /* 0..15 SID0, 15..31 SID1 */ 148#define PPPOE_SID_0203 0x0c 149#define PPPOE_SID_0405 0x10 150#define PPPOE_SID_0607 0x14 151#define PPPOE_SID_0809 0x18 152#define PPPOE_SID_1011 0x1c 153#define PPPOE_SID_1213 0x20 154#define PPPOE_SID_1415 0x24 155#define VLAN_ID_0001 0x28 /* 0..11 VID0, 15..26 VID1 */ 156#define VLAN_ID_0203 0x2c 157#define VLAN_ID_0405 0x30 158#define VLAN_ID_0607 0x34 159#define VLAN_ID_0809 0x38 160#define VLAN_ID_1011 0x3c 161#define VLAN_ID_1213 0x40 162#define VLAN_ID_1415 0x44 163 164#define PSE_BASE 0x0040 165#define PSE_FQFC_CFG 0x00 166#define FQ_MAX_PCNT_MASK 0xff000000 167#define FQ_MAX_PCNT_SHIFT 24 168#define FQ_FC_RLS_MASK 0x00ff0000 169#define FQ_FC_RLS_SHIFT 16 170#define FQ_FC_ASRT_MASK 0x0000ff00 171#define FQ_FC_ASRT_SHIFT 8 172#define FQ_FC_DROP_MASK 0x000000ff 173#define FQ_FC_DROP_SHIFT 0 174 175#define CDMA_FC_CFG 0x04 176#define GDMA1_FC_CFG 0x08 177#define GDMA2_FC_CFG 0x0C 178#define P_SHARING (1<<28) 179#define P_HQ_DEF_MASK 0x0f000000 180#define P_HQ_DEF_SHIFT 24 181#define P_HQ_RESV_MASK 0x00ff0000 182#define P_HQ_RESV_SHIFT 16 183#define P_LQ_RESV_MASK 0x0000ff00 184#define P_LQ_RESV_SHIFT 8 185#define P_IQ_ASRT_MASK 0x000000ff 186#define P_IQ_ASRT_SHIFT 0 187 188#define CDMA_OQ_STA 0x10 189#define GDMA1_OQ_STA 0x14 190#define GDMA2_OQ_STA 0x18 191#define P_OQ3_PCNT_MASK 0xff000000 192#define P_OQ3_PCNT_SHIFT 24 193#define P_OQ2_PCNT_MASK 0x00ff0000 194#define P_OQ2_PCNT_SHIFT 16 195#define P_OQ1_PCNT_MASK 0x0000ff00 196#define P_OQ1_PCNT_SHIFT 8 197#define P_OQ0_PCNT_MASK 0x000000ff 198#define P_OQ0_PCNT_SHIFT 0 199 200#define PSE_IQ_STA 0x1C 201#define P6_OQ0_PCNT_MASK 0xff000000 202#define P6_OQ0_PCNT_SHIFT 24 203#define P2_IQ_PCNT_MASK 0x00ff0000 204#define P2_IQ_PCNT_SHIFT 16 205#define P1_IQ_PCNT_MASK 0x0000ff00 206#define P1_IQ_PCNT_SHIFT 8 207#define P0_IQ_PCNT_MASK 0x000000ff 208#define P0_IQ_PCNT_SHIFT 0 209 210#define PDMA_BASE 0x0100 211#define PDMA_GLO_CFG 0x00 212#define FE_TX_WB_DDONE (1<<6) 213#define FE_DMA_BT_SIZE4 (0<<4) 214#define FE_DMA_BT_SIZE8 (1<<4) 215#define FE_DMA_BT_SIZE16 (2<<4) 216#define FE_RX_DMA_BUSY (1<<3) 217#define FE_RX_DMA_EN (1<<2) 218#define FE_TX_DMA_BUSY (1<<1) 219#define FE_TX_DMA_EN (1<<0) 220#define PDMA_RST_IDX 0x04 221#define FE_RST_DRX_IDX0 (1<<16) 222#define FE_RST_DTX_IDX3 (1<<3) 223#define FE_RST_DTX_IDX2 (1<<2) 224#define FE_RST_DTX_IDX1 (1<<1) 225#define FE_RST_DTX_IDX0 (1<<0) 226 227#define PDMA_SCH_CFG 0x08 228#define DELAY_INT_CFG 0x0C 229#define TXDLY_INT_EN (1<<31) 230#define TXMAX_PINT_SHIFT 24 231#define TXMAX_PTIME_SHIFT 16 232#define RXDLY_INT_EN (1<<15) 233#define RXMAX_PINT_SHIFT 8 234#define RXMAX_PTIME_SHIFT 0 235 236#define TX_BASE_PTR0 0x10 237#define TX_MAX_CNT0 0x14 238#define TX_CTX_IDX0 0x18 239#define TX_DTX_IDX0 0x1C 240 241#define TX_BASE_PTR1 0x20 242#define TX_MAX_CNT1 0x24 243#define TX_CTX_IDX1 0x28 244#define TX_DTX_IDX1 0x2C 245 246#define RX_BASE_PTR0 0x30 247#define RX_MAX_CNT0 0x34 248#define RX_CALC_IDX0 0x38 249#define RX_DRX_IDX0 0x3C 250 251#define TX_BASE_PTR2 0x40 252#define TX_MAX_CNT2 0x44 253#define TX_CTX_IDX2 0x48 254#define TX_DTX_IDX2 0x4C 255 256#define TX_BASE_PTR3 0x50 257#define TX_MAX_CNT3 0x54 258#define TX_CTX_IDX3 0x58 259#define TX_DTX_IDX3 0x5C 260 261#define TX_BASE_PTR(qid) (((qid>1)?(0x20):(0x10)) + (qid) * 16) 262#define TX_MAX_CNT(qid) (((qid>1)?(0x24):(0x14)) + (qid) * 16) 263#define TX_CTX_IDX(qid) (((qid>1)?(0x28):(0x18)) + (qid) * 16) 264#define TX_DTX_IDX(qid) (((qid>1)?(0x2c):(0x1c)) + (qid) * 16) 265 266#define PPE_BASE 0x0200 267 268#define CNTR_BASE 0x0400 269#define PPE_AC_BCNT0 0x000 270#define PPE_AC_PCNT0 0x004 271#define PPE_AC_BCNT63 0x1F8 272#define PPE_AC_PCNT63 0x1FC 273#define PPE_MTR_CNT0 0x200 274#define PPE_MTR_CNT63 0x2FC 275#define GDMA_TX_GBCNT0 0x300 276#define GDMA_TX_GPCNT0 0x304 277#define GDMA_TX_SKIPCNT0 0x308 278#define GDMA_TX_COLCNT0 0x30C 279#define GDMA_RX_GBCNT0 0x320 280#define GDMA_RX_GPCNT0 0x324 281#define GDMA_RX_OERCNT0 0x328 282#define GDMA_RX_FERCNT0 0x32C 283#define GDMA_RX_SHORT_ERCNT0 0x330 284#define GDMA_RX_LONG_ERCNT0 0x334 285#define GDMA_RX_CSUM_ERCNT0 0x338 286 287#define POLICYTABLE_BASE 0x1000 288 289#endif /* _IF_RTREG_H_ */ 290