1/*-
2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice unmodified, this list of conditions, and the following
10 *    disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * $FreeBSD$
27 *
28 */
29
30#ifndef _PCIVAR_H_
31#define	_PCIVAR_H_
32
33#include <sys/queue.h>
34
35/* some PCI bus constants */
36#define	PCI_MAXMAPS_0	6	/* max. no. of memory/port maps */
37#define	PCI_MAXMAPS_1	2	/* max. no. of maps for PCI to PCI bridge */
38#define	PCI_MAXMAPS_2	1	/* max. no. of maps for CardBus bridge */
39
40typedef uint64_t pci_addr_t;
41
42/* Interesting values for PCI power management */
43struct pcicfg_pp {
44    uint16_t	pp_cap;		/* PCI power management capabilities */
45    uint8_t	pp_status;	/* conf. space addr. of PM control/status reg */
46    uint8_t	pp_bse;		/* conf. space addr. of PM BSE reg */
47    uint8_t	pp_data;	/* conf. space addr. of PM data reg */
48};
49
50struct pci_map {
51    pci_addr_t	pm_value;	/* Raw BAR value */
52    pci_addr_t	pm_size;
53    uint8_t	pm_reg;
54    STAILQ_ENTRY(pci_map) pm_link;
55};
56
57struct vpd_readonly {
58    char	keyword[2];
59    char	*value;
60};
61
62struct vpd_write {
63    char	keyword[2];
64    char	*value;
65    int 	start;
66    int 	len;
67};
68
69struct pcicfg_vpd {
70    uint8_t	vpd_reg;	/* base register, + 2 for addr, + 4 data */
71    char	vpd_cached;
72    char	*vpd_ident;	/* string identifier */
73    int 	vpd_rocnt;
74    struct vpd_readonly *vpd_ros;
75    int 	vpd_wcnt;
76    struct vpd_write *vpd_w;
77};
78
79/* Interesting values for PCI MSI */
80struct pcicfg_msi {
81    uint16_t	msi_ctrl;	/* Message Control */
82    uint8_t	msi_location;	/* Offset of MSI capability registers. */
83    uint8_t	msi_msgnum;	/* Number of messages */
84    int		msi_alloc;	/* Number of allocated messages. */
85    uint64_t	msi_addr;	/* Contents of address register. */
86    uint16_t	msi_data;	/* Contents of data register. */
87    u_int	msi_handlers;
88};
89
90/* Interesting values for PCI MSI-X */
91struct msix_vector {
92    uint64_t	mv_address;	/* Contents of address register. */
93    uint32_t	mv_data;	/* Contents of data register. */
94    int		mv_irq;
95};
96
97struct msix_table_entry {
98    u_int	mte_vector;	/* 1-based index into msix_vectors array. */
99    u_int	mte_handlers;
100};
101
102struct pcicfg_msix {
103    uint16_t	msix_ctrl;	/* Message Control */
104    uint16_t	msix_msgnum;	/* Number of messages */
105    uint8_t	msix_location;	/* Offset of MSI-X capability registers. */
106    uint8_t	msix_table_bar;	/* BAR containing vector table. */
107    uint8_t	msix_pba_bar;	/* BAR containing PBA. */
108    uint32_t	msix_table_offset;
109    uint32_t	msix_pba_offset;
110    int		msix_alloc;	/* Number of allocated vectors. */
111    int		msix_table_len;	/* Length of virtual table. */
112    struct msix_table_entry *msix_table; /* Virtual table. */
113    struct msix_vector *msix_vectors;	/* Array of allocated vectors. */
114    struct resource *msix_table_res;	/* Resource containing vector table. */
115    struct resource *msix_pba_res;	/* Resource containing PBA. */
116};
117
118/* Interesting values for HyperTransport */
119struct pcicfg_ht {
120    uint8_t	ht_slave;	/* Non-zero if device is an HT slave. */
121    uint8_t	ht_msimap;	/* Offset of MSI mapping cap registers. */
122    uint16_t	ht_msictrl;	/* MSI mapping control */
123    uint64_t	ht_msiaddr;	/* MSI mapping base address */
124};
125
126/* Interesting values for PCI-express */
127struct pcicfg_pcie {
128    uint8_t	pcie_location;	/* Offset of PCI-e capability registers. */
129    uint8_t	pcie_type;	/* Device type. */
130    uint16_t	pcie_flags;	/* Device capabilities register. */
131    uint16_t	pcie_device_ctl; /* Device control register. */
132    uint16_t	pcie_link_ctl;	/* Link control register. */
133    uint16_t	pcie_slot_ctl;	/* Slot control register. */
134    uint16_t	pcie_root_ctl;	/* Root control register. */
135    uint16_t	pcie_device_ctl2; /* Second device control register. */
136    uint16_t	pcie_link_ctl2;	/* Second link control register. */
137    uint16_t	pcie_slot_ctl2;	/* Second slot control register. */
138};
139
140struct pcicfg_pcix {
141    uint16_t	pcix_command;
142    uint8_t	pcix_location;	/* Offset of PCI-X capability registers. */
143};
144
145/* config header information common to all header types */
146typedef struct pcicfg {
147    struct device *dev;		/* device which owns this */
148
149    STAILQ_HEAD(, pci_map) maps; /* BARs */
150
151    uint16_t	subvendor;	/* card vendor ID */
152    uint16_t	subdevice;	/* card device ID, assigned by card vendor */
153    uint16_t	vendor;		/* chip vendor ID */
154    uint16_t	device;		/* chip device ID, assigned by chip vendor */
155
156    uint16_t	cmdreg;		/* disable/enable chip and PCI options */
157    uint16_t	statreg;	/* supported PCI features and error state */
158
159    uint8_t	baseclass;	/* chip PCI class */
160    uint8_t	subclass;	/* chip PCI subclass */
161    uint8_t	progif;		/* chip PCI programming interface */
162    uint8_t	revid;		/* chip revision ID */
163
164    uint8_t	hdrtype;	/* chip config header type */
165    uint8_t	cachelnsz;	/* cache line size in 4byte units */
166    uint8_t	intpin;		/* PCI interrupt pin */
167    uint8_t	intline;	/* interrupt line (IRQ for PC arch) */
168
169    uint8_t	mingnt;		/* min. useful bus grant time in 250ns units */
170    uint8_t	maxlat;		/* max. tolerated bus grant latency in 250ns */
171    uint8_t	lattimer;	/* latency timer in units of 30ns bus cycles */
172
173    uint8_t	mfdev;		/* multi-function device (from hdrtype reg) */
174    uint8_t	nummaps;	/* actual number of PCI maps used */
175
176    uint32_t	domain;		/* PCI domain */
177    uint8_t	bus;		/* config space bus address */
178    uint8_t	slot;		/* config space slot address */
179    uint8_t	func;		/* config space function number */
180
181    struct pcicfg_pp pp;	/* Power management */
182    struct pcicfg_vpd vpd;	/* Vital product data */
183    struct pcicfg_msi msi;	/* PCI MSI */
184    struct pcicfg_msix msix;	/* PCI MSI-X */
185    struct pcicfg_ht ht;	/* HyperTransport */
186    struct pcicfg_pcie pcie;	/* PCI Express */
187    struct pcicfg_pcix pcix;	/* PCI-X */
188} pcicfgregs;
189
190/* additional type 1 device config header information (PCI to PCI bridge) */
191
192#define	PCI_PPBMEMBASE(h,l)  ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff)
193#define	PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff)
194#define	PCI_PPBIOBASE(h,l)   ((((h)<<16) + ((l)<<8)) & ~0xfff)
195#define	PCI_PPBIOLIMIT(h,l)  ((((h)<<16) + ((l)<<8)) | 0xfff)
196
197typedef struct {
198    pci_addr_t	pmembase;	/* base address of prefetchable memory */
199    pci_addr_t	pmemlimit;	/* topmost address of prefetchable memory */
200    uint32_t	membase;	/* base address of memory window */
201    uint32_t	memlimit;	/* topmost address of memory window */
202    uint32_t	iobase;		/* base address of port window */
203    uint32_t	iolimit;	/* topmost address of port window */
204    uint16_t	secstat;	/* secondary bus status register */
205    uint16_t	bridgectl;	/* bridge control register */
206    uint8_t	seclat;		/* CardBus latency timer */
207} pcih1cfgregs;
208
209/* additional type 2 device config header information (CardBus bridge) */
210
211typedef struct {
212    uint32_t	membase0;	/* base address of memory window */
213    uint32_t	memlimit0;	/* topmost address of memory window */
214    uint32_t	membase1;	/* base address of memory window */
215    uint32_t	memlimit1;	/* topmost address of memory window */
216    uint32_t	iobase0;	/* base address of port window */
217    uint32_t	iolimit0;	/* topmost address of port window */
218    uint32_t	iobase1;	/* base address of port window */
219    uint32_t	iolimit1;	/* topmost address of port window */
220    uint32_t	pccardif;	/* PC Card 16bit IF legacy more base addr. */
221    uint16_t	secstat;	/* secondary bus status register */
222    uint16_t	bridgectl;	/* bridge control register */
223    uint8_t	seclat;		/* CardBus latency timer */
224} pcih2cfgregs;
225
226extern uint32_t pci_numdevs;
227
228/* Only if the prerequisites are present */
229#if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_)
230struct pci_devinfo {
231        STAILQ_ENTRY(pci_devinfo) pci_links;
232	struct resource_list resources;
233	pcicfgregs		cfg;
234	struct pci_conf		conf;
235};
236#endif
237
238#ifdef _SYS_BUS_H_
239
240#include "pci_if.h"
241
242enum pci_device_ivars {
243    PCI_IVAR_SUBVENDOR,
244    PCI_IVAR_SUBDEVICE,
245    PCI_IVAR_VENDOR,
246    PCI_IVAR_DEVICE,
247    PCI_IVAR_DEVID,
248    PCI_IVAR_CLASS,
249    PCI_IVAR_SUBCLASS,
250    PCI_IVAR_PROGIF,
251    PCI_IVAR_REVID,
252    PCI_IVAR_INTPIN,
253    PCI_IVAR_IRQ,
254    PCI_IVAR_DOMAIN,
255    PCI_IVAR_BUS,
256    PCI_IVAR_SLOT,
257    PCI_IVAR_FUNCTION,
258    PCI_IVAR_ETHADDR,
259    PCI_IVAR_CMDREG,
260    PCI_IVAR_CACHELNSZ,
261    PCI_IVAR_MINGNT,
262    PCI_IVAR_MAXLAT,
263    PCI_IVAR_LATTIMER
264};
265
266/*
267 * Simplified accessors for pci devices
268 */
269#define	PCI_ACCESSOR(var, ivar, type)					\
270	__BUS_ACCESSOR(pci, var, PCI, ivar, type)
271
272PCI_ACCESSOR(subvendor,		SUBVENDOR,	uint16_t)
273PCI_ACCESSOR(subdevice,		SUBDEVICE,	uint16_t)
274PCI_ACCESSOR(vendor,		VENDOR,		uint16_t)
275PCI_ACCESSOR(device,		DEVICE,		uint16_t)
276PCI_ACCESSOR(devid,		DEVID,		uint32_t)
277PCI_ACCESSOR(class,		CLASS,		uint8_t)
278PCI_ACCESSOR(subclass,		SUBCLASS,	uint8_t)
279PCI_ACCESSOR(progif,		PROGIF,		uint8_t)
280PCI_ACCESSOR(revid,		REVID,		uint8_t)
281PCI_ACCESSOR(intpin,		INTPIN,		uint8_t)
282PCI_ACCESSOR(irq,		IRQ,		uint8_t)
283PCI_ACCESSOR(domain,		DOMAIN,		uint32_t)
284PCI_ACCESSOR(bus,		BUS,		uint8_t)
285PCI_ACCESSOR(slot,		SLOT,		uint8_t)
286PCI_ACCESSOR(function,		FUNCTION,	uint8_t)
287PCI_ACCESSOR(ether,		ETHADDR,	uint8_t *)
288PCI_ACCESSOR(cmdreg,		CMDREG,		uint8_t)
289PCI_ACCESSOR(cachelnsz,		CACHELNSZ,	uint8_t)
290PCI_ACCESSOR(mingnt,		MINGNT,		uint8_t)
291PCI_ACCESSOR(maxlat,		MAXLAT,		uint8_t)
292PCI_ACCESSOR(lattimer,		LATTIMER,	uint8_t)
293
294#undef PCI_ACCESSOR
295
296/*
297 * Operations on configuration space.
298 */
299static __inline uint32_t
300pci_read_config(device_t dev, int reg, int width)
301{
302    return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width);
303}
304
305static __inline void
306pci_write_config(device_t dev, int reg, uint32_t val, int width)
307{
308    PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width);
309}
310
311/*
312 * Ivars for pci bridges.
313 */
314
315/*typedef enum pci_device_ivars pcib_device_ivars;*/
316enum pcib_device_ivars {
317	PCIB_IVAR_DOMAIN,
318	PCIB_IVAR_BUS
319};
320
321#define	PCIB_ACCESSOR(var, ivar, type)					 \
322    __BUS_ACCESSOR(pcib, var, PCIB, ivar, type)
323
324PCIB_ACCESSOR(domain,		DOMAIN,		uint32_t)
325PCIB_ACCESSOR(bus,		BUS,		uint32_t)
326
327#undef PCIB_ACCESSOR
328
329/*
330 * PCI interrupt validation.  Invalid interrupt values such as 0 or 128
331 * on i386 or other platforms should be mapped out in the MD pcireadconf
332 * code and not here, since the only MI invalid IRQ is 255.
333 */
334#define	PCI_INVALID_IRQ		255
335#define	PCI_INTERRUPT_VALID(x)	((x) != PCI_INVALID_IRQ)
336
337/*
338 * Convenience functions.
339 *
340 * These should be used in preference to manually manipulating
341 * configuration space.
342 */
343static __inline int
344pci_enable_busmaster(device_t dev)
345{
346    return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev));
347}
348
349static __inline int
350pci_disable_busmaster(device_t dev)
351{
352    return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev));
353}
354
355static __inline int
356pci_enable_io(device_t dev, int space)
357{
358    return(PCI_ENABLE_IO(device_get_parent(dev), dev, space));
359}
360
361static __inline int
362pci_disable_io(device_t dev, int space)
363{
364    return(PCI_DISABLE_IO(device_get_parent(dev), dev, space));
365}
366
367static __inline int
368pci_get_vpd_ident(device_t dev, const char **identptr)
369{
370    return(PCI_GET_VPD_IDENT(device_get_parent(dev), dev, identptr));
371}
372
373static __inline int
374pci_get_vpd_readonly(device_t dev, const char *kw, const char **vptr)
375{
376    return(PCI_GET_VPD_READONLY(device_get_parent(dev), dev, kw, vptr));
377}
378
379/*
380 * Check if the address range falls within the VGA defined address range(s)
381 */
382static __inline int
383pci_is_vga_ioport_range(u_long start, u_long end)
384{
385
386	return (((start >= 0x3b0 && end <= 0x3bb) ||
387	    (start >= 0x3c0 && end <= 0x3df)) ? 1 : 0);
388}
389
390static __inline int
391pci_is_vga_memory_range(u_long start, u_long end)
392{
393
394	return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0);
395}
396
397/*
398 * PCI power states are as defined by ACPI:
399 *
400 * D0	State in which device is on and running.  It is receiving full
401 *	power from the system and delivering full functionality to the user.
402 * D1	Class-specific low-power state in which device context may or may not
403 *	be lost.  Buses in D1 cannot do anything to the bus that would force
404 *	devices on that bus to lose context.
405 * D2	Class-specific low-power state in which device context may or may
406 *	not be lost.  Attains greater power savings than D1.  Buses in D2
407 *	can cause devices on that bus to lose some context.  Devices in D2
408 *	must be prepared for the bus to be in D2 or higher.
409 * D3	State in which the device is off and not running.  Device context is
410 *	lost.  Power can be removed from the device.
411 */
412#define	PCI_POWERSTATE_D0	0
413#define	PCI_POWERSTATE_D1	1
414#define	PCI_POWERSTATE_D2	2
415#define	PCI_POWERSTATE_D3	3
416#define	PCI_POWERSTATE_UNKNOWN	-1
417
418static __inline int
419pci_set_powerstate(device_t dev, int state)
420{
421    return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state);
422}
423
424static __inline int
425pci_get_powerstate(device_t dev)
426{
427    return PCI_GET_POWERSTATE(device_get_parent(dev), dev);
428}
429
430static __inline int
431pci_find_cap(device_t dev, int capability, int *capreg)
432{
433    return (PCI_FIND_CAP(device_get_parent(dev), dev, capability, capreg));
434}
435
436static __inline int
437pci_find_extcap(device_t dev, int capability, int *capreg)
438{
439    return (PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg));
440}
441
442static __inline int
443pci_find_htcap(device_t dev, int capability, int *capreg)
444{
445    return (PCI_FIND_HTCAP(device_get_parent(dev), dev, capability, capreg));
446}
447
448static __inline int
449pci_alloc_msi(device_t dev, int *count)
450{
451    return (PCI_ALLOC_MSI(device_get_parent(dev), dev, count));
452}
453
454static __inline int
455pci_alloc_msix(device_t dev, int *count)
456{
457    return (PCI_ALLOC_MSIX(device_get_parent(dev), dev, count));
458}
459
460static __inline int
461pci_remap_msix(device_t dev, int count, const u_int *vectors)
462{
463    return (PCI_REMAP_MSIX(device_get_parent(dev), dev, count, vectors));
464}
465
466static __inline int
467pci_release_msi(device_t dev)
468{
469    return (PCI_RELEASE_MSI(device_get_parent(dev), dev));
470}
471
472static __inline int
473pci_msi_count(device_t dev)
474{
475    return (PCI_MSI_COUNT(device_get_parent(dev), dev));
476}
477
478static __inline int
479pci_msix_count(device_t dev)
480{
481    return (PCI_MSIX_COUNT(device_get_parent(dev), dev));
482}
483
484device_t pci_find_bsf(uint8_t, uint8_t, uint8_t);
485device_t pci_find_dbsf(uint32_t, uint8_t, uint8_t, uint8_t);
486device_t pci_find_device(uint16_t, uint16_t);
487device_t pci_find_class(uint8_t class, uint8_t subclass);
488
489/* Can be used by drivers to manage the MSI-X table. */
490int	pci_pending_msix(device_t dev, u_int index);
491
492int	pci_msi_device_blacklisted(device_t dev);
493int	pci_msix_device_blacklisted(device_t dev);
494
495void	pci_ht_map_msi(device_t dev, uint64_t addr);
496
497int	pci_get_max_read_req(device_t dev);
498void	pci_restore_state(device_t dev);
499void	pci_save_state(device_t dev);
500int	pci_set_max_read_req(device_t dev, int size);
501
502
503#ifdef BUS_SPACE_MAXADDR
504#if (BUS_SPACE_MAXADDR > 0xFFFFFFFF)
505#define	PCI_DMA_BOUNDARY	0x100000000
506#else
507#define	PCI_DMA_BOUNDARY	0
508#endif
509#endif
510
511#endif	/* _SYS_BUS_H_ */
512
513/*
514 * cdev switch for control device, initialised in generic PCI code
515 */
516extern struct cdevsw pcicdev;
517
518/*
519 * List of all PCI devices, generation count for the list.
520 */
521STAILQ_HEAD(devlist, pci_devinfo);
522
523extern struct devlist	pci_devq;
524extern uint32_t	pci_generation;
525
526struct pci_map *pci_find_bar(device_t dev, int reg);
527int	pci_bar_enabled(device_t dev, struct pci_map *pm);
528
529#define	VGA_PCI_BIOS_SHADOW_ADDR	0xC0000
530#define	VGA_PCI_BIOS_SHADOW_SIZE	131072
531
532int	vga_pci_is_boot_display(device_t dev);
533void *	vga_pci_map_bios(device_t dev, size_t *size);
534void	vga_pci_unmap_bios(device_t dev, void *bios);
535
536#endif /* _PCIVAR_H_ */
537