1/*- 2 * This file is provided under a dual BSD/GPLv2 license. When using or 3 * redistributing this file, you may do so under either license. 4 * 5 * GPL LICENSE SUMMARY 6 * 7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of version 2 of the GNU General Public License as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 21 * The full GNU General Public License is included in this distribution 22 * in the file called LICENSE.GPL. 23 * 24 * BSD LICENSE 25 * 26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 27 * All rights reserved. 28 * 29 * Redistribution and use in source and binary forms, with or without 30 * modification, are permitted provided that the following conditions 31 * are met: 32 * 33 * * Redistributions of source code must retain the above copyright 34 * notice, this list of conditions and the following disclaimer. 35 * * Redistributions in binary form must reproduce the above copyright 36 * notice, this list of conditions and the following disclaimer in 37 * the documentation and/or other materials provided with the 38 * distribution. 39 * 40 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 41 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 42 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 43 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 44 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 45 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 46 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 47 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 48 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 50 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 51 * 52 * $FreeBSD$ 53 */ 54#ifndef _SCU_BIOS_DEFINITIONS_H_ 55#define _SCU_BIOS_DEFINITIONS_H_ 56 57#ifdef __cplusplus 58extern "C" { 59#endif // __cplusplus 60 61/** 62 * IMPORTANT NOTE: 63 * This file can be used by an SCI Library based driver or 64 * stand-alone where the library is excluded. By excluding 65 * the SCI Library, inclusion of OS specific header files can 66 * be avoided. For example, a BIOS utility probably does not 67 * want to be bothered with inclusion of nested OS DDK include 68 * files that are not necessary for its function. 69 * 70 * To exclude the SCI Library, either uncomment the EXCLUDE_SCI_LIBRARY 71 * #define statement in environment.h or define the statement as an input 72 * to your compiler. 73 */ 74 75#include <dev/isci/environment.h> 76 77#ifndef EXCLUDE_SCI_LIBRARY 78#include <dev/isci/scil/sci_types.h> 79#include <dev/isci/scil/intel_sas.h> 80#include <dev/isci/scil/sci_controller_constants.h> 81#endif /* EXCLUDE_SCI_LIBRARY */ 82 83 84 85// For Intel Storage Controller Unit OEM Block 86#define SCI_OEM_PARAM_SIGNATURE "ISCUOEMB" 87 88#define SCI_PREBOOT_SOURCE_INIT (0x00) 89#define SCI_PREBOOT_SOURCE_OROM (0x80) 90#define SCI_PREBOOT_SOURCE_EFI (0x81) 91 92#define SCI_OEM_PARAM_VER_1_0 (0x10) 93#define SCI_OEM_PARAM_VER_1_1 (0x11) 94#define SCI_OEM_PARAM_VER_1_2 (0x12) 95#define SCI_OEM_PARAM_VER_1_3 (0x13) 96 97// current version 98#define SCI_OEM_PARAM_VER_CUR SCI_OEM_PARAM_VER_1_3 99 100// port configuration mode 101#define SCI_BIOS_MODE_MPC (0x00) 102#define SCI_BIOS_MODE_APC (0x01) 103 104 105#ifndef SCI_MAX_PHYS 106#define SCI_MAX_PHYS (4) 107#endif 108 109#ifndef SCI_MAX_PORTS 110#define SCI_MAX_PORTS (4) 111#endif 112 113 114/** 115 * @struct SCI_BIOS_OEM_PARAM_BLOCK_HDR 116 * 117 * @brief This structure defines the OEM Parameter block header. 118 */ 119typedef struct SCI_BIOS_OEM_PARAM_BLOCK_HDR 120{ 121 /** 122 * This field contains the OEM Parameter Block Signature which is 123 * used by BIOS and driver software to identify that the memory location 124 * contains valid OEM Parameter data. The value must be set to 125 * SCI_OEM_PARAM_SIGNATURE which is the string "ISCUOEMB" which 126 * stands for Intel Storage Controller Unit OEM Block. 127 */ 128 U8 signature[8]; 129 /** 130 * This field contains the size in bytes of the complete OEM 131 * Parameter Block, both header and payload hdr_length + 132 * (num_elements * element_length). 133 */ 134 U16 total_block_length; 135 /** 136 * This field contains the size in bytes of the 137 * SCI_BIOS_OEM_PARAM_BLOCK_HDR. It also indicates the offset from 138 * the beginning of this data structure to where the actual 139 * parameter data payload begins. 140 */ 141 U8 hdr_length; 142 /** 143 * This field contains the version info defining the structure 144 * of the OEM Parameter block. 145 */ 146 U8 version; 147 /** 148 * This field contains a value indicating the preboot initialization 149 * method (Option ROM or UEFI driver) so that after OS transition, 150 * the OS driver can know the preboot method. OEMs who build a single 151 * flash image where the preboot method is unknown at manufacturing 152 * time should set this field to SCI_PREBOOT_SOURCE_INIT. Then 153 * after the block is retrieved into host memory and under preboot 154 * driver control, the OROM or UEFI driver can set this field 155 * appropriately (SCI_PREBOOT_SOURCE_OROM and SCI_PREBOOT_SOURCE_EFI, 156 * respectively). 157 */ 158 U8 preboot_source; 159 /** 160 * This field contains the number of parameter descriptor elements 161 * (i.e. controller_elements) following this header. The number of 162 * elements corresponds to the number of SCU controller units contained 163 * in the platform: 164 * controller_element[0] = SCU0 165 * controller_element[1] = SCU1 166 */ 167 U8 num_elements; 168 /** 169 * This field contains the size in bytes of the descriptor element(s) 170 * in the block. 171 */ 172 U16 element_length; 173 /** 174 * Reserve fields for future use. 175 */ 176 U8 reserved[8]; 177 178} SCI_BIOS_OEM_PARAM_BLOCK_HDR_T; 179 180 181/** 182 * @struct SCIC_SDS_OEM_PARAMETERS VER 1.0 183 * 184 * @brief This structure delineates the various OEM parameters that must 185 * be set for the Intel SAS Storage Controller Unit (SCU). 186 */ 187typedef struct SCI_BIOS_OEM_PARAM_ELEMENT 188{ 189 /** 190 * Per SCU Controller Data 191 */ 192 struct 193 { 194 /** 195 * This field indicates the port configuration mode for 196 * this controller: 197 * Automatic Port Configuration(APC) or 198 * Manual Port Configuration (MPC). 199 * 200 * APC means the Platform OEM expects SCI to configure 201 * SAS Ports automatically according to the discovered SAS 202 * Address pairs of the endpoints, wide and/or narrow. 203 * 204 * MPC means the Platform OEM manually defines wide or narrow 205 * connectors by apriori assigning PHYs to SAS Ports. 206 * 207 * By default, the mode type is APC 208 * in APC mode, if ANY of the phy mask is non-zero, 209 * SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned 210 * from scic_oem_parameters_set AND the default oem 211 * configuration will be applied 212 * in MPC mode, if ALL of the phy masks are zero, 213 * SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned 214 * from scic_oem_parameters_set AND the default oem 215 * configuration will be applied 216 */ 217 U8 mode_type; 218 219 /** 220 * This field specifies the maximum number of direct attached 221 * devices the OEM will allow to have powered up simultaneously 222 * on this controller. This allows the OEM to avoid exceeding 223 * power supply limits for this platform. A value of zero 224 * indicates there are no restrictions. 225 */ 226 U8 max_number_concurrent_device_spin_up; 227 228 /** 229 * This field indicates OEM's desired default 230 * Spread Spectrum Clocking (SSC) setting for Tx: 231 * enabled = 1 232 * disabled = 0 233 */ 234 U8 do_enable_ssc; 235 236 U8 reserved; 237 238 } controller; 239 240 /** 241 * Per SAS Port data. 242 */ 243 struct 244 { 245 /** 246 * This field specifies the phys to be contained inside a port. 247 * The bit position in the mask specifies the index of the phy 248 * to be contained in the port. Multiple bits (i.e. phys) 249 * can be contained in a single port: 250 * Bit 0 = This controller's PHY index 0 (0x01) 251 * Bit 1 = This controller's PHY index 1 (0x02) 252 * Bit 2 = This controller's PHY index 2 (0x04) 253 * Bit 3 = This controller's PHY index 3 (0x08) 254 * 255 * Refer to the mode_type field for rules regarding APC and MPC mode. 256 * General rule: For APC mode phy_mask = 0 257 */ 258 U8 phy_mask; 259 260 } ports[SCI_MAX_PORTS]; // Up to 4 Ports per SCU controller unit 261 262 /** 263 * Per PHY Parameter data. 264 */ 265 struct 266 { 267 /** 268 * This field indicates the SAS Address that will be transmitted on 269 * this PHY index. The field is defined as a union, however, the 270 * OEM should use the U8 array definition when encoding it to ensure 271 * correct byte ordering. 272 * 273 * NOTE: If using APC MODE, along with phy_mask being set to ZERO, the 274 * SAS Addresses for all PHYs within a controller group SHALL be the 275 * same. 276 */ 277 union 278 { 279 /** 280 * The array should be stored in little endian order. For example, 281 * if the desired SAS Address is 0x50010B90_0003538D, then it 282 * should be stored in the following manner: 283 * array[0] = 0x90 284 * array[1] = 0x0B 285 * array[2] = 0x01 286 * array[3] = 0x50 287 * array[4] = 0x8D 288 * array[5] = 0x53 289 * array[6] = 0x03 290 * array[7] = 0x00 291 */ 292 U8 array[8]; 293 /** 294 * This is the typedef'd version of the SAS Address used in 295 * the SCI Library. 296 */ 297 SCI_SAS_ADDRESS_T sci_format; 298 299 } sas_address; 300 301 /** 302 * These are the per PHY equalization settings associated with the 303 * AFE XCVR Tx Amplitude and Equalization Control Register Set 304 * (0 thru 3). 305 * 306 * Operational Note: The following Look-Up-Table registers are engaged 307 * by the AFE block after the following: 308 * - Software programs the Link Layer AFE Look Up Table Control 309 * Registers (AFE_LUTCR). 310 * - Software sets AFE XCVR Tx Control Register Tx Equalization 311 * Enable bit. 312 */ 313 /** 314 * AFE_TX_AMP_CTRL0. This register is associated with AFE_LUTCR 315 * LUTSel=00b. It contains the Tx Equalization settings that will be 316 * used if a SATA 1.5Gbs or SATA 3.0Gbs device is direct-attached. 317 */ 318 U32 afe_tx_amp_control0; 319 320 /** 321 * AFE_TX_AMP_CTRL1. This register is associated with AFE_LUTCR 322 * LUTSel=01b. It contains the Tx Equalization settings that will 323 * be used if a SATA 6.0Gbs device is direct-attached. 324 */ 325 U32 afe_tx_amp_control1; 326 327 /** 328 * AFE_TX_AMP_CTRL2. This register is associated with AFE_LUTCR 329 * LUTSel=10b. It contains the Tx Equalization settings that will 330 * be used if a SAS 1.5Gbs or SAS 3.0Gbs device is direct-attached. 331 */ 332 U32 afe_tx_amp_control2; 333 334 /** 335 * AFE_TX_AMP_CTRL3. This register is associated with AFE_LUTCR 336 * LUTSel=11b. It contains the Tx Equalization settings that will 337 * be used if a SAS 6.0Gbs device is direct-attached. 338 */ 339 U32 afe_tx_amp_control3; 340 341 } phys[SCI_MAX_PHYS]; // 4 PHYs per SCU controller unit 342 343} SCI_BIOS_OEM_PARAM_ELEMENT_T; 344 345/** 346 * @struct SCIC_SDS_OEM_PARAMETERS VER 1.1 347 * 348 * @brief This structure delineates the various OEM parameters that must 349 * be set for the Intel SAS Storage Controller Unit (SCU). 350 */ 351typedef struct SCI_BIOS_OEM_PARAM_ELEMENT_v_1_1 352{ 353 /** 354 * Per SCU Controller Data 355 */ 356 struct 357 { 358 /** 359 * This field indicates the port configuration mode for 360 * this controller: 361 * Automatic Port Configuration(APC) or 362 * Manual Port Configuration (MPC). 363 * 364 * APC means the Platform OEM expects SCI to configure 365 * SAS Ports automatically according to the discovered SAS 366 * Address pairs of the endpoints, wide and/or narrow. 367 * 368 * MPC means the Platform OEM manually defines wide or narrow 369 * connectors by apriori assigning PHYs to SAS Ports. 370 * 371 * By default, the mode type is APC 372 * in APC mode, if ANY of the phy mask is non-zero, 373 * SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned 374 * from scic_oem_parameters_set AND the default oem 375 * configuration will be applied 376 * in MPC mode, if ALL of the phy masks are zero, 377 * SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned 378 * from scic_oem_parameters_set AND the default oem 379 * configuration will be applied 380 */ 381 U8 mode_type; 382 383 /** 384 * This field specifies the maximum number of direct attached 385 * devices the OEM will allow to have powered up simultaneously 386 * on this controller. This allows the OEM to avoid exceeding 387 * power supply limits for this platform. A value of zero 388 * indicates there are no restrictions. 389 */ 390 U8 max_number_concurrent_device_spin_up; 391 392 /** 393 * This bitfield indicates the OEM's desired default Tx 394 * Spread Spectrum Clocking (SSC) settings for SATA and SAS. 395 * NOTE: Default SSC Modulation Frequency is 31.5KHz. 396 *--------------------------------------------------------------------*/ 397 /** 398 * NOTE: Max spread for SATA is +0 / -5000 PPM. 399 * Down-spreading SSC (only method allowed for SATA): 400 * SATA SSC Tx Disabled = 0x0 401 * SATA SSC Tx at +0 / -1419 PPM Spread = 0x2 402 * SATA SSC Tx at +0 / -2129 PPM Spread = 0x3 403 * SATA SSC Tx at +0 / -4257 PPM Spread = 0x6 404 * SATA SSC Tx at +0 / -4967 PPM Spread = 0x7 405 */ 406 U8 ssc_sata_tx_spread_level : 4; 407 408 /** 409 * SAS SSC Tx Disabled = 0x0 410 * 411 * NOTE: Max spread for SAS down-spreading +0 / -2300 PPM 412 * Down-spreading SSC: 413 * SAS SSC Tx at +0 / -1419 PPM Spread = 0x2 414 * SAS SSC Tx at +0 / -2129 PPM Spread = 0x3 415 * 416 * NOTE: Max spread for SAS center-spreading +2300 / -2300 PPM 417 * Center-spreading SSC: 418 * SAS SSC Tx at +1064 / -1064 PPM Spread = 0x3 419 * SAS SSC Tx at +2129 / -2129 PPM Spread = 0x6 420 */ 421 U8 ssc_sas_tx_spread_level : 3; 422 /** 423 * NOTE: Refer to the SSC section of the SAS 2.x Specification 424 * for proper setting of this field. For standard SAS Initiator 425 * SAS PHY operation it should be 0 for Down-spreading. 426 * SAS SSC Tx spread type: 427 * Down-spreading SSC = 0 428 * Center-spreading SSC = 1 429 */ 430 U8 ssc_sas_tx_type : 1; 431 /*--------------------------------------------------------------------*/ 432 433 U8 reserved; 434 435 } controller; 436 437 /** 438 * Per SAS Port data. 439 */ 440 struct 441 { 442 /** 443 * This field specifies the phys to be contained inside a port. 444 * The bit position in the mask specifies the index of the phy 445 * to be contained in the port. Multiple bits (i.e. phys) 446 * can be contained in a single port: 447 * Bit 0 = This controller's PHY index 0 (0x01) 448 * Bit 1 = This controller's PHY index 1 (0x02) 449 * Bit 2 = This controller's PHY index 2 (0x04) 450 * Bit 3 = This controller's PHY index 3 (0x08) 451 * 452 * Refer to the mode_type field for rules regarding APC and MPC mode. 453 * General rule: For APC mode phy_mask = 0 454 */ 455 U8 phy_mask; 456 457 } ports[SCI_MAX_PORTS]; // Up to 4 Ports per SCU controller unit 458 459 /** 460 * Per PHY Parameter data. 461 */ 462 struct 463 { 464 /** 465 * This field indicates the SAS Address that will be transmitted on 466 * this PHY index. The field is defined as a union, however, the 467 * OEM should use the U8 array definition when encoding it to ensure 468 * correct byte ordering. 469 * 470 * NOTE: If using APC MODE, along with phy_mask being set to ZERO, the 471 * SAS Addresses for all PHYs within a controller group SHALL be the 472 * same. 473 */ 474 union 475 { 476 /** 477 * The array should be stored in little endian order. For example, 478 * if the desired SAS Address is 0x50010B90_0003538D, then it 479 * should be stored in the following manner: 480 * array[0] = 0x90 481 * array[1] = 0x0B 482 * array[2] = 0x01 483 * array[3] = 0x50 484 * array[4] = 0x8D 485 * array[5] = 0x53 486 * array[6] = 0x03 487 * array[7] = 0x00 488 */ 489 U8 array[8]; 490 /** 491 * This is the typedef'd version of the SAS Address used in 492 * the SCI Library. 493 */ 494 SCI_SAS_ADDRESS_T sci_format; 495 496 } sas_address; 497 498 /** 499 * These are the per PHY equalization settings associated with the 500 * AFE XCVR Tx Amplitude and Equalization Control Register Set 501 * (0 thru 3). 502 * 503 * Operational Note: The following Look-Up-Table registers are engaged 504 * by the AFE block after the following: 505 * - Software programs the Link Layer AFE Look Up Table Control 506 * Registers (AFE_LUTCR). 507 * - Software sets AFE XCVR Tx Control Register Tx Equalization 508 * Enable bit. 509 */ 510 /** 511 * AFE_TX_AMP_CTRL0. This register is associated with AFE_LUTCR 512 * LUTSel=00b. It contains the Tx Equalization settings that will be 513 * used if a SATA 1.5Gbs or SATA 3.0Gbs device is direct-attached. 514 */ 515 U32 afe_tx_amp_control0; 516 517 /** 518 * AFE_TX_AMP_CTRL1. This register is associated with AFE_LUTCR 519 * LUTSel=01b. It contains the Tx Equalization settings that will 520 * be used if a SATA 6.0Gbs device is direct-attached. 521 */ 522 U32 afe_tx_amp_control1; 523 524 /** 525 * AFE_TX_AMP_CTRL2. This register is associated with AFE_LUTCR 526 * LUTSel=10b. It contains the Tx Equalization settings that will 527 * be used if a SAS 1.5Gbs or SAS 3.0Gbs device is direct-attached. 528 */ 529 U32 afe_tx_amp_control2; 530 531 /** 532 * AFE_TX_AMP_CTRL3. This register is associated with AFE_LUTCR 533 * LUTSel=11b. It contains the Tx Equalization settings that will 534 * be used if a SAS 6.0Gbs device is direct-attached. 535 */ 536 U32 afe_tx_amp_control3; 537 538 } phys[SCI_MAX_PHYS]; // 4 PHYs per SCU controller unit 539 540} SCI_BIOS_OEM_PARAM_ELEMENT_v_1_1_T; 541 542/** 543 * @struct SCIC_SDS_OEM_PARAMETERS VER 1.2 544 * 545 * @brief This structure delineates the various OEM parameters that must 546 * be set for the Intel SAS Storage Controller Unit (SCU). 547 */ 548typedef struct SCI_BIOS_OEM_PARAM_ELEMENT_v_1_2 549{ 550 /** 551 * Per SCU Controller Data 552 */ 553 struct 554 { 555 /** 556 * This field indicates the port configuration mode for 557 * this controller: 558 * Automatic Port Configuration(APC) or 559 * Manual Port Configuration (MPC). 560 * 561 * APC means the Platform OEM expects SCI to configure 562 * SAS Ports automatically according to the discovered SAS 563 * Address pairs of the endpoints, wide and/or narrow. 564 * 565 * MPC means the Platform OEM manually defines wide or narrow 566 * connectors by apriori assigning PHYs to SAS Ports. 567 * 568 * By default, the mode type is APC 569 * in APC mode, if ANY of the phy mask is non-zero, 570 * SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned 571 * from scic_oem_parameters_set AND the default oem 572 * configuration will be applied 573 * in MPC mode, if ALL of the phy masks are zero, 574 * SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned 575 * from scic_oem_parameters_set AND the default oem 576 * configuration will be applied 577 */ 578 U8 mode_type; 579 580 /** 581 * This field specifies the maximum number of direct attached 582 * devices the OEM will allow to have powered up simultaneously 583 * on this controller. This allows the OEM to avoid exceeding 584 * power supply limits for this platform. A value of zero 585 * indicates there are no restrictions. 586 */ 587 U8 max_number_concurrent_device_spin_up; 588 589 /** 590 * This bitfield indicates the OEM's desired default Tx 591 * Spread Spectrum Clocking (SSC) settings for SATA and SAS. 592 * NOTE: Default SSC Modulation Frequency is 31.5KHz. 593 *--------------------------------------------------------------------*/ 594 /** 595 * NOTE: Max spread for SATA is +0 / -5000 PPM. 596 * Down-spreading SSC (only method allowed for SATA): 597 * SATA SSC Tx Disabled = 0x0 598 * SATA SSC Tx at +0 / -1419 PPM Spread = 0x2 599 * SATA SSC Tx at +0 / -2129 PPM Spread = 0x3 600 * SATA SSC Tx at +0 / -4257 PPM Spread = 0x6 601 * SATA SSC Tx at +0 / -4967 PPM Spread = 0x7 602 */ 603 U8 ssc_sata_tx_spread_level : 4; 604 605 /** 606 * SAS SSC Tx Disabled = 0x0 607 * 608 * NOTE: Max spread for SAS down-spreading +0 / -2300 PPM 609 * Down-spreading SSC: 610 * SAS SSC Tx at +0 / -1419 PPM Spread = 0x2 611 * SAS SSC Tx at +0 / -2129 PPM Spread = 0x3 612 * 613 * NOTE: Max spread for SAS center-spreading +2300 / -2300 PPM 614 * Center-spreading SSC: 615 * SAS SSC Tx at +1064 / -1064 PPM Spread = 0x3 616 * SAS SSC Tx at +2129 / -2129 PPM Spread = 0x6 617 */ 618 U8 ssc_sas_tx_spread_level : 3; 619 /** 620 * NOTE: Refer to the SSC section of the SAS 2.x Specification 621 * for proper setting of this field. For standard SAS Initiator 622 * SAS PHY operation it should be 0 for Down-spreading. 623 * SAS SSC Tx spread type: 624 * Down-spreading SSC = 0 625 * Center-spreading SSC = 1 626 */ 627 U8 ssc_sas_tx_type : 1; 628 629 /** 630 * This field indicates length of the SAS/SATA cable between 631 * host and device. 632 * This field is used make relationship between analog parameters of 633 * the phy in the silicon and length of the cable. 634 * Supported length: "short"- up to 3m, "long"- more than 3m 635 * This is bit mask field: 636 * 637 * BIT: 7 6 5 4 3 2 1 0 (LSB) 638 * ASSIGNMENT: <-><-><-><-><phy3><phy2><phy1><phy0> 639 * 640 * For short cable corresponding bit shall be reset, 641 * for long cable shall be set. 642 */ 643 U8 long_cable_selection_mask; 644 645 } controller; 646 647 /** 648 * Per SAS Port data. 649 */ 650 struct 651 { 652 /** 653 * This field specifies the phys to be contained inside a port. 654 * The bit position in the mask specifies the index of the phy 655 * to be contained in the port. Multiple bits (i.e. phys) 656 * can be contained in a single port: 657 * Bit 0 = This controller's PHY index 0 (0x01) 658 * Bit 1 = This controller's PHY index 1 (0x02) 659 * Bit 2 = This controller's PHY index 2 (0x04) 660 * Bit 3 = This controller's PHY index 3 (0x08) 661 * 662 * Refer to the mode_type field for rules regarding APC and MPC mode. 663 * General rule: For APC mode phy_mask = 0 664 */ 665 U8 phy_mask; 666 667 } ports[SCI_MAX_PORTS]; // Up to 4 Ports per SCU controller unit 668 669 /** 670 * Per PHY Parameter data. 671 */ 672 struct 673 { 674 /** 675 * This field indicates the SAS Address that will be transmitted on 676 * this PHY index. The field is defined as a union, however, the 677 * OEM should use the U8 array definition when encoding it to ensure 678 * correct byte ordering. 679 * 680 * NOTE: If using APC MODE, along with phy_mask being set to ZERO, the 681 * SAS Addresses for all PHYs within a controller group SHALL be the 682 * same. 683 */ 684 union 685 { 686 /** 687 * The array should be stored in little endian order. For example, 688 * if the desired SAS Address is 0x50010B90_0003538D, then it 689 * should be stored in the following manner: 690 * array[0] = 0x90 691 * array[1] = 0x0B 692 * array[2] = 0x01 693 * array[3] = 0x50 694 * array[4] = 0x8D 695 * array[5] = 0x53 696 * array[6] = 0x03 697 * array[7] = 0x00 698 */ 699 U8 array[8]; 700 /** 701 * This is the typedef'd version of the SAS Address used in 702 * the SCI Library. 703 */ 704 SCI_SAS_ADDRESS_T sci_format; 705 706 } sas_address; 707 708 /** 709 * These are the per PHY equalization settings associated with the 710 * AFE XCVR Tx Amplitude and Equalization Control Register Set 711 * (0 thru 3). 712 * 713 * Operational Note: The following Look-Up-Table registers are engaged 714 * by the AFE block after the following: 715 * - Software programs the Link Layer AFE Look Up Table Control 716 * Registers (AFE_LUTCR). 717 * - Software sets AFE XCVR Tx Control Register Tx Equalization 718 * Enable bit. 719 */ 720 /** 721 * AFE_TX_AMP_CTRL0. This register is associated with AFE_LUTCR 722 * LUTSel=00b. It contains the Tx Equalization settings that will be 723 * used if a SATA 1.5Gbs or SATA 3.0Gbs device is direct-attached. 724 */ 725 U32 afe_tx_amp_control0; 726 727 /** 728 * AFE_TX_AMP_CTRL1. This register is associated with AFE_LUTCR 729 * LUTSel=01b. It contains the Tx Equalization settings that will 730 * be used if a SATA 6.0Gbs device is direct-attached. 731 */ 732 U32 afe_tx_amp_control1; 733 734 /** 735 * AFE_TX_AMP_CTRL2. This register is associated with AFE_LUTCR 736 * LUTSel=10b. It contains the Tx Equalization settings that will 737 * be used if a SAS 1.5Gbs or SAS 3.0Gbs device is direct-attached. 738 */ 739 U32 afe_tx_amp_control2; 740 741 /** 742 * AFE_TX_AMP_CTRL3. This register is associated with AFE_LUTCR 743 * LUTSel=11b. It contains the Tx Equalization settings that will 744 * be used if a SAS 6.0Gbs device is direct-attached. 745 */ 746 U32 afe_tx_amp_control3; 747 748 } phys[SCI_MAX_PHYS]; // 4 PHYs per SCU controller unit 749 750} SCI_BIOS_OEM_PARAM_ELEMENT_v_1_2_T; 751 752/** 753 * @struct SCIC_SDS_OEM_PARAMETERS VER 1.3 754 * 755 * @brief This structure delineates the various OEM parameters that must 756 * be set for the Intel SAS Storage Controller Unit (SCU). 757 */ 758typedef struct SCI_BIOS_OEM_PARAM_ELEMENT_v_1_3 759{ 760 /** 761 * Per SCU Controller Data 762 */ 763 struct 764 { 765 /** 766 * This field indicates the port configuration mode for 767 * this controller: 768 * Automatic Port Configuration(APC) or 769 * Manual Port Configuration (MPC). 770 * 771 * APC means the Platform OEM expects SCI to configure 772 * SAS Ports automatically according to the discovered SAS 773 * Address pairs of the endpoints, wide and/or narrow. 774 * 775 * MPC means the Platform OEM manually defines wide or narrow 776 * connectors by apriori assigning PHYs to SAS Ports. 777 * 778 * By default, the mode type is APC 779 * in APC mode, if ANY of the phy mask is non-zero, 780 * SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned 781 * from scic_oem_parameters_set AND the default oem 782 * configuration will be applied 783 * in MPC mode, if ALL of the phy masks are zero, 784 * SCI_FAILURE_INVALID_PARAMETER_VALUE will be returned 785 * from scic_oem_parameters_set AND the default oem 786 * configuration will be applied 787 */ 788 U8 mode_type; 789 790 /** 791 * This field specifies the maximum number of direct attached 792 * devices the OEM will allow to have powered up simultaneously 793 * on this controller. This allows the OEM to avoid exceeding 794 * power supply limits for this platform. A value of zero 795 * indicates there are no restrictions. 796 */ 797 U8 max_number_concurrent_device_spin_up; 798 799 /** 800 * This bitfield indicates the OEM's desired default Tx 801 * Spread Spectrum Clocking (SSC) settings for SATA and SAS. 802 * NOTE: Default SSC Modulation Frequency is 31.5KHz. 803 *--------------------------------------------------------------------*/ 804 /** 805 * NOTE: Max spread for SATA is +0 / -5000 PPM. 806 * Down-spreading SSC (only method allowed for SATA): 807 * SATA SSC Tx Disabled = 0x0 808 * SATA SSC Tx at +0 / -1419 PPM Spread = 0x2 809 * SATA SSC Tx at +0 / -2129 PPM Spread = 0x3 810 * SATA SSC Tx at +0 / -4257 PPM Spread = 0x6 811 * SATA SSC Tx at +0 / -4967 PPM Spread = 0x7 812 */ 813 U8 ssc_sata_tx_spread_level : 4; 814 815 /** 816 * SAS SSC Tx Disabled = 0x0 817 * 818 * NOTE: Max spread for SAS down-spreading +0 / -2300 PPM 819 * Down-spreading SSC: 820 * SAS SSC Tx at +0 / -1419 PPM Spread = 0x2 821 * SAS SSC Tx at +0 / -2129 PPM Spread = 0x3 822 * 823 * NOTE: Max spread for SAS center-spreading +2300 / -2300 PPM 824 * Center-spreading SSC: 825 * SAS SSC Tx at +1064 / -1064 PPM Spread = 0x3 826 * SAS SSC Tx at +2129 / -2129 PPM Spread = 0x6 827 */ 828 U8 ssc_sas_tx_spread_level : 3; 829 /** 830 * NOTE: Refer to the SSC section of the SAS 2.x Specification 831 * for proper setting of this field. For standard SAS Initiator 832 * SAS PHY operation it should be 0 for Down-spreading. 833 * SAS SSC Tx spread type: 834 * Down-spreading SSC = 0 835 * Center-spreading SSC = 1 836 */ 837 U8 ssc_sas_tx_type : 1; 838 839 /** 840 * This field indicates length of the SAS/SATA cable between 841 * host and device. 842 * This field is used make relationship between analog parameters of 843 * the phy in the silicon and length of the cable. 844 * Supported cable attenuation levels: 845 * "short"- up to 3m, "medium"-3m to 6m, and "long"- more than 6m 846 * This is bit mask field: 847 * 848 * BIT: (MSB) 7 6 5 4 849 * ASSIGNMENT: <phy3><phy2><phy1><phy0> - Medium cable length assignment 850 * BIT: 3 2 1 0 (LSB) 851 * ASSIGNMENT: <phy3><phy2><phy1><phy0> - Long cable length assignment 852 * 853 * BITS 7-4 are set when the cable length is assigned to medium 854 * BITS 3-0 are set when the cable length is assigned to long 855 * The BIT positions are clear when the cable length is assigned to short 856 * Setting the bits for both long and medium cable length is undefined. 857 * 858 * A value of 0x84 would assign 859 * phy3 - medium 860 * phy2 - long 861 * phy1 - short 862 * phy0 - short 863 */ 864 U8 cable_selection_mask; 865 866 } controller; 867 868 /** 869 * Per SAS Port data. 870 */ 871 struct 872 { 873 /** 874 * This field specifies the phys to be contained inside a port. 875 * The bit position in the mask specifies the index of the phy 876 * to be contained in the port. Multiple bits (i.e. phys) 877 * can be contained in a single port: 878 * Bit 0 = This controller's PHY index 0 (0x01) 879 * Bit 1 = This controller's PHY index 1 (0x02) 880 * Bit 2 = This controller's PHY index 2 (0x04) 881 * Bit 3 = This controller's PHY index 3 (0x08) 882 * 883 * Refer to the mode_type field for rules regarding APC and MPC mode. 884 * General rule: For APC mode phy_mask = 0 885 */ 886 U8 phy_mask; 887 888 } ports[SCI_MAX_PORTS]; // Up to 4 Ports per SCU controller unit 889 890 /** 891 * Per PHY Parameter data. 892 */ 893 struct 894 { 895 /** 896 * This field indicates the SAS Address that will be transmitted on 897 * this PHY index. The field is defined as a union, however, the 898 * OEM should use the U8 array definition when encoding it to ensure 899 * correct byte ordering. 900 * 901 * NOTE: If using APC MODE, along with phy_mask being set to ZERO, the 902 * SAS Addresses for all PHYs within a controller group SHALL be the 903 * same. 904 */ 905 union 906 { 907 /** 908 * The array should be stored in little endian order. For example, 909 * if the desired SAS Address is 0x50010B90_0003538D, then it 910 * should be stored in the following manner: 911 * array[0] = 0x90 912 * array[1] = 0x0B 913 * array[2] = 0x01 914 * array[3] = 0x50 915 * array[4] = 0x8D 916 * array[5] = 0x53 917 * array[6] = 0x03 918 * array[7] = 0x00 919 */ 920 U8 array[8]; 921 /** 922 * This is the typedef'd version of the SAS Address used in 923 * the SCI Library. 924 */ 925 SCI_SAS_ADDRESS_T sci_format; 926 927 } sas_address; 928 929 /** 930 * These are the per PHY equalization settings associated with the 931 * AFE XCVR Tx Amplitude and Equalization Control Register Set 932 * (0 thru 3). 933 * 934 * Operational Note: The following Look-Up-Table registers are engaged 935 * by the AFE block after the following: 936 * - Software programs the Link Layer AFE Look Up Table Control 937 * Registers (AFE_LUTCR). 938 * - Software sets AFE XCVR Tx Control Register Tx Equalization 939 * Enable bit. 940 */ 941 /** 942 * AFE_TX_AMP_CTRL0. This register is associated with AFE_LUTCR 943 * LUTSel=00b. It contains the Tx Equalization settings that will be 944 * used if a SATA 1.5Gbs or SATA 3.0Gbs device is direct-attached. 945 */ 946 U32 afe_tx_amp_control0; 947 948 /** 949 * AFE_TX_AMP_CTRL1. This register is associated with AFE_LUTCR 950 * LUTSel=01b. It contains the Tx Equalization settings that will 951 * be used if a SATA 6.0Gbs device is direct-attached. 952 */ 953 U32 afe_tx_amp_control1; 954 955 /** 956 * AFE_TX_AMP_CTRL2. This register is associated with AFE_LUTCR 957 * LUTSel=10b. It contains the Tx Equalization settings that will 958 * be used if a SAS 1.5Gbs or SAS 3.0Gbs device is direct-attached. 959 */ 960 U32 afe_tx_amp_control2; 961 962 /** 963 * AFE_TX_AMP_CTRL3. This register is associated with AFE_LUTCR 964 * LUTSel=11b. It contains the Tx Equalization settings that will 965 * be used if a SAS 6.0Gbs device is direct-attached. 966 */ 967 U32 afe_tx_amp_control3; 968 969 } phys[SCI_MAX_PHYS]; // 4 PHYs per SCU controller unit 970 971} SCI_BIOS_OEM_PARAM_ELEMENT_v_1_3_T; 972 973/** 974 * @struct SCI_BIOS_OEM_PARAM_BLOCK 975 * 976 * @brief This structure defines the OEM Parameter block as it will be stored 977 * in the last 512 bytes of the PDR region in the SPI flash. It must be 978 * unpacked or pack(1). 979 */ 980typedef struct SCI_BIOS_OEM_PARAM_BLOCK 981{ 982 /** 983 * OEM Parameter Block header. 984 */ 985 SCI_BIOS_OEM_PARAM_BLOCK_HDR_T header; 986 987 /** 988 * Per controller element descriptor containing the controller's 989 * parameter data. The prototype defines just one of these descriptors, 990 * however, the actual runtime number is determined by the num_elements 991 * field in the header. 992 */ 993 SCI_BIOS_OEM_PARAM_ELEMENT_T controller_element[1]; 994 995} SCI_BIOS_OEM_PARAM_BLOCK_T; 996 997#ifdef __cplusplus 998} 999#endif // __cplusplus 1000 1001#endif // _SCU_BIOS_DEFINITIONS_H_ 1002 1003