1230557Sjimharris/*-
2230557Sjimharris * This file is provided under a dual BSD/GPLv2 license.  When using or
3230557Sjimharris * redistributing this file, you may do so under either license.
4230557Sjimharris *
5230557Sjimharris * GPL LICENSE SUMMARY
6230557Sjimharris *
7230557Sjimharris * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
8230557Sjimharris *
9230557Sjimharris * This program is free software; you can redistribute it and/or modify
10230557Sjimharris * it under the terms of version 2 of the GNU General Public License as
11230557Sjimharris * published by the Free Software Foundation.
12230557Sjimharris *
13230557Sjimharris * This program is distributed in the hope that it will be useful, but
14230557Sjimharris * WITHOUT ANY WARRANTY; without even the implied warranty of
15230557Sjimharris * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
16230557Sjimharris * General Public License for more details.
17230557Sjimharris *
18230557Sjimharris * You should have received a copy of the GNU General Public License
19230557Sjimharris * along with this program; if not, write to the Free Software
20230557Sjimharris * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
21230557Sjimharris * The full GNU General Public License is included in this distribution
22230557Sjimharris * in the file called LICENSE.GPL.
23230557Sjimharris *
24230557Sjimharris * BSD LICENSE
25230557Sjimharris *
26230557Sjimharris * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
27230557Sjimharris * All rights reserved.
28230557Sjimharris *
29230557Sjimharris * Redistribution and use in source and binary forms, with or without
30230557Sjimharris * modification, are permitted provided that the following conditions
31230557Sjimharris * are met:
32230557Sjimharris *
33230557Sjimharris *   * Redistributions of source code must retain the above copyright
34230557Sjimharris *     notice, this list of conditions and the following disclaimer.
35230557Sjimharris *   * Redistributions in binary form must reproduce the above copyright
36230557Sjimharris *     notice, this list of conditions and the following disclaimer in
37230557Sjimharris *     the documentation and/or other materials provided with the
38230557Sjimharris *     distribution.
39230557Sjimharris *
40230557Sjimharris * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
41230557Sjimharris * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
42230557Sjimharris * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
43230557Sjimharris * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
44230557Sjimharris * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
45230557Sjimharris * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
46230557Sjimharris * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
47230557Sjimharris * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
48230557Sjimharris * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
49230557Sjimharris * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
50230557Sjimharris * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
51230557Sjimharris *
52230557Sjimharris * $FreeBSD$
53230557Sjimharris */
54230557Sjimharris#ifndef _SCIC_SDS_PHY_H_
55230557Sjimharris#define _SCIC_SDS_PHY_H_
56230557Sjimharris
57230557Sjimharris/**
58230557Sjimharris * @file
59230557Sjimharris *
60230557Sjimharris * @brief This file contains the structures, constants and prototypes for the
61230557Sjimharris *        SCIC_SDS_PHY object.
62230557Sjimharris */
63230557Sjimharris
64230557Sjimharris#ifdef __cplusplus
65230557Sjimharrisextern "C" {
66230557Sjimharris#endif // __cplusplus
67230557Sjimharris
68230557Sjimharris#include <dev/isci/scil/intel_sata.h>
69230557Sjimharris#include <dev/isci/scil/intel_sas.h>
70230557Sjimharris#include <dev/isci/scil/sci_base_phy.h>
71230557Sjimharris#include <dev/isci/scil/scu_registers.h>
72230557Sjimharris#include <dev/isci/scil/scu_event_codes.h>
73230557Sjimharris
74230557Sjimharris/**
75230557Sjimharris * This is the timeout value for the SATA phy to wait for a SIGNATURE FIS
76230557Sjimharris * before restarting the starting state machine.  Technically, the old
77230557Sjimharris * parallel ATA specification required up to 30 seconds for a device to
78230557Sjimharris * issue its signature FIS as a result of a soft reset.  Now we see that
79230557Sjimharris * devices respond generally within 15 seconds, but we'll use 25 for now.
80230557Sjimharris */
81230557Sjimharris#define SCIC_SDS_SIGNATURE_FIS_TIMEOUT    25000
82230557Sjimharris
83230557Sjimharris/**
84230557Sjimharris * This is the timeout for the SATA OOB/SN because the hardware does not
85230557Sjimharris * recognize a hot plug after OOB signal but before the SN signals.  We
86230557Sjimharris * need to make sure after a hotplug timeout if we have not received the
87230557Sjimharris * speed event notification from the hardware that we restart the hardware
88230557Sjimharris * OOB state machine.
89230557Sjimharris */
90230557Sjimharris#define SCIC_SDS_SATA_LINK_TRAINING_TIMEOUT  250
91230557Sjimharris
92230557Sjimharris/**
93230557Sjimharris * @enum SCIC_SDS_PHY_STARTING_SUBSTATES
94230557Sjimharris */
95230557Sjimharrisenum SCIC_SDS_PHY_STARTING_SUBSTATES
96230557Sjimharris{
97230557Sjimharris   /**
98230557Sjimharris    * Initial state
99230557Sjimharris    */
100230557Sjimharris   SCIC_SDS_PHY_STARTING_SUBSTATE_INITIAL,
101230557Sjimharris
102230557Sjimharris   /**
103230557Sjimharris    * Wait state for the hardware OSSP event type notification
104230557Sjimharris    */
105230557Sjimharris   SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_OSSP_EN,
106230557Sjimharris
107230557Sjimharris   /**
108230557Sjimharris    * Wait state for the PHY speed notification
109230557Sjimharris    */
110230557Sjimharris   SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SAS_SPEED_EN,
111230557Sjimharris
112230557Sjimharris   /**
113230557Sjimharris    * Wait state for the IAF Unsolicited frame notification
114230557Sjimharris    */
115230557Sjimharris   SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_IAF_UF,
116230557Sjimharris
117230557Sjimharris   /**
118230557Sjimharris    * Wait state for the request to consume power
119230557Sjimharris    */
120230557Sjimharris   SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SAS_POWER,
121230557Sjimharris
122230557Sjimharris   /**
123230557Sjimharris    * Wait state for request to consume power
124230557Sjimharris    */
125230557Sjimharris   SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SATA_POWER,
126230557Sjimharris
127230557Sjimharris   /**
128230557Sjimharris    * Wait state for the SATA PHY notification
129230557Sjimharris    */
130230557Sjimharris   SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SATA_PHY_EN,
131230557Sjimharris
132230557Sjimharris   /**
133230557Sjimharris    * Wait for the SATA PHY speed notification
134230557Sjimharris    */
135230557Sjimharris   SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SATA_SPEED_EN,
136230557Sjimharris
137230557Sjimharris   /**
138230557Sjimharris    * Wait state for the SIGNATURE FIS unsolicited frame notification
139230557Sjimharris    */
140230557Sjimharris   SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SIG_FIS_UF,
141230557Sjimharris
142230557Sjimharris   /**
143230557Sjimharris    * Exit state for this state machine
144230557Sjimharris    */
145230557Sjimharris   SCIC_SDS_PHY_STARTING_SUBSTATE_FINAL,
146230557Sjimharris
147230557Sjimharris   /**
148230557Sjimharris    * Maximum number of substates for the STARTING state machine
149230557Sjimharris    */
150230557Sjimharris   SCIC_SDS_PHY_STARTING_MAX_SUBSTATES
151230557Sjimharris};
152230557Sjimharris
153230557Sjimharrisstruct SCIC_SDS_PORT;
154230557Sjimharrisstruct SCIC_SDS_CONTROLLER;
155230557Sjimharris
156230557Sjimharris#ifdef SCIC_DEBUG_ENABLED
157230557Sjimharris#define MAX_STATE_TRANSITION_RECORD    (256)
158230557Sjimharris
159230557Sjimharris/**
160230557Sjimharris * Debug code to record the state transitions for the phy object
161230557Sjimharris */
162230557Sjimharristypedef struct SCIC_SDS_PHY_STATE_RECORD
163230557Sjimharris{
164230557Sjimharris   SCI_BASE_OBSERVER_T  base_state_observer;
165230557Sjimharris   SCI_BASE_OBSERVER_T  starting_state_observer;
166230557Sjimharris
167230557Sjimharris   U16 index;
168230557Sjimharris
169230557Sjimharris   U32 state_transition_table[MAX_STATE_TRANSITION_RECORD];
170230557Sjimharris
171230557Sjimharris} SCIC_SDS_PHY_STATE_RECORD_T;
172230557Sjimharris#endif // SCIC_DEBUG_ENABLED
173230557Sjimharris
174230557Sjimharris/**
175230557Sjimharris * @enum
176230557Sjimharris *
177230557Sjimharris * @brief This enumeration provides a named phy type for the state machine
178230557Sjimharris */
179230557Sjimharrisenum SCIC_SDS_PHY_PROTOCOL
180230557Sjimharris{
181230557Sjimharris   /**
182230557Sjimharris    * This is an unknown phy type since there is either nothing on the other
183230557Sjimharris    * end or we have not detected the phy type as yet.
184230557Sjimharris    */
185230557Sjimharris   SCIC_SDS_PHY_PROTOCOL_UNKNOWN,
186230557Sjimharris
187230557Sjimharris   /**
188230557Sjimharris    * This is a SAS PHY
189230557Sjimharris    */
190230557Sjimharris   SCIC_SDS_PHY_PROTOCOL_SAS,
191230557Sjimharris
192230557Sjimharris   /**
193230557Sjimharris    * This is a SATA PHY
194230557Sjimharris    */
195230557Sjimharris   SCIC_SDS_PHY_PROTOCOL_SATA,
196230557Sjimharris
197230557Sjimharris   SCIC_SDS_MAX_PHY_PROTOCOLS
198230557Sjimharris};
199230557Sjimharris
200230557Sjimharris/**
201230557Sjimharris * @struct SCIC_SDS_PHY
202230557Sjimharris *
203230557Sjimharris * @brief This structure  contains or references all of the data necessary to
204230557Sjimharris *        represent the core phy object and SCU harware protocol engine.
205230557Sjimharris */
206230557Sjimharristypedef struct SCIC_SDS_PHY
207230557Sjimharris{
208230557Sjimharris   SCI_BASE_PHY_T parent;
209230557Sjimharris
210230557Sjimharris   /**
211230557Sjimharris    * This field specifies the port object that owns/contains this phy.
212230557Sjimharris    */
213230557Sjimharris   struct SCIC_SDS_PORT * owning_port;
214230557Sjimharris
215230557Sjimharris   /**
216230557Sjimharris    * This field indicates whether the phy supports 1.5 Gb/s, 3.0 Gb/s,
217230557Sjimharris    * or 6.0 Gb/s operation.
218230557Sjimharris    */
219230557Sjimharris   SCI_SAS_LINK_RATE max_negotiated_speed;
220230557Sjimharris
221230557Sjimharris   /**
222230557Sjimharris    * This member specifies the protocol being utilized on this phy.  This
223230557Sjimharris    * field contains a legitamite value once the PHY has link trained with
224230557Sjimharris    * a remote phy.
225230557Sjimharris    */
226230557Sjimharris   enum SCIC_SDS_PHY_PROTOCOL protocol;
227230557Sjimharris
228230557Sjimharris   /**
229230557Sjimharris    * This field specifies the index with which this phy is associated (0-3).
230230557Sjimharris    */
231230557Sjimharris   U8 phy_index;
232230557Sjimharris
233230557Sjimharris   /**
234230557Sjimharris    * This member indicates if this particular PHY has received a BCN while
235230557Sjimharris    * it had no port assignement.  This BCN will be reported once the phy is
236230557Sjimharris    * assigned to a port.
237230557Sjimharris    */
238230557Sjimharris   BOOL bcn_received_while_port_unassigned;
239230557Sjimharris
240230557Sjimharris   /**
241230557Sjimharris    * This field indicates if this PHY is currently in the process of
242230557Sjimharris    * link training (i.e. it has started OOB, but has yet to perform
243230557Sjimharris    * IAF exchange/Signature FIS reception).
244230557Sjimharris    */
245230557Sjimharris   BOOL is_in_link_training;
246230557Sjimharris
247230557Sjimharris   union
248230557Sjimharris   {
249230557Sjimharris      struct
250230557Sjimharris      {
251230557Sjimharris         SCI_SAS_IDENTIFY_ADDRESS_FRAME_T identify_address_frame_buffer;
252230557Sjimharris
253230557Sjimharris      } sas;
254230557Sjimharris
255230557Sjimharris      struct
256230557Sjimharris      {
257230557Sjimharris         SATA_FIS_REG_D2H_T signature_fis_buffer;
258230557Sjimharris
259230557Sjimharris      } sata;
260230557Sjimharris
261230557Sjimharris   } phy_type;
262230557Sjimharris
263230557Sjimharris   /**
264230557Sjimharris    * This field contains a reference to the timer utilized in detecting
265230557Sjimharris    * when a signature FIS timeout has occurred.  The signature FIS is the
266230557Sjimharris    * first FIS sent by an attached SATA device after OOB/SN.
267230557Sjimharris    */
268230557Sjimharris   void * sata_timeout_timer;
269230557Sjimharris
270230557Sjimharris   struct SCIC_SDS_PHY_STATE_HANDLER *state_handlers;
271230557Sjimharris
272230557Sjimharris   SCI_BASE_STATE_MACHINE_T starting_substate_machine;
273230557Sjimharris
274230557Sjimharris   #ifdef SCI_LOGGING
275230557Sjimharris   SCI_BASE_STATE_MACHINE_LOGGER_T starting_substate_machine_logger;
276230557Sjimharris   #endif
277230557Sjimharris
278230557Sjimharris   #ifdef SCIC_DEBUG_ENABLED
279230557Sjimharris   SCIC_SDS_PHY_STATE_RECORD_T state_record;
280230557Sjimharris   #endif // SCIC_DEBUG_ENABLED
281230557Sjimharris
282230557Sjimharris   /**
283230557Sjimharris    * This field tracks how many errors of each type have been detected since
284230557Sjimharris    *  the last controller reset or counter clear.  Note that these are only
285230557Sjimharris    *  for the error types that our driver needs to count manually.  See
286230557Sjimharris    *  SCU_ERR_CNT_* values defined in scu_event_codes.h.
287230557Sjimharris    */
288230557Sjimharris   U32   error_counter[SCU_ERR_CNT_MAX_INDEX];
289230557Sjimharris
290230557Sjimharris   /**
291230557Sjimharris    * This field is the pointer to the transport layer register for the SCU
292230557Sjimharris    * hardware.
293230557Sjimharris    */
294230557Sjimharris   SCU_TRANSPORT_LAYER_REGISTERS_T *transport_layer_registers;
295230557Sjimharris
296230557Sjimharris   /**
297230557Sjimharris    * This field points to the link layer register set within the SCU.
298230557Sjimharris    */
299230557Sjimharris   SCU_LINK_LAYER_REGISTERS_T *link_layer_registers;
300230557Sjimharris
301230557Sjimharris} SCIC_SDS_PHY_T;
302230557Sjimharris
303230557Sjimharris
304230557Sjimharristypedef SCI_STATUS (*SCIC_SDS_PHY_EVENT_HANDLER_T)(SCIC_SDS_PHY_T *, U32);
305230557Sjimharristypedef SCI_STATUS (*SCIC_SDS_PHY_FRAME_HANDLER_T)(SCIC_SDS_PHY_T *, U32);
306230557Sjimharristypedef SCI_STATUS (*SCIC_SDS_PHY_POWER_HANDLER_T)(SCIC_SDS_PHY_T *);
307230557Sjimharris
308230557Sjimharris/**
309230557Sjimharris * @struct SCIC_SDS_PHY_STATE_HANDLER
310230557Sjimharris */
311230557Sjimharristypedef struct SCIC_SDS_PHY_STATE_HANDLER
312230557Sjimharris{
313230557Sjimharris   /**
314230557Sjimharris    * This is the SCI_BASE_PHY object state handlers.
315230557Sjimharris    */
316230557Sjimharris   SCI_BASE_PHY_STATE_HANDLER_T parent;
317230557Sjimharris
318230557Sjimharris   /**
319230557Sjimharris    * The state handler for unsolicited frames received from the SCU hardware.
320230557Sjimharris    */
321230557Sjimharris   SCIC_SDS_PHY_FRAME_HANDLER_T frame_handler;
322230557Sjimharris
323230557Sjimharris   /**
324230557Sjimharris    * The state handler for events received from the SCU hardware.
325230557Sjimharris    */
326230557Sjimharris   SCIC_SDS_PHY_EVENT_HANDLER_T event_handler;
327230557Sjimharris
328230557Sjimharris   /**
329230557Sjimharris    * The state handler for staggered spinup.
330230557Sjimharris    */
331230557Sjimharris   SCIC_SDS_PHY_POWER_HANDLER_T consume_power_handler;
332230557Sjimharris
333230557Sjimharris} SCIC_SDS_PHY_STATE_HANDLER_T;
334230557Sjimharris
335230557Sjimharrisextern SCIC_SDS_PHY_STATE_HANDLER_T scic_sds_phy_state_handler_table[];
336230557Sjimharrisextern SCI_BASE_STATE_T scic_sds_phy_state_table[];
337230557Sjimharrisextern SCI_BASE_STATE_T scic_sds_phy_starting_substates[];
338230557Sjimharrisextern SCIC_SDS_PHY_STATE_HANDLER_T
339230557Sjimharris       scic_sds_phy_starting_substate_handler_table[];
340230557Sjimharris
341230557Sjimharris
342230557Sjimharris/**
343230557Sjimharris * This macro returns the phy index for the specified phy
344230557Sjimharris */
345230557Sjimharris#define scic_sds_phy_get_index(phy) \
346230557Sjimharris   ((phy)->phy_index)
347230557Sjimharris
348230557Sjimharris/**
349230557Sjimharris * @brief This macro returns the controller for this phy
350230557Sjimharris */
351230557Sjimharris#define scic_sds_phy_get_controller(phy) \
352230557Sjimharris   (scic_sds_port_get_controller((phy)->owning_port))
353230557Sjimharris
354230557Sjimharris/**
355230557Sjimharris * @brief This macro returns the state machine for the base phy
356230557Sjimharris */
357230557Sjimharris#define scic_sds_phy_get_base_state_machine(phy) \
358230557Sjimharris   (&(phy)->parent.state_machine)
359230557Sjimharris
360230557Sjimharris/**
361230557Sjimharris * @brief This macro returns the starting substate machine for
362230557Sjimharris *        this phy
363230557Sjimharris */
364230557Sjimharris#define scic_sds_phy_get_starting_substate_machine(phy) \
365230557Sjimharris   (&(phy)->starting_substate_machine)
366230557Sjimharris
367230557Sjimharris/**
368230557Sjimharris * @brief This macro sets the state handlers for this phy object
369230557Sjimharris */
370230557Sjimharris#define scic_sds_phy_set_state_handlers(phy, handlers) \
371230557Sjimharris   ((phy)->state_handlers = (handlers))
372230557Sjimharris
373230557Sjimharris/**
374230557Sjimharris * This macro set the base state handlers for the phy object.
375230557Sjimharris */
376230557Sjimharris#define scic_sds_phy_set_base_state_handlers(phy, state_id) \
377230557Sjimharris   scic_sds_phy_set_state_handlers( \
378230557Sjimharris      (phy), \
379230557Sjimharris      &scic_sds_phy_state_handler_table[(state_id)] \
380230557Sjimharris   )
381230557Sjimharris
382230557Sjimharris/**
383230557Sjimharris * This macro returns TRUE if the current base state for this phy is
384230557Sjimharris * SCI_BASE_PHY_STATE_READY
385230557Sjimharris */
386230557Sjimharris#define scic_sds_phy_is_ready(phy) \
387230557Sjimharris   ( \
388230557Sjimharris         SCI_BASE_PHY_STATE_READY \
389230557Sjimharris      == sci_base_state_machine_get_state( \
390230557Sjimharris            scic_sds_phy_get_base_state_machine(phy) \
391230557Sjimharris         ) \
392230557Sjimharris   )
393230557Sjimharris
394230557Sjimharris// ---------------------------------------------------------------------------
395230557Sjimharris
396230557SjimharrisU32 scic_sds_phy_get_object_size(void);
397230557Sjimharris
398230557SjimharrisU32 scic_sds_phy_get_min_timer_count(void);
399230557Sjimharris
400230557SjimharrisU32 scic_sds_phy_get_max_timer_count(void);
401230557Sjimharris
402230557Sjimharris// ---------------------------------------------------------------------------
403230557Sjimharris
404230557Sjimharrisvoid scic_sds_phy_construct(
405230557Sjimharris   struct SCIC_SDS_PHY  *this_phy,
406230557Sjimharris   struct SCIC_SDS_PORT *owning_port,
407230557Sjimharris   U8                    phy_index
408230557Sjimharris);
409230557Sjimharris
410230557SjimharrisSCI_PORT_HANDLE_T scic_sds_phy_get_port(
411230557Sjimharris   SCIC_SDS_PHY_T *this_phy
412230557Sjimharris);
413230557Sjimharris
414230557Sjimharrisvoid scic_sds_phy_set_port(
415230557Sjimharris   struct SCIC_SDS_PHY  *this_phy,
416230557Sjimharris   struct SCIC_SDS_PORT *owning_port
417230557Sjimharris);
418230557Sjimharris
419230557SjimharrisSCI_STATUS scic_sds_phy_initialize(
420230557Sjimharris   SCIC_SDS_PHY_T             *this_phy,
421230557Sjimharris   void                       *transport_layer_registers,
422230557Sjimharris   SCU_LINK_LAYER_REGISTERS_T *link_layer_registers
423230557Sjimharris);
424230557Sjimharris
425230557SjimharrisSCI_STATUS scic_sds_phy_reset(
426230557Sjimharris   SCIC_SDS_PHY_T * this_phy
427230557Sjimharris);
428230557Sjimharris
429230557Sjimharrisvoid scic_sds_phy_sata_timeout(
430230557Sjimharris   SCI_OBJECT_HANDLE_T cookie
431230557Sjimharris);
432230557Sjimharris
433230557Sjimharris// ---------------------------------------------------------------------------
434230557Sjimharris
435230557Sjimharrisvoid scic_sds_phy_suspend(
436230557Sjimharris   struct SCIC_SDS_PHY  *this_phy
437230557Sjimharris);
438230557Sjimharris
439230557Sjimharrisvoid scic_sds_phy_resume(
440230557Sjimharris   struct SCIC_SDS_PHY  *this_phy
441230557Sjimharris);
442230557Sjimharris
443230557Sjimharrisvoid scic_sds_phy_setup_transport(
444230557Sjimharris   struct SCIC_SDS_PHY * this_phy,
445230557Sjimharris   U32                   device_id
446230557Sjimharris);
447230557Sjimharris
448230557Sjimharris// ---------------------------------------------------------------------------
449230557Sjimharris
450230557SjimharrisSCI_STATUS scic_sds_phy_event_handler(
451230557Sjimharris   SCIC_SDS_PHY_T *this_phy,
452230557Sjimharris   U32 event_code
453230557Sjimharris);
454230557Sjimharris
455230557SjimharrisSCI_STATUS scic_sds_phy_frame_handler(
456230557Sjimharris   SCIC_SDS_PHY_T *this_phy,
457230557Sjimharris   U32 frame_index
458230557Sjimharris);
459230557Sjimharris
460230557SjimharrisSCI_STATUS scic_sds_phy_consume_power_handler(
461230557Sjimharris   SCIC_SDS_PHY_T *this_phy
462230557Sjimharris);
463230557Sjimharris
464230557Sjimharrisvoid scic_sds_phy_get_sas_address(
465230557Sjimharris   SCIC_SDS_PHY_T    *this_phy,
466230557Sjimharris   SCI_SAS_ADDRESS_T *sas_address
467230557Sjimharris);
468230557Sjimharris
469230557Sjimharrisvoid scic_sds_phy_get_attached_sas_address(
470230557Sjimharris   SCIC_SDS_PHY_T    *this_phy,
471230557Sjimharris   SCI_SAS_ADDRESS_T *sas_address
472230557Sjimharris);
473230557Sjimharris
474230557Sjimharrisvoid scic_sds_phy_get_protocols(
475230557Sjimharris   SCIC_SDS_PHY_T *this_phy,
476230557Sjimharris   SCI_SAS_IDENTIFY_ADDRESS_FRAME_PROTOCOLS_T * protocols
477230557Sjimharris);
478230557Sjimharris
479230557Sjimharrisvoid scic_sds_phy_get_attached_phy_protocols(
480230557Sjimharris   SCIC_SDS_PHY_T *this_phy,
481230557Sjimharris   SCI_SAS_IDENTIFY_ADDRESS_FRAME_PROTOCOLS_T * protocols
482230557Sjimharris);
483230557Sjimharris
484230557Sjimharris//****************************************************************************-
485230557Sjimharris//* SCIC SDS PHY Handler Methods
486230557Sjimharris//****************************************************************************-
487230557Sjimharris
488230557SjimharrisSCI_STATUS scic_sds_phy_default_start_handler(
489230557Sjimharris   SCI_BASE_PHY_T *phy
490230557Sjimharris);
491230557Sjimharris
492230557SjimharrisSCI_STATUS scic_sds_phy_default_stop_handler(
493230557Sjimharris   SCI_BASE_PHY_T *phy
494230557Sjimharris);
495230557Sjimharris
496230557SjimharrisSCI_STATUS scic_sds_phy_default_reset_handler(
497230557Sjimharris   SCI_BASE_PHY_T * phy
498230557Sjimharris);
499230557Sjimharris
500230557SjimharrisSCI_STATUS scic_sds_phy_default_destroy_handler(
501230557Sjimharris   SCI_BASE_PHY_T *phy
502230557Sjimharris);
503230557Sjimharris
504230557SjimharrisSCI_STATUS scic_sds_phy_default_frame_handler(
505230557Sjimharris   SCIC_SDS_PHY_T *phy,
506230557Sjimharris   U32 frame_index
507230557Sjimharris);
508230557Sjimharris
509230557SjimharrisSCI_STATUS scic_sds_phy_default_event_handler(
510230557Sjimharris   SCIC_SDS_PHY_T *phy,
511230557Sjimharris   U32 evnet_code
512230557Sjimharris);
513230557Sjimharris
514230557SjimharrisSCI_STATUS scic_sds_phy_default_consume_power_handler(
515230557Sjimharris   SCIC_SDS_PHY_T *phy
516230557Sjimharris);
517230557Sjimharris
518230557Sjimharrisvoid scic_sds_phy_release_resource(
519230557Sjimharris   struct SCIC_SDS_CONTROLLER * controller,
520230557Sjimharris   struct SCIC_SDS_PHY        * phy
521230557Sjimharris);
522230557Sjimharris
523230557Sjimharrisvoid scic_sds_phy_restart_starting_state(
524230557Sjimharris   struct SCIC_SDS_PHY        * this_phy
525230557Sjimharris);
526230557Sjimharris
527230557Sjimharris#ifdef __cplusplus
528230557Sjimharris}
529230557Sjimharris#endif // __cplusplus
530230557Sjimharris
531230557Sjimharris#endif // _SCIC_SDS_PHY_H_
532