1/*- 2 * This file is provided under a dual BSD/GPLv2 license. When using or 3 * redistributing this file, you may do so under either license. 4 * 5 * GPL LICENSE SUMMARY 6 * 7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of version 2 of the GNU General Public License as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 21 * The full GNU General Public License is included in this distribution 22 * in the file called LICENSE.GPL. 23 * 24 * BSD LICENSE 25 * 26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. 27 * All rights reserved. 28 * 29 * Redistribution and use in source and binary forms, with or without 30 * modification, are permitted provided that the following conditions 31 * are met: 32 * 33 * * Redistributions of source code must retain the above copyright 34 * notice, this list of conditions and the following disclaimer. 35 * * Redistributions in binary form must reproduce the above copyright 36 * notice, this list of conditions and the following disclaimer in 37 * the documentation and/or other materials provided with the 38 * distribution. 39 * 40 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 41 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 42 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 43 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 44 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 45 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 46 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 47 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 48 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 50 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 51 * 52 * $FreeBSD$ 53 */ 54#ifndef _SCIC_SDS_PHY_H_ 55#define _SCIC_SDS_PHY_H_ 56 57/** 58 * @file 59 * 60 * @brief This file contains the structures, constants and prototypes for the 61 * SCIC_SDS_PHY object. 62 */ 63 64#ifdef __cplusplus 65extern "C" { 66#endif // __cplusplus 67 68#include <dev/isci/scil/intel_sata.h> 69#include <dev/isci/scil/intel_sas.h> 70#include <dev/isci/scil/sci_base_phy.h> 71#include <dev/isci/scil/scu_registers.h> 72#include <dev/isci/scil/scu_event_codes.h> 73 74/** 75 * This is the timeout value for the SATA phy to wait for a SIGNATURE FIS 76 * before restarting the starting state machine. Technically, the old 77 * parallel ATA specification required up to 30 seconds for a device to 78 * issue its signature FIS as a result of a soft reset. Now we see that 79 * devices respond generally within 15 seconds, but we'll use 25 for now. 80 */ 81#define SCIC_SDS_SIGNATURE_FIS_TIMEOUT 25000 82 83/** 84 * This is the timeout for the SATA OOB/SN because the hardware does not 85 * recognize a hot plug after OOB signal but before the SN signals. We 86 * need to make sure after a hotplug timeout if we have not received the 87 * speed event notification from the hardware that we restart the hardware 88 * OOB state machine. 89 */ 90#define SCIC_SDS_SATA_LINK_TRAINING_TIMEOUT 250 91 92/** 93 * @enum SCIC_SDS_PHY_STARTING_SUBSTATES 94 */ 95enum SCIC_SDS_PHY_STARTING_SUBSTATES 96{ 97 /** 98 * Initial state 99 */ 100 SCIC_SDS_PHY_STARTING_SUBSTATE_INITIAL, 101 102 /** 103 * Wait state for the hardware OSSP event type notification 104 */ 105 SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_OSSP_EN, 106 107 /** 108 * Wait state for the PHY speed notification 109 */ 110 SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SAS_SPEED_EN, 111 112 /** 113 * Wait state for the IAF Unsolicited frame notification 114 */ 115 SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_IAF_UF, 116 117 /** 118 * Wait state for the request to consume power 119 */ 120 SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SAS_POWER, 121 122 /** 123 * Wait state for request to consume power 124 */ 125 SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SATA_POWER, 126 127 /** 128 * Wait state for the SATA PHY notification 129 */ 130 SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SATA_PHY_EN, 131 132 /** 133 * Wait for the SATA PHY speed notification 134 */ 135 SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SATA_SPEED_EN, 136 137 /** 138 * Wait state for the SIGNATURE FIS unsolicited frame notification 139 */ 140 SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SIG_FIS_UF, 141 142 /** 143 * Exit state for this state machine 144 */ 145 SCIC_SDS_PHY_STARTING_SUBSTATE_FINAL, 146 147 /** 148 * Maximum number of substates for the STARTING state machine 149 */ 150 SCIC_SDS_PHY_STARTING_MAX_SUBSTATES 151}; 152 153struct SCIC_SDS_PORT; 154struct SCIC_SDS_CONTROLLER; 155 156#ifdef SCIC_DEBUG_ENABLED 157#define MAX_STATE_TRANSITION_RECORD (256) 158 159/** 160 * Debug code to record the state transitions for the phy object 161 */ 162typedef struct SCIC_SDS_PHY_STATE_RECORD 163{ 164 SCI_BASE_OBSERVER_T base_state_observer; 165 SCI_BASE_OBSERVER_T starting_state_observer; 166 167 U16 index; 168 169 U32 state_transition_table[MAX_STATE_TRANSITION_RECORD]; 170 171} SCIC_SDS_PHY_STATE_RECORD_T; 172#endif // SCIC_DEBUG_ENABLED 173 174/** 175 * @enum 176 * 177 * @brief This enumeration provides a named phy type for the state machine 178 */ 179enum SCIC_SDS_PHY_PROTOCOL 180{ 181 /** 182 * This is an unknown phy type since there is either nothing on the other 183 * end or we have not detected the phy type as yet. 184 */ 185 SCIC_SDS_PHY_PROTOCOL_UNKNOWN, 186 187 /** 188 * This is a SAS PHY 189 */ 190 SCIC_SDS_PHY_PROTOCOL_SAS, 191 192 /** 193 * This is a SATA PHY 194 */ 195 SCIC_SDS_PHY_PROTOCOL_SATA, 196 197 SCIC_SDS_MAX_PHY_PROTOCOLS 198}; 199 200/** 201 * @struct SCIC_SDS_PHY 202 * 203 * @brief This structure contains or references all of the data necessary to 204 * represent the core phy object and SCU harware protocol engine. 205 */ 206typedef struct SCIC_SDS_PHY 207{ 208 SCI_BASE_PHY_T parent; 209 210 /** 211 * This field specifies the port object that owns/contains this phy. 212 */ 213 struct SCIC_SDS_PORT * owning_port; 214 215 /** 216 * This field indicates whether the phy supports 1.5 Gb/s, 3.0 Gb/s, 217 * or 6.0 Gb/s operation. 218 */ 219 SCI_SAS_LINK_RATE max_negotiated_speed; 220 221 /** 222 * This member specifies the protocol being utilized on this phy. This 223 * field contains a legitamite value once the PHY has link trained with 224 * a remote phy. 225 */ 226 enum SCIC_SDS_PHY_PROTOCOL protocol; 227 228 /** 229 * This field specifies the index with which this phy is associated (0-3). 230 */ 231 U8 phy_index; 232 233 /** 234 * This member indicates if this particular PHY has received a BCN while 235 * it had no port assignement. This BCN will be reported once the phy is 236 * assigned to a port. 237 */ 238 BOOL bcn_received_while_port_unassigned; 239 240 /** 241 * This field indicates if this PHY is currently in the process of 242 * link training (i.e. it has started OOB, but has yet to perform 243 * IAF exchange/Signature FIS reception). 244 */ 245 BOOL is_in_link_training; 246 247 union 248 { 249 struct 250 { 251 SCI_SAS_IDENTIFY_ADDRESS_FRAME_T identify_address_frame_buffer; 252 253 } sas; 254 255 struct 256 { 257 SATA_FIS_REG_D2H_T signature_fis_buffer; 258 259 } sata; 260 261 } phy_type; 262 263 /** 264 * This field contains a reference to the timer utilized in detecting 265 * when a signature FIS timeout has occurred. The signature FIS is the 266 * first FIS sent by an attached SATA device after OOB/SN. 267 */ 268 void * sata_timeout_timer; 269 270 struct SCIC_SDS_PHY_STATE_HANDLER *state_handlers; 271 272 SCI_BASE_STATE_MACHINE_T starting_substate_machine; 273 274 #ifdef SCI_LOGGING 275 SCI_BASE_STATE_MACHINE_LOGGER_T starting_substate_machine_logger; 276 #endif 277 278 #ifdef SCIC_DEBUG_ENABLED 279 SCIC_SDS_PHY_STATE_RECORD_T state_record; 280 #endif // SCIC_DEBUG_ENABLED 281 282 /** 283 * This field tracks how many errors of each type have been detected since 284 * the last controller reset or counter clear. Note that these are only 285 * for the error types that our driver needs to count manually. See 286 * SCU_ERR_CNT_* values defined in scu_event_codes.h. 287 */ 288 U32 error_counter[SCU_ERR_CNT_MAX_INDEX]; 289 290 /** 291 * This field is the pointer to the transport layer register for the SCU 292 * hardware. 293 */ 294 SCU_TRANSPORT_LAYER_REGISTERS_T *transport_layer_registers; 295 296 /** 297 * This field points to the link layer register set within the SCU. 298 */ 299 SCU_LINK_LAYER_REGISTERS_T *link_layer_registers; 300 301} SCIC_SDS_PHY_T; 302 303 304typedef SCI_STATUS (*SCIC_SDS_PHY_EVENT_HANDLER_T)(SCIC_SDS_PHY_T *, U32); 305typedef SCI_STATUS (*SCIC_SDS_PHY_FRAME_HANDLER_T)(SCIC_SDS_PHY_T *, U32); 306typedef SCI_STATUS (*SCIC_SDS_PHY_POWER_HANDLER_T)(SCIC_SDS_PHY_T *); 307 308/** 309 * @struct SCIC_SDS_PHY_STATE_HANDLER 310 */ 311typedef struct SCIC_SDS_PHY_STATE_HANDLER 312{ 313 /** 314 * This is the SCI_BASE_PHY object state handlers. 315 */ 316 SCI_BASE_PHY_STATE_HANDLER_T parent; 317 318 /** 319 * The state handler for unsolicited frames received from the SCU hardware. 320 */ 321 SCIC_SDS_PHY_FRAME_HANDLER_T frame_handler; 322 323 /** 324 * The state handler for events received from the SCU hardware. 325 */ 326 SCIC_SDS_PHY_EVENT_HANDLER_T event_handler; 327 328 /** 329 * The state handler for staggered spinup. 330 */ 331 SCIC_SDS_PHY_POWER_HANDLER_T consume_power_handler; 332 333} SCIC_SDS_PHY_STATE_HANDLER_T; 334 335extern SCIC_SDS_PHY_STATE_HANDLER_T scic_sds_phy_state_handler_table[]; 336extern SCI_BASE_STATE_T scic_sds_phy_state_table[]; 337extern SCI_BASE_STATE_T scic_sds_phy_starting_substates[]; 338extern SCIC_SDS_PHY_STATE_HANDLER_T 339 scic_sds_phy_starting_substate_handler_table[]; 340 341 342/** 343 * This macro returns the phy index for the specified phy 344 */ 345#define scic_sds_phy_get_index(phy) \ 346 ((phy)->phy_index) 347 348/** 349 * @brief This macro returns the controller for this phy 350 */ 351#define scic_sds_phy_get_controller(phy) \ 352 (scic_sds_port_get_controller((phy)->owning_port)) 353 354/** 355 * @brief This macro returns the state machine for the base phy 356 */ 357#define scic_sds_phy_get_base_state_machine(phy) \ 358 (&(phy)->parent.state_machine) 359 360/** 361 * @brief This macro returns the starting substate machine for 362 * this phy 363 */ 364#define scic_sds_phy_get_starting_substate_machine(phy) \ 365 (&(phy)->starting_substate_machine) 366 367/** 368 * @brief This macro sets the state handlers for this phy object 369 */ 370#define scic_sds_phy_set_state_handlers(phy, handlers) \ 371 ((phy)->state_handlers = (handlers)) 372 373/** 374 * This macro set the base state handlers for the phy object. 375 */ 376#define scic_sds_phy_set_base_state_handlers(phy, state_id) \ 377 scic_sds_phy_set_state_handlers( \ 378 (phy), \ 379 &scic_sds_phy_state_handler_table[(state_id)] \ 380 ) 381 382/** 383 * This macro returns TRUE if the current base state for this phy is 384 * SCI_BASE_PHY_STATE_READY 385 */ 386#define scic_sds_phy_is_ready(phy) \ 387 ( \ 388 SCI_BASE_PHY_STATE_READY \ 389 == sci_base_state_machine_get_state( \ 390 scic_sds_phy_get_base_state_machine(phy) \ 391 ) \ 392 ) 393 394// --------------------------------------------------------------------------- 395 396U32 scic_sds_phy_get_object_size(void); 397 398U32 scic_sds_phy_get_min_timer_count(void); 399 400U32 scic_sds_phy_get_max_timer_count(void); 401 402// --------------------------------------------------------------------------- 403 404void scic_sds_phy_construct( 405 struct SCIC_SDS_PHY *this_phy, 406 struct SCIC_SDS_PORT *owning_port, 407 U8 phy_index 408); 409 410SCI_PORT_HANDLE_T scic_sds_phy_get_port( 411 SCIC_SDS_PHY_T *this_phy 412); 413 414void scic_sds_phy_set_port( 415 struct SCIC_SDS_PHY *this_phy, 416 struct SCIC_SDS_PORT *owning_port 417); 418 419SCI_STATUS scic_sds_phy_initialize( 420 SCIC_SDS_PHY_T *this_phy, 421 void *transport_layer_registers, 422 SCU_LINK_LAYER_REGISTERS_T *link_layer_registers 423); 424 425SCI_STATUS scic_sds_phy_reset( 426 SCIC_SDS_PHY_T * this_phy 427); 428 429void scic_sds_phy_sata_timeout( 430 SCI_OBJECT_HANDLE_T cookie 431); 432 433// --------------------------------------------------------------------------- 434 435void scic_sds_phy_suspend( 436 struct SCIC_SDS_PHY *this_phy 437); 438 439void scic_sds_phy_resume( 440 struct SCIC_SDS_PHY *this_phy 441); 442 443void scic_sds_phy_setup_transport( 444 struct SCIC_SDS_PHY * this_phy, 445 U32 device_id 446); 447 448// --------------------------------------------------------------------------- 449 450SCI_STATUS scic_sds_phy_event_handler( 451 SCIC_SDS_PHY_T *this_phy, 452 U32 event_code 453); 454 455SCI_STATUS scic_sds_phy_frame_handler( 456 SCIC_SDS_PHY_T *this_phy, 457 U32 frame_index 458); 459 460SCI_STATUS scic_sds_phy_consume_power_handler( 461 SCIC_SDS_PHY_T *this_phy 462); 463 464void scic_sds_phy_get_sas_address( 465 SCIC_SDS_PHY_T *this_phy, 466 SCI_SAS_ADDRESS_T *sas_address 467); 468 469void scic_sds_phy_get_attached_sas_address( 470 SCIC_SDS_PHY_T *this_phy, 471 SCI_SAS_ADDRESS_T *sas_address 472); 473 474void scic_sds_phy_get_protocols( 475 SCIC_SDS_PHY_T *this_phy, 476 SCI_SAS_IDENTIFY_ADDRESS_FRAME_PROTOCOLS_T * protocols 477); 478 479void scic_sds_phy_get_attached_phy_protocols( 480 SCIC_SDS_PHY_T *this_phy, 481 SCI_SAS_IDENTIFY_ADDRESS_FRAME_PROTOCOLS_T * protocols 482); 483 484//****************************************************************************- 485//* SCIC SDS PHY Handler Methods 486//****************************************************************************- 487 488SCI_STATUS scic_sds_phy_default_start_handler( 489 SCI_BASE_PHY_T *phy 490); 491 492SCI_STATUS scic_sds_phy_default_stop_handler( 493 SCI_BASE_PHY_T *phy 494); 495 496SCI_STATUS scic_sds_phy_default_reset_handler( 497 SCI_BASE_PHY_T * phy 498); 499 500SCI_STATUS scic_sds_phy_default_destroy_handler( 501 SCI_BASE_PHY_T *phy 502); 503 504SCI_STATUS scic_sds_phy_default_frame_handler( 505 SCIC_SDS_PHY_T *phy, 506 U32 frame_index 507); 508 509SCI_STATUS scic_sds_phy_default_event_handler( 510 SCIC_SDS_PHY_T *phy, 511 U32 evnet_code 512); 513 514SCI_STATUS scic_sds_phy_default_consume_power_handler( 515 SCIC_SDS_PHY_T *phy 516); 517 518void scic_sds_phy_release_resource( 519 struct SCIC_SDS_CONTROLLER * controller, 520 struct SCIC_SDS_PHY * phy 521); 522 523void scic_sds_phy_restart_starting_state( 524 struct SCIC_SDS_PHY * this_phy 525); 526 527#ifdef __cplusplus 528} 529#endif // __cplusplus 530 531#endif // _SCIC_SDS_PHY_H_ 532