1226381Smarius/* $NetBSD: ncr53c9xvar.h,v 1.55 2011/07/31 18:39:00 jakllsch Exp $ */ 2130293Sscottl 3130293Sscottl/*- 4130293Sscottl * Copyright (c) 1997 The NetBSD Foundation, Inc. 5130293Sscottl * All rights reserved. 6130293Sscottl * 7130293Sscottl * This code is derived from software contributed to The NetBSD Foundation 8130293Sscottl * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9130293Sscottl * NASA Ames Research Center. 10130293Sscottl * 11130293Sscottl * Redistribution and use in source and binary forms, with or without 12130293Sscottl * modification, are permitted provided that the following conditions 13130293Sscottl * are met: 14130293Sscottl * 1. Redistributions of source code must retain the above copyright 15130293Sscottl * notice, this list of conditions and the following disclaimer. 16130293Sscottl * 2. Redistributions in binary form must reproduce the above copyright 17130293Sscottl * notice, this list of conditions and the following disclaimer in the 18130293Sscottl * documentation and/or other materials provided with the distribution. 19130293Sscottl * 3. All advertising materials mentioning features or use of this software 20130293Sscottl * must display the following acknowledgement: 21130293Sscottl * This product includes software developed by the NetBSD 22130293Sscottl * Foundation, Inc. and its contributors. 23130293Sscottl * 4. Neither the name of The NetBSD Foundation nor the names of its 24130293Sscottl * contributors may be used to endorse or promote products derived 25130293Sscottl * from this software without specific prior written permission. 26130293Sscottl * 27130293Sscottl * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28130293Sscottl * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29130293Sscottl * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30130293Sscottl * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31130293Sscottl * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32130293Sscottl * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33130293Sscottl * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34130293Sscottl * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35130293Sscottl * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36130293Sscottl * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37130293Sscottl * POSSIBILITY OF SUCH DAMAGE. 38130293Sscottl */ 39130293Sscottl 40139749Simp/*- 41130293Sscottl * Copyright (c) 1994 Peter Galbavy. All rights reserved. 42130293Sscottl * 43130293Sscottl * Redistribution and use in source and binary forms, with or without 44130293Sscottl * modification, are permitted provided that the following conditions 45130293Sscottl * are met: 46130293Sscottl * 1. Redistributions of source code must retain the above copyright 47130293Sscottl * notice, this list of conditions and the following disclaimer. 48130293Sscottl * 2. Redistributions in binary form must reproduce the above copyright 49130293Sscottl * notice, this list of conditions and the following disclaimer in the 50130293Sscottl * documentation and/or other materials provided with the distribution. 51130293Sscottl * 3. All advertising materials mentioning features or use of this software 52130293Sscottl * must display the following acknowledgement: 53130293Sscottl * This product includes software developed by Peter Galbavy. 54130293Sscottl * 4. The name of the author may not be used to endorse or promote products 55130293Sscottl * derived from this software without specific prior written permission. 56130293Sscottl * 57130293Sscottl * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 58130293Sscottl * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 59130293Sscottl * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 60130293Sscottl * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 61130293Sscottl * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 62130293Sscottl * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 63130293Sscottl * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 64130293Sscottl * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 65130293Sscottl * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 66130293Sscottl * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 67130293Sscottl */ 68130293Sscottl 69130293Sscottl/* $FreeBSD$ */ 70130293Sscottl 71226947Smarius#ifndef _NCR53C9XVAR_H_ 72226947Smarius#define _NCR53C9XVAR_H_ 73130293Sscottl 74130293Sscottl#include <sys/lock.h> 75130293Sscottl 76130293Sscottl/* Set this to 1 for normal debug, or 2 for per-target tracing. */ 77180692Smarius/* #define NCR53C9X_DEBUG 2 */ 78130293Sscottl 79130293Sscottl/* Wide or differential can have 16 targets */ 80180692Smarius#define NCR_NLUN 8 81130293Sscottl 82130293Sscottl#define NCR_ABORT_TIMEOUT 2000 /* time to wait for abort */ 83130293Sscottl#define NCR_SENSE_TIMEOUT 1000 /* time to wait for sense */ 84130293Sscottl 85180692Smarius#define FREQTOCCF(freq) (((freq + 4) / 5)) 86130293Sscottl 87130293Sscottl/* 88133039Strhodes * NCR 53c9x variants. Note these values are used as indexes into 89133039Strhodes * a table; do not modify them unless you know what you are doing. 90130293Sscottl */ 91130293Sscottl#define NCR_VARIANT_ESP100 0 92130293Sscottl#define NCR_VARIANT_ESP100A 1 93130293Sscottl#define NCR_VARIANT_ESP200 2 94130293Sscottl#define NCR_VARIANT_NCR53C94 3 95130293Sscottl#define NCR_VARIANT_NCR53C96 4 96130293Sscottl#define NCR_VARIANT_ESP406 5 97130293Sscottl#define NCR_VARIANT_FAS408 6 98130293Sscottl#define NCR_VARIANT_FAS216 7 99130293Sscottl#define NCR_VARIANT_AM53C974 8 100130293Sscottl#define NCR_VARIANT_FAS366 9 101130293Sscottl#define NCR_VARIANT_NCR53C90_86C01 10 102146392Smarius#define NCR_VARIANT_FAS100A 11 103146392Smarius#define NCR_VARIANT_FAS236 12 104146392Smarius#define NCR_VARIANT_MAX 13 105130293Sscottl 106130406Sscottl/* XXX Max tag depth. Should this be defined in the register header? */ 107180692Smarius#define NCR_TAG_DEPTH 256 108130406Sscottl 109130293Sscottl/* 110130293Sscottl * ECB. Holds additional information for each SCSI command Comments: We 111130293Sscottl * need a separate scsi command block because we may need to overwrite it 112130293Sscottl * with a request sense command. Basicly, we refrain from fiddling with 113182876Smarius * the ccb union (except do the expected updating of return values). 114182876Smarius * We'll generally update: ccb->ccb_h.status and ccb->csio.{resid, 115182876Smarius * scsi_status,sense_data}. 116130293Sscottl */ 117130293Sscottlstruct ncr53c9x_ecb { 118226947Smarius /* These fields are preserved between alloc and free. */ 119226947Smarius struct callout ch; 120130293Sscottl struct ncr53c9x_softc *sc; 121130406Sscottl int tag_id; 122130293Sscottl int flags; 123130406Sscottl 124130406Sscottl union ccb *ccb; /* SCSI xfer ctrl block from above */ 125130406Sscottl TAILQ_ENTRY(ncr53c9x_ecb) free_links; 126130406Sscottl TAILQ_ENTRY(ncr53c9x_ecb) chain; 127130293Sscottl#define ECB_ALLOC 0x01 128130293Sscottl#define ECB_READY 0x02 129130293Sscottl#define ECB_SENSE 0x04 130130293Sscottl#define ECB_ABORT 0x40 131130293Sscottl#define ECB_RESET 0x80 132130293Sscottl#define ECB_TENTATIVE_DONE 0x100 133130293Sscottl int timeout; 134130293Sscottl 135130293Sscottl struct { 136226381Smarius uint8_t msg[3]; /* Selection Id msg and tags */ 137130293Sscottl struct scsi_generic cmd; /* SCSI command block */ 138130293Sscottl } cmd; 139226381Smarius uint8_t *daddr; /* Saved data pointer */ 140130293Sscottl int clen; /* Size of command in cmd.cmd */ 141130293Sscottl int dleft; /* Residue */ 142226381Smarius uint8_t stat; /* SCSI status byte */ 143226381Smarius uint8_t tag[2]; /* TAG bytes */ 144226381Smarius uint8_t pad[1]; 145130293Sscottl 146153084Sru#if defined(NCR53C9X_DEBUG) && NCR53C9X_DEBUG > 1 147130293Sscottl char trace[1000]; 148130293Sscottl#endif 149130293Sscottl}; 150153084Sru#if defined(NCR53C9X_DEBUG) && NCR53C9X_DEBUG > 1 151226381Smarius#define ECB_TRACE(ecb, msg, a, b) do { \ 152226381Smarius const char *f = "[" msg "]"; \ 153226381Smarius int n = strlen((ecb)->trace); \ 154226381Smarius if (n < (sizeof((ecb)->trace)-100)) \ 155226381Smarius sprintf((ecb)->trace + n, f, a, b); \ 156226381Smarius} while (/* CONSTCOND */0) 157130293Sscottl#else 158180692Smarius#define ECB_TRACE(ecb, msg, a, b) 159130293Sscottl#endif 160130293Sscottl 161130293Sscottl/* 162130293Sscottl * Some info about each (possible) target and LUN on the SCSI bus. 163130293Sscottl * 164130293Sscottl * SCSI I and II devices can have up to 8 LUNs, each with up to 256 165130293Sscottl * outstanding tags. SCSI III devices have 64-bit LUN identifiers 166130293Sscottl * that can be sparsely allocated. 167130293Sscottl * 168130293Sscottl * Since SCSI II devices can have up to 8 LUNs, we use an array 169130293Sscottl * of 8 pointers to ncr53c9x_linfo structures for fast lookup. 170130293Sscottl * Longer LUNs need to traverse the linked list. 171130293Sscottl */ 172130293Sscottl 173130293Sscottlstruct ncr53c9x_linfo { 174130293Sscottl int64_t lun; 175130293Sscottl LIST_ENTRY(ncr53c9x_linfo) link; 176130293Sscottl time_t last_used; 177226381Smarius uint8_t used; /* # slots in use */ 178226381Smarius uint8_t avail; /* where to start scanning */ 179226381Smarius uint8_t busy; 180130293Sscottl struct ncr53c9x_ecb *untagged; 181130406Sscottl struct ncr53c9x_ecb *queued[NCR_TAG_DEPTH]; 182130293Sscottl}; 183130293Sscottl 184182876Smariusstruct ncr53c9x_xinfo { 185226381Smarius uint8_t period; 186226381Smarius uint8_t offset; 187226381Smarius uint8_t width; 188182876Smarius}; 189182876Smarius 190130293Sscottlstruct ncr53c9x_tinfo { 191130293Sscottl int cmds; /* # of commands processed */ 192130293Sscottl int dconns; /* # of disconnects */ 193130293Sscottl int touts; /* # of timeouts */ 194130293Sscottl int perrs; /* # of parity errors */ 195130293Sscottl int senses; /* # of request sense commands sent */ 196226381Smarius uint8_t flags; 197182876Smarius#define T_SYNCHOFF 0x01 /* SYNC mode is permanently off */ 198182876Smarius#define T_RSELECTOFF 0x02 /* RE-SELECT mode is off */ 199182876Smarius#define T_TAG 0x04 /* Turn on TAG QUEUEs */ 200182876Smarius#define T_SDTRSENT 0x08 /* SDTR message has been sent to */ 201182876Smarius#define T_WDTRSENT 0x10 /* WDTR message has been sent to */ 202182876Smarius struct ncr53c9x_xinfo curr; 203182876Smarius struct ncr53c9x_xinfo goal; 204130293Sscottl LIST_HEAD(lun_list, ncr53c9x_linfo) luns; 205130293Sscottl struct ncr53c9x_linfo *lun[NCR_NLUN]; /* For speedy lookups */ 206130293Sscottl}; 207130293Sscottl 208130293Sscottl/* Look up a lun in a tinfo */ 209226381Smarius#define TINFO_LUN(t, l) ( \ 210226381Smarius (((l) < NCR_NLUN) && (((t)->lun[(l)]) != NULL)) \ 211226381Smarius ? ((t)->lun[(l)]) \ 212226381Smarius : ncr53c9x_lunsearch((t), (int64_t)(l)) \ 213130293Sscottl) 214130293Sscottl 215226381Smarius/* Register a linenumber (for debugging). */ 216180692Smarius#define LOGLINE(p) 217130293Sscottl 218180692Smarius#define NCR_SHOWECBS 0x01 219180692Smarius#define NCR_SHOWINTS 0x02 220180692Smarius#define NCR_SHOWCMDS 0x04 221180692Smarius#define NCR_SHOWMISC 0x08 222180692Smarius#define NCR_SHOWTRAC 0x10 223180692Smarius#define NCR_SHOWSTART 0x20 224180692Smarius#define NCR_SHOWPHASE 0x40 225180692Smarius#define NCR_SHOWDMA 0x80 226180692Smarius#define NCR_SHOWCCMDS 0x100 227180692Smarius#define NCR_SHOWMSGS 0x200 228130293Sscottl 229130293Sscottl#ifdef NCR53C9X_DEBUG 230130293Sscottlextern int ncr53c9x_debug; 231226381Smarius#define NCR_ECBS(str) \ 232226381Smarius do { \ 233226381Smarius if ((ncr53c9x_debug & NCR_SHOWECBS) != 0) \ 234226381Smarius printf str; \ 235226381Smarius } while (/* CONSTCOND */0) 236226381Smarius#define NCR_MISC(str) \ 237226381Smarius do { \ 238226381Smarius if ((ncr53c9x_debug & NCR_SHOWMISC) != 0) \ 239226381Smarius printf str; \ 240226381Smarius } while (/* CONSTCOND */0) 241226381Smarius#define NCR_INTS(str) \ 242226381Smarius do { \ 243226381Smarius if ((ncr53c9x_debug & NCR_SHOWINTS) != 0) \ 244226381Smarius printf str; \ 245226381Smarius } while (/* CONSTCOND */0) 246226381Smarius#define NCR_TRACE(str) \ 247226381Smarius do { \ 248226381Smarius if ((ncr53c9x_debug & NCR_SHOWTRAC) != 0) \ 249226381Smarius printf str; \ 250226381Smarius } while (/* CONSTCOND */0) 251226381Smarius#define NCR_CMDS(str) \ 252226381Smarius do { \ 253226381Smarius if ((ncr53c9x_debug & NCR_SHOWCMDS) != 0) \ 254226381Smarius printf str; \ 255226381Smarius } while (/* CONSTCOND */0) 256226381Smarius#define NCR_START(str) \ 257226381Smarius do { \ 258226381Smarius if ((ncr53c9x_debug & NCR_SHOWSTART) != 0) \ 259226381Smarius printf str; \ 260226381Smarius } while (/* CONSTCOND */0) 261226381Smarius#define NCR_PHASE(str) \ 262226381Smarius do { \ 263226381Smarius if ((ncr53c9x_debug & NCR_SHOWPHASE) != 0) \ 264226381Smarius printf str; \ 265226381Smarius } while (/* CONSTCOND */0) 266226381Smarius#define NCR_DMA(str) \ 267226381Smarius do { \ 268226381Smarius if ((ncr53c9x_debug & NCR_SHOWDMA) != 0) \ 269226381Smarius printf str; \ 270226381Smarius } while (/* CONSTCOND */0) 271226381Smarius#define NCR_MSGS(str) \ 272226381Smarius do { \ 273226381Smarius if ((ncr53c9x_debug & NCR_SHOWMSGS) != 0) \ 274226381Smarius printf str; \ 275226381Smarius } while (/* CONSTCOND */0) 276130293Sscottl#else 277180692Smarius#define NCR_ECBS(str) 278180692Smarius#define NCR_MISC(str) 279180692Smarius#define NCR_INTS(str) 280180692Smarius#define NCR_TRACE(str) 281180692Smarius#define NCR_CMDS(str) 282180692Smarius#define NCR_START(str) 283180692Smarius#define NCR_PHASE(str) 284180692Smarius#define NCR_DMA(str) 285180692Smarius#define NCR_MSGS(str) 286130293Sscottl#endif 287130293Sscottl 288180692Smarius#define NCR_MAX_MSG_LEN 8 289130293Sscottl 290130293Sscottlstruct ncr53c9x_softc; 291130293Sscottl 292130293Sscottl/* 293226947Smarius * Function switch used as glue to MD code 294130293Sscottl */ 295130293Sscottlstruct ncr53c9x_glue { 296130293Sscottl /* Mandatory entry points. */ 297226381Smarius uint8_t (*gl_read_reg)(struct ncr53c9x_softc *, int); 298226381Smarius void (*gl_write_reg)(struct ncr53c9x_softc *, int, uint8_t); 299130293Sscottl int (*gl_dma_isintr)(struct ncr53c9x_softc *); 300130293Sscottl void (*gl_dma_reset)(struct ncr53c9x_softc *); 301130293Sscottl int (*gl_dma_intr)(struct ncr53c9x_softc *); 302226381Smarius int (*gl_dma_setup)(struct ncr53c9x_softc *, void **, size_t *, 303226381Smarius int, size_t *); 304130293Sscottl void (*gl_dma_go)(struct ncr53c9x_softc *); 305130293Sscottl void (*gl_dma_stop)(struct ncr53c9x_softc *); 306130293Sscottl int (*gl_dma_isactive)(struct ncr53c9x_softc *); 307130293Sscottl}; 308130293Sscottl 309130293Sscottlstruct ncr53c9x_softc { 310130293Sscottl device_t sc_dev; /* us as a device */ 311130293Sscottl 312130293Sscottl struct cam_sim *sc_sim; /* our scsi adapter */ 313130293Sscottl struct cam_path *sc_path; /* our scsi channel */ 314130293Sscottl struct callout sc_watchdog; /* periodic timer */ 315130293Sscottl 316145202Smarius const struct ncr53c9x_glue *sc_glue; /* glue to MD code */ 317130293Sscottl 318130293Sscottl int sc_cfflags; /* Copy of config flags */ 319130293Sscottl 320130293Sscottl /* register defaults */ 321226381Smarius uint8_t sc_cfg1; /* Config 1 */ 322226381Smarius uint8_t sc_cfg2; /* Config 2, not ESP100 */ 323226381Smarius uint8_t sc_cfg3; /* Config 3, ESP200,FAS */ 324226381Smarius uint8_t sc_cfg3_fscsi; /* Chip-specific FSCSI bit */ 325226381Smarius uint8_t sc_cfg4; /* Config 4, only ESP200 */ 326226381Smarius uint8_t sc_cfg5; /* Config 5, only ESP200 */ 327226381Smarius uint8_t sc_ccf; /* Clock Conversion */ 328226381Smarius uint8_t sc_timeout; 329130293Sscottl 330226947Smarius /* register copies, see ncr53c9x_readregs() */ 331226381Smarius uint8_t sc_espintr; 332226381Smarius uint8_t sc_espstat; 333226381Smarius uint8_t sc_espstep; 334226381Smarius uint8_t sc_espstat2; 335226381Smarius uint8_t sc_espfflags; 336130293Sscottl 337130293Sscottl /* Lists of command blocks */ 338180692Smarius TAILQ_HEAD(ecb_list, ncr53c9x_ecb) ready_list; 339130293Sscottl 340130293Sscottl struct ncr53c9x_ecb *sc_nexus; /* Current command */ 341130293Sscottl int sc_ntarg; 342130293Sscottl struct ncr53c9x_tinfo *sc_tinfo; 343130293Sscottl 344130293Sscottl /* Data about the current nexus (updated for every cmd switch) */ 345226381Smarius void *sc_dp; /* Current data pointer */ 346130293Sscottl ssize_t sc_dleft; /* Data left to transfer */ 347130293Sscottl 348130293Sscottl /* Adapter state */ 349130293Sscottl int sc_phase; /* Copy of what bus phase we are in */ 350130293Sscottl int sc_prevphase; /* Copy of what bus phase we were in */ 351226381Smarius uint8_t sc_state; /* State applicable to the adapter */ 352226381Smarius uint8_t sc_flags; /* See below */ 353226381Smarius uint8_t sc_selid; 354226381Smarius uint8_t sc_lastcmd; 355130293Sscottl 356130293Sscottl /* Message stuff */ 357226381Smarius uint16_t sc_msgify; /* IDENTIFY message associated with nexus */ 358226381Smarius uint16_t sc_msgout; /* What message is on its way out? */ 359226381Smarius uint16_t sc_msgpriq; /* One or more messages to send (encoded) */ 360226381Smarius uint16_t sc_msgoutq; /* What messages have been sent so far? */ 361130293Sscottl 362226381Smarius uint8_t *sc_omess; /* MSGOUT buffer */ 363146392Smarius int sc_omess_self; /* MSGOUT buffer is self-allocated */ 364226381Smarius void *sc_omp; /* Message pointer (for multibyte messages) */ 365130293Sscottl size_t sc_omlen; 366226381Smarius uint8_t *sc_imess; /* MSGIN buffer */ 367146392Smarius int sc_imess_self; /* MSGIN buffer is self-allocated */ 368226381Smarius void *sc_imp; /* Message pointer (for multibyte messages) */ 369130293Sscottl size_t sc_imlen; 370130293Sscottl 371226381Smarius void *sc_cmdp; /* Command pointer (for DMAed commands) */ 372130293Sscottl size_t sc_cmdlen; /* Size of command in transit */ 373130293Sscottl 374130293Sscottl /* Hardware attributes */ 375130293Sscottl int sc_freq; /* SCSI bus frequency in MHz */ 376130293Sscottl int sc_id; /* Our SCSI id */ 377130293Sscottl int sc_rev; /* Chip revision */ 378130293Sscottl int sc_features; /* Chip features */ 379130293Sscottl int sc_minsync; /* Minimum sync period / 4 */ 380130293Sscottl int sc_maxxfer; /* Maximum transfer size */ 381130293Sscottl int sc_maxoffset; /* Maximum offset */ 382130293Sscottl int sc_maxwidth; /* Maximum width */ 383130349Sscottl int sc_extended_geom; /* Should we return extended geometry */ 384130293Sscottl 385130293Sscottl struct mtx sc_lock; /* driver mutex */ 386130406Sscottl 387130406Sscottl struct ncr53c9x_ecb *ecb_array; 388130406Sscottl TAILQ_HEAD(,ncr53c9x_ecb) free_list; 389130293Sscottl}; 390130293Sscottl 391130293Sscottl/* values for sc_state */ 392180692Smarius#define NCR_IDLE 1 /* Waiting for something to do */ 393180692Smarius#define NCR_SELECTING 2 /* SCSI command is arbiting */ 394180692Smarius#define NCR_RESELECTED 3 /* Has been reselected */ 395180692Smarius#define NCR_IDENTIFIED 4 /* Has gotten IFY but not TAG */ 396180692Smarius#define NCR_CONNECTED 5 /* Actively using the SCSI bus */ 397130293Sscottl#define NCR_DISCONNECT 6 /* MSG_DISCONNECT received */ 398130293Sscottl#define NCR_CMDCOMPLETE 7 /* MSG_CMDCOMPLETE received */ 399130293Sscottl#define NCR_CLEANING 8 400180692Smarius#define NCR_SBR 9 /* Expect a SCSI RST because we commanded it */ 401130293Sscottl 402130293Sscottl/* values for sc_flags */ 403180692Smarius#define NCR_DROP_MSGI 0x01 /* Discard all msgs (parity err detected) */ 404180692Smarius#define NCR_ABORTING 0x02 /* Bailing out */ 405182876Smarius#define NCR_ICCS 0x04 /* Expect status phase results */ 406182876Smarius#define NCR_WAITI 0x08 /* Waiting for non-DMA data to arrive */ 407182876Smarius#define NCR_ATN 0x10 /* ATN asserted */ 408182876Smarius#define NCR_EXPECT_ILLCMD 0x20 /* Expect Illegal Command Interrupt */ 409130293Sscottl 410130293Sscottl/* values for sc_features */ 411130293Sscottl#define NCR_F_HASCFG3 0x01 /* chip has CFG3 register */ 412130293Sscottl#define NCR_F_FASTSCSI 0x02 /* chip supports Fast mode */ 413180692Smarius#define NCR_F_DMASELECT 0x04 /* can do dmaselect */ 414130293Sscottl#define NCR_F_SELATN3 0x08 /* chip supports SELATN3 command */ 415226947Smarius#define NCR_F_LARGEXFER 0x10 /* chip supports transfers > 64k */ 416130293Sscottl 417130293Sscottl/* values for sc_msgout */ 418180692Smarius#define SEND_DEV_RESET 0x0001 419180692Smarius#define SEND_PARITY_ERROR 0x0002 420180692Smarius#define SEND_INIT_DET_ERR 0x0004 421180692Smarius#define SEND_REJECT 0x0008 422180692Smarius#define SEND_IDENTIFY 0x0010 423180692Smarius#define SEND_ABORT 0x0020 424182876Smarius#define SEND_TAG 0x0040 425182876Smarius#define SEND_WDTR 0x0080 426182876Smarius#define SEND_SDTR 0x0100 427130293Sscottl 428130293Sscottl/* SCSI Status codes */ 429180692Smarius#define ST_MASK 0x3e /* bit 0,6,7 is reserved */ 430130293Sscottl 431130293Sscottl/* phase bits */ 432180692Smarius#define IOI 0x01 433180692Smarius#define CDI 0x02 434180692Smarius#define MSGI 0x04 435130293Sscottl 436130293Sscottl/* Information transfer phases */ 437180692Smarius#define DATA_OUT_PHASE (0) 438180692Smarius#define DATA_IN_PHASE (IOI) 439180692Smarius#define COMMAND_PHASE (CDI) 440180692Smarius#define STATUS_PHASE (CDI | IOI) 441180692Smarius#define MESSAGE_OUT_PHASE (MSGI | CDI) 442180692Smarius#define MESSAGE_IN_PHASE (MSGI | CDI | IOI) 443130293Sscottl 444180692Smarius#define PHASE_MASK (MSGI | CDI | IOI) 445130293Sscottl 446130293Sscottl/* Some pseudo phases for getphase()*/ 447180692Smarius#define BUSFREE_PHASE 0x100 /* Re/Selection no longer valid */ 448180692Smarius#define INVALID_PHASE 0x101 /* Re/Selection valid, but no REQ yet */ 449180692Smarius#define PSEUDO_PHASE 0x100 /* "pseudo" bit */ 450130293Sscottl 451130293Sscottl/* 452130293Sscottl * Macros to read and write the chip's registers. 453130293Sscottl */ 454180692Smarius#define NCR_READ_REG(sc, reg) \ 455130293Sscottl (*(sc)->sc_glue->gl_read_reg)((sc), (reg)) 456180692Smarius#define NCR_WRITE_REG(sc, reg, val) \ 457130293Sscottl (*(sc)->sc_glue->gl_write_reg)((sc), (reg), (val)) 458130293Sscottl 459130293Sscottl#ifdef NCR53C9X_DEBUG 460130293Sscottl#define NCRCMD(sc, cmd) do { \ 461130293Sscottl if ((ncr53c9x_debug & NCR_SHOWCCMDS) != 0) \ 462226381Smarius printf("<CMD:0x%x %d>", (unsigned int)cmd, __LINE__); \ 463130293Sscottl sc->sc_lastcmd = cmd; \ 464130293Sscottl NCR_WRITE_REG(sc, NCR_CMD, cmd); \ 465226381Smarius} while (/* CONSTCOND */ 0) 466130293Sscottl#else 467130293Sscottl#define NCRCMD(sc, cmd) NCR_WRITE_REG(sc, NCR_CMD, cmd) 468130293Sscottl#endif 469130293Sscottl 470130293Sscottl/* 471182876Smarius * Macros for locking 472182876Smarius */ 473182876Smarius#define NCR_LOCK_INIT(_sc) \ 474182876Smarius mtx_init(&(_sc)->sc_lock, "ncr", "ncr53c9x lock", MTX_DEF); 475182876Smarius#define NCR_LOCK_INITIALIZED(_sc) mtx_initialized(&(_sc)->sc_lock) 476182876Smarius#define NCR_LOCK(_sc) mtx_lock(&(_sc)->sc_lock) 477182876Smarius#define NCR_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_lock) 478182876Smarius#define NCR_LOCK_ASSERT(_sc, _what) mtx_assert(&(_sc)->sc_lock, (_what)) 479182876Smarius#define NCR_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_lock) 480182876Smarius 481182876Smarius/* 482130293Sscottl * DMA macros for NCR53c9x 483130293Sscottl */ 484130293Sscottl#define NCRDMA_ISINTR(sc) (*(sc)->sc_glue->gl_dma_isintr)((sc)) 485130293Sscottl#define NCRDMA_RESET(sc) (*(sc)->sc_glue->gl_dma_reset)((sc)) 486130293Sscottl#define NCRDMA_INTR(sc) (*(sc)->sc_glue->gl_dma_intr)((sc)) 487180692Smarius#define NCRDMA_SETUP(sc, addr, len, datain, dmasize) \ 488180692Smarius (*(sc)->sc_glue->gl_dma_setup)((sc), (addr), (len), (datain), (dmasize)) 489130293Sscottl#define NCRDMA_GO(sc) (*(sc)->sc_glue->gl_dma_go)((sc)) 490182876Smarius#define NCRDMA_STOP(sc) (*(sc)->sc_glue->gl_dma_stop)((sc)) 491130293Sscottl#define NCRDMA_ISACTIVE(sc) (*(sc)->sc_glue->gl_dma_isactive)((sc)) 492130293Sscottl 493130293Sscottl/* 494130293Sscottl * Macro to convert the chip register Clock Per Byte value to 495145202Smarius * Synchronous Transfer Period. 496130293Sscottl */ 497180692Smarius#define ncr53c9x_cpb2stp(sc, cpb) \ 498130293Sscottl ((250 * (cpb)) / (sc)->sc_freq) 499130293Sscottl 500226947Smariusextern devclass_t esp_devclass; 501226947Smarius 502180692Smariusint ncr53c9x_attach(struct ncr53c9x_softc *sc); 503180692Smariusint ncr53c9x_detach(struct ncr53c9x_softc *sc); 504180692Smariusvoid ncr53c9x_intr(void *arg); 505130293Sscottl 506226947Smarius#endif /* _NCR53C9XVAR_H_ */ 507