1/* $NetBSD: ncr53c9xvar.h,v 1.55 2011/07/31 18:39:00 jakllsch Exp $ */ 2 3/*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40/*- 41 * Copyright (c) 1994 Peter Galbavy. All rights reserved. 42 * 43 * Redistribution and use in source and binary forms, with or without 44 * modification, are permitted provided that the following conditions 45 * are met: 46 * 1. Redistributions of source code must retain the above copyright 47 * notice, this list of conditions and the following disclaimer. 48 * 2. Redistributions in binary form must reproduce the above copyright 49 * notice, this list of conditions and the following disclaimer in the 50 * documentation and/or other materials provided with the distribution. 51 * 3. All advertising materials mentioning features or use of this software 52 * must display the following acknowledgement: 53 * This product includes software developed by Peter Galbavy. 54 * 4. The name of the author may not be used to endorse or promote products 55 * derived from this software without specific prior written permission. 56 * 57 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 58 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 59 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 60 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 61 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 62 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 63 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 64 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 65 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 66 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69/* $FreeBSD$ */ 70 71#ifndef _NCR53C9XVAR_H_ 72#define _NCR53C9XVAR_H_ 73 74#include <sys/lock.h> 75 76/* Set this to 1 for normal debug, or 2 for per-target tracing. */ 77/* #define NCR53C9X_DEBUG 2 */ 78 79/* Wide or differential can have 16 targets */ 80#define NCR_NLUN 8 81 82#define NCR_ABORT_TIMEOUT 2000 /* time to wait for abort */ 83#define NCR_SENSE_TIMEOUT 1000 /* time to wait for sense */ 84 85#define FREQTOCCF(freq) (((freq + 4) / 5)) 86 87/* 88 * NCR 53c9x variants. Note these values are used as indexes into 89 * a table; do not modify them unless you know what you are doing. 90 */ 91#define NCR_VARIANT_ESP100 0 92#define NCR_VARIANT_ESP100A 1 93#define NCR_VARIANT_ESP200 2 94#define NCR_VARIANT_NCR53C94 3 95#define NCR_VARIANT_NCR53C96 4 96#define NCR_VARIANT_ESP406 5 97#define NCR_VARIANT_FAS408 6 98#define NCR_VARIANT_FAS216 7 99#define NCR_VARIANT_AM53C974 8 100#define NCR_VARIANT_FAS366 9 101#define NCR_VARIANT_NCR53C90_86C01 10 102#define NCR_VARIANT_FAS100A 11 103#define NCR_VARIANT_FAS236 12 104#define NCR_VARIANT_MAX 13 105 106/* XXX Max tag depth. Should this be defined in the register header? */ 107#define NCR_TAG_DEPTH 256 108 109/* 110 * ECB. Holds additional information for each SCSI command Comments: We 111 * need a separate scsi command block because we may need to overwrite it 112 * with a request sense command. Basicly, we refrain from fiddling with 113 * the ccb union (except do the expected updating of return values). 114 * We'll generally update: ccb->ccb_h.status and ccb->csio.{resid, 115 * scsi_status,sense_data}. 116 */ 117struct ncr53c9x_ecb { 118 /* These fields are preserved between alloc and free. */ 119 struct callout ch; 120 struct ncr53c9x_softc *sc; 121 int tag_id; 122 int flags; 123 124 union ccb *ccb; /* SCSI xfer ctrl block from above */ 125 TAILQ_ENTRY(ncr53c9x_ecb) free_links; 126 TAILQ_ENTRY(ncr53c9x_ecb) chain; 127#define ECB_ALLOC 0x01 128#define ECB_READY 0x02 129#define ECB_SENSE 0x04 130#define ECB_ABORT 0x40 131#define ECB_RESET 0x80 132#define ECB_TENTATIVE_DONE 0x100 133 int timeout; 134 135 struct { 136 uint8_t msg[3]; /* Selection Id msg and tags */ 137 struct scsi_generic cmd; /* SCSI command block */ 138 } cmd; 139 uint8_t *daddr; /* Saved data pointer */ 140 int clen; /* Size of command in cmd.cmd */ 141 int dleft; /* Residue */ 142 uint8_t stat; /* SCSI status byte */ 143 uint8_t tag[2]; /* TAG bytes */ 144 uint8_t pad[1]; 145 146#if defined(NCR53C9X_DEBUG) && NCR53C9X_DEBUG > 1 147 char trace[1000]; 148#endif 149}; 150#if defined(NCR53C9X_DEBUG) && NCR53C9X_DEBUG > 1 151#define ECB_TRACE(ecb, msg, a, b) do { \ 152 const char *f = "[" msg "]"; \ 153 int n = strlen((ecb)->trace); \ 154 if (n < (sizeof((ecb)->trace)-100)) \ 155 sprintf((ecb)->trace + n, f, a, b); \ 156} while (/* CONSTCOND */0) 157#else 158#define ECB_TRACE(ecb, msg, a, b) 159#endif 160 161/* 162 * Some info about each (possible) target and LUN on the SCSI bus. 163 * 164 * SCSI I and II devices can have up to 8 LUNs, each with up to 256 165 * outstanding tags. SCSI III devices have 64-bit LUN identifiers 166 * that can be sparsely allocated. 167 * 168 * Since SCSI II devices can have up to 8 LUNs, we use an array 169 * of 8 pointers to ncr53c9x_linfo structures for fast lookup. 170 * Longer LUNs need to traverse the linked list. 171 */ 172 173struct ncr53c9x_linfo { 174 int64_t lun; 175 LIST_ENTRY(ncr53c9x_linfo) link; 176 time_t last_used; 177 uint8_t used; /* # slots in use */ 178 uint8_t avail; /* where to start scanning */ 179 uint8_t busy; 180 struct ncr53c9x_ecb *untagged; 181 struct ncr53c9x_ecb *queued[NCR_TAG_DEPTH]; 182}; 183 184struct ncr53c9x_xinfo { 185 uint8_t period; 186 uint8_t offset; 187 uint8_t width; 188}; 189 190struct ncr53c9x_tinfo { 191 int cmds; /* # of commands processed */ 192 int dconns; /* # of disconnects */ 193 int touts; /* # of timeouts */ 194 int perrs; /* # of parity errors */ 195 int senses; /* # of request sense commands sent */ 196 uint8_t flags; 197#define T_SYNCHOFF 0x01 /* SYNC mode is permanently off */ 198#define T_RSELECTOFF 0x02 /* RE-SELECT mode is off */ 199#define T_TAG 0x04 /* Turn on TAG QUEUEs */ 200#define T_SDTRSENT 0x08 /* SDTR message has been sent to */ 201#define T_WDTRSENT 0x10 /* WDTR message has been sent to */ 202 struct ncr53c9x_xinfo curr; 203 struct ncr53c9x_xinfo goal; 204 LIST_HEAD(lun_list, ncr53c9x_linfo) luns; 205 struct ncr53c9x_linfo *lun[NCR_NLUN]; /* For speedy lookups */ 206}; 207 208/* Look up a lun in a tinfo */ 209#define TINFO_LUN(t, l) ( \ 210 (((l) < NCR_NLUN) && (((t)->lun[(l)]) != NULL)) \ 211 ? ((t)->lun[(l)]) \ 212 : ncr53c9x_lunsearch((t), (int64_t)(l)) \ 213) 214 215/* Register a linenumber (for debugging). */ 216#define LOGLINE(p) 217 218#define NCR_SHOWECBS 0x01 219#define NCR_SHOWINTS 0x02 220#define NCR_SHOWCMDS 0x04 221#define NCR_SHOWMISC 0x08 222#define NCR_SHOWTRAC 0x10 223#define NCR_SHOWSTART 0x20 224#define NCR_SHOWPHASE 0x40 225#define NCR_SHOWDMA 0x80 226#define NCR_SHOWCCMDS 0x100 227#define NCR_SHOWMSGS 0x200 228 229#ifdef NCR53C9X_DEBUG 230extern int ncr53c9x_debug; 231#define NCR_ECBS(str) \ 232 do { \ 233 if ((ncr53c9x_debug & NCR_SHOWECBS) != 0) \ 234 printf str; \ 235 } while (/* CONSTCOND */0) 236#define NCR_MISC(str) \ 237 do { \ 238 if ((ncr53c9x_debug & NCR_SHOWMISC) != 0) \ 239 printf str; \ 240 } while (/* CONSTCOND */0) 241#define NCR_INTS(str) \ 242 do { \ 243 if ((ncr53c9x_debug & NCR_SHOWINTS) != 0) \ 244 printf str; \ 245 } while (/* CONSTCOND */0) 246#define NCR_TRACE(str) \ 247 do { \ 248 if ((ncr53c9x_debug & NCR_SHOWTRAC) != 0) \ 249 printf str; \ 250 } while (/* CONSTCOND */0) 251#define NCR_CMDS(str) \ 252 do { \ 253 if ((ncr53c9x_debug & NCR_SHOWCMDS) != 0) \ 254 printf str; \ 255 } while (/* CONSTCOND */0) 256#define NCR_START(str) \ 257 do { \ 258 if ((ncr53c9x_debug & NCR_SHOWSTART) != 0) \ 259 printf str; \ 260 } while (/* CONSTCOND */0) 261#define NCR_PHASE(str) \ 262 do { \ 263 if ((ncr53c9x_debug & NCR_SHOWPHASE) != 0) \ 264 printf str; \ 265 } while (/* CONSTCOND */0) 266#define NCR_DMA(str) \ 267 do { \ 268 if ((ncr53c9x_debug & NCR_SHOWDMA) != 0) \ 269 printf str; \ 270 } while (/* CONSTCOND */0) 271#define NCR_MSGS(str) \ 272 do { \ 273 if ((ncr53c9x_debug & NCR_SHOWMSGS) != 0) \ 274 printf str; \ 275 } while (/* CONSTCOND */0) 276#else 277#define NCR_ECBS(str) 278#define NCR_MISC(str) 279#define NCR_INTS(str) 280#define NCR_TRACE(str) 281#define NCR_CMDS(str) 282#define NCR_START(str) 283#define NCR_PHASE(str) 284#define NCR_DMA(str) 285#define NCR_MSGS(str) 286#endif 287 288#define NCR_MAX_MSG_LEN 8 289 290struct ncr53c9x_softc; 291 292/* 293 * Function switch used as glue to MD code 294 */ 295struct ncr53c9x_glue { 296 /* Mandatory entry points. */ 297 uint8_t (*gl_read_reg)(struct ncr53c9x_softc *, int); 298 void (*gl_write_reg)(struct ncr53c9x_softc *, int, uint8_t); 299 int (*gl_dma_isintr)(struct ncr53c9x_softc *); 300 void (*gl_dma_reset)(struct ncr53c9x_softc *); 301 int (*gl_dma_intr)(struct ncr53c9x_softc *); 302 int (*gl_dma_setup)(struct ncr53c9x_softc *, void **, size_t *, 303 int, size_t *); 304 void (*gl_dma_go)(struct ncr53c9x_softc *); 305 void (*gl_dma_stop)(struct ncr53c9x_softc *); 306 int (*gl_dma_isactive)(struct ncr53c9x_softc *); 307}; 308 309struct ncr53c9x_softc { 310 device_t sc_dev; /* us as a device */ 311 312 struct cam_sim *sc_sim; /* our scsi adapter */ 313 struct cam_path *sc_path; /* our scsi channel */ 314 struct callout sc_watchdog; /* periodic timer */ 315 316 const struct ncr53c9x_glue *sc_glue; /* glue to MD code */ 317 318 int sc_cfflags; /* Copy of config flags */ 319 320 /* register defaults */ 321 uint8_t sc_cfg1; /* Config 1 */ 322 uint8_t sc_cfg2; /* Config 2, not ESP100 */ 323 uint8_t sc_cfg3; /* Config 3, ESP200,FAS */ 324 uint8_t sc_cfg3_fscsi; /* Chip-specific FSCSI bit */ 325 uint8_t sc_cfg4; /* Config 4, only ESP200 */ 326 uint8_t sc_cfg5; /* Config 5, only ESP200 */ 327 uint8_t sc_ccf; /* Clock Conversion */ 328 uint8_t sc_timeout; 329 330 /* register copies, see ncr53c9x_readregs() */ 331 uint8_t sc_espintr; 332 uint8_t sc_espstat; 333 uint8_t sc_espstep; 334 uint8_t sc_espstat2; 335 uint8_t sc_espfflags; 336 337 /* Lists of command blocks */ 338 TAILQ_HEAD(ecb_list, ncr53c9x_ecb) ready_list; 339 340 struct ncr53c9x_ecb *sc_nexus; /* Current command */ 341 int sc_ntarg; 342 struct ncr53c9x_tinfo *sc_tinfo; 343 344 /* Data about the current nexus (updated for every cmd switch) */ 345 void *sc_dp; /* Current data pointer */ 346 ssize_t sc_dleft; /* Data left to transfer */ 347 348 /* Adapter state */ 349 int sc_phase; /* Copy of what bus phase we are in */ 350 int sc_prevphase; /* Copy of what bus phase we were in */ 351 uint8_t sc_state; /* State applicable to the adapter */ 352 uint8_t sc_flags; /* See below */ 353 uint8_t sc_selid; 354 uint8_t sc_lastcmd; 355 356 /* Message stuff */ 357 uint16_t sc_msgify; /* IDENTIFY message associated with nexus */ 358 uint16_t sc_msgout; /* What message is on its way out? */ 359 uint16_t sc_msgpriq; /* One or more messages to send (encoded) */ 360 uint16_t sc_msgoutq; /* What messages have been sent so far? */ 361 362 uint8_t *sc_omess; /* MSGOUT buffer */ 363 int sc_omess_self; /* MSGOUT buffer is self-allocated */ 364 void *sc_omp; /* Message pointer (for multibyte messages) */ 365 size_t sc_omlen; 366 uint8_t *sc_imess; /* MSGIN buffer */ 367 int sc_imess_self; /* MSGIN buffer is self-allocated */ 368 void *sc_imp; /* Message pointer (for multibyte messages) */ 369 size_t sc_imlen; 370 371 void *sc_cmdp; /* Command pointer (for DMAed commands) */ 372 size_t sc_cmdlen; /* Size of command in transit */ 373 374 /* Hardware attributes */ 375 int sc_freq; /* SCSI bus frequency in MHz */ 376 int sc_id; /* Our SCSI id */ 377 int sc_rev; /* Chip revision */ 378 int sc_features; /* Chip features */ 379 int sc_minsync; /* Minimum sync period / 4 */ 380 int sc_maxxfer; /* Maximum transfer size */ 381 int sc_maxoffset; /* Maximum offset */ 382 int sc_maxwidth; /* Maximum width */ 383 int sc_extended_geom; /* Should we return extended geometry */ 384 385 struct mtx sc_lock; /* driver mutex */ 386 387 struct ncr53c9x_ecb *ecb_array; 388 TAILQ_HEAD(,ncr53c9x_ecb) free_list; 389}; 390 391/* values for sc_state */ 392#define NCR_IDLE 1 /* Waiting for something to do */ 393#define NCR_SELECTING 2 /* SCSI command is arbiting */ 394#define NCR_RESELECTED 3 /* Has been reselected */ 395#define NCR_IDENTIFIED 4 /* Has gotten IFY but not TAG */ 396#define NCR_CONNECTED 5 /* Actively using the SCSI bus */ 397#define NCR_DISCONNECT 6 /* MSG_DISCONNECT received */ 398#define NCR_CMDCOMPLETE 7 /* MSG_CMDCOMPLETE received */ 399#define NCR_CLEANING 8 400#define NCR_SBR 9 /* Expect a SCSI RST because we commanded it */ 401 402/* values for sc_flags */ 403#define NCR_DROP_MSGI 0x01 /* Discard all msgs (parity err detected) */ 404#define NCR_ABORTING 0x02 /* Bailing out */ 405#define NCR_ICCS 0x04 /* Expect status phase results */ 406#define NCR_WAITI 0x08 /* Waiting for non-DMA data to arrive */ 407#define NCR_ATN 0x10 /* ATN asserted */ 408#define NCR_EXPECT_ILLCMD 0x20 /* Expect Illegal Command Interrupt */ 409 410/* values for sc_features */ 411#define NCR_F_HASCFG3 0x01 /* chip has CFG3 register */ 412#define NCR_F_FASTSCSI 0x02 /* chip supports Fast mode */ 413#define NCR_F_DMASELECT 0x04 /* can do dmaselect */ 414#define NCR_F_SELATN3 0x08 /* chip supports SELATN3 command */ 415#define NCR_F_LARGEXFER 0x10 /* chip supports transfers > 64k */ 416 417/* values for sc_msgout */ 418#define SEND_DEV_RESET 0x0001 419#define SEND_PARITY_ERROR 0x0002 420#define SEND_INIT_DET_ERR 0x0004 421#define SEND_REJECT 0x0008 422#define SEND_IDENTIFY 0x0010 423#define SEND_ABORT 0x0020 424#define SEND_TAG 0x0040 425#define SEND_WDTR 0x0080 426#define SEND_SDTR 0x0100 427 428/* SCSI Status codes */ 429#define ST_MASK 0x3e /* bit 0,6,7 is reserved */ 430 431/* phase bits */ 432#define IOI 0x01 433#define CDI 0x02 434#define MSGI 0x04 435 436/* Information transfer phases */ 437#define DATA_OUT_PHASE (0) 438#define DATA_IN_PHASE (IOI) 439#define COMMAND_PHASE (CDI) 440#define STATUS_PHASE (CDI | IOI) 441#define MESSAGE_OUT_PHASE (MSGI | CDI) 442#define MESSAGE_IN_PHASE (MSGI | CDI | IOI) 443 444#define PHASE_MASK (MSGI | CDI | IOI) 445 446/* Some pseudo phases for getphase()*/ 447#define BUSFREE_PHASE 0x100 /* Re/Selection no longer valid */ 448#define INVALID_PHASE 0x101 /* Re/Selection valid, but no REQ yet */ 449#define PSEUDO_PHASE 0x100 /* "pseudo" bit */ 450 451/* 452 * Macros to read and write the chip's registers. 453 */ 454#define NCR_READ_REG(sc, reg) \ 455 (*(sc)->sc_glue->gl_read_reg)((sc), (reg)) 456#define NCR_WRITE_REG(sc, reg, val) \ 457 (*(sc)->sc_glue->gl_write_reg)((sc), (reg), (val)) 458 459#ifdef NCR53C9X_DEBUG 460#define NCRCMD(sc, cmd) do { \ 461 if ((ncr53c9x_debug & NCR_SHOWCCMDS) != 0) \ 462 printf("<CMD:0x%x %d>", (unsigned int)cmd, __LINE__); \ 463 sc->sc_lastcmd = cmd; \ 464 NCR_WRITE_REG(sc, NCR_CMD, cmd); \ 465} while (/* CONSTCOND */ 0) 466#else 467#define NCRCMD(sc, cmd) NCR_WRITE_REG(sc, NCR_CMD, cmd) 468#endif 469 470/* 471 * Macros for locking 472 */ 473#define NCR_LOCK_INIT(_sc) \ 474 mtx_init(&(_sc)->sc_lock, "ncr", "ncr53c9x lock", MTX_DEF); 475#define NCR_LOCK_INITIALIZED(_sc) mtx_initialized(&(_sc)->sc_lock) 476#define NCR_LOCK(_sc) mtx_lock(&(_sc)->sc_lock) 477#define NCR_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_lock) 478#define NCR_LOCK_ASSERT(_sc, _what) mtx_assert(&(_sc)->sc_lock, (_what)) 479#define NCR_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_lock) 480 481/* 482 * DMA macros for NCR53c9x 483 */ 484#define NCRDMA_ISINTR(sc) (*(sc)->sc_glue->gl_dma_isintr)((sc)) 485#define NCRDMA_RESET(sc) (*(sc)->sc_glue->gl_dma_reset)((sc)) 486#define NCRDMA_INTR(sc) (*(sc)->sc_glue->gl_dma_intr)((sc)) 487#define NCRDMA_SETUP(sc, addr, len, datain, dmasize) \ 488 (*(sc)->sc_glue->gl_dma_setup)((sc), (addr), (len), (datain), (dmasize)) 489#define NCRDMA_GO(sc) (*(sc)->sc_glue->gl_dma_go)((sc)) 490#define NCRDMA_STOP(sc) (*(sc)->sc_glue->gl_dma_stop)((sc)) 491#define NCRDMA_ISACTIVE(sc) (*(sc)->sc_glue->gl_dma_isactive)((sc)) 492 493/* 494 * Macro to convert the chip register Clock Per Byte value to 495 * Synchronous Transfer Period. 496 */ 497#define ncr53c9x_cpb2stp(sc, cpb) \ 498 ((250 * (cpb)) / (sc)->sc_freq) 499 500extern devclass_t esp_devclass; 501 502int ncr53c9x_attach(struct ncr53c9x_softc *sc); 503int ncr53c9x_detach(struct ncr53c9x_softc *sc); 504void ncr53c9x_intr(void *arg); 505 506#endif /* _NCR53C9XVAR_H_ */ 507