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32******************************************************************************/
33/*$FreeBSD$*/
34
35#ifndef _E1000_VF_H_
36#define _E1000_VF_H_
37
38#include "e1000_osdep.h"
39#include "e1000_regs.h"
40#include "e1000_defines.h"
41
42struct e1000_hw;
43
44#define E1000_DEV_ID_82576_VF		0x10CA
45#define E1000_DEV_ID_I350_VF		0x1520
46
47#define E1000_VF_INIT_TIMEOUT		200 /* Num of retries to clear RSTI */
48
49/* Additional Descriptor Control definitions */
50#define E1000_TXDCTL_QUEUE_ENABLE	0x02000000 /* Ena specific Tx Queue */
51#define E1000_RXDCTL_QUEUE_ENABLE	0x02000000 /* Ena specific Rx Queue */
52
53/* SRRCTL bit definitions */
54#define E1000_SRRCTL(_n)	((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : \
55				 (0x0C00C + ((_n) * 0x40)))
56#define E1000_SRRCTL_BSIZEPKT_SHIFT		10 /* Shift _right_ */
57#define E1000_SRRCTL_BSIZEHDRSIZE_MASK		0x00000F00
58#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT		2  /* Shift _left_ */
59#define E1000_SRRCTL_DESCTYPE_LEGACY		0x00000000
60#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF	0x02000000
61#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT		0x04000000
62#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS	0x0A000000
63#define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION	0x06000000
64#define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
65#define E1000_SRRCTL_DESCTYPE_MASK		0x0E000000
66#define E1000_SRRCTL_DROP_EN			0x80000000
67
68#define E1000_SRRCTL_BSIZEPKT_MASK	0x0000007F
69#define E1000_SRRCTL_BSIZEHDR_MASK	0x00003F00
70
71/* Interrupt Defines */
72#define E1000_EICR		0x01580 /* Ext. Interrupt Cause Read - R/clr */
73#define E1000_EITR(_n)		(0x01680 + ((_n) << 2))
74#define E1000_EICS		0x01520 /* Ext. Intr Cause Set -W0 */
75#define E1000_EIMS		0x01524 /* Ext. Intr Mask Set/Read -RW */
76#define E1000_EIMC		0x01528 /* Ext. Intr Mask Clear -WO */
77#define E1000_EIAC		0x0152C /* Ext. Intr Auto Clear -RW */
78#define E1000_EIAM		0x01530 /* Ext. Intr Ack Auto Clear Mask -RW */
79#define E1000_IVAR0		0x01700 /* Intr Vector Alloc (array) -RW */
80#define E1000_IVAR_MISC		0x01740 /* IVAR for "other" causes -RW */
81#define E1000_IVAR_VALID	0x80
82
83/* Receive Descriptor - Advanced */
84union e1000_adv_rx_desc {
85	struct {
86		u64 pkt_addr; /* Packet buffer address */
87		u64 hdr_addr; /* Header buffer address */
88	} read;
89	struct {
90		struct {
91			union {
92				u32 data;
93				struct {
94					/* RSS type, Packet type */
95					u16 pkt_info;
96					/* Split Header, header buffer len */
97					u16 hdr_info;
98				} hs_rss;
99			} lo_dword;
100			union {
101				u32 rss; /* RSS Hash */
102				struct {
103					u16 ip_id; /* IP id */
104					u16 csum; /* Packet Checksum */
105				} csum_ip;
106			} hi_dword;
107		} lower;
108		struct {
109			u32 status_error; /* ext status/error */
110			u16 length; /* Packet length */
111			u16 vlan; /* VLAN tag */
112		} upper;
113	} wb;  /* writeback */
114};
115
116#define E1000_RXDADV_HDRBUFLEN_MASK	0x7FE0
117#define E1000_RXDADV_HDRBUFLEN_SHIFT	5
118
119/* Transmit Descriptor - Advanced */
120union e1000_adv_tx_desc {
121	struct {
122		u64 buffer_addr;    /* Address of descriptor's data buf */
123		u32 cmd_type_len;
124		u32 olinfo_status;
125	} read;
126	struct {
127		u64 rsvd;       /* Reserved */
128		u32 nxtseq_seed;
129		u32 status;
130	} wb;
131};
132
133/* Adv Transmit Descriptor Config Masks */
134#define E1000_ADVTXD_DTYP_CTXT	0x00200000 /* Advanced Context Descriptor */
135#define E1000_ADVTXD_DTYP_DATA	0x00300000 /* Advanced Data Descriptor */
136#define E1000_ADVTXD_DCMD_EOP	0x01000000 /* End of Packet */
137#define E1000_ADVTXD_DCMD_IFCS	0x02000000 /* Insert FCS (Ethernet CRC) */
138#define E1000_ADVTXD_DCMD_RS	0x08000000 /* Report Status */
139#define E1000_ADVTXD_DCMD_DEXT	0x20000000 /* Descriptor extension (1=Adv) */
140#define E1000_ADVTXD_DCMD_VLE	0x40000000 /* VLAN pkt enable */
141#define E1000_ADVTXD_DCMD_TSE	0x80000000 /* TCP Seg enable */
142#define E1000_ADVTXD_PAYLEN_SHIFT	14 /* Adv desc PAYLEN shift */
143
144/* Context descriptors */
145struct e1000_adv_tx_context_desc {
146	u32 vlan_macip_lens;
147	u32 seqnum_seed;
148	u32 type_tucmd_mlhl;
149	u32 mss_l4len_idx;
150};
151
152#define E1000_ADVTXD_MACLEN_SHIFT	9  /* Adv ctxt desc mac len shift */
153#define E1000_ADVTXD_TUCMD_IPV4		0x00000400  /* IP Packet Type: 1=IPv4 */
154#define E1000_ADVTXD_TUCMD_L4T_TCP	0x00000800  /* L4 Packet TYPE of TCP */
155#define E1000_ADVTXD_L4LEN_SHIFT	8  /* Adv ctxt L4LEN shift */
156#define E1000_ADVTXD_MSS_SHIFT		16  /* Adv ctxt MSS shift */
157
158enum e1000_mac_type {
159	e1000_undefined = 0,
160	e1000_vfadapt,
161	e1000_vfadapt_i350,
162	e1000_num_macs  /* List is 1-based, so subtract 1 for TRUE count. */
163};
164
165struct e1000_vf_stats {
166	u64 base_gprc;
167	u64 base_gptc;
168	u64 base_gorc;
169	u64 base_gotc;
170	u64 base_mprc;
171	u64 base_gotlbc;
172	u64 base_gptlbc;
173	u64 base_gorlbc;
174	u64 base_gprlbc;
175
176	u32 last_gprc;
177	u32 last_gptc;
178	u32 last_gorc;
179	u32 last_gotc;
180	u32 last_mprc;
181	u32 last_gotlbc;
182	u32 last_gptlbc;
183	u32 last_gorlbc;
184	u32 last_gprlbc;
185
186	u64 gprc;
187	u64 gptc;
188	u64 gorc;
189	u64 gotc;
190	u64 mprc;
191	u64 gotlbc;
192	u64 gptlbc;
193	u64 gorlbc;
194	u64 gprlbc;
195};
196
197#include "e1000_mbx.h"
198
199struct e1000_mac_operations {
200	/* Function pointers for the MAC. */
201	s32  (*init_params)(struct e1000_hw *);
202	s32  (*check_for_link)(struct e1000_hw *);
203	void (*clear_vfta)(struct e1000_hw *);
204	s32  (*get_bus_info)(struct e1000_hw *);
205	s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
206	void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
207	s32  (*reset_hw)(struct e1000_hw *);
208	s32  (*init_hw)(struct e1000_hw *);
209	s32  (*setup_link)(struct e1000_hw *);
210	void (*write_vfta)(struct e1000_hw *, u32, u32);
211	void (*rar_set)(struct e1000_hw *, u8*, u32);
212	s32  (*read_mac_addr)(struct e1000_hw *);
213};
214
215struct e1000_mac_info {
216	struct e1000_mac_operations ops;
217	u8 addr[6];
218	u8 perm_addr[6];
219
220	enum e1000_mac_type type;
221
222	u16 mta_reg_count;
223	u16 rar_entry_count;
224
225	bool get_link_status;
226};
227
228struct e1000_mbx_operations {
229	s32 (*init_params)(struct e1000_hw *hw);
230	s32 (*read)(struct e1000_hw *, u32 *, u16,  u16);
231	s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
232	s32 (*read_posted)(struct e1000_hw *, u32 *, u16,  u16);
233	s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
234	s32 (*check_for_msg)(struct e1000_hw *, u16);
235	s32 (*check_for_ack)(struct e1000_hw *, u16);
236	s32 (*check_for_rst)(struct e1000_hw *, u16);
237};
238
239struct e1000_mbx_stats {
240	u32 msgs_tx;
241	u32 msgs_rx;
242
243	u32 acks;
244	u32 reqs;
245	u32 rsts;
246};
247
248struct e1000_mbx_info {
249	struct e1000_mbx_operations ops;
250	struct e1000_mbx_stats stats;
251	u32 timeout;
252	u32 usec_delay;
253	u16 size;
254};
255
256struct e1000_dev_spec_vf {
257	u32 vf_number;
258	u32 v2p_mailbox;
259};
260
261struct e1000_hw {
262	void *back;
263
264	u8 *hw_addr;
265	u8 *flash_address;
266	unsigned long io_base;
267
268	struct e1000_mac_info  mac;
269	struct e1000_mbx_info mbx;
270
271	union {
272		struct e1000_dev_spec_vf vf;
273	} dev_spec;
274
275	u16 device_id;
276	u16 subsystem_vendor_id;
277	u16 subsystem_device_id;
278	u16 vendor_id;
279
280	u8  revision_id;
281};
282
283enum e1000_promisc_type {
284	e1000_promisc_disabled = 0,   /* all promisc modes disabled */
285	e1000_promisc_unicast = 1,    /* unicast promiscuous enabled */
286	e1000_promisc_multicast = 2,  /* multicast promiscuous enabled */
287	e1000_promisc_enabled = 3,    /* both uni and multicast promisc */
288	e1000_num_promisc_types
289};
290
291/* These functions must be implemented by drivers */
292s32  e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
293void e1000_vfta_set_vf(struct e1000_hw *, u16, bool);
294void e1000_rlpml_set_vf(struct e1000_hw *, u16);
295s32 e1000_promisc_set_vf(struct e1000_hw *, enum e1000_promisc_type);
296#endif /* _E1000_VF_H_ */
297