1/****************************************************************************** 2 3 Copyright (c) 2001-2013, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD$*/ 34 35#include "e1000_api.h" 36 37static s32 e1000_wait_autoneg(struct e1000_hw *hw); 38static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, 39 u16 *data, bool read, bool page_set); 40static u32 e1000_get_phy_addr_for_hv_page(u32 page); 41static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, 42 u16 *data, bool read); 43 44/* Cable length tables */ 45static const u16 e1000_m88_cable_length_table[] = { 46 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED }; 47#define M88E1000_CABLE_LENGTH_TABLE_SIZE \ 48 (sizeof(e1000_m88_cable_length_table) / \ 49 sizeof(e1000_m88_cable_length_table[0])) 50 51static const u16 e1000_igp_2_cable_length_table[] = { 52 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3, 53 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22, 54 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40, 55 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61, 56 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82, 57 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95, 58 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121, 59 124}; 60#define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \ 61 (sizeof(e1000_igp_2_cable_length_table) / \ 62 sizeof(e1000_igp_2_cable_length_table[0])) 63 64/** 65 * e1000_init_phy_ops_generic - Initialize PHY function pointers 66 * @hw: pointer to the HW structure 67 * 68 * Setups up the function pointers to no-op functions 69 **/ 70void e1000_init_phy_ops_generic(struct e1000_hw *hw) 71{ 72 struct e1000_phy_info *phy = &hw->phy; 73 DEBUGFUNC("e1000_init_phy_ops_generic"); 74 75 /* Initialize function pointers */ 76 phy->ops.init_params = e1000_null_ops_generic; 77 phy->ops.acquire = e1000_null_ops_generic; 78 phy->ops.check_polarity = e1000_null_ops_generic; 79 phy->ops.check_reset_block = e1000_null_ops_generic; 80 phy->ops.commit = e1000_null_ops_generic; 81 phy->ops.force_speed_duplex = e1000_null_ops_generic; 82 phy->ops.get_cfg_done = e1000_null_ops_generic; 83 phy->ops.get_cable_length = e1000_null_ops_generic; 84 phy->ops.get_info = e1000_null_ops_generic; 85 phy->ops.set_page = e1000_null_set_page; 86 phy->ops.read_reg = e1000_null_read_reg; 87 phy->ops.read_reg_locked = e1000_null_read_reg; 88 phy->ops.read_reg_page = e1000_null_read_reg; 89 phy->ops.release = e1000_null_phy_generic; 90 phy->ops.reset = e1000_null_ops_generic; 91 phy->ops.set_d0_lplu_state = e1000_null_lplu_state; 92 phy->ops.set_d3_lplu_state = e1000_null_lplu_state; 93 phy->ops.write_reg = e1000_null_write_reg; 94 phy->ops.write_reg_locked = e1000_null_write_reg; 95 phy->ops.write_reg_page = e1000_null_write_reg; 96 phy->ops.power_up = e1000_null_phy_generic; 97 phy->ops.power_down = e1000_null_phy_generic; 98 phy->ops.read_i2c_byte = e1000_read_i2c_byte_null; 99 phy->ops.write_i2c_byte = e1000_write_i2c_byte_null; 100 phy->ops.cfg_on_link_up = e1000_null_ops_generic; 101} 102 103/** 104 * e1000_null_set_page - No-op function, return 0 105 * @hw: pointer to the HW structure 106 **/ 107s32 e1000_null_set_page(struct e1000_hw E1000_UNUSEDARG *hw, 108 u16 E1000_UNUSEDARG data) 109{ 110 DEBUGFUNC("e1000_null_set_page"); 111 return E1000_SUCCESS; 112} 113 114/** 115 * e1000_null_read_reg - No-op function, return 0 116 * @hw: pointer to the HW structure 117 **/ 118s32 e1000_null_read_reg(struct e1000_hw E1000_UNUSEDARG *hw, 119 u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG *data) 120{ 121 DEBUGFUNC("e1000_null_read_reg"); 122 return E1000_SUCCESS; 123} 124 125/** 126 * e1000_null_phy_generic - No-op function, return void 127 * @hw: pointer to the HW structure 128 **/ 129void e1000_null_phy_generic(struct e1000_hw E1000_UNUSEDARG *hw) 130{ 131 DEBUGFUNC("e1000_null_phy_generic"); 132 return; 133} 134 135/** 136 * e1000_null_lplu_state - No-op function, return 0 137 * @hw: pointer to the HW structure 138 **/ 139s32 e1000_null_lplu_state(struct e1000_hw E1000_UNUSEDARG *hw, 140 bool E1000_UNUSEDARG active) 141{ 142 DEBUGFUNC("e1000_null_lplu_state"); 143 return E1000_SUCCESS; 144} 145 146/** 147 * e1000_null_write_reg - No-op function, return 0 148 * @hw: pointer to the HW structure 149 **/ 150s32 e1000_null_write_reg(struct e1000_hw E1000_UNUSEDARG *hw, 151 u32 E1000_UNUSEDARG offset, u16 E1000_UNUSEDARG data) 152{ 153 DEBUGFUNC("e1000_null_write_reg"); 154 return E1000_SUCCESS; 155} 156 157/** 158 * e1000_read_i2c_byte_null - No-op function, return 0 159 * @hw: pointer to hardware structure 160 * @byte_offset: byte offset to write 161 * @dev_addr: device address 162 * @data: data value read 163 * 164 **/ 165s32 e1000_read_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw, 166 u8 E1000_UNUSEDARG byte_offset, 167 u8 E1000_UNUSEDARG dev_addr, 168 u8 E1000_UNUSEDARG *data) 169{ 170 DEBUGFUNC("e1000_read_i2c_byte_null"); 171 return E1000_SUCCESS; 172} 173 174/** 175 * e1000_write_i2c_byte_null - No-op function, return 0 176 * @hw: pointer to hardware structure 177 * @byte_offset: byte offset to write 178 * @dev_addr: device address 179 * @data: data value to write 180 * 181 **/ 182s32 e1000_write_i2c_byte_null(struct e1000_hw E1000_UNUSEDARG *hw, 183 u8 E1000_UNUSEDARG byte_offset, 184 u8 E1000_UNUSEDARG dev_addr, 185 u8 E1000_UNUSEDARG data) 186{ 187 DEBUGFUNC("e1000_write_i2c_byte_null"); 188 return E1000_SUCCESS; 189} 190 191/** 192 * e1000_check_reset_block_generic - Check if PHY reset is blocked 193 * @hw: pointer to the HW structure 194 * 195 * Read the PHY management control register and check whether a PHY reset 196 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise 197 * return E1000_BLK_PHY_RESET (12). 198 **/ 199s32 e1000_check_reset_block_generic(struct e1000_hw *hw) 200{ 201 u32 manc; 202 203 DEBUGFUNC("e1000_check_reset_block"); 204 205 manc = E1000_READ_REG(hw, E1000_MANC); 206 207 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ? 208 E1000_BLK_PHY_RESET : E1000_SUCCESS; 209} 210 211/** 212 * e1000_get_phy_id - Retrieve the PHY ID and revision 213 * @hw: pointer to the HW structure 214 * 215 * Reads the PHY registers and stores the PHY ID and possibly the PHY 216 * revision in the hardware structure. 217 **/ 218s32 e1000_get_phy_id(struct e1000_hw *hw) 219{ 220 struct e1000_phy_info *phy = &hw->phy; 221 s32 ret_val = E1000_SUCCESS; 222 u16 phy_id; 223 u16 retry_count = 0; 224 225 DEBUGFUNC("e1000_get_phy_id"); 226 227 if (!phy->ops.read_reg) 228 return E1000_SUCCESS; 229 230 while (retry_count < 2) { 231 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); 232 if (ret_val) 233 return ret_val; 234 235 phy->id = (u32)(phy_id << 16); 236 usec_delay(20); 237 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id); 238 if (ret_val) 239 return ret_val; 240 241 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); 242 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK); 243 244 if (phy->id != 0 && phy->id != PHY_REVISION_MASK) 245 return E1000_SUCCESS; 246 247 retry_count++; 248 } 249 250 return E1000_SUCCESS; 251} 252 253/** 254 * e1000_phy_reset_dsp_generic - Reset PHY DSP 255 * @hw: pointer to the HW structure 256 * 257 * Reset the digital signal processor. 258 **/ 259s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw) 260{ 261 s32 ret_val; 262 263 DEBUGFUNC("e1000_phy_reset_dsp_generic"); 264 265 if (!hw->phy.ops.write_reg) 266 return E1000_SUCCESS; 267 268 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1); 269 if (ret_val) 270 return ret_val; 271 272 return hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0); 273} 274 275/** 276 * e1000_read_phy_reg_mdic - Read MDI control register 277 * @hw: pointer to the HW structure 278 * @offset: register offset to be read 279 * @data: pointer to the read data 280 * 281 * Reads the MDI control register in the PHY at offset and stores the 282 * information read to data. 283 **/ 284s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) 285{ 286 struct e1000_phy_info *phy = &hw->phy; 287 u32 i, mdic = 0; 288 289 DEBUGFUNC("e1000_read_phy_reg_mdic"); 290 291 if (offset > MAX_PHY_REG_ADDRESS) { 292 DEBUGOUT1("PHY Address %d is out of range\n", offset); 293 return -E1000_ERR_PARAM; 294 } 295 296 /* Set up Op-code, Phy Address, and register offset in the MDI 297 * Control register. The MAC will take care of interfacing with the 298 * PHY to retrieve the desired data. 299 */ 300 mdic = ((offset << E1000_MDIC_REG_SHIFT) | 301 (phy->addr << E1000_MDIC_PHY_SHIFT) | 302 (E1000_MDIC_OP_READ)); 303 304 E1000_WRITE_REG(hw, E1000_MDIC, mdic); 305 306 /* Poll the ready bit to see if the MDI read completed 307 * Increasing the time out as testing showed failures with 308 * the lower time out 309 */ 310 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 311 usec_delay_irq(50); 312 mdic = E1000_READ_REG(hw, E1000_MDIC); 313 if (mdic & E1000_MDIC_READY) 314 break; 315 } 316 if (!(mdic & E1000_MDIC_READY)) { 317 DEBUGOUT("MDI Read did not complete\n"); 318 return -E1000_ERR_PHY; 319 } 320 if (mdic & E1000_MDIC_ERROR) { 321 DEBUGOUT("MDI Error\n"); 322 return -E1000_ERR_PHY; 323 } 324 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) { 325 DEBUGOUT2("MDI Read offset error - requested %d, returned %d\n", 326 offset, 327 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); 328 return -E1000_ERR_PHY; 329 } 330 *data = (u16) mdic; 331 332 /* Allow some time after each MDIC transaction to avoid 333 * reading duplicate data in the next MDIC transaction. 334 */ 335 if (hw->mac.type == e1000_pch2lan) 336 usec_delay_irq(100); 337 338 return E1000_SUCCESS; 339} 340 341/** 342 * e1000_write_phy_reg_mdic - Write MDI control register 343 * @hw: pointer to the HW structure 344 * @offset: register offset to write to 345 * @data: data to write to register at offset 346 * 347 * Writes data to MDI control register in the PHY at offset. 348 **/ 349s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) 350{ 351 struct e1000_phy_info *phy = &hw->phy; 352 u32 i, mdic = 0; 353 354 DEBUGFUNC("e1000_write_phy_reg_mdic"); 355 356 if (offset > MAX_PHY_REG_ADDRESS) { 357 DEBUGOUT1("PHY Address %d is out of range\n", offset); 358 return -E1000_ERR_PARAM; 359 } 360 361 /* Set up Op-code, Phy Address, and register offset in the MDI 362 * Control register. The MAC will take care of interfacing with the 363 * PHY to retrieve the desired data. 364 */ 365 mdic = (((u32)data) | 366 (offset << E1000_MDIC_REG_SHIFT) | 367 (phy->addr << E1000_MDIC_PHY_SHIFT) | 368 (E1000_MDIC_OP_WRITE)); 369 370 E1000_WRITE_REG(hw, E1000_MDIC, mdic); 371 372 /* Poll the ready bit to see if the MDI read completed 373 * Increasing the time out as testing showed failures with 374 * the lower time out 375 */ 376 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) { 377 usec_delay_irq(50); 378 mdic = E1000_READ_REG(hw, E1000_MDIC); 379 if (mdic & E1000_MDIC_READY) 380 break; 381 } 382 if (!(mdic & E1000_MDIC_READY)) { 383 DEBUGOUT("MDI Write did not complete\n"); 384 return -E1000_ERR_PHY; 385 } 386 if (mdic & E1000_MDIC_ERROR) { 387 DEBUGOUT("MDI Error\n"); 388 return -E1000_ERR_PHY; 389 } 390 if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) { 391 DEBUGOUT2("MDI Write offset error - requested %d, returned %d\n", 392 offset, 393 (mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT); 394 return -E1000_ERR_PHY; 395 } 396 397 /* Allow some time after each MDIC transaction to avoid 398 * reading duplicate data in the next MDIC transaction. 399 */ 400 if (hw->mac.type == e1000_pch2lan) 401 usec_delay_irq(100); 402 403 return E1000_SUCCESS; 404} 405 406/** 407 * e1000_read_phy_reg_i2c - Read PHY register using i2c 408 * @hw: pointer to the HW structure 409 * @offset: register offset to be read 410 * @data: pointer to the read data 411 * 412 * Reads the PHY register at offset using the i2c interface and stores the 413 * retrieved information in data. 414 **/ 415s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data) 416{ 417 struct e1000_phy_info *phy = &hw->phy; 418 u32 i, i2ccmd = 0; 419 420 DEBUGFUNC("e1000_read_phy_reg_i2c"); 421 422 /* Set up Op-code, Phy Address, and register address in the I2CCMD 423 * register. The MAC will take care of interfacing with the 424 * PHY to retrieve the desired data. 425 */ 426 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 427 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 428 (E1000_I2CCMD_OPCODE_READ)); 429 430 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 431 432 /* Poll the ready bit to see if the I2C read completed */ 433 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 434 usec_delay(50); 435 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 436 if (i2ccmd & E1000_I2CCMD_READY) 437 break; 438 } 439 if (!(i2ccmd & E1000_I2CCMD_READY)) { 440 DEBUGOUT("I2CCMD Read did not complete\n"); 441 return -E1000_ERR_PHY; 442 } 443 if (i2ccmd & E1000_I2CCMD_ERROR) { 444 DEBUGOUT("I2CCMD Error bit set\n"); 445 return -E1000_ERR_PHY; 446 } 447 448 /* Need to byte-swap the 16-bit value. */ 449 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00); 450 451 return E1000_SUCCESS; 452} 453 454/** 455 * e1000_write_phy_reg_i2c - Write PHY register using i2c 456 * @hw: pointer to the HW structure 457 * @offset: register offset to write to 458 * @data: data to write at register offset 459 * 460 * Writes the data to PHY register at the offset using the i2c interface. 461 **/ 462s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data) 463{ 464 struct e1000_phy_info *phy = &hw->phy; 465 u32 i, i2ccmd = 0; 466 u16 phy_data_swapped; 467 468 DEBUGFUNC("e1000_write_phy_reg_i2c"); 469 470 /* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/ 471 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) { 472 DEBUGOUT1("PHY I2C Address %d is out of range.\n", 473 hw->phy.addr); 474 return -E1000_ERR_CONFIG; 475 } 476 477 /* Swap the data bytes for the I2C interface */ 478 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00); 479 480 /* Set up Op-code, Phy Address, and register address in the I2CCMD 481 * register. The MAC will take care of interfacing with the 482 * PHY to retrieve the desired data. 483 */ 484 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 485 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) | 486 E1000_I2CCMD_OPCODE_WRITE | 487 phy_data_swapped); 488 489 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 490 491 /* Poll the ready bit to see if the I2C read completed */ 492 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 493 usec_delay(50); 494 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 495 if (i2ccmd & E1000_I2CCMD_READY) 496 break; 497 } 498 if (!(i2ccmd & E1000_I2CCMD_READY)) { 499 DEBUGOUT("I2CCMD Write did not complete\n"); 500 return -E1000_ERR_PHY; 501 } 502 if (i2ccmd & E1000_I2CCMD_ERROR) { 503 DEBUGOUT("I2CCMD Error bit set\n"); 504 return -E1000_ERR_PHY; 505 } 506 507 return E1000_SUCCESS; 508} 509 510/** 511 * e1000_read_sfp_data_byte - Reads SFP module data. 512 * @hw: pointer to the HW structure 513 * @offset: byte location offset to be read 514 * @data: read data buffer pointer 515 * 516 * Reads one byte from SFP module data stored 517 * in SFP resided EEPROM memory or SFP diagnostic area. 518 * Function should be called with 519 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access 520 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters 521 * access 522 **/ 523s32 e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data) 524{ 525 u32 i = 0; 526 u32 i2ccmd = 0; 527 u32 data_local = 0; 528 529 DEBUGFUNC("e1000_read_sfp_data_byte"); 530 531 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) { 532 DEBUGOUT("I2CCMD command address exceeds upper limit\n"); 533 return -E1000_ERR_PHY; 534 } 535 536 /* Set up Op-code, EEPROM Address,in the I2CCMD 537 * register. The MAC will take care of interfacing with the 538 * EEPROM to retrieve the desired data. 539 */ 540 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 541 E1000_I2CCMD_OPCODE_READ); 542 543 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 544 545 /* Poll the ready bit to see if the I2C read completed */ 546 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 547 usec_delay(50); 548 data_local = E1000_READ_REG(hw, E1000_I2CCMD); 549 if (data_local & E1000_I2CCMD_READY) 550 break; 551 } 552 if (!(data_local & E1000_I2CCMD_READY)) { 553 DEBUGOUT("I2CCMD Read did not complete\n"); 554 return -E1000_ERR_PHY; 555 } 556 if (data_local & E1000_I2CCMD_ERROR) { 557 DEBUGOUT("I2CCMD Error bit set\n"); 558 return -E1000_ERR_PHY; 559 } 560 *data = (u8) data_local & 0xFF; 561 562 return E1000_SUCCESS; 563} 564 565/** 566 * e1000_write_sfp_data_byte - Writes SFP module data. 567 * @hw: pointer to the HW structure 568 * @offset: byte location offset to write to 569 * @data: data to write 570 * 571 * Writes one byte to SFP module data stored 572 * in SFP resided EEPROM memory or SFP diagnostic area. 573 * Function should be called with 574 * E1000_I2CCMD_SFP_DATA_ADDR(<byte offset>) for SFP module database access 575 * E1000_I2CCMD_SFP_DIAG_ADDR(<byte offset>) for SFP diagnostics parameters 576 * access 577 **/ 578s32 e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data) 579{ 580 u32 i = 0; 581 u32 i2ccmd = 0; 582 u32 data_local = 0; 583 584 DEBUGFUNC("e1000_write_sfp_data_byte"); 585 586 if (offset > E1000_I2CCMD_SFP_DIAG_ADDR(255)) { 587 DEBUGOUT("I2CCMD command address exceeds upper limit\n"); 588 return -E1000_ERR_PHY; 589 } 590 /* The programming interface is 16 bits wide 591 * so we need to read the whole word first 592 * then update appropriate byte lane and write 593 * the updated word back. 594 */ 595 /* Set up Op-code, EEPROM Address,in the I2CCMD 596 * register. The MAC will take care of interfacing 597 * with an EEPROM to write the data given. 598 */ 599 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) | 600 E1000_I2CCMD_OPCODE_READ); 601 /* Set a command to read single word */ 602 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 603 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) { 604 usec_delay(50); 605 /* Poll the ready bit to see if lastly 606 * launched I2C operation completed 607 */ 608 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD); 609 if (i2ccmd & E1000_I2CCMD_READY) { 610 /* Check if this is READ or WRITE phase */ 611 if ((i2ccmd & E1000_I2CCMD_OPCODE_READ) == 612 E1000_I2CCMD_OPCODE_READ) { 613 /* Write the selected byte 614 * lane and update whole word 615 */ 616 data_local = i2ccmd & 0xFF00; 617 data_local |= data; 618 i2ccmd = ((offset << 619 E1000_I2CCMD_REG_ADDR_SHIFT) | 620 E1000_I2CCMD_OPCODE_WRITE | data_local); 621 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd); 622 } else { 623 break; 624 } 625 } 626 } 627 if (!(i2ccmd & E1000_I2CCMD_READY)) { 628 DEBUGOUT("I2CCMD Write did not complete\n"); 629 return -E1000_ERR_PHY; 630 } 631 if (i2ccmd & E1000_I2CCMD_ERROR) { 632 DEBUGOUT("I2CCMD Error bit set\n"); 633 return -E1000_ERR_PHY; 634 } 635 return E1000_SUCCESS; 636} 637 638/** 639 * e1000_read_phy_reg_m88 - Read m88 PHY register 640 * @hw: pointer to the HW structure 641 * @offset: register offset to be read 642 * @data: pointer to the read data 643 * 644 * Acquires semaphore, if necessary, then reads the PHY register at offset 645 * and storing the retrieved information in data. Release any acquired 646 * semaphores before exiting. 647 **/ 648s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data) 649{ 650 s32 ret_val; 651 652 DEBUGFUNC("e1000_read_phy_reg_m88"); 653 654 if (!hw->phy.ops.acquire) 655 return E1000_SUCCESS; 656 657 ret_val = hw->phy.ops.acquire(hw); 658 if (ret_val) 659 return ret_val; 660 661 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 662 data); 663 664 hw->phy.ops.release(hw); 665 666 return ret_val; 667} 668 669/** 670 * e1000_write_phy_reg_m88 - Write m88 PHY register 671 * @hw: pointer to the HW structure 672 * @offset: register offset to write to 673 * @data: data to write at register offset 674 * 675 * Acquires semaphore, if necessary, then writes the data to PHY register 676 * at the offset. Release any acquired semaphores before exiting. 677 **/ 678s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data) 679{ 680 s32 ret_val; 681 682 DEBUGFUNC("e1000_write_phy_reg_m88"); 683 684 if (!hw->phy.ops.acquire) 685 return E1000_SUCCESS; 686 687 ret_val = hw->phy.ops.acquire(hw); 688 if (ret_val) 689 return ret_val; 690 691 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 692 data); 693 694 hw->phy.ops.release(hw); 695 696 return ret_val; 697} 698 699/** 700 * e1000_set_page_igp - Set page as on IGP-like PHY(s) 701 * @hw: pointer to the HW structure 702 * @page: page to set (shifted left when necessary) 703 * 704 * Sets PHY page required for PHY register access. Assumes semaphore is 705 * already acquired. Note, this function sets phy.addr to 1 so the caller 706 * must set it appropriately (if necessary) after this function returns. 707 **/ 708s32 e1000_set_page_igp(struct e1000_hw *hw, u16 page) 709{ 710 DEBUGFUNC("e1000_set_page_igp"); 711 712 DEBUGOUT1("Setting page 0x%x\n", page); 713 714 hw->phy.addr = 1; 715 716 return e1000_write_phy_reg_mdic(hw, IGP01E1000_PHY_PAGE_SELECT, page); 717} 718 719/** 720 * __e1000_read_phy_reg_igp - Read igp PHY register 721 * @hw: pointer to the HW structure 722 * @offset: register offset to be read 723 * @data: pointer to the read data 724 * @locked: semaphore has already been acquired or not 725 * 726 * Acquires semaphore, if necessary, then reads the PHY register at offset 727 * and stores the retrieved information in data. Release any acquired 728 * semaphores before exiting. 729 **/ 730static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data, 731 bool locked) 732{ 733 s32 ret_val = E1000_SUCCESS; 734 735 DEBUGFUNC("__e1000_read_phy_reg_igp"); 736 737 if (!locked) { 738 if (!hw->phy.ops.acquire) 739 return E1000_SUCCESS; 740 741 ret_val = hw->phy.ops.acquire(hw); 742 if (ret_val) 743 return ret_val; 744 } 745 746 if (offset > MAX_PHY_MULTI_PAGE_REG) 747 ret_val = e1000_write_phy_reg_mdic(hw, 748 IGP01E1000_PHY_PAGE_SELECT, 749 (u16)offset); 750 if (!ret_val) 751 ret_val = e1000_read_phy_reg_mdic(hw, 752 MAX_PHY_REG_ADDRESS & offset, 753 data); 754 if (!locked) 755 hw->phy.ops.release(hw); 756 757 return ret_val; 758} 759 760/** 761 * e1000_read_phy_reg_igp - Read igp PHY register 762 * @hw: pointer to the HW structure 763 * @offset: register offset to be read 764 * @data: pointer to the read data 765 * 766 * Acquires semaphore then reads the PHY register at offset and stores the 767 * retrieved information in data. 768 * Release the acquired semaphore before exiting. 769 **/ 770s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data) 771{ 772 return __e1000_read_phy_reg_igp(hw, offset, data, FALSE); 773} 774 775/** 776 * e1000_read_phy_reg_igp_locked - Read igp PHY register 777 * @hw: pointer to the HW structure 778 * @offset: register offset to be read 779 * @data: pointer to the read data 780 * 781 * Reads the PHY register at offset and stores the retrieved information 782 * in data. Assumes semaphore already acquired. 783 **/ 784s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data) 785{ 786 return __e1000_read_phy_reg_igp(hw, offset, data, TRUE); 787} 788 789/** 790 * e1000_write_phy_reg_igp - Write igp PHY register 791 * @hw: pointer to the HW structure 792 * @offset: register offset to write to 793 * @data: data to write at register offset 794 * @locked: semaphore has already been acquired or not 795 * 796 * Acquires semaphore, if necessary, then writes the data to PHY register 797 * at the offset. Release any acquired semaphores before exiting. 798 **/ 799static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data, 800 bool locked) 801{ 802 s32 ret_val = E1000_SUCCESS; 803 804 DEBUGFUNC("e1000_write_phy_reg_igp"); 805 806 if (!locked) { 807 if (!hw->phy.ops.acquire) 808 return E1000_SUCCESS; 809 810 ret_val = hw->phy.ops.acquire(hw); 811 if (ret_val) 812 return ret_val; 813 } 814 815 if (offset > MAX_PHY_MULTI_PAGE_REG) 816 ret_val = e1000_write_phy_reg_mdic(hw, 817 IGP01E1000_PHY_PAGE_SELECT, 818 (u16)offset); 819 if (!ret_val) 820 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & 821 offset, 822 data); 823 if (!locked) 824 hw->phy.ops.release(hw); 825 826 return ret_val; 827} 828 829/** 830 * e1000_write_phy_reg_igp - Write igp PHY register 831 * @hw: pointer to the HW structure 832 * @offset: register offset to write to 833 * @data: data to write at register offset 834 * 835 * Acquires semaphore then writes the data to PHY register 836 * at the offset. Release any acquired semaphores before exiting. 837 **/ 838s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data) 839{ 840 return __e1000_write_phy_reg_igp(hw, offset, data, FALSE); 841} 842 843/** 844 * e1000_write_phy_reg_igp_locked - Write igp PHY register 845 * @hw: pointer to the HW structure 846 * @offset: register offset to write to 847 * @data: data to write at register offset 848 * 849 * Writes the data to PHY register at the offset. 850 * Assumes semaphore already acquired. 851 **/ 852s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data) 853{ 854 return __e1000_write_phy_reg_igp(hw, offset, data, TRUE); 855} 856 857/** 858 * __e1000_read_kmrn_reg - Read kumeran register 859 * @hw: pointer to the HW structure 860 * @offset: register offset to be read 861 * @data: pointer to the read data 862 * @locked: semaphore has already been acquired or not 863 * 864 * Acquires semaphore, if necessary. Then reads the PHY register at offset 865 * using the kumeran interface. The information retrieved is stored in data. 866 * Release any acquired semaphores before exiting. 867 **/ 868static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data, 869 bool locked) 870{ 871 u32 kmrnctrlsta; 872 873 DEBUGFUNC("__e1000_read_kmrn_reg"); 874 875 if (!locked) { 876 s32 ret_val = E1000_SUCCESS; 877 878 if (!hw->phy.ops.acquire) 879 return E1000_SUCCESS; 880 881 ret_val = hw->phy.ops.acquire(hw); 882 if (ret_val) 883 return ret_val; 884 } 885 886 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 887 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN; 888 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 889 E1000_WRITE_FLUSH(hw); 890 891 usec_delay(2); 892 893 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA); 894 *data = (u16)kmrnctrlsta; 895 896 if (!locked) 897 hw->phy.ops.release(hw); 898 899 return E1000_SUCCESS; 900} 901 902/** 903 * e1000_read_kmrn_reg_generic - Read kumeran register 904 * @hw: pointer to the HW structure 905 * @offset: register offset to be read 906 * @data: pointer to the read data 907 * 908 * Acquires semaphore then reads the PHY register at offset using the 909 * kumeran interface. The information retrieved is stored in data. 910 * Release the acquired semaphore before exiting. 911 **/ 912s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data) 913{ 914 return __e1000_read_kmrn_reg(hw, offset, data, FALSE); 915} 916 917/** 918 * e1000_read_kmrn_reg_locked - Read kumeran register 919 * @hw: pointer to the HW structure 920 * @offset: register offset to be read 921 * @data: pointer to the read data 922 * 923 * Reads the PHY register at offset using the kumeran interface. The 924 * information retrieved is stored in data. 925 * Assumes semaphore already acquired. 926 **/ 927s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data) 928{ 929 return __e1000_read_kmrn_reg(hw, offset, data, TRUE); 930} 931 932/** 933 * __e1000_write_kmrn_reg - Write kumeran register 934 * @hw: pointer to the HW structure 935 * @offset: register offset to write to 936 * @data: data to write at register offset 937 * @locked: semaphore has already been acquired or not 938 * 939 * Acquires semaphore, if necessary. Then write the data to PHY register 940 * at the offset using the kumeran interface. Release any acquired semaphores 941 * before exiting. 942 **/ 943static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data, 944 bool locked) 945{ 946 u32 kmrnctrlsta; 947 948 DEBUGFUNC("e1000_write_kmrn_reg_generic"); 949 950 if (!locked) { 951 s32 ret_val = E1000_SUCCESS; 952 953 if (!hw->phy.ops.acquire) 954 return E1000_SUCCESS; 955 956 ret_val = hw->phy.ops.acquire(hw); 957 if (ret_val) 958 return ret_val; 959 } 960 961 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) & 962 E1000_KMRNCTRLSTA_OFFSET) | data; 963 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta); 964 E1000_WRITE_FLUSH(hw); 965 966 usec_delay(2); 967 968 if (!locked) 969 hw->phy.ops.release(hw); 970 971 return E1000_SUCCESS; 972} 973 974/** 975 * e1000_write_kmrn_reg_generic - Write kumeran register 976 * @hw: pointer to the HW structure 977 * @offset: register offset to write to 978 * @data: data to write at register offset 979 * 980 * Acquires semaphore then writes the data to the PHY register at the offset 981 * using the kumeran interface. Release the acquired semaphore before exiting. 982 **/ 983s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data) 984{ 985 return __e1000_write_kmrn_reg(hw, offset, data, FALSE); 986} 987 988/** 989 * e1000_write_kmrn_reg_locked - Write kumeran register 990 * @hw: pointer to the HW structure 991 * @offset: register offset to write to 992 * @data: data to write at register offset 993 * 994 * Write the data to PHY register at the offset using the kumeran interface. 995 * Assumes semaphore already acquired. 996 **/ 997s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data) 998{ 999 return __e1000_write_kmrn_reg(hw, offset, data, TRUE); 1000} 1001 1002/** 1003 * e1000_set_master_slave_mode - Setup PHY for Master/slave mode 1004 * @hw: pointer to the HW structure 1005 * 1006 * Sets up Master/slave mode 1007 **/ 1008static s32 e1000_set_master_slave_mode(struct e1000_hw *hw) 1009{ 1010 s32 ret_val; 1011 u16 phy_data; 1012 1013 /* Resolve Master/Slave mode */ 1014 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data); 1015 if (ret_val) 1016 return ret_val; 1017 1018 /* load defaults for future use */ 1019 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ? 1020 ((phy_data & CR_1000T_MS_VALUE) ? 1021 e1000_ms_force_master : 1022 e1000_ms_force_slave) : e1000_ms_auto; 1023 1024 switch (hw->phy.ms_type) { 1025 case e1000_ms_force_master: 1026 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE); 1027 break; 1028 case e1000_ms_force_slave: 1029 phy_data |= CR_1000T_MS_ENABLE; 1030 phy_data &= ~(CR_1000T_MS_VALUE); 1031 break; 1032 case e1000_ms_auto: 1033 phy_data &= ~CR_1000T_MS_ENABLE; 1034 /* fall-through */ 1035 default: 1036 break; 1037 } 1038 1039 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data); 1040} 1041 1042/** 1043 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link 1044 * @hw: pointer to the HW structure 1045 * 1046 * Sets up Carrier-sense on Transmit and downshift values. 1047 **/ 1048s32 e1000_copper_link_setup_82577(struct e1000_hw *hw) 1049{ 1050 s32 ret_val; 1051 u16 phy_data; 1052 1053 DEBUGFUNC("e1000_copper_link_setup_82577"); 1054 1055 if (hw->phy.type == e1000_phy_82580) { 1056 ret_val = hw->phy.ops.reset(hw); 1057 if (ret_val) { 1058 DEBUGOUT("Error resetting the PHY.\n"); 1059 return ret_val; 1060 } 1061 } 1062 1063 /* Enable CRS on Tx. This must be set for half-duplex operation. */ 1064 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data); 1065 if (ret_val) 1066 return ret_val; 1067 1068 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX; 1069 1070 /* Enable downshift */ 1071 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT; 1072 1073 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data); 1074 if (ret_val) 1075 return ret_val; 1076 1077 /* Set MDI/MDIX mode */ 1078 ret_val = hw->phy.ops.read_reg(hw, I82577_PHY_CTRL_2, &phy_data); 1079 if (ret_val) 1080 return ret_val; 1081 phy_data &= ~I82577_PHY_CTRL2_MDIX_CFG_MASK; 1082 /* Options: 1083 * 0 - Auto (default) 1084 * 1 - MDI mode 1085 * 2 - MDI-X mode 1086 */ 1087 switch (hw->phy.mdix) { 1088 case 1: 1089 break; 1090 case 2: 1091 phy_data |= I82577_PHY_CTRL2_MANUAL_MDIX; 1092 break; 1093 case 0: 1094 default: 1095 phy_data |= I82577_PHY_CTRL2_AUTO_MDI_MDIX; 1096 break; 1097 } 1098 ret_val = hw->phy.ops.write_reg(hw, I82577_PHY_CTRL_2, phy_data); 1099 if (ret_val) 1100 return ret_val; 1101 1102 return e1000_set_master_slave_mode(hw); 1103} 1104 1105/** 1106 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link 1107 * @hw: pointer to the HW structure 1108 * 1109 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock 1110 * and downshift values are set also. 1111 **/ 1112s32 e1000_copper_link_setup_m88(struct e1000_hw *hw) 1113{ 1114 struct e1000_phy_info *phy = &hw->phy; 1115 s32 ret_val; 1116 u16 phy_data; 1117 1118 DEBUGFUNC("e1000_copper_link_setup_m88"); 1119 1120 1121 /* Enable CRS on Tx. This must be set for half-duplex operation. */ 1122 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1123 if (ret_val) 1124 return ret_val; 1125 1126 /* For BM PHY this bit is downshift enable */ 1127 if (phy->type != e1000_phy_bm) 1128 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1129 1130 /* Options: 1131 * MDI/MDI-X = 0 (default) 1132 * 0 - Auto for all speeds 1133 * 1 - MDI mode 1134 * 2 - MDI-X mode 1135 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1136 */ 1137 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1138 1139 switch (phy->mdix) { 1140 case 1: 1141 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 1142 break; 1143 case 2: 1144 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 1145 break; 1146 case 3: 1147 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 1148 break; 1149 case 0: 1150 default: 1151 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 1152 break; 1153 } 1154 1155 /* Options: 1156 * disable_polarity_correction = 0 (default) 1157 * Automatic Correction for Reversed Cable Polarity 1158 * 0 - Disabled 1159 * 1 - Enabled 1160 */ 1161 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1162 if (phy->disable_polarity_correction) 1163 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 1164 1165 /* Enable downshift on BM (disabled by default) */ 1166 if (phy->type == e1000_phy_bm) { 1167 /* For 82574/82583, first disable then enable downshift */ 1168 if (phy->id == BME1000_E_PHY_ID_R2) { 1169 phy_data &= ~BME1000_PSCR_ENABLE_DOWNSHIFT; 1170 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, 1171 phy_data); 1172 if (ret_val) 1173 return ret_val; 1174 /* Commit the changes. */ 1175 ret_val = phy->ops.commit(hw); 1176 if (ret_val) { 1177 DEBUGOUT("Error committing the PHY changes\n"); 1178 return ret_val; 1179 } 1180 } 1181 1182 phy_data |= BME1000_PSCR_ENABLE_DOWNSHIFT; 1183 } 1184 1185 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1186 if (ret_val) 1187 return ret_val; 1188 1189 if ((phy->type == e1000_phy_m88) && 1190 (phy->revision < E1000_REVISION_4) && 1191 (phy->id != BME1000_E_PHY_ID_R2)) { 1192 /* Force TX_CLK in the Extended PHY Specific Control Register 1193 * to 25MHz clock. 1194 */ 1195 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1196 &phy_data); 1197 if (ret_val) 1198 return ret_val; 1199 1200 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1201 1202 if ((phy->revision == E1000_REVISION_2) && 1203 (phy->id == M88E1111_I_PHY_ID)) { 1204 /* 82573L PHY - set the downshift counter to 5x. */ 1205 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK; 1206 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X; 1207 } else { 1208 /* Configure Master and Slave downshift values */ 1209 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK | 1210 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK); 1211 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X | 1212 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X); 1213 } 1214 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1215 phy_data); 1216 if (ret_val) 1217 return ret_val; 1218 } 1219 1220 if ((phy->type == e1000_phy_bm) && (phy->id == BME1000_E_PHY_ID_R2)) { 1221 /* Set PHY page 0, register 29 to 0x0003 */ 1222 ret_val = phy->ops.write_reg(hw, 29, 0x0003); 1223 if (ret_val) 1224 return ret_val; 1225 1226 /* Set PHY page 0, register 30 to 0x0000 */ 1227 ret_val = phy->ops.write_reg(hw, 30, 0x0000); 1228 if (ret_val) 1229 return ret_val; 1230 } 1231 1232 /* Commit the changes. */ 1233 ret_val = phy->ops.commit(hw); 1234 if (ret_val) { 1235 DEBUGOUT("Error committing the PHY changes\n"); 1236 return ret_val; 1237 } 1238 1239 if (phy->type == e1000_phy_82578) { 1240 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1241 &phy_data); 1242 if (ret_val) 1243 return ret_val; 1244 1245 /* 82578 PHY - set the downshift count to 1x. */ 1246 phy_data |= I82578_EPSCR_DOWNSHIFT_ENABLE; 1247 phy_data &= ~I82578_EPSCR_DOWNSHIFT_COUNTER_MASK; 1248 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, 1249 phy_data); 1250 if (ret_val) 1251 return ret_val; 1252 } 1253 1254 return E1000_SUCCESS; 1255} 1256 1257/** 1258 * e1000_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link 1259 * @hw: pointer to the HW structure 1260 * 1261 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's. 1262 * Also enables and sets the downshift parameters. 1263 **/ 1264s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw) 1265{ 1266 struct e1000_phy_info *phy = &hw->phy; 1267 s32 ret_val; 1268 u16 phy_data; 1269 1270 DEBUGFUNC("e1000_copper_link_setup_m88_gen2"); 1271 1272 1273 /* Enable CRS on Tx. This must be set for half-duplex operation. */ 1274 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1275 if (ret_val) 1276 return ret_val; 1277 1278 /* Options: 1279 * MDI/MDI-X = 0 (default) 1280 * 0 - Auto for all speeds 1281 * 1 - MDI mode 1282 * 2 - MDI-X mode 1283 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) 1284 */ 1285 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1286 1287 switch (phy->mdix) { 1288 case 1: 1289 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE; 1290 break; 1291 case 2: 1292 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE; 1293 break; 1294 case 3: 1295 /* M88E1112 does not support this mode) */ 1296 if (phy->id != M88E1112_E_PHY_ID) { 1297 phy_data |= M88E1000_PSCR_AUTO_X_1000T; 1298 break; 1299 } 1300 case 0: 1301 default: 1302 phy_data |= M88E1000_PSCR_AUTO_X_MODE; 1303 break; 1304 } 1305 1306 /* Options: 1307 * disable_polarity_correction = 0 (default) 1308 * Automatic Correction for Reversed Cable Polarity 1309 * 0 - Disabled 1310 * 1 - Enabled 1311 */ 1312 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL; 1313 if (phy->disable_polarity_correction) 1314 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL; 1315 1316 /* Enable downshift and setting it to X6 */ 1317 if (phy->id == M88E1543_E_PHY_ID) { 1318 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_ENABLE; 1319 ret_val = 1320 phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1321 if (ret_val) 1322 return ret_val; 1323 1324 ret_val = phy->ops.commit(hw); 1325 if (ret_val) { 1326 DEBUGOUT("Error committing the PHY changes\n"); 1327 return ret_val; 1328 } 1329 } 1330 1331 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK; 1332 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X; 1333 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE; 1334 1335 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1336 if (ret_val) 1337 return ret_val; 1338 1339 /* Commit the changes. */ 1340 ret_val = phy->ops.commit(hw); 1341 if (ret_val) { 1342 DEBUGOUT("Error committing the PHY changes\n"); 1343 return ret_val; 1344 } 1345 1346 ret_val = e1000_set_master_slave_mode(hw); 1347 if (ret_val) 1348 return ret_val; 1349 1350 return E1000_SUCCESS; 1351} 1352 1353/** 1354 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link 1355 * @hw: pointer to the HW structure 1356 * 1357 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for 1358 * igp PHY's. 1359 **/ 1360s32 e1000_copper_link_setup_igp(struct e1000_hw *hw) 1361{ 1362 struct e1000_phy_info *phy = &hw->phy; 1363 s32 ret_val; 1364 u16 data; 1365 1366 DEBUGFUNC("e1000_copper_link_setup_igp"); 1367 1368 1369 ret_val = hw->phy.ops.reset(hw); 1370 if (ret_val) { 1371 DEBUGOUT("Error resetting the PHY.\n"); 1372 return ret_val; 1373 } 1374 1375 /* Wait 100ms for MAC to configure PHY from NVM settings, to avoid 1376 * timeout issues when LFS is enabled. 1377 */ 1378 msec_delay(100); 1379 1380 /* The NVM settings will configure LPLU in D3 for 1381 * non-IGP1 PHYs. 1382 */ 1383 if (phy->type == e1000_phy_igp) { 1384 /* disable lplu d3 during driver init */ 1385 ret_val = hw->phy.ops.set_d3_lplu_state(hw, FALSE); 1386 if (ret_val) { 1387 DEBUGOUT("Error Disabling LPLU D3\n"); 1388 return ret_val; 1389 } 1390 } 1391 1392 /* disable lplu d0 during driver init */ 1393 if (hw->phy.ops.set_d0_lplu_state) { 1394 ret_val = hw->phy.ops.set_d0_lplu_state(hw, FALSE); 1395 if (ret_val) { 1396 DEBUGOUT("Error Disabling LPLU D0\n"); 1397 return ret_val; 1398 } 1399 } 1400 /* Configure mdi-mdix settings */ 1401 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data); 1402 if (ret_val) 1403 return ret_val; 1404 1405 data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1406 1407 switch (phy->mdix) { 1408 case 1: 1409 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1410 break; 1411 case 2: 1412 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX; 1413 break; 1414 case 0: 1415 default: 1416 data |= IGP01E1000_PSCR_AUTO_MDIX; 1417 break; 1418 } 1419 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data); 1420 if (ret_val) 1421 return ret_val; 1422 1423 /* set auto-master slave resolution settings */ 1424 if (hw->mac.autoneg) { 1425 /* when autonegotiation advertisement is only 1000Mbps then we 1426 * should disable SmartSpeed and enable Auto MasterSlave 1427 * resolution as hardware default. 1428 */ 1429 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) { 1430 /* Disable SmartSpeed */ 1431 ret_val = phy->ops.read_reg(hw, 1432 IGP01E1000_PHY_PORT_CONFIG, 1433 &data); 1434 if (ret_val) 1435 return ret_val; 1436 1437 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1438 ret_val = phy->ops.write_reg(hw, 1439 IGP01E1000_PHY_PORT_CONFIG, 1440 data); 1441 if (ret_val) 1442 return ret_val; 1443 1444 /* Set auto Master/Slave resolution process */ 1445 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data); 1446 if (ret_val) 1447 return ret_val; 1448 1449 data &= ~CR_1000T_MS_ENABLE; 1450 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data); 1451 if (ret_val) 1452 return ret_val; 1453 } 1454 1455 ret_val = e1000_set_master_slave_mode(hw); 1456 } 1457 1458 return ret_val; 1459} 1460 1461/** 1462 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation 1463 * @hw: pointer to the HW structure 1464 * 1465 * Reads the MII auto-neg advertisement register and/or the 1000T control 1466 * register and if the PHY is already setup for auto-negotiation, then 1467 * return successful. Otherwise, setup advertisement and flow control to 1468 * the appropriate values for the wanted auto-negotiation. 1469 **/ 1470s32 e1000_phy_setup_autoneg(struct e1000_hw *hw) 1471{ 1472 struct e1000_phy_info *phy = &hw->phy; 1473 s32 ret_val; 1474 u16 mii_autoneg_adv_reg; 1475 u16 mii_1000t_ctrl_reg = 0; 1476 1477 DEBUGFUNC("e1000_phy_setup_autoneg"); 1478 1479 phy->autoneg_advertised &= phy->autoneg_mask; 1480 1481 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ 1482 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg); 1483 if (ret_val) 1484 return ret_val; 1485 1486 if (phy->autoneg_mask & ADVERTISE_1000_FULL) { 1487 /* Read the MII 1000Base-T Control Register (Address 9). */ 1488 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, 1489 &mii_1000t_ctrl_reg); 1490 if (ret_val) 1491 return ret_val; 1492 } 1493 1494 /* Need to parse both autoneg_advertised and fc and set up 1495 * the appropriate PHY registers. First we will parse for 1496 * autoneg_advertised software override. Since we can advertise 1497 * a plethora of combinations, we need to check each bit 1498 * individually. 1499 */ 1500 1501 /* First we clear all the 10/100 mb speed bits in the Auto-Neg 1502 * Advertisement Register (Address 4) and the 1000 mb speed bits in 1503 * the 1000Base-T Control Register (Address 9). 1504 */ 1505 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS | 1506 NWAY_AR_100TX_HD_CAPS | 1507 NWAY_AR_10T_FD_CAPS | 1508 NWAY_AR_10T_HD_CAPS); 1509 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS); 1510 1511 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised); 1512 1513 /* Do we want to advertise 10 Mb Half Duplex? */ 1514 if (phy->autoneg_advertised & ADVERTISE_10_HALF) { 1515 DEBUGOUT("Advertise 10mb Half duplex\n"); 1516 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS; 1517 } 1518 1519 /* Do we want to advertise 10 Mb Full Duplex? */ 1520 if (phy->autoneg_advertised & ADVERTISE_10_FULL) { 1521 DEBUGOUT("Advertise 10mb Full duplex\n"); 1522 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS; 1523 } 1524 1525 /* Do we want to advertise 100 Mb Half Duplex? */ 1526 if (phy->autoneg_advertised & ADVERTISE_100_HALF) { 1527 DEBUGOUT("Advertise 100mb Half duplex\n"); 1528 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS; 1529 } 1530 1531 /* Do we want to advertise 100 Mb Full Duplex? */ 1532 if (phy->autoneg_advertised & ADVERTISE_100_FULL) { 1533 DEBUGOUT("Advertise 100mb Full duplex\n"); 1534 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS; 1535 } 1536 1537 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ 1538 if (phy->autoneg_advertised & ADVERTISE_1000_HALF) 1539 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n"); 1540 1541 /* Do we want to advertise 1000 Mb Full Duplex? */ 1542 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) { 1543 DEBUGOUT("Advertise 1000mb Full duplex\n"); 1544 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS; 1545 } 1546 1547 /* Check for a software override of the flow control settings, and 1548 * setup the PHY advertisement registers accordingly. If 1549 * auto-negotiation is enabled, then software will have to set the 1550 * "PAUSE" bits to the correct value in the Auto-Negotiation 1551 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto- 1552 * negotiation. 1553 * 1554 * The possible values of the "fc" parameter are: 1555 * 0: Flow control is completely disabled 1556 * 1: Rx flow control is enabled (we can receive pause frames 1557 * but not send pause frames). 1558 * 2: Tx flow control is enabled (we can send pause frames 1559 * but we do not support receiving pause frames). 1560 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1561 * other: No software override. The flow control configuration 1562 * in the EEPROM is used. 1563 */ 1564 switch (hw->fc.current_mode) { 1565 case e1000_fc_none: 1566 /* Flow control (Rx & Tx) is completely disabled by a 1567 * software over-ride. 1568 */ 1569 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1570 break; 1571 case e1000_fc_rx_pause: 1572 /* Rx Flow control is enabled, and Tx Flow control is 1573 * disabled, by a software over-ride. 1574 * 1575 * Since there really isn't a way to advertise that we are 1576 * capable of Rx Pause ONLY, we will advertise that we 1577 * support both symmetric and asymmetric Rx PAUSE. Later 1578 * (in e1000_config_fc_after_link_up) we will disable the 1579 * hw's ability to send PAUSE frames. 1580 */ 1581 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1582 break; 1583 case e1000_fc_tx_pause: 1584 /* Tx Flow control is enabled, and Rx Flow control is 1585 * disabled, by a software over-ride. 1586 */ 1587 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR; 1588 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE; 1589 break; 1590 case e1000_fc_full: 1591 /* Flow control (both Rx and Tx) is enabled by a software 1592 * over-ride. 1593 */ 1594 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE); 1595 break; 1596 default: 1597 DEBUGOUT("Flow control param set incorrectly\n"); 1598 return -E1000_ERR_CONFIG; 1599 } 1600 1601 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg); 1602 if (ret_val) 1603 return ret_val; 1604 1605 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); 1606 1607 if (phy->autoneg_mask & ADVERTISE_1000_FULL) 1608 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, 1609 mii_1000t_ctrl_reg); 1610 1611 return ret_val; 1612} 1613 1614/** 1615 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link 1616 * @hw: pointer to the HW structure 1617 * 1618 * Performs initial bounds checking on autoneg advertisement parameter, then 1619 * configure to advertise the full capability. Setup the PHY to autoneg 1620 * and restart the negotiation process between the link partner. If 1621 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting. 1622 **/ 1623s32 e1000_copper_link_autoneg(struct e1000_hw *hw) 1624{ 1625 struct e1000_phy_info *phy = &hw->phy; 1626 s32 ret_val; 1627 u16 phy_ctrl; 1628 1629 DEBUGFUNC("e1000_copper_link_autoneg"); 1630 1631 /* Perform some bounds checking on the autoneg advertisement 1632 * parameter. 1633 */ 1634 phy->autoneg_advertised &= phy->autoneg_mask; 1635 1636 /* If autoneg_advertised is zero, we assume it was not defaulted 1637 * by the calling code so we set to advertise full capability. 1638 */ 1639 if (!phy->autoneg_advertised) 1640 phy->autoneg_advertised = phy->autoneg_mask; 1641 1642 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); 1643 ret_val = e1000_phy_setup_autoneg(hw); 1644 if (ret_val) { 1645 DEBUGOUT("Error Setting up Auto-Negotiation\n"); 1646 return ret_val; 1647 } 1648 DEBUGOUT("Restarting Auto-Neg\n"); 1649 1650 /* Restart auto-negotiation by setting the Auto Neg Enable bit and 1651 * the Auto Neg Restart bit in the PHY control register. 1652 */ 1653 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 1654 if (ret_val) 1655 return ret_val; 1656 1657 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG); 1658 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 1659 if (ret_val) 1660 return ret_val; 1661 1662 /* Does the user want to wait for Auto-Neg to complete here, or 1663 * check at a later time (for example, callback routine). 1664 */ 1665 if (phy->autoneg_wait_to_complete) { 1666 ret_val = e1000_wait_autoneg(hw); 1667 if (ret_val) { 1668 DEBUGOUT("Error while waiting for autoneg to complete\n"); 1669 return ret_val; 1670 } 1671 } 1672 1673 hw->mac.get_link_status = TRUE; 1674 1675 return ret_val; 1676} 1677 1678/** 1679 * e1000_setup_copper_link_generic - Configure copper link settings 1680 * @hw: pointer to the HW structure 1681 * 1682 * Calls the appropriate function to configure the link for auto-neg or forced 1683 * speed and duplex. Then we check for link, once link is established calls 1684 * to configure collision distance and flow control are called. If link is 1685 * not established, we return -E1000_ERR_PHY (-2). 1686 **/ 1687s32 e1000_setup_copper_link_generic(struct e1000_hw *hw) 1688{ 1689 s32 ret_val; 1690 bool link; 1691 1692 DEBUGFUNC("e1000_setup_copper_link_generic"); 1693 1694 if (hw->mac.autoneg) { 1695 /* Setup autoneg and flow control advertisement and perform 1696 * autonegotiation. 1697 */ 1698 ret_val = e1000_copper_link_autoneg(hw); 1699 if (ret_val) 1700 return ret_val; 1701 } else { 1702 /* PHY will be set to 10H, 10F, 100H or 100F 1703 * depending on user settings. 1704 */ 1705 DEBUGOUT("Forcing Speed and Duplex\n"); 1706 ret_val = hw->phy.ops.force_speed_duplex(hw); 1707 if (ret_val) { 1708 DEBUGOUT("Error Forcing Speed and Duplex\n"); 1709 return ret_val; 1710 } 1711 } 1712 1713 /* Check link status. Wait up to 100 microseconds for link to become 1714 * valid. 1715 */ 1716 ret_val = e1000_phy_has_link_generic(hw, COPPER_LINK_UP_LIMIT, 10, 1717 &link); 1718 if (ret_val) 1719 return ret_val; 1720 1721 if (link) { 1722 DEBUGOUT("Valid link established!!!\n"); 1723 hw->mac.ops.config_collision_dist(hw); 1724 ret_val = e1000_config_fc_after_link_up_generic(hw); 1725 } else { 1726 DEBUGOUT("Unable to establish link!!!\n"); 1727 } 1728 1729 return ret_val; 1730} 1731 1732/** 1733 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY 1734 * @hw: pointer to the HW structure 1735 * 1736 * Calls the PHY setup function to force speed and duplex. Clears the 1737 * auto-crossover to force MDI manually. Waits for link and returns 1738 * successful if link up is successful, else -E1000_ERR_PHY (-2). 1739 **/ 1740s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw) 1741{ 1742 struct e1000_phy_info *phy = &hw->phy; 1743 s32 ret_val; 1744 u16 phy_data; 1745 bool link; 1746 1747 DEBUGFUNC("e1000_phy_force_speed_duplex_igp"); 1748 1749 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1750 if (ret_val) 1751 return ret_val; 1752 1753 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 1754 1755 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1756 if (ret_val) 1757 return ret_val; 1758 1759 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI 1760 * forced whenever speed and duplex are forced. 1761 */ 1762 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data); 1763 if (ret_val) 1764 return ret_val; 1765 1766 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX; 1767 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX; 1768 1769 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data); 1770 if (ret_val) 1771 return ret_val; 1772 1773 DEBUGOUT1("IGP PSCR: %X\n", phy_data); 1774 1775 usec_delay(1); 1776 1777 if (phy->autoneg_wait_to_complete) { 1778 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n"); 1779 1780 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1781 100000, &link); 1782 if (ret_val) 1783 return ret_val; 1784 1785 if (!link) 1786 DEBUGOUT("Link taking longer than expected.\n"); 1787 1788 /* Try once more */ 1789 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1790 100000, &link); 1791 } 1792 1793 return ret_val; 1794} 1795 1796/** 1797 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY 1798 * @hw: pointer to the HW structure 1799 * 1800 * Calls the PHY setup function to force speed and duplex. Clears the 1801 * auto-crossover to force MDI manually. Resets the PHY to commit the 1802 * changes. If time expires while waiting for link up, we reset the DSP. 1803 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon 1804 * successful completion, else return corresponding error code. 1805 **/ 1806s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw) 1807{ 1808 struct e1000_phy_info *phy = &hw->phy; 1809 s32 ret_val; 1810 u16 phy_data; 1811 bool link; 1812 1813 DEBUGFUNC("e1000_phy_force_speed_duplex_m88"); 1814 1815 /* I210 and I211 devices support Auto-Crossover in forced operation. */ 1816 if (phy->type != e1000_phy_i210) { 1817 /* Clear Auto-Crossover to force MDI manually. M88E1000 1818 * requires MDI forced whenever speed and duplex are forced. 1819 */ 1820 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, 1821 &phy_data); 1822 if (ret_val) 1823 return ret_val; 1824 1825 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE; 1826 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, 1827 phy_data); 1828 if (ret_val) 1829 return ret_val; 1830 } 1831 1832 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data); 1833 1834 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 1835 if (ret_val) 1836 return ret_val; 1837 1838 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 1839 1840 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 1841 if (ret_val) 1842 return ret_val; 1843 1844 /* Reset the phy to commit changes. */ 1845 ret_val = hw->phy.ops.commit(hw); 1846 if (ret_val) 1847 return ret_val; 1848 1849 if (phy->autoneg_wait_to_complete) { 1850 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n"); 1851 1852 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1853 100000, &link); 1854 if (ret_val) 1855 return ret_val; 1856 1857 if (!link) { 1858 bool reset_dsp = TRUE; 1859 1860 switch (hw->phy.id) { 1861 case I347AT4_E_PHY_ID: 1862 case M88E1340M_E_PHY_ID: 1863 case M88E1112_E_PHY_ID: 1864 case M88E1543_E_PHY_ID: 1865 case M88E1512_E_PHY_ID: 1866 case I210_I_PHY_ID: 1867 reset_dsp = FALSE; 1868 break; 1869 default: 1870 if (hw->phy.type != e1000_phy_m88) 1871 reset_dsp = FALSE; 1872 break; 1873 } 1874 1875 if (!reset_dsp) { 1876 DEBUGOUT("Link taking longer than expected.\n"); 1877 } else { 1878 /* We didn't get link. 1879 * Reset the DSP and cross our fingers. 1880 */ 1881 ret_val = phy->ops.write_reg(hw, 1882 M88E1000_PHY_PAGE_SELECT, 1883 0x001d); 1884 if (ret_val) 1885 return ret_val; 1886 ret_val = e1000_phy_reset_dsp_generic(hw); 1887 if (ret_val) 1888 return ret_val; 1889 } 1890 } 1891 1892 /* Try once more */ 1893 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1894 100000, &link); 1895 if (ret_val) 1896 return ret_val; 1897 } 1898 1899 if (hw->phy.type != e1000_phy_m88) 1900 return E1000_SUCCESS; 1901 1902 if (hw->phy.id == I347AT4_E_PHY_ID || 1903 hw->phy.id == M88E1340M_E_PHY_ID || 1904 hw->phy.id == M88E1112_E_PHY_ID) 1905 return E1000_SUCCESS; 1906 if (hw->phy.id == I210_I_PHY_ID) 1907 return E1000_SUCCESS; 1908 if ((hw->phy.id == M88E1543_E_PHY_ID) || 1909 (hw->phy.id == M88E1512_E_PHY_ID)) 1910 return E1000_SUCCESS; 1911 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data); 1912 if (ret_val) 1913 return ret_val; 1914 1915 /* Resetting the phy means we need to re-force TX_CLK in the 1916 * Extended PHY Specific Control Register to 25MHz clock from 1917 * the reset value of 2.5MHz. 1918 */ 1919 phy_data |= M88E1000_EPSCR_TX_CLK_25; 1920 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data); 1921 if (ret_val) 1922 return ret_val; 1923 1924 /* In addition, we must re-enable CRS on Tx for both half and full 1925 * duplex. 1926 */ 1927 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 1928 if (ret_val) 1929 return ret_val; 1930 1931 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX; 1932 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data); 1933 1934 return ret_val; 1935} 1936 1937/** 1938 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex 1939 * @hw: pointer to the HW structure 1940 * 1941 * Forces the speed and duplex settings of the PHY. 1942 * This is a function pointer entry point only called by 1943 * PHY setup routines. 1944 **/ 1945s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw) 1946{ 1947 struct e1000_phy_info *phy = &hw->phy; 1948 s32 ret_val; 1949 u16 data; 1950 bool link; 1951 1952 DEBUGFUNC("e1000_phy_force_speed_duplex_ife"); 1953 1954 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data); 1955 if (ret_val) 1956 return ret_val; 1957 1958 e1000_phy_force_speed_duplex_setup(hw, &data); 1959 1960 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data); 1961 if (ret_val) 1962 return ret_val; 1963 1964 /* Disable MDI-X support for 10/100 */ 1965 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data); 1966 if (ret_val) 1967 return ret_val; 1968 1969 data &= ~IFE_PMC_AUTO_MDIX; 1970 data &= ~IFE_PMC_FORCE_MDIX; 1971 1972 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data); 1973 if (ret_val) 1974 return ret_val; 1975 1976 DEBUGOUT1("IFE PMC: %X\n", data); 1977 1978 usec_delay(1); 1979 1980 if (phy->autoneg_wait_to_complete) { 1981 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n"); 1982 1983 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1984 100000, &link); 1985 if (ret_val) 1986 return ret_val; 1987 1988 if (!link) 1989 DEBUGOUT("Link taking longer than expected.\n"); 1990 1991 /* Try once more */ 1992 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 1993 100000, &link); 1994 if (ret_val) 1995 return ret_val; 1996 } 1997 1998 return E1000_SUCCESS; 1999} 2000 2001/** 2002 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex 2003 * @hw: pointer to the HW structure 2004 * @phy_ctrl: pointer to current value of PHY_CONTROL 2005 * 2006 * Forces speed and duplex on the PHY by doing the following: disable flow 2007 * control, force speed/duplex on the MAC, disable auto speed detection, 2008 * disable auto-negotiation, configure duplex, configure speed, configure 2009 * the collision distance, write configuration to CTRL register. The 2010 * caller must write to the PHY_CONTROL register for these settings to 2011 * take affect. 2012 **/ 2013void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl) 2014{ 2015 struct e1000_mac_info *mac = &hw->mac; 2016 u32 ctrl; 2017 2018 DEBUGFUNC("e1000_phy_force_speed_duplex_setup"); 2019 2020 /* Turn off flow control when forcing speed/duplex */ 2021 hw->fc.current_mode = e1000_fc_none; 2022 2023 /* Force speed/duplex on the mac */ 2024 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2025 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 2026 ctrl &= ~E1000_CTRL_SPD_SEL; 2027 2028 /* Disable Auto Speed Detection */ 2029 ctrl &= ~E1000_CTRL_ASDE; 2030 2031 /* Disable autoneg on the phy */ 2032 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN; 2033 2034 /* Forcing Full or Half Duplex? */ 2035 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) { 2036 ctrl &= ~E1000_CTRL_FD; 2037 *phy_ctrl &= ~MII_CR_FULL_DUPLEX; 2038 DEBUGOUT("Half Duplex\n"); 2039 } else { 2040 ctrl |= E1000_CTRL_FD; 2041 *phy_ctrl |= MII_CR_FULL_DUPLEX; 2042 DEBUGOUT("Full Duplex\n"); 2043 } 2044 2045 /* Forcing 10mb or 100mb? */ 2046 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) { 2047 ctrl |= E1000_CTRL_SPD_100; 2048 *phy_ctrl |= MII_CR_SPEED_100; 2049 *phy_ctrl &= ~MII_CR_SPEED_1000; 2050 DEBUGOUT("Forcing 100mb\n"); 2051 } else { 2052 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100); 2053 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100); 2054 DEBUGOUT("Forcing 10mb\n"); 2055 } 2056 2057 hw->mac.ops.config_collision_dist(hw); 2058 2059 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2060} 2061 2062/** 2063 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3 2064 * @hw: pointer to the HW structure 2065 * @active: boolean used to enable/disable lplu 2066 * 2067 * Success returns 0, Failure returns 1 2068 * 2069 * The low power link up (lplu) state is set to the power management level D3 2070 * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3 2071 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 2072 * is used during Dx states where the power conservation is most important. 2073 * During driver activity, SmartSpeed should be enabled so performance is 2074 * maintained. 2075 **/ 2076s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active) 2077{ 2078 struct e1000_phy_info *phy = &hw->phy; 2079 s32 ret_val; 2080 u16 data; 2081 2082 DEBUGFUNC("e1000_set_d3_lplu_state_generic"); 2083 2084 if (!hw->phy.ops.read_reg) 2085 return E1000_SUCCESS; 2086 2087 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 2088 if (ret_val) 2089 return ret_val; 2090 2091 if (!active) { 2092 data &= ~IGP02E1000_PM_D3_LPLU; 2093 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 2094 data); 2095 if (ret_val) 2096 return ret_val; 2097 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used 2098 * during Dx states where the power conservation is most 2099 * important. During driver activity we should enable 2100 * SmartSpeed, so performance is maintained. 2101 */ 2102 if (phy->smart_speed == e1000_smart_speed_on) { 2103 ret_val = phy->ops.read_reg(hw, 2104 IGP01E1000_PHY_PORT_CONFIG, 2105 &data); 2106 if (ret_val) 2107 return ret_val; 2108 2109 data |= IGP01E1000_PSCFR_SMART_SPEED; 2110 ret_val = phy->ops.write_reg(hw, 2111 IGP01E1000_PHY_PORT_CONFIG, 2112 data); 2113 if (ret_val) 2114 return ret_val; 2115 } else if (phy->smart_speed == e1000_smart_speed_off) { 2116 ret_val = phy->ops.read_reg(hw, 2117 IGP01E1000_PHY_PORT_CONFIG, 2118 &data); 2119 if (ret_val) 2120 return ret_val; 2121 2122 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2123 ret_val = phy->ops.write_reg(hw, 2124 IGP01E1000_PHY_PORT_CONFIG, 2125 data); 2126 if (ret_val) 2127 return ret_val; 2128 } 2129 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 2130 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 2131 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 2132 data |= IGP02E1000_PM_D3_LPLU; 2133 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 2134 data); 2135 if (ret_val) 2136 return ret_val; 2137 2138 /* When LPLU is enabled, we should disable SmartSpeed */ 2139 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 2140 &data); 2141 if (ret_val) 2142 return ret_val; 2143 2144 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 2145 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 2146 data); 2147 } 2148 2149 return ret_val; 2150} 2151 2152/** 2153 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred 2154 * @hw: pointer to the HW structure 2155 * 2156 * Success returns 0, Failure returns 1 2157 * 2158 * A downshift is detected by querying the PHY link health. 2159 **/ 2160s32 e1000_check_downshift_generic(struct e1000_hw *hw) 2161{ 2162 struct e1000_phy_info *phy = &hw->phy; 2163 s32 ret_val; 2164 u16 phy_data, offset, mask; 2165 2166 DEBUGFUNC("e1000_check_downshift_generic"); 2167 2168 switch (phy->type) { 2169 case e1000_phy_i210: 2170 case e1000_phy_m88: 2171 case e1000_phy_gg82563: 2172 case e1000_phy_bm: 2173 case e1000_phy_82578: 2174 offset = M88E1000_PHY_SPEC_STATUS; 2175 mask = M88E1000_PSSR_DOWNSHIFT; 2176 break; 2177 case e1000_phy_igp: 2178 case e1000_phy_igp_2: 2179 case e1000_phy_igp_3: 2180 offset = IGP01E1000_PHY_LINK_HEALTH; 2181 mask = IGP01E1000_PLHR_SS_DOWNGRADE; 2182 break; 2183 default: 2184 /* speed downshift not supported */ 2185 phy->speed_downgraded = FALSE; 2186 return E1000_SUCCESS; 2187 } 2188 2189 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 2190 2191 if (!ret_val) 2192 phy->speed_downgraded = !!(phy_data & mask); 2193 2194 return ret_val; 2195} 2196 2197/** 2198 * e1000_check_polarity_m88 - Checks the polarity. 2199 * @hw: pointer to the HW structure 2200 * 2201 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 2202 * 2203 * Polarity is determined based on the PHY specific status register. 2204 **/ 2205s32 e1000_check_polarity_m88(struct e1000_hw *hw) 2206{ 2207 struct e1000_phy_info *phy = &hw->phy; 2208 s32 ret_val; 2209 u16 data; 2210 2211 DEBUGFUNC("e1000_check_polarity_m88"); 2212 2213 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data); 2214 2215 if (!ret_val) 2216 phy->cable_polarity = ((data & M88E1000_PSSR_REV_POLARITY) 2217 ? e1000_rev_polarity_reversed 2218 : e1000_rev_polarity_normal); 2219 2220 return ret_val; 2221} 2222 2223/** 2224 * e1000_check_polarity_igp - Checks the polarity. 2225 * @hw: pointer to the HW structure 2226 * 2227 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 2228 * 2229 * Polarity is determined based on the PHY port status register, and the 2230 * current speed (since there is no polarity at 100Mbps). 2231 **/ 2232s32 e1000_check_polarity_igp(struct e1000_hw *hw) 2233{ 2234 struct e1000_phy_info *phy = &hw->phy; 2235 s32 ret_val; 2236 u16 data, offset, mask; 2237 2238 DEBUGFUNC("e1000_check_polarity_igp"); 2239 2240 /* Polarity is determined based on the speed of 2241 * our connection. 2242 */ 2243 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 2244 if (ret_val) 2245 return ret_val; 2246 2247 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 2248 IGP01E1000_PSSR_SPEED_1000MBPS) { 2249 offset = IGP01E1000_PHY_PCS_INIT_REG; 2250 mask = IGP01E1000_PHY_POLARITY_MASK; 2251 } else { 2252 /* This really only applies to 10Mbps since 2253 * there is no polarity for 100Mbps (always 0). 2254 */ 2255 offset = IGP01E1000_PHY_PORT_STATUS; 2256 mask = IGP01E1000_PSSR_POLARITY_REVERSED; 2257 } 2258 2259 ret_val = phy->ops.read_reg(hw, offset, &data); 2260 2261 if (!ret_val) 2262 phy->cable_polarity = ((data & mask) 2263 ? e1000_rev_polarity_reversed 2264 : e1000_rev_polarity_normal); 2265 2266 return ret_val; 2267} 2268 2269/** 2270 * e1000_check_polarity_ife - Check cable polarity for IFE PHY 2271 * @hw: pointer to the HW structure 2272 * 2273 * Polarity is determined on the polarity reversal feature being enabled. 2274 **/ 2275s32 e1000_check_polarity_ife(struct e1000_hw *hw) 2276{ 2277 struct e1000_phy_info *phy = &hw->phy; 2278 s32 ret_val; 2279 u16 phy_data, offset, mask; 2280 2281 DEBUGFUNC("e1000_check_polarity_ife"); 2282 2283 /* Polarity is determined based on the reversal feature being enabled. 2284 */ 2285 if (phy->polarity_correction) { 2286 offset = IFE_PHY_EXTENDED_STATUS_CONTROL; 2287 mask = IFE_PESC_POLARITY_REVERSED; 2288 } else { 2289 offset = IFE_PHY_SPECIAL_CONTROL; 2290 mask = IFE_PSC_FORCE_POLARITY; 2291 } 2292 2293 ret_val = phy->ops.read_reg(hw, offset, &phy_data); 2294 2295 if (!ret_val) 2296 phy->cable_polarity = ((phy_data & mask) 2297 ? e1000_rev_polarity_reversed 2298 : e1000_rev_polarity_normal); 2299 2300 return ret_val; 2301} 2302 2303/** 2304 * e1000_wait_autoneg - Wait for auto-neg completion 2305 * @hw: pointer to the HW structure 2306 * 2307 * Waits for auto-negotiation to complete or for the auto-negotiation time 2308 * limit to expire, which ever happens first. 2309 **/ 2310static s32 e1000_wait_autoneg(struct e1000_hw *hw) 2311{ 2312 s32 ret_val = E1000_SUCCESS; 2313 u16 i, phy_status; 2314 2315 DEBUGFUNC("e1000_wait_autoneg"); 2316 2317 if (!hw->phy.ops.read_reg) 2318 return E1000_SUCCESS; 2319 2320 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */ 2321 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) { 2322 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2323 if (ret_val) 2324 break; 2325 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2326 if (ret_val) 2327 break; 2328 if (phy_status & MII_SR_AUTONEG_COMPLETE) 2329 break; 2330 msec_delay(100); 2331 } 2332 2333 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation 2334 * has completed. 2335 */ 2336 return ret_val; 2337} 2338 2339/** 2340 * e1000_phy_has_link_generic - Polls PHY for link 2341 * @hw: pointer to the HW structure 2342 * @iterations: number of times to poll for link 2343 * @usec_interval: delay between polling attempts 2344 * @success: pointer to whether polling was successful or not 2345 * 2346 * Polls the PHY status register for link, 'iterations' number of times. 2347 **/ 2348s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, 2349 u32 usec_interval, bool *success) 2350{ 2351 s32 ret_val = E1000_SUCCESS; 2352 u16 i, phy_status; 2353 2354 DEBUGFUNC("e1000_phy_has_link_generic"); 2355 2356 if (!hw->phy.ops.read_reg) 2357 return E1000_SUCCESS; 2358 2359 for (i = 0; i < iterations; i++) { 2360 /* Some PHYs require the PHY_STATUS register to be read 2361 * twice due to the link bit being sticky. No harm doing 2362 * it across the board. 2363 */ 2364 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2365 if (ret_val) 2366 /* If the first read fails, another entity may have 2367 * ownership of the resources, wait and try again to 2368 * see if they have relinquished the resources yet. 2369 */ 2370 usec_delay(usec_interval); 2371 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status); 2372 if (ret_val) 2373 break; 2374 if (phy_status & MII_SR_LINK_STATUS) 2375 break; 2376 if (usec_interval >= 1000) 2377 msec_delay_irq(usec_interval/1000); 2378 else 2379 usec_delay(usec_interval); 2380 } 2381 2382 *success = (i < iterations); 2383 2384 return ret_val; 2385} 2386 2387/** 2388 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY 2389 * @hw: pointer to the HW structure 2390 * 2391 * Reads the PHY specific status register to retrieve the cable length 2392 * information. The cable length is determined by averaging the minimum and 2393 * maximum values to get the "average" cable length. The m88 PHY has four 2394 * possible cable length values, which are: 2395 * Register Value Cable Length 2396 * 0 < 50 meters 2397 * 1 50 - 80 meters 2398 * 2 80 - 110 meters 2399 * 3 110 - 140 meters 2400 * 4 > 140 meters 2401 **/ 2402s32 e1000_get_cable_length_m88(struct e1000_hw *hw) 2403{ 2404 struct e1000_phy_info *phy = &hw->phy; 2405 s32 ret_val; 2406 u16 phy_data, index; 2407 2408 DEBUGFUNC("e1000_get_cable_length_m88"); 2409 2410 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 2411 if (ret_val) 2412 return ret_val; 2413 2414 index = ((phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 2415 M88E1000_PSSR_CABLE_LENGTH_SHIFT); 2416 2417 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) 2418 return -E1000_ERR_PHY; 2419 2420 phy->min_cable_length = e1000_m88_cable_length_table[index]; 2421 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; 2422 2423 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 2424 2425 return E1000_SUCCESS; 2426} 2427 2428s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw) 2429{ 2430 struct e1000_phy_info *phy = &hw->phy; 2431 s32 ret_val; 2432 u16 phy_data, phy_data2, is_cm; 2433 u16 index, default_page; 2434 2435 DEBUGFUNC("e1000_get_cable_length_m88_gen2"); 2436 2437 switch (hw->phy.id) { 2438 case I210_I_PHY_ID: 2439 /* Get cable length from PHY Cable Diagnostics Control Reg */ 2440 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) + 2441 (I347AT4_PCDL + phy->addr), 2442 &phy_data); 2443 if (ret_val) 2444 return ret_val; 2445 2446 /* Check if the unit of cable length is meters or cm */ 2447 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) + 2448 I347AT4_PCDC, &phy_data2); 2449 if (ret_val) 2450 return ret_val; 2451 2452 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT); 2453 2454 /* Populate the phy structure with cable length in meters */ 2455 phy->min_cable_length = phy_data / (is_cm ? 100 : 1); 2456 phy->max_cable_length = phy_data / (is_cm ? 100 : 1); 2457 phy->cable_length = phy_data / (is_cm ? 100 : 1); 2458 break; 2459 case M88E1543_E_PHY_ID: 2460 case M88E1512_E_PHY_ID: 2461 case M88E1340M_E_PHY_ID: 2462 case I347AT4_E_PHY_ID: 2463 /* Remember the original page select and set it to 7 */ 2464 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, 2465 &default_page); 2466 if (ret_val) 2467 return ret_val; 2468 2469 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07); 2470 if (ret_val) 2471 return ret_val; 2472 2473 /* Get cable length from PHY Cable Diagnostics Control Reg */ 2474 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr), 2475 &phy_data); 2476 if (ret_val) 2477 return ret_val; 2478 2479 /* Check if the unit of cable length is meters or cm */ 2480 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2); 2481 if (ret_val) 2482 return ret_val; 2483 2484 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT); 2485 2486 /* Populate the phy structure with cable length in meters */ 2487 phy->min_cable_length = phy_data / (is_cm ? 100 : 1); 2488 phy->max_cable_length = phy_data / (is_cm ? 100 : 1); 2489 phy->cable_length = phy_data / (is_cm ? 100 : 1); 2490 2491 /* Reset the page select to its original value */ 2492 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 2493 default_page); 2494 if (ret_val) 2495 return ret_val; 2496 break; 2497 2498 case M88E1112_E_PHY_ID: 2499 /* Remember the original page select and set it to 5 */ 2500 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT, 2501 &default_page); 2502 if (ret_val) 2503 return ret_val; 2504 2505 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05); 2506 if (ret_val) 2507 return ret_val; 2508 2509 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE, 2510 &phy_data); 2511 if (ret_val) 2512 return ret_val; 2513 2514 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >> 2515 M88E1000_PSSR_CABLE_LENGTH_SHIFT; 2516 2517 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) 2518 return -E1000_ERR_PHY; 2519 2520 phy->min_cable_length = e1000_m88_cable_length_table[index]; 2521 phy->max_cable_length = e1000_m88_cable_length_table[index + 1]; 2522 2523 phy->cable_length = (phy->min_cable_length + 2524 phy->max_cable_length) / 2; 2525 2526 /* Reset the page select to its original value */ 2527 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 2528 default_page); 2529 if (ret_val) 2530 return ret_val; 2531 2532 break; 2533 default: 2534 return -E1000_ERR_PHY; 2535 } 2536 2537 return ret_val; 2538} 2539 2540/** 2541 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY 2542 * @hw: pointer to the HW structure 2543 * 2544 * The automatic gain control (agc) normalizes the amplitude of the 2545 * received signal, adjusting for the attenuation produced by the 2546 * cable. By reading the AGC registers, which represent the 2547 * combination of coarse and fine gain value, the value can be put 2548 * into a lookup table to obtain the approximate cable length 2549 * for each channel. 2550 **/ 2551s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw) 2552{ 2553 struct e1000_phy_info *phy = &hw->phy; 2554 s32 ret_val; 2555 u16 phy_data, i, agc_value = 0; 2556 u16 cur_agc_index, max_agc_index = 0; 2557 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1; 2558 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = { 2559 IGP02E1000_PHY_AGC_A, 2560 IGP02E1000_PHY_AGC_B, 2561 IGP02E1000_PHY_AGC_C, 2562 IGP02E1000_PHY_AGC_D 2563 }; 2564 2565 DEBUGFUNC("e1000_get_cable_length_igp_2"); 2566 2567 /* Read the AGC registers for all channels */ 2568 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) { 2569 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data); 2570 if (ret_val) 2571 return ret_val; 2572 2573 /* Getting bits 15:9, which represent the combination of 2574 * coarse and fine gain values. The result is a number 2575 * that can be put into the lookup table to obtain the 2576 * approximate cable length. 2577 */ 2578 cur_agc_index = ((phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) & 2579 IGP02E1000_AGC_LENGTH_MASK); 2580 2581 /* Array index bound check. */ 2582 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) || 2583 (cur_agc_index == 0)) 2584 return -E1000_ERR_PHY; 2585 2586 /* Remove min & max AGC values from calculation. */ 2587 if (e1000_igp_2_cable_length_table[min_agc_index] > 2588 e1000_igp_2_cable_length_table[cur_agc_index]) 2589 min_agc_index = cur_agc_index; 2590 if (e1000_igp_2_cable_length_table[max_agc_index] < 2591 e1000_igp_2_cable_length_table[cur_agc_index]) 2592 max_agc_index = cur_agc_index; 2593 2594 agc_value += e1000_igp_2_cable_length_table[cur_agc_index]; 2595 } 2596 2597 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] + 2598 e1000_igp_2_cable_length_table[max_agc_index]); 2599 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2); 2600 2601 /* Calculate cable length with the error range of +/- 10 meters. */ 2602 phy->min_cable_length = (((agc_value - IGP02E1000_AGC_RANGE) > 0) ? 2603 (agc_value - IGP02E1000_AGC_RANGE) : 0); 2604 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE; 2605 2606 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 2607 2608 return E1000_SUCCESS; 2609} 2610 2611/** 2612 * e1000_get_phy_info_m88 - Retrieve PHY information 2613 * @hw: pointer to the HW structure 2614 * 2615 * Valid for only copper links. Read the PHY status register (sticky read) 2616 * to verify that link is up. Read the PHY special control register to 2617 * determine the polarity and 10base-T extended distance. Read the PHY 2618 * special status register to determine MDI/MDIx and current speed. If 2619 * speed is 1000, then determine cable length, local and remote receiver. 2620 **/ 2621s32 e1000_get_phy_info_m88(struct e1000_hw *hw) 2622{ 2623 struct e1000_phy_info *phy = &hw->phy; 2624 s32 ret_val; 2625 u16 phy_data; 2626 bool link; 2627 2628 DEBUGFUNC("e1000_get_phy_info_m88"); 2629 2630 if (phy->media_type != e1000_media_type_copper) { 2631 DEBUGOUT("Phy info is only valid for copper media\n"); 2632 return -E1000_ERR_CONFIG; 2633 } 2634 2635 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2636 if (ret_val) 2637 return ret_val; 2638 2639 if (!link) { 2640 DEBUGOUT("Phy info is only valid if link is up\n"); 2641 return -E1000_ERR_CONFIG; 2642 } 2643 2644 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data); 2645 if (ret_val) 2646 return ret_val; 2647 2648 phy->polarity_correction = !!(phy_data & 2649 M88E1000_PSCR_POLARITY_REVERSAL); 2650 2651 ret_val = e1000_check_polarity_m88(hw); 2652 if (ret_val) 2653 return ret_val; 2654 2655 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data); 2656 if (ret_val) 2657 return ret_val; 2658 2659 phy->is_mdix = !!(phy_data & M88E1000_PSSR_MDIX); 2660 2661 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) { 2662 ret_val = hw->phy.ops.get_cable_length(hw); 2663 if (ret_val) 2664 return ret_val; 2665 2666 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); 2667 if (ret_val) 2668 return ret_val; 2669 2670 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS) 2671 ? e1000_1000t_rx_status_ok 2672 : e1000_1000t_rx_status_not_ok; 2673 2674 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS) 2675 ? e1000_1000t_rx_status_ok 2676 : e1000_1000t_rx_status_not_ok; 2677 } else { 2678 /* Set values to "undefined" */ 2679 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2680 phy->local_rx = e1000_1000t_rx_status_undefined; 2681 phy->remote_rx = e1000_1000t_rx_status_undefined; 2682 } 2683 2684 return ret_val; 2685} 2686 2687/** 2688 * e1000_get_phy_info_igp - Retrieve igp PHY information 2689 * @hw: pointer to the HW structure 2690 * 2691 * Read PHY status to determine if link is up. If link is up, then 2692 * set/determine 10base-T extended distance and polarity correction. Read 2693 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 2694 * determine on the cable length, local and remote receiver. 2695 **/ 2696s32 e1000_get_phy_info_igp(struct e1000_hw *hw) 2697{ 2698 struct e1000_phy_info *phy = &hw->phy; 2699 s32 ret_val; 2700 u16 data; 2701 bool link; 2702 2703 DEBUGFUNC("e1000_get_phy_info_igp"); 2704 2705 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2706 if (ret_val) 2707 return ret_val; 2708 2709 if (!link) { 2710 DEBUGOUT("Phy info is only valid if link is up\n"); 2711 return -E1000_ERR_CONFIG; 2712 } 2713 2714 phy->polarity_correction = TRUE; 2715 2716 ret_val = e1000_check_polarity_igp(hw); 2717 if (ret_val) 2718 return ret_val; 2719 2720 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data); 2721 if (ret_val) 2722 return ret_val; 2723 2724 phy->is_mdix = !!(data & IGP01E1000_PSSR_MDIX); 2725 2726 if ((data & IGP01E1000_PSSR_SPEED_MASK) == 2727 IGP01E1000_PSSR_SPEED_1000MBPS) { 2728 ret_val = phy->ops.get_cable_length(hw); 2729 if (ret_val) 2730 return ret_val; 2731 2732 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 2733 if (ret_val) 2734 return ret_val; 2735 2736 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 2737 ? e1000_1000t_rx_status_ok 2738 : e1000_1000t_rx_status_not_ok; 2739 2740 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 2741 ? e1000_1000t_rx_status_ok 2742 : e1000_1000t_rx_status_not_ok; 2743 } else { 2744 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2745 phy->local_rx = e1000_1000t_rx_status_undefined; 2746 phy->remote_rx = e1000_1000t_rx_status_undefined; 2747 } 2748 2749 return ret_val; 2750} 2751 2752/** 2753 * e1000_get_phy_info_ife - Retrieves various IFE PHY states 2754 * @hw: pointer to the HW structure 2755 * 2756 * Populates "phy" structure with various feature states. 2757 **/ 2758s32 e1000_get_phy_info_ife(struct e1000_hw *hw) 2759{ 2760 struct e1000_phy_info *phy = &hw->phy; 2761 s32 ret_val; 2762 u16 data; 2763 bool link; 2764 2765 DEBUGFUNC("e1000_get_phy_info_ife"); 2766 2767 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 2768 if (ret_val) 2769 return ret_val; 2770 2771 if (!link) { 2772 DEBUGOUT("Phy info is only valid if link is up\n"); 2773 return -E1000_ERR_CONFIG; 2774 } 2775 2776 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data); 2777 if (ret_val) 2778 return ret_val; 2779 phy->polarity_correction = !(data & IFE_PSC_AUTO_POLARITY_DISABLE); 2780 2781 if (phy->polarity_correction) { 2782 ret_val = e1000_check_polarity_ife(hw); 2783 if (ret_val) 2784 return ret_val; 2785 } else { 2786 /* Polarity is forced */ 2787 phy->cable_polarity = ((data & IFE_PSC_FORCE_POLARITY) 2788 ? e1000_rev_polarity_reversed 2789 : e1000_rev_polarity_normal); 2790 } 2791 2792 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data); 2793 if (ret_val) 2794 return ret_val; 2795 2796 phy->is_mdix = !!(data & IFE_PMC_MDIX_STATUS); 2797 2798 /* The following parameters are undefined for 10/100 operation. */ 2799 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 2800 phy->local_rx = e1000_1000t_rx_status_undefined; 2801 phy->remote_rx = e1000_1000t_rx_status_undefined; 2802 2803 return E1000_SUCCESS; 2804} 2805 2806/** 2807 * e1000_phy_sw_reset_generic - PHY software reset 2808 * @hw: pointer to the HW structure 2809 * 2810 * Does a software reset of the PHY by reading the PHY control register and 2811 * setting/write the control register reset bit to the PHY. 2812 **/ 2813s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw) 2814{ 2815 s32 ret_val; 2816 u16 phy_ctrl; 2817 2818 DEBUGFUNC("e1000_phy_sw_reset_generic"); 2819 2820 if (!hw->phy.ops.read_reg) 2821 return E1000_SUCCESS; 2822 2823 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl); 2824 if (ret_val) 2825 return ret_val; 2826 2827 phy_ctrl |= MII_CR_RESET; 2828 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl); 2829 if (ret_val) 2830 return ret_val; 2831 2832 usec_delay(1); 2833 2834 return ret_val; 2835} 2836 2837/** 2838 * e1000_phy_hw_reset_generic - PHY hardware reset 2839 * @hw: pointer to the HW structure 2840 * 2841 * Verify the reset block is not blocking us from resetting. Acquire 2842 * semaphore (if necessary) and read/set/write the device control reset 2843 * bit in the PHY. Wait the appropriate delay time for the device to 2844 * reset and release the semaphore (if necessary). 2845 **/ 2846s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw) 2847{ 2848 struct e1000_phy_info *phy = &hw->phy; 2849 s32 ret_val; 2850 u32 ctrl; 2851 2852 DEBUGFUNC("e1000_phy_hw_reset_generic"); 2853 2854 if (phy->ops.check_reset_block) { 2855 ret_val = phy->ops.check_reset_block(hw); 2856 if (ret_val) 2857 return E1000_SUCCESS; 2858 } 2859 2860 ret_val = phy->ops.acquire(hw); 2861 if (ret_val) 2862 return ret_val; 2863 2864 ctrl = E1000_READ_REG(hw, E1000_CTRL); 2865 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST); 2866 E1000_WRITE_FLUSH(hw); 2867 2868 usec_delay(phy->reset_delay_us); 2869 2870 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 2871 E1000_WRITE_FLUSH(hw); 2872 2873 usec_delay(150); 2874 2875 phy->ops.release(hw); 2876 2877 return phy->ops.get_cfg_done(hw); 2878} 2879 2880/** 2881 * e1000_get_cfg_done_generic - Generic configuration done 2882 * @hw: pointer to the HW structure 2883 * 2884 * Generic function to wait 10 milli-seconds for configuration to complete 2885 * and return success. 2886 **/ 2887s32 e1000_get_cfg_done_generic(struct e1000_hw E1000_UNUSEDARG *hw) 2888{ 2889 DEBUGFUNC("e1000_get_cfg_done_generic"); 2890 2891 msec_delay_irq(10); 2892 2893 return E1000_SUCCESS; 2894} 2895 2896/** 2897 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY 2898 * @hw: pointer to the HW structure 2899 * 2900 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present. 2901 **/ 2902s32 e1000_phy_init_script_igp3(struct e1000_hw *hw) 2903{ 2904 DEBUGOUT("Running IGP 3 PHY init script\n"); 2905 2906 /* PHY init IGP 3 */ 2907 /* Enable rise/fall, 10-mode work in class-A */ 2908 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018); 2909 /* Remove all caps from Replica path filter */ 2910 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000); 2911 /* Bias trimming for ADC, AFE and Driver (Default) */ 2912 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24); 2913 /* Increase Hybrid poly bias */ 2914 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0); 2915 /* Add 4% to Tx amplitude in Gig mode */ 2916 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0); 2917 /* Disable trimming (TTT) */ 2918 hw->phy.ops.write_reg(hw, 0x2011, 0x0000); 2919 /* Poly DC correction to 94.6% + 2% for all channels */ 2920 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A); 2921 /* ABS DC correction to 95.9% */ 2922 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3); 2923 /* BG temp curve trim */ 2924 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE); 2925 /* Increasing ADC OPAMP stage 1 currents to max */ 2926 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4); 2927 /* Force 1000 ( required for enabling PHY regs configuration) */ 2928 hw->phy.ops.write_reg(hw, 0x0000, 0x0140); 2929 /* Set upd_freq to 6 */ 2930 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606); 2931 /* Disable NPDFE */ 2932 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814); 2933 /* Disable adaptive fixed FFE (Default) */ 2934 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A); 2935 /* Enable FFE hysteresis */ 2936 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067); 2937 /* Fixed FFE for short cable lengths */ 2938 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065); 2939 /* Fixed FFE for medium cable lengths */ 2940 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A); 2941 /* Fixed FFE for long cable lengths */ 2942 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A); 2943 /* Enable Adaptive Clip Threshold */ 2944 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0); 2945 /* AHT reset limit to 1 */ 2946 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF); 2947 /* Set AHT master delay to 127 msec */ 2948 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC); 2949 /* Set scan bits for AHT */ 2950 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF); 2951 /* Set AHT Preset bits */ 2952 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210); 2953 /* Change integ_factor of channel A to 3 */ 2954 hw->phy.ops.write_reg(hw, 0x1895, 0x0003); 2955 /* Change prop_factor of channels BCD to 8 */ 2956 hw->phy.ops.write_reg(hw, 0x1796, 0x0008); 2957 /* Change cg_icount + enable integbp for channels BCD */ 2958 hw->phy.ops.write_reg(hw, 0x1798, 0xD008); 2959 /* Change cg_icount + enable integbp + change prop_factor_master 2960 * to 8 for channel A 2961 */ 2962 hw->phy.ops.write_reg(hw, 0x1898, 0xD918); 2963 /* Disable AHT in Slave mode on channel A */ 2964 hw->phy.ops.write_reg(hw, 0x187A, 0x0800); 2965 /* Enable LPLU and disable AN to 1000 in non-D0a states, 2966 * Enable SPD+B2B 2967 */ 2968 hw->phy.ops.write_reg(hw, 0x0019, 0x008D); 2969 /* Enable restart AN on an1000_dis change */ 2970 hw->phy.ops.write_reg(hw, 0x001B, 0x2080); 2971 /* Enable wh_fifo read clock in 10/100 modes */ 2972 hw->phy.ops.write_reg(hw, 0x0014, 0x0045); 2973 /* Restart AN, Speed selection is 1000 */ 2974 hw->phy.ops.write_reg(hw, 0x0000, 0x1340); 2975 2976 return E1000_SUCCESS; 2977} 2978 2979/** 2980 * e1000_get_phy_type_from_id - Get PHY type from id 2981 * @phy_id: phy_id read from the phy 2982 * 2983 * Returns the phy type from the id. 2984 **/ 2985enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id) 2986{ 2987 enum e1000_phy_type phy_type = e1000_phy_unknown; 2988 2989 switch (phy_id) { 2990 case M88E1000_I_PHY_ID: 2991 case M88E1000_E_PHY_ID: 2992 case M88E1111_I_PHY_ID: 2993 case M88E1011_I_PHY_ID: 2994 case M88E1543_E_PHY_ID: 2995 case M88E1512_E_PHY_ID: 2996 case I347AT4_E_PHY_ID: 2997 case M88E1112_E_PHY_ID: 2998 case M88E1340M_E_PHY_ID: 2999 phy_type = e1000_phy_m88; 3000 break; 3001 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */ 3002 phy_type = e1000_phy_igp_2; 3003 break; 3004 case GG82563_E_PHY_ID: 3005 phy_type = e1000_phy_gg82563; 3006 break; 3007 case IGP03E1000_E_PHY_ID: 3008 phy_type = e1000_phy_igp_3; 3009 break; 3010 case IFE_E_PHY_ID: 3011 case IFE_PLUS_E_PHY_ID: 3012 case IFE_C_E_PHY_ID: 3013 phy_type = e1000_phy_ife; 3014 break; 3015 case BME1000_E_PHY_ID: 3016 case BME1000_E_PHY_ID_R2: 3017 phy_type = e1000_phy_bm; 3018 break; 3019 case I82578_E_PHY_ID: 3020 phy_type = e1000_phy_82578; 3021 break; 3022 case I82577_E_PHY_ID: 3023 phy_type = e1000_phy_82577; 3024 break; 3025 case I82579_E_PHY_ID: 3026 phy_type = e1000_phy_82579; 3027 break; 3028 case I217_E_PHY_ID: 3029 phy_type = e1000_phy_i217; 3030 break; 3031 case I82580_I_PHY_ID: 3032 phy_type = e1000_phy_82580; 3033 break; 3034 case I210_I_PHY_ID: 3035 phy_type = e1000_phy_i210; 3036 break; 3037 default: 3038 phy_type = e1000_phy_unknown; 3039 break; 3040 } 3041 return phy_type; 3042} 3043 3044/** 3045 * e1000_determine_phy_address - Determines PHY address. 3046 * @hw: pointer to the HW structure 3047 * 3048 * This uses a trial and error method to loop through possible PHY 3049 * addresses. It tests each by reading the PHY ID registers and 3050 * checking for a match. 3051 **/ 3052s32 e1000_determine_phy_address(struct e1000_hw *hw) 3053{ 3054 u32 phy_addr = 0; 3055 u32 i; 3056 enum e1000_phy_type phy_type = e1000_phy_unknown; 3057 3058 hw->phy.id = phy_type; 3059 3060 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) { 3061 hw->phy.addr = phy_addr; 3062 i = 0; 3063 3064 do { 3065 e1000_get_phy_id(hw); 3066 phy_type = e1000_get_phy_type_from_id(hw->phy.id); 3067 3068 /* If phy_type is valid, break - we found our 3069 * PHY address 3070 */ 3071 if (phy_type != e1000_phy_unknown) 3072 return E1000_SUCCESS; 3073 3074 msec_delay(1); 3075 i++; 3076 } while (i < 10); 3077 } 3078 3079 return -E1000_ERR_PHY_TYPE; 3080} 3081 3082/** 3083 * e1000_get_phy_addr_for_bm_page - Retrieve PHY page address 3084 * @page: page to access 3085 * 3086 * Returns the phy address for the page requested. 3087 **/ 3088static u32 e1000_get_phy_addr_for_bm_page(u32 page, u32 reg) 3089{ 3090 u32 phy_addr = 2; 3091 3092 if ((page >= 768) || (page == 0 && reg == 25) || (reg == 31)) 3093 phy_addr = 1; 3094 3095 return phy_addr; 3096} 3097 3098/** 3099 * e1000_write_phy_reg_bm - Write BM PHY register 3100 * @hw: pointer to the HW structure 3101 * @offset: register offset to write to 3102 * @data: data to write at register offset 3103 * 3104 * Acquires semaphore, if necessary, then writes the data to PHY register 3105 * at the offset. Release any acquired semaphores before exiting. 3106 **/ 3107s32 e1000_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data) 3108{ 3109 s32 ret_val; 3110 u32 page = offset >> IGP_PAGE_SHIFT; 3111 3112 DEBUGFUNC("e1000_write_phy_reg_bm"); 3113 3114 ret_val = hw->phy.ops.acquire(hw); 3115 if (ret_val) 3116 return ret_val; 3117 3118 /* Page 800 works differently than the rest so it has its own func */ 3119 if (page == BM_WUC_PAGE) { 3120 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 3121 FALSE, FALSE); 3122 goto release; 3123 } 3124 3125 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 3126 3127 if (offset > MAX_PHY_MULTI_PAGE_REG) { 3128 u32 page_shift, page_select; 3129 3130 /* Page select is register 31 for phy address 1 and 22 for 3131 * phy address 2 and 3. Page select is shifted only for 3132 * phy address 1. 3133 */ 3134 if (hw->phy.addr == 1) { 3135 page_shift = IGP_PAGE_SHIFT; 3136 page_select = IGP01E1000_PHY_PAGE_SELECT; 3137 } else { 3138 page_shift = 0; 3139 page_select = BM_PHY_PAGE_SELECT; 3140 } 3141 3142 /* Page is shifted left, PHY expects (page x 32) */ 3143 ret_val = e1000_write_phy_reg_mdic(hw, page_select, 3144 (page << page_shift)); 3145 if (ret_val) 3146 goto release; 3147 } 3148 3149 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 3150 data); 3151 3152release: 3153 hw->phy.ops.release(hw); 3154 return ret_val; 3155} 3156 3157/** 3158 * e1000_read_phy_reg_bm - Read BM PHY register 3159 * @hw: pointer to the HW structure 3160 * @offset: register offset to be read 3161 * @data: pointer to the read data 3162 * 3163 * Acquires semaphore, if necessary, then reads the PHY register at offset 3164 * and storing the retrieved information in data. Release any acquired 3165 * semaphores before exiting. 3166 **/ 3167s32 e1000_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data) 3168{ 3169 s32 ret_val; 3170 u32 page = offset >> IGP_PAGE_SHIFT; 3171 3172 DEBUGFUNC("e1000_read_phy_reg_bm"); 3173 3174 ret_val = hw->phy.ops.acquire(hw); 3175 if (ret_val) 3176 return ret_val; 3177 3178 /* Page 800 works differently than the rest so it has its own func */ 3179 if (page == BM_WUC_PAGE) { 3180 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 3181 TRUE, FALSE); 3182 goto release; 3183 } 3184 3185 hw->phy.addr = e1000_get_phy_addr_for_bm_page(page, offset); 3186 3187 if (offset > MAX_PHY_MULTI_PAGE_REG) { 3188 u32 page_shift, page_select; 3189 3190 /* Page select is register 31 for phy address 1 and 22 for 3191 * phy address 2 and 3. Page select is shifted only for 3192 * phy address 1. 3193 */ 3194 if (hw->phy.addr == 1) { 3195 page_shift = IGP_PAGE_SHIFT; 3196 page_select = IGP01E1000_PHY_PAGE_SELECT; 3197 } else { 3198 page_shift = 0; 3199 page_select = BM_PHY_PAGE_SELECT; 3200 } 3201 3202 /* Page is shifted left, PHY expects (page x 32) */ 3203 ret_val = e1000_write_phy_reg_mdic(hw, page_select, 3204 (page << page_shift)); 3205 if (ret_val) 3206 goto release; 3207 } 3208 3209 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 3210 data); 3211release: 3212 hw->phy.ops.release(hw); 3213 return ret_val; 3214} 3215 3216/** 3217 * e1000_read_phy_reg_bm2 - Read BM PHY register 3218 * @hw: pointer to the HW structure 3219 * @offset: register offset to be read 3220 * @data: pointer to the read data 3221 * 3222 * Acquires semaphore, if necessary, then reads the PHY register at offset 3223 * and storing the retrieved information in data. Release any acquired 3224 * semaphores before exiting. 3225 **/ 3226s32 e1000_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data) 3227{ 3228 s32 ret_val; 3229 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 3230 3231 DEBUGFUNC("e1000_read_phy_reg_bm2"); 3232 3233 ret_val = hw->phy.ops.acquire(hw); 3234 if (ret_val) 3235 return ret_val; 3236 3237 /* Page 800 works differently than the rest so it has its own func */ 3238 if (page == BM_WUC_PAGE) { 3239 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 3240 TRUE, FALSE); 3241 goto release; 3242 } 3243 3244 hw->phy.addr = 1; 3245 3246 if (offset > MAX_PHY_MULTI_PAGE_REG) { 3247 /* Page is shifted left, PHY expects (page x 32) */ 3248 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, 3249 page); 3250 3251 if (ret_val) 3252 goto release; 3253 } 3254 3255 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 3256 data); 3257release: 3258 hw->phy.ops.release(hw); 3259 return ret_val; 3260} 3261 3262/** 3263 * e1000_write_phy_reg_bm2 - Write BM PHY register 3264 * @hw: pointer to the HW structure 3265 * @offset: register offset to write to 3266 * @data: data to write at register offset 3267 * 3268 * Acquires semaphore, if necessary, then writes the data to PHY register 3269 * at the offset. Release any acquired semaphores before exiting. 3270 **/ 3271s32 e1000_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data) 3272{ 3273 s32 ret_val; 3274 u16 page = (u16)(offset >> IGP_PAGE_SHIFT); 3275 3276 DEBUGFUNC("e1000_write_phy_reg_bm2"); 3277 3278 ret_val = hw->phy.ops.acquire(hw); 3279 if (ret_val) 3280 return ret_val; 3281 3282 /* Page 800 works differently than the rest so it has its own func */ 3283 if (page == BM_WUC_PAGE) { 3284 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 3285 FALSE, FALSE); 3286 goto release; 3287 } 3288 3289 hw->phy.addr = 1; 3290 3291 if (offset > MAX_PHY_MULTI_PAGE_REG) { 3292 /* Page is shifted left, PHY expects (page x 32) */ 3293 ret_val = e1000_write_phy_reg_mdic(hw, BM_PHY_PAGE_SELECT, 3294 page); 3295 3296 if (ret_val) 3297 goto release; 3298 } 3299 3300 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, 3301 data); 3302 3303release: 3304 hw->phy.ops.release(hw); 3305 return ret_val; 3306} 3307 3308/** 3309 * e1000_enable_phy_wakeup_reg_access_bm - enable access to BM wakeup registers 3310 * @hw: pointer to the HW structure 3311 * @phy_reg: pointer to store original contents of BM_WUC_ENABLE_REG 3312 * 3313 * Assumes semaphore already acquired and phy_reg points to a valid memory 3314 * address to store contents of the BM_WUC_ENABLE_REG register. 3315 **/ 3316s32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) 3317{ 3318 s32 ret_val; 3319 u16 temp; 3320 3321 DEBUGFUNC("e1000_enable_phy_wakeup_reg_access_bm"); 3322 3323 if (!phy_reg) 3324 return -E1000_ERR_PARAM; 3325 3326 /* All page select, port ctrl and wakeup registers use phy address 1 */ 3327 hw->phy.addr = 1; 3328 3329 /* Select Port Control Registers page */ 3330 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); 3331 if (ret_val) { 3332 DEBUGOUT("Could not set Port Control page\n"); 3333 return ret_val; 3334 } 3335 3336 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, phy_reg); 3337 if (ret_val) { 3338 DEBUGOUT2("Could not read PHY register %d.%d\n", 3339 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); 3340 return ret_val; 3341 } 3342 3343 /* Enable both PHY wakeup mode and Wakeup register page writes. 3344 * Prevent a power state change by disabling ME and Host PHY wakeup. 3345 */ 3346 temp = *phy_reg; 3347 temp |= BM_WUC_ENABLE_BIT; 3348 temp &= ~(BM_WUC_ME_WU_BIT | BM_WUC_HOST_WU_BIT); 3349 3350 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, temp); 3351 if (ret_val) { 3352 DEBUGOUT2("Could not write PHY register %d.%d\n", 3353 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); 3354 return ret_val; 3355 } 3356 3357 /* Select Host Wakeup Registers page - caller now able to write 3358 * registers on the Wakeup registers page 3359 */ 3360 return e1000_set_page_igp(hw, (BM_WUC_PAGE << IGP_PAGE_SHIFT)); 3361} 3362 3363/** 3364 * e1000_disable_phy_wakeup_reg_access_bm - disable access to BM wakeup regs 3365 * @hw: pointer to the HW structure 3366 * @phy_reg: pointer to original contents of BM_WUC_ENABLE_REG 3367 * 3368 * Restore BM_WUC_ENABLE_REG to its original value. 3369 * 3370 * Assumes semaphore already acquired and *phy_reg is the contents of the 3371 * BM_WUC_ENABLE_REG before register(s) on BM_WUC_PAGE were accessed by 3372 * caller. 3373 **/ 3374s32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg) 3375{ 3376 s32 ret_val; 3377 3378 DEBUGFUNC("e1000_disable_phy_wakeup_reg_access_bm"); 3379 3380 if (!phy_reg) 3381 return -E1000_ERR_PARAM; 3382 3383 /* Select Port Control Registers page */ 3384 ret_val = e1000_set_page_igp(hw, (BM_PORT_CTRL_PAGE << IGP_PAGE_SHIFT)); 3385 if (ret_val) { 3386 DEBUGOUT("Could not set Port Control page\n"); 3387 return ret_val; 3388 } 3389 3390 /* Restore 769.17 to its original value */ 3391 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ENABLE_REG, *phy_reg); 3392 if (ret_val) 3393 DEBUGOUT2("Could not restore PHY register %d.%d\n", 3394 BM_PORT_CTRL_PAGE, BM_WUC_ENABLE_REG); 3395 3396 return ret_val; 3397} 3398 3399/** 3400 * e1000_access_phy_wakeup_reg_bm - Read/write BM PHY wakeup register 3401 * @hw: pointer to the HW structure 3402 * @offset: register offset to be read or written 3403 * @data: pointer to the data to read or write 3404 * @read: determines if operation is read or write 3405 * @page_set: BM_WUC_PAGE already set and access enabled 3406 * 3407 * Read the PHY register at offset and store the retrieved information in 3408 * data, or write data to PHY register at offset. Note the procedure to 3409 * access the PHY wakeup registers is different than reading the other PHY 3410 * registers. It works as such: 3411 * 1) Set 769.17.2 (page 769, register 17, bit 2) = 1 3412 * 2) Set page to 800 for host (801 if we were manageability) 3413 * 3) Write the address using the address opcode (0x11) 3414 * 4) Read or write the data using the data opcode (0x12) 3415 * 5) Restore 769.17.2 to its original value 3416 * 3417 * Steps 1 and 2 are done by e1000_enable_phy_wakeup_reg_access_bm() and 3418 * step 5 is done by e1000_disable_phy_wakeup_reg_access_bm(). 3419 * 3420 * Assumes semaphore is already acquired. When page_set==TRUE, assumes 3421 * the PHY page is set to BM_WUC_PAGE (i.e. a function in the call stack 3422 * is responsible for calls to e1000_[enable|disable]_phy_wakeup_reg_bm()). 3423 **/ 3424static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset, 3425 u16 *data, bool read, bool page_set) 3426{ 3427 s32 ret_val; 3428 u16 reg = BM_PHY_REG_NUM(offset); 3429 u16 page = BM_PHY_REG_PAGE(offset); 3430 u16 phy_reg = 0; 3431 3432 DEBUGFUNC("e1000_access_phy_wakeup_reg_bm"); 3433 3434 /* Gig must be disabled for MDIO accesses to Host Wakeup reg page */ 3435 if ((hw->mac.type == e1000_pchlan) && 3436 (!(E1000_READ_REG(hw, E1000_PHY_CTRL) & E1000_PHY_CTRL_GBE_DISABLE))) 3437 DEBUGOUT1("Attempting to access page %d while gig enabled.\n", 3438 page); 3439 3440 if (!page_set) { 3441 /* Enable access to PHY wakeup registers */ 3442 ret_val = e1000_enable_phy_wakeup_reg_access_bm(hw, &phy_reg); 3443 if (ret_val) { 3444 DEBUGOUT("Could not enable PHY wakeup reg access\n"); 3445 return ret_val; 3446 } 3447 } 3448 3449 DEBUGOUT2("Accessing PHY page %d reg 0x%x\n", page, reg); 3450 3451 /* Write the Wakeup register page offset value using opcode 0x11 */ 3452 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_ADDRESS_OPCODE, reg); 3453 if (ret_val) { 3454 DEBUGOUT1("Could not write address opcode to page %d\n", page); 3455 return ret_val; 3456 } 3457 3458 if (read) { 3459 /* Read the Wakeup register page value using opcode 0x12 */ 3460 ret_val = e1000_read_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 3461 data); 3462 } else { 3463 /* Write the Wakeup register page value using opcode 0x12 */ 3464 ret_val = e1000_write_phy_reg_mdic(hw, BM_WUC_DATA_OPCODE, 3465 *data); 3466 } 3467 3468 if (ret_val) { 3469 DEBUGOUT2("Could not access PHY reg %d.%d\n", page, reg); 3470 return ret_val; 3471 } 3472 3473 if (!page_set) 3474 ret_val = e1000_disable_phy_wakeup_reg_access_bm(hw, &phy_reg); 3475 3476 return ret_val; 3477} 3478 3479/** 3480 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down 3481 * @hw: pointer to the HW structure 3482 * 3483 * In the case of a PHY power down to save power, or to turn off link during a 3484 * driver unload, or wake on lan is not enabled, restore the link to previous 3485 * settings. 3486 **/ 3487void e1000_power_up_phy_copper(struct e1000_hw *hw) 3488{ 3489 u16 mii_reg = 0; 3490 u16 power_reg = 0; 3491 3492 /* The PHY will retain its settings across a power down/up cycle */ 3493 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 3494 mii_reg &= ~MII_CR_POWER_DOWN; 3495 if (hw->phy.type == e1000_phy_i210) { 3496 hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg); 3497 power_reg &= ~GS40G_CS_POWER_DOWN; 3498 hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg); 3499 } 3500 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 3501} 3502 3503/** 3504 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down 3505 * @hw: pointer to the HW structure 3506 * 3507 * In the case of a PHY power down to save power, or to turn off link during a 3508 * driver unload, or wake on lan is not enabled, restore the link to previous 3509 * settings. 3510 **/ 3511void e1000_power_down_phy_copper(struct e1000_hw *hw) 3512{ 3513 u16 mii_reg = 0; 3514 u16 power_reg = 0; 3515 3516 /* The PHY will retain its settings across a power down/up cycle */ 3517 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg); 3518 mii_reg |= MII_CR_POWER_DOWN; 3519 /* i210 Phy requires an additional bit for power up/down */ 3520 if (hw->phy.type == e1000_phy_i210) { 3521 hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg); 3522 power_reg |= GS40G_CS_POWER_DOWN; 3523 hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg); 3524 } 3525 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg); 3526 msec_delay(1); 3527} 3528 3529/** 3530 * __e1000_read_phy_reg_hv - Read HV PHY register 3531 * @hw: pointer to the HW structure 3532 * @offset: register offset to be read 3533 * @data: pointer to the read data 3534 * @locked: semaphore has already been acquired or not 3535 * 3536 * Acquires semaphore, if necessary, then reads the PHY register at offset 3537 * and stores the retrieved information in data. Release any acquired 3538 * semaphore before exiting. 3539 **/ 3540static s32 __e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data, 3541 bool locked, bool page_set) 3542{ 3543 s32 ret_val; 3544 u16 page = BM_PHY_REG_PAGE(offset); 3545 u16 reg = BM_PHY_REG_NUM(offset); 3546 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); 3547 3548 DEBUGFUNC("__e1000_read_phy_reg_hv"); 3549 3550 if (!locked) { 3551 ret_val = hw->phy.ops.acquire(hw); 3552 if (ret_val) 3553 return ret_val; 3554 } 3555 3556 /* Page 800 works differently than the rest so it has its own func */ 3557 if (page == BM_WUC_PAGE) { 3558 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, data, 3559 TRUE, page_set); 3560 goto out; 3561 } 3562 3563 if (page > 0 && page < HV_INTC_FC_PAGE_START) { 3564 ret_val = e1000_access_phy_debug_regs_hv(hw, offset, 3565 data, TRUE); 3566 goto out; 3567 } 3568 3569 if (!page_set) { 3570 if (page == HV_INTC_FC_PAGE_START) 3571 page = 0; 3572 3573 if (reg > MAX_PHY_MULTI_PAGE_REG) { 3574 /* Page is shifted left, PHY expects (page x 32) */ 3575 ret_val = e1000_set_page_igp(hw, 3576 (page << IGP_PAGE_SHIFT)); 3577 3578 hw->phy.addr = phy_addr; 3579 3580 if (ret_val) 3581 goto out; 3582 } 3583 } 3584 3585 DEBUGOUT3("reading PHY page %d (or 0x%x shifted) reg 0x%x\n", page, 3586 page << IGP_PAGE_SHIFT, reg); 3587 3588 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, 3589 data); 3590out: 3591 if (!locked) 3592 hw->phy.ops.release(hw); 3593 3594 return ret_val; 3595} 3596 3597/** 3598 * e1000_read_phy_reg_hv - Read HV PHY register 3599 * @hw: pointer to the HW structure 3600 * @offset: register offset to be read 3601 * @data: pointer to the read data 3602 * 3603 * Acquires semaphore then reads the PHY register at offset and stores 3604 * the retrieved information in data. Release the acquired semaphore 3605 * before exiting. 3606 **/ 3607s32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data) 3608{ 3609 return __e1000_read_phy_reg_hv(hw, offset, data, FALSE, FALSE); 3610} 3611 3612/** 3613 * e1000_read_phy_reg_hv_locked - Read HV PHY register 3614 * @hw: pointer to the HW structure 3615 * @offset: register offset to be read 3616 * @data: pointer to the read data 3617 * 3618 * Reads the PHY register at offset and stores the retrieved information 3619 * in data. Assumes semaphore already acquired. 3620 **/ 3621s32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data) 3622{ 3623 return __e1000_read_phy_reg_hv(hw, offset, data, TRUE, FALSE); 3624} 3625 3626/** 3627 * e1000_read_phy_reg_page_hv - Read HV PHY register 3628 * @hw: pointer to the HW structure 3629 * @offset: register offset to write to 3630 * @data: data to write at register offset 3631 * 3632 * Reads the PHY register at offset and stores the retrieved information 3633 * in data. Assumes semaphore already acquired and page already set. 3634 **/ 3635s32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data) 3636{ 3637 return __e1000_read_phy_reg_hv(hw, offset, data, TRUE, true); 3638} 3639 3640/** 3641 * __e1000_write_phy_reg_hv - Write HV PHY register 3642 * @hw: pointer to the HW structure 3643 * @offset: register offset to write to 3644 * @data: data to write at register offset 3645 * @locked: semaphore has already been acquired or not 3646 * 3647 * Acquires semaphore, if necessary, then writes the data to PHY register 3648 * at the offset. Release any acquired semaphores before exiting. 3649 **/ 3650static s32 __e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data, 3651 bool locked, bool page_set) 3652{ 3653 s32 ret_val; 3654 u16 page = BM_PHY_REG_PAGE(offset); 3655 u16 reg = BM_PHY_REG_NUM(offset); 3656 u32 phy_addr = hw->phy.addr = e1000_get_phy_addr_for_hv_page(page); 3657 3658 DEBUGFUNC("__e1000_write_phy_reg_hv"); 3659 3660 if (!locked) { 3661 ret_val = hw->phy.ops.acquire(hw); 3662 if (ret_val) 3663 return ret_val; 3664 } 3665 3666 /* Page 800 works differently than the rest so it has its own func */ 3667 if (page == BM_WUC_PAGE) { 3668 ret_val = e1000_access_phy_wakeup_reg_bm(hw, offset, &data, 3669 FALSE, page_set); 3670 goto out; 3671 } 3672 3673 if (page > 0 && page < HV_INTC_FC_PAGE_START) { 3674 ret_val = e1000_access_phy_debug_regs_hv(hw, offset, 3675 &data, FALSE); 3676 goto out; 3677 } 3678 3679 if (!page_set) { 3680 if (page == HV_INTC_FC_PAGE_START) 3681 page = 0; 3682 3683 /* Workaround MDIO accesses being disabled after entering IEEE 3684 * Power Down (when bit 11 of the PHY Control register is set) 3685 */ 3686 if ((hw->phy.type == e1000_phy_82578) && 3687 (hw->phy.revision >= 1) && 3688 (hw->phy.addr == 2) && 3689 !(MAX_PHY_REG_ADDRESS & reg) && 3690 (data & (1 << 11))) { 3691 u16 data2 = 0x7EFF; 3692 ret_val = e1000_access_phy_debug_regs_hv(hw, 3693 (1 << 6) | 0x3, 3694 &data2, FALSE); 3695 if (ret_val) 3696 goto out; 3697 } 3698 3699 if (reg > MAX_PHY_MULTI_PAGE_REG) { 3700 /* Page is shifted left, PHY expects (page x 32) */ 3701 ret_val = e1000_set_page_igp(hw, 3702 (page << IGP_PAGE_SHIFT)); 3703 3704 hw->phy.addr = phy_addr; 3705 3706 if (ret_val) 3707 goto out; 3708 } 3709 } 3710 3711 DEBUGOUT3("writing PHY page %d (or 0x%x shifted) reg 0x%x\n", page, 3712 page << IGP_PAGE_SHIFT, reg); 3713 3714 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & reg, 3715 data); 3716 3717out: 3718 if (!locked) 3719 hw->phy.ops.release(hw); 3720 3721 return ret_val; 3722} 3723 3724/** 3725 * e1000_write_phy_reg_hv - Write HV PHY register 3726 * @hw: pointer to the HW structure 3727 * @offset: register offset to write to 3728 * @data: data to write at register offset 3729 * 3730 * Acquires semaphore then writes the data to PHY register at the offset. 3731 * Release the acquired semaphores before exiting. 3732 **/ 3733s32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data) 3734{ 3735 return __e1000_write_phy_reg_hv(hw, offset, data, FALSE, FALSE); 3736} 3737 3738/** 3739 * e1000_write_phy_reg_hv_locked - Write HV PHY register 3740 * @hw: pointer to the HW structure 3741 * @offset: register offset to write to 3742 * @data: data to write at register offset 3743 * 3744 * Writes the data to PHY register at the offset. Assumes semaphore 3745 * already acquired. 3746 **/ 3747s32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data) 3748{ 3749 return __e1000_write_phy_reg_hv(hw, offset, data, TRUE, FALSE); 3750} 3751 3752/** 3753 * e1000_write_phy_reg_page_hv - Write HV PHY register 3754 * @hw: pointer to the HW structure 3755 * @offset: register offset to write to 3756 * @data: data to write at register offset 3757 * 3758 * Writes the data to PHY register at the offset. Assumes semaphore 3759 * already acquired and page already set. 3760 **/ 3761s32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data) 3762{ 3763 return __e1000_write_phy_reg_hv(hw, offset, data, TRUE, true); 3764} 3765 3766/** 3767 * e1000_get_phy_addr_for_hv_page - Get PHY adrress based on page 3768 * @page: page to be accessed 3769 **/ 3770static u32 e1000_get_phy_addr_for_hv_page(u32 page) 3771{ 3772 u32 phy_addr = 2; 3773 3774 if (page >= HV_INTC_FC_PAGE_START) 3775 phy_addr = 1; 3776 3777 return phy_addr; 3778} 3779 3780/** 3781 * e1000_access_phy_debug_regs_hv - Read HV PHY vendor specific high registers 3782 * @hw: pointer to the HW structure 3783 * @offset: register offset to be read or written 3784 * @data: pointer to the data to be read or written 3785 * @read: determines if operation is read or write 3786 * 3787 * Reads the PHY register at offset and stores the retreived information 3788 * in data. Assumes semaphore already acquired. Note that the procedure 3789 * to access these regs uses the address port and data port to read/write. 3790 * These accesses done with PHY address 2 and without using pages. 3791 **/ 3792static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset, 3793 u16 *data, bool read) 3794{ 3795 s32 ret_val; 3796 u32 addr_reg; 3797 u32 data_reg; 3798 3799 DEBUGFUNC("e1000_access_phy_debug_regs_hv"); 3800 3801 /* This takes care of the difference with desktop vs mobile phy */ 3802 addr_reg = ((hw->phy.type == e1000_phy_82578) ? 3803 I82578_ADDR_REG : I82577_ADDR_REG); 3804 data_reg = addr_reg + 1; 3805 3806 /* All operations in this function are phy address 2 */ 3807 hw->phy.addr = 2; 3808 3809 /* masking with 0x3F to remove the page from offset */ 3810 ret_val = e1000_write_phy_reg_mdic(hw, addr_reg, (u16)offset & 0x3F); 3811 if (ret_val) { 3812 DEBUGOUT("Could not write the Address Offset port register\n"); 3813 return ret_val; 3814 } 3815 3816 /* Read or write the data value next */ 3817 if (read) 3818 ret_val = e1000_read_phy_reg_mdic(hw, data_reg, data); 3819 else 3820 ret_val = e1000_write_phy_reg_mdic(hw, data_reg, *data); 3821 3822 if (ret_val) 3823 DEBUGOUT("Could not access the Data port register\n"); 3824 3825 return ret_val; 3826} 3827 3828/** 3829 * e1000_link_stall_workaround_hv - Si workaround 3830 * @hw: pointer to the HW structure 3831 * 3832 * This function works around a Si bug where the link partner can get 3833 * a link up indication before the PHY does. If small packets are sent 3834 * by the link partner they can be placed in the packet buffer without 3835 * being properly accounted for by the PHY and will stall preventing 3836 * further packets from being received. The workaround is to clear the 3837 * packet buffer after the PHY detects link up. 3838 **/ 3839s32 e1000_link_stall_workaround_hv(struct e1000_hw *hw) 3840{ 3841 s32 ret_val = E1000_SUCCESS; 3842 u16 data; 3843 3844 DEBUGFUNC("e1000_link_stall_workaround_hv"); 3845 3846 if (hw->phy.type != e1000_phy_82578) 3847 return E1000_SUCCESS; 3848 3849 /* Do not apply workaround if in PHY loopback bit 14 set */ 3850 hw->phy.ops.read_reg(hw, PHY_CONTROL, &data); 3851 if (data & PHY_CONTROL_LB) 3852 return E1000_SUCCESS; 3853 3854 /* check if link is up and at 1Gbps */ 3855 ret_val = hw->phy.ops.read_reg(hw, BM_CS_STATUS, &data); 3856 if (ret_val) 3857 return ret_val; 3858 3859 data &= (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED | 3860 BM_CS_STATUS_SPEED_MASK); 3861 3862 if (data != (BM_CS_STATUS_LINK_UP | BM_CS_STATUS_RESOLVED | 3863 BM_CS_STATUS_SPEED_1000)) 3864 return E1000_SUCCESS; 3865 3866 msec_delay(200); 3867 3868 /* flush the packets in the fifo buffer */ 3869 ret_val = hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL, 3870 (HV_MUX_DATA_CTRL_GEN_TO_MAC | 3871 HV_MUX_DATA_CTRL_FORCE_SPEED)); 3872 if (ret_val) 3873 return ret_val; 3874 3875 return hw->phy.ops.write_reg(hw, HV_MUX_DATA_CTRL, 3876 HV_MUX_DATA_CTRL_GEN_TO_MAC); 3877} 3878 3879/** 3880 * e1000_check_polarity_82577 - Checks the polarity. 3881 * @hw: pointer to the HW structure 3882 * 3883 * Success returns 0, Failure returns -E1000_ERR_PHY (-2) 3884 * 3885 * Polarity is determined based on the PHY specific status register. 3886 **/ 3887s32 e1000_check_polarity_82577(struct e1000_hw *hw) 3888{ 3889 struct e1000_phy_info *phy = &hw->phy; 3890 s32 ret_val; 3891 u16 data; 3892 3893 DEBUGFUNC("e1000_check_polarity_82577"); 3894 3895 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data); 3896 3897 if (!ret_val) 3898 phy->cable_polarity = ((data & I82577_PHY_STATUS2_REV_POLARITY) 3899 ? e1000_rev_polarity_reversed 3900 : e1000_rev_polarity_normal); 3901 3902 return ret_val; 3903} 3904 3905/** 3906 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY 3907 * @hw: pointer to the HW structure 3908 * 3909 * Calls the PHY setup function to force speed and duplex. 3910 **/ 3911s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw) 3912{ 3913 struct e1000_phy_info *phy = &hw->phy; 3914 s32 ret_val; 3915 u16 phy_data; 3916 bool link; 3917 3918 DEBUGFUNC("e1000_phy_force_speed_duplex_82577"); 3919 3920 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data); 3921 if (ret_val) 3922 return ret_val; 3923 3924 e1000_phy_force_speed_duplex_setup(hw, &phy_data); 3925 3926 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data); 3927 if (ret_val) 3928 return ret_val; 3929 3930 usec_delay(1); 3931 3932 if (phy->autoneg_wait_to_complete) { 3933 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n"); 3934 3935 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 3936 100000, &link); 3937 if (ret_val) 3938 return ret_val; 3939 3940 if (!link) 3941 DEBUGOUT("Link taking longer than expected.\n"); 3942 3943 /* Try once more */ 3944 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT, 3945 100000, &link); 3946 } 3947 3948 return ret_val; 3949} 3950 3951/** 3952 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information 3953 * @hw: pointer to the HW structure 3954 * 3955 * Read PHY status to determine if link is up. If link is up, then 3956 * set/determine 10base-T extended distance and polarity correction. Read 3957 * PHY port status to determine MDI/MDIx and speed. Based on the speed, 3958 * determine on the cable length, local and remote receiver. 3959 **/ 3960s32 e1000_get_phy_info_82577(struct e1000_hw *hw) 3961{ 3962 struct e1000_phy_info *phy = &hw->phy; 3963 s32 ret_val; 3964 u16 data; 3965 bool link; 3966 3967 DEBUGFUNC("e1000_get_phy_info_82577"); 3968 3969 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 3970 if (ret_val) 3971 return ret_val; 3972 3973 if (!link) { 3974 DEBUGOUT("Phy info is only valid if link is up\n"); 3975 return -E1000_ERR_CONFIG; 3976 } 3977 3978 phy->polarity_correction = TRUE; 3979 3980 ret_val = e1000_check_polarity_82577(hw); 3981 if (ret_val) 3982 return ret_val; 3983 3984 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data); 3985 if (ret_val) 3986 return ret_val; 3987 3988 phy->is_mdix = !!(data & I82577_PHY_STATUS2_MDIX); 3989 3990 if ((data & I82577_PHY_STATUS2_SPEED_MASK) == 3991 I82577_PHY_STATUS2_SPEED_1000MBPS) { 3992 ret_val = hw->phy.ops.get_cable_length(hw); 3993 if (ret_val) 3994 return ret_val; 3995 3996 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data); 3997 if (ret_val) 3998 return ret_val; 3999 4000 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS) 4001 ? e1000_1000t_rx_status_ok 4002 : e1000_1000t_rx_status_not_ok; 4003 4004 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS) 4005 ? e1000_1000t_rx_status_ok 4006 : e1000_1000t_rx_status_not_ok; 4007 } else { 4008 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED; 4009 phy->local_rx = e1000_1000t_rx_status_undefined; 4010 phy->remote_rx = e1000_1000t_rx_status_undefined; 4011 } 4012 4013 return E1000_SUCCESS; 4014} 4015 4016/** 4017 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY 4018 * @hw: pointer to the HW structure 4019 * 4020 * Reads the diagnostic status register and verifies result is valid before 4021 * placing it in the phy_cable_length field. 4022 **/ 4023s32 e1000_get_cable_length_82577(struct e1000_hw *hw) 4024{ 4025 struct e1000_phy_info *phy = &hw->phy; 4026 s32 ret_val; 4027 u16 phy_data, length; 4028 4029 DEBUGFUNC("e1000_get_cable_length_82577"); 4030 4031 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data); 4032 if (ret_val) 4033 return ret_val; 4034 4035 length = ((phy_data & I82577_DSTATUS_CABLE_LENGTH) >> 4036 I82577_DSTATUS_CABLE_LENGTH_SHIFT); 4037 4038 if (length == E1000_CABLE_LENGTH_UNDEFINED) 4039 return -E1000_ERR_PHY; 4040 4041 phy->cable_length = length; 4042 4043 return E1000_SUCCESS; 4044} 4045 4046/** 4047 * e1000_write_phy_reg_gs40g - Write GS40G PHY register 4048 * @hw: pointer to the HW structure 4049 * @offset: register offset to write to 4050 * @data: data to write at register offset 4051 * 4052 * Acquires semaphore, if necessary, then writes the data to PHY register 4053 * at the offset. Release any acquired semaphores before exiting. 4054 **/ 4055s32 e1000_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data) 4056{ 4057 s32 ret_val; 4058 u16 page = offset >> GS40G_PAGE_SHIFT; 4059 4060 DEBUGFUNC("e1000_write_phy_reg_gs40g"); 4061 4062 offset = offset & GS40G_OFFSET_MASK; 4063 ret_val = hw->phy.ops.acquire(hw); 4064 if (ret_val) 4065 return ret_val; 4066 4067 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page); 4068 if (ret_val) 4069 goto release; 4070 ret_val = e1000_write_phy_reg_mdic(hw, offset, data); 4071 4072release: 4073 hw->phy.ops.release(hw); 4074 return ret_val; 4075} 4076 4077/** 4078 * e1000_read_phy_reg_gs40g - Read GS40G PHY register 4079 * @hw: pointer to the HW structure 4080 * @offset: lower half is register offset to read to 4081 * upper half is page to use. 4082 * @data: data to read at register offset 4083 * 4084 * Acquires semaphore, if necessary, then reads the data in the PHY register 4085 * at the offset. Release any acquired semaphores before exiting. 4086 **/ 4087s32 e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data) 4088{ 4089 s32 ret_val; 4090 u16 page = offset >> GS40G_PAGE_SHIFT; 4091 4092 DEBUGFUNC("e1000_read_phy_reg_gs40g"); 4093 4094 offset = offset & GS40G_OFFSET_MASK; 4095 ret_val = hw->phy.ops.acquire(hw); 4096 if (ret_val) 4097 return ret_val; 4098 4099 ret_val = e1000_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page); 4100 if (ret_val) 4101 goto release; 4102 ret_val = e1000_read_phy_reg_mdic(hw, offset, data); 4103 4104release: 4105 hw->phy.ops.release(hw); 4106 return ret_val; 4107} 4108 4109/** 4110 * e1000_read_phy_reg_mphy - Read mPHY control register 4111 * @hw: pointer to the HW structure 4112 * @address: address to be read 4113 * @data: pointer to the read data 4114 * 4115 * Reads the mPHY control register in the PHY at offset and stores the 4116 * information read to data. 4117 **/ 4118s32 e1000_read_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 *data) 4119{ 4120 u32 mphy_ctrl = 0; 4121 bool locked = FALSE; 4122 bool ready = FALSE; 4123 4124 DEBUGFUNC("e1000_read_phy_reg_mphy"); 4125 4126 /* Check if mPHY is ready to read/write operations */ 4127 ready = e1000_is_mphy_ready(hw); 4128 if (!ready) 4129 return -E1000_ERR_PHY; 4130 4131 /* Check if mPHY access is disabled and enable it if so */ 4132 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL); 4133 if (mphy_ctrl & E1000_MPHY_DIS_ACCESS) { 4134 locked = TRUE; 4135 ready = e1000_is_mphy_ready(hw); 4136 if (!ready) 4137 return -E1000_ERR_PHY; 4138 mphy_ctrl |= E1000_MPHY_ENA_ACCESS; 4139 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl); 4140 } 4141 4142 /* Set the address that we want to read */ 4143 ready = e1000_is_mphy_ready(hw); 4144 if (!ready) 4145 return -E1000_ERR_PHY; 4146 4147 /* We mask address, because we want to use only current lane */ 4148 mphy_ctrl = (mphy_ctrl & ~E1000_MPHY_ADDRESS_MASK & 4149 ~E1000_MPHY_ADDRESS_FNC_OVERRIDE) | 4150 (address & E1000_MPHY_ADDRESS_MASK); 4151 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl); 4152 4153 /* Read data from the address */ 4154 ready = e1000_is_mphy_ready(hw); 4155 if (!ready) 4156 return -E1000_ERR_PHY; 4157 *data = E1000_READ_REG(hw, E1000_MPHY_DATA); 4158 4159 /* Disable access to mPHY if it was originally disabled */ 4160 if (locked) 4161 ready = e1000_is_mphy_ready(hw); 4162 if (!ready) 4163 return -E1000_ERR_PHY; 4164 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, 4165 E1000_MPHY_DIS_ACCESS); 4166 4167 return E1000_SUCCESS; 4168} 4169 4170/** 4171 * e1000_write_phy_reg_mphy - Write mPHY control register 4172 * @hw: pointer to the HW structure 4173 * @address: address to write to 4174 * @data: data to write to register at offset 4175 * @line_override: used when we want to use different line than default one 4176 * 4177 * Writes data to mPHY control register. 4178 **/ 4179s32 e1000_write_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 data, 4180 bool line_override) 4181{ 4182 u32 mphy_ctrl = 0; 4183 bool locked = FALSE; 4184 bool ready = FALSE; 4185 4186 DEBUGFUNC("e1000_write_phy_reg_mphy"); 4187 4188 /* Check if mPHY is ready to read/write operations */ 4189 ready = e1000_is_mphy_ready(hw); 4190 if (!ready) 4191 return -E1000_ERR_PHY; 4192 4193 /* Check if mPHY access is disabled and enable it if so */ 4194 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL); 4195 if (mphy_ctrl & E1000_MPHY_DIS_ACCESS) { 4196 locked = TRUE; 4197 ready = e1000_is_mphy_ready(hw); 4198 if (!ready) 4199 return -E1000_ERR_PHY; 4200 mphy_ctrl |= E1000_MPHY_ENA_ACCESS; 4201 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl); 4202 } 4203 4204 /* Set the address that we want to read */ 4205 ready = e1000_is_mphy_ready(hw); 4206 if (!ready) 4207 return -E1000_ERR_PHY; 4208 4209 /* We mask address, because we want to use only current lane */ 4210 if (line_override) 4211 mphy_ctrl |= E1000_MPHY_ADDRESS_FNC_OVERRIDE; 4212 else 4213 mphy_ctrl &= ~E1000_MPHY_ADDRESS_FNC_OVERRIDE; 4214 mphy_ctrl = (mphy_ctrl & ~E1000_MPHY_ADDRESS_MASK) | 4215 (address & E1000_MPHY_ADDRESS_MASK); 4216 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, mphy_ctrl); 4217 4218 /* Read data from the address */ 4219 ready = e1000_is_mphy_ready(hw); 4220 if (!ready) 4221 return -E1000_ERR_PHY; 4222 E1000_WRITE_REG(hw, E1000_MPHY_DATA, data); 4223 4224 /* Disable access to mPHY if it was originally disabled */ 4225 if (locked) 4226 ready = e1000_is_mphy_ready(hw); 4227 if (!ready) 4228 return -E1000_ERR_PHY; 4229 E1000_WRITE_REG(hw, E1000_MPHY_ADDR_CTRL, 4230 E1000_MPHY_DIS_ACCESS); 4231 4232 return E1000_SUCCESS; 4233} 4234 4235/** 4236 * e1000_is_mphy_ready - Check if mPHY control register is not busy 4237 * @hw: pointer to the HW structure 4238 * 4239 * Returns mPHY control register status. 4240 **/ 4241bool e1000_is_mphy_ready(struct e1000_hw *hw) 4242{ 4243 u16 retry_count = 0; 4244 u32 mphy_ctrl = 0; 4245 bool ready = FALSE; 4246 4247 while (retry_count < 2) { 4248 mphy_ctrl = E1000_READ_REG(hw, E1000_MPHY_ADDR_CTRL); 4249 if (mphy_ctrl & E1000_MPHY_BUSY) { 4250 usec_delay(20); 4251 retry_count++; 4252 continue; 4253 } 4254 ready = TRUE; 4255 break; 4256 } 4257 4258 if (!ready) 4259 DEBUGOUT("ERROR READING mPHY control register, phy is busy.\n"); 4260 4261 return ready; 4262} 4263