1/****************************************************************************** 2 3 Copyright (c) 2001-2013, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD$*/ 34 35#ifndef _E1000_HW_H_ 36#define _E1000_HW_H_ 37 38#include "e1000_osdep.h" 39#include "e1000_regs.h" 40#include "e1000_defines.h" 41 42struct e1000_hw; 43 44#define E1000_DEV_ID_82542 0x1000 45#define E1000_DEV_ID_82543GC_FIBER 0x1001 46#define E1000_DEV_ID_82543GC_COPPER 0x1004 47#define E1000_DEV_ID_82544EI_COPPER 0x1008 48#define E1000_DEV_ID_82544EI_FIBER 0x1009 49#define E1000_DEV_ID_82544GC_COPPER 0x100C 50#define E1000_DEV_ID_82544GC_LOM 0x100D 51#define E1000_DEV_ID_82540EM 0x100E 52#define E1000_DEV_ID_82540EM_LOM 0x1015 53#define E1000_DEV_ID_82540EP_LOM 0x1016 54#define E1000_DEV_ID_82540EP 0x1017 55#define E1000_DEV_ID_82540EP_LP 0x101E 56#define E1000_DEV_ID_82545EM_COPPER 0x100F 57#define E1000_DEV_ID_82545EM_FIBER 0x1011 58#define E1000_DEV_ID_82545GM_COPPER 0x1026 59#define E1000_DEV_ID_82545GM_FIBER 0x1027 60#define E1000_DEV_ID_82545GM_SERDES 0x1028 61#define E1000_DEV_ID_82546EB_COPPER 0x1010 62#define E1000_DEV_ID_82546EB_FIBER 0x1012 63#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 64#define E1000_DEV_ID_82546GB_COPPER 0x1079 65#define E1000_DEV_ID_82546GB_FIBER 0x107A 66#define E1000_DEV_ID_82546GB_SERDES 0x107B 67#define E1000_DEV_ID_82546GB_PCIE 0x108A 68#define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 69#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 70#define E1000_DEV_ID_82541EI 0x1013 71#define E1000_DEV_ID_82541EI_MOBILE 0x1018 72#define E1000_DEV_ID_82541ER_LOM 0x1014 73#define E1000_DEV_ID_82541ER 0x1078 74#define E1000_DEV_ID_82541GI 0x1076 75#define E1000_DEV_ID_82541GI_LF 0x107C 76#define E1000_DEV_ID_82541GI_MOBILE 0x1077 77#define E1000_DEV_ID_82547EI 0x1019 78#define E1000_DEV_ID_82547EI_MOBILE 0x101A 79#define E1000_DEV_ID_82547GI 0x1075 80#define E1000_DEV_ID_82571EB_COPPER 0x105E 81#define E1000_DEV_ID_82571EB_FIBER 0x105F 82#define E1000_DEV_ID_82571EB_SERDES 0x1060 83#define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 84#define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 85#define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 86#define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 87#define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 88#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC 89#define E1000_DEV_ID_82572EI_COPPER 0x107D 90#define E1000_DEV_ID_82572EI_FIBER 0x107E 91#define E1000_DEV_ID_82572EI_SERDES 0x107F 92#define E1000_DEV_ID_82572EI 0x10B9 93#define E1000_DEV_ID_82573E 0x108B 94#define E1000_DEV_ID_82573E_IAMT 0x108C 95#define E1000_DEV_ID_82573L 0x109A 96#define E1000_DEV_ID_82574L 0x10D3 97#define E1000_DEV_ID_82574LA 0x10F6 98#define E1000_DEV_ID_82583V 0x150C 99#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 100#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 101#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 102#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 103#define E1000_DEV_ID_ICH8_82567V_3 0x1501 104#define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 105#define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 106#define E1000_DEV_ID_ICH8_IGP_C 0x104B 107#define E1000_DEV_ID_ICH8_IFE 0x104C 108#define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 109#define E1000_DEV_ID_ICH8_IFE_G 0x10C5 110#define E1000_DEV_ID_ICH8_IGP_M 0x104D 111#define E1000_DEV_ID_ICH9_IGP_M 0x10BF 112#define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 113#define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB 114#define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 115#define E1000_DEV_ID_ICH9_BM 0x10E5 116#define E1000_DEV_ID_ICH9_IGP_C 0x294C 117#define E1000_DEV_ID_ICH9_IFE 0x10C0 118#define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 119#define E1000_DEV_ID_ICH9_IFE_G 0x10C2 120#define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC 121#define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD 122#define E1000_DEV_ID_ICH10_R_BM_V 0x10CE 123#define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE 124#define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF 125#define E1000_DEV_ID_ICH10_D_BM_V 0x1525 126#define E1000_DEV_ID_PCH_M_HV_LM 0x10EA 127#define E1000_DEV_ID_PCH_M_HV_LC 0x10EB 128#define E1000_DEV_ID_PCH_D_HV_DM 0x10EF 129#define E1000_DEV_ID_PCH_D_HV_DC 0x10F0 130#define E1000_DEV_ID_PCH2_LV_LM 0x1502 131#define E1000_DEV_ID_PCH2_LV_V 0x1503 132#define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A 133#define E1000_DEV_ID_PCH_LPT_I217_V 0x153B 134#define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A 135#define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559 136#define E1000_DEV_ID_82576 0x10C9 137#define E1000_DEV_ID_82576_FIBER 0x10E6 138#define E1000_DEV_ID_82576_SERDES 0x10E7 139#define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8 140#define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526 141#define E1000_DEV_ID_82576_NS 0x150A 142#define E1000_DEV_ID_82576_NS_SERDES 0x1518 143#define E1000_DEV_ID_82576_SERDES_QUAD 0x150D 144#define E1000_DEV_ID_82576_VF 0x10CA 145#define E1000_DEV_ID_82576_VF_HV 0x152D 146#define E1000_DEV_ID_I350_VF 0x1520 147#define E1000_DEV_ID_I350_VF_HV 0x152F 148#define E1000_DEV_ID_82575EB_COPPER 0x10A7 149#define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 150#define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 151#define E1000_DEV_ID_82580_COPPER 0x150E 152#define E1000_DEV_ID_82580_FIBER 0x150F 153#define E1000_DEV_ID_82580_SERDES 0x1510 154#define E1000_DEV_ID_82580_SGMII 0x1511 155#define E1000_DEV_ID_82580_COPPER_DUAL 0x1516 156#define E1000_DEV_ID_82580_QUAD_FIBER 0x1527 157#define E1000_DEV_ID_I350_COPPER 0x1521 158#define E1000_DEV_ID_I350_FIBER 0x1522 159#define E1000_DEV_ID_I350_SERDES 0x1523 160#define E1000_DEV_ID_I350_SGMII 0x1524 161#define E1000_DEV_ID_I350_DA4 0x1546 162#define E1000_DEV_ID_I210_COPPER 0x1533 163#define E1000_DEV_ID_I210_COPPER_OEM1 0x1534 164#define E1000_DEV_ID_I210_COPPER_IT 0x1535 165#define E1000_DEV_ID_I210_FIBER 0x1536 166#define E1000_DEV_ID_I210_SERDES 0x1537 167#define E1000_DEV_ID_I210_SGMII 0x1538 168#define E1000_DEV_ID_I210_COPPER_FLASHLESS 0x157B 169#define E1000_DEV_ID_I210_SERDES_FLASHLESS 0x157C 170#define E1000_DEV_ID_I211_COPPER 0x1539 171#define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40 172#define E1000_DEV_ID_I354_SGMII 0x1F41 173#define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45 174#define E1000_DEV_ID_DH89XXCC_SGMII 0x0438 175#define E1000_DEV_ID_DH89XXCC_SERDES 0x043A 176#define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C 177#define E1000_DEV_ID_DH89XXCC_SFP 0x0440 178 179#define E1000_REVISION_0 0 180#define E1000_REVISION_1 1 181#define E1000_REVISION_2 2 182#define E1000_REVISION_3 3 183#define E1000_REVISION_4 4 184 185#define E1000_FUNC_0 0 186#define E1000_FUNC_1 1 187#define E1000_FUNC_2 2 188#define E1000_FUNC_3 3 189 190#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 191#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 192#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6 193#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9 194 195enum e1000_mac_type { 196 e1000_undefined = 0, 197 e1000_82542, 198 e1000_82543, 199 e1000_82544, 200 e1000_82540, 201 e1000_82545, 202 e1000_82545_rev_3, 203 e1000_82546, 204 e1000_82546_rev_3, 205 e1000_82541, 206 e1000_82541_rev_2, 207 e1000_82547, 208 e1000_82547_rev_2, 209 e1000_82571, 210 e1000_82572, 211 e1000_82573, 212 e1000_82574, 213 e1000_82583, 214 e1000_80003es2lan, 215 e1000_ich8lan, 216 e1000_ich9lan, 217 e1000_ich10lan, 218 e1000_pchlan, 219 e1000_pch2lan, 220 e1000_pch_lpt, 221 e1000_82575, 222 e1000_82576, 223 e1000_82580, 224 e1000_i350, 225 e1000_i354, 226 e1000_i210, 227 e1000_i211, 228 e1000_vfadapt, 229 e1000_vfadapt_i350, 230 e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */ 231}; 232 233enum e1000_media_type { 234 e1000_media_type_unknown = 0, 235 e1000_media_type_copper = 1, 236 e1000_media_type_fiber = 2, 237 e1000_media_type_internal_serdes = 3, 238 e1000_num_media_types 239}; 240 241enum e1000_nvm_type { 242 e1000_nvm_unknown = 0, 243 e1000_nvm_none, 244 e1000_nvm_eeprom_spi, 245 e1000_nvm_eeprom_microwire, 246 e1000_nvm_flash_hw, 247 e1000_nvm_invm, 248 e1000_nvm_flash_sw 249}; 250 251enum e1000_nvm_override { 252 e1000_nvm_override_none = 0, 253 e1000_nvm_override_spi_small, 254 e1000_nvm_override_spi_large, 255 e1000_nvm_override_microwire_small, 256 e1000_nvm_override_microwire_large 257}; 258 259enum e1000_phy_type { 260 e1000_phy_unknown = 0, 261 e1000_phy_none, 262 e1000_phy_m88, 263 e1000_phy_igp, 264 e1000_phy_igp_2, 265 e1000_phy_gg82563, 266 e1000_phy_igp_3, 267 e1000_phy_ife, 268 e1000_phy_bm, 269 e1000_phy_82578, 270 e1000_phy_82577, 271 e1000_phy_82579, 272 e1000_phy_i217, 273 e1000_phy_82580, 274 e1000_phy_vf, 275 e1000_phy_i210, 276}; 277 278enum e1000_bus_type { 279 e1000_bus_type_unknown = 0, 280 e1000_bus_type_pci, 281 e1000_bus_type_pcix, 282 e1000_bus_type_pci_express, 283 e1000_bus_type_reserved 284}; 285 286enum e1000_bus_speed { 287 e1000_bus_speed_unknown = 0, 288 e1000_bus_speed_33, 289 e1000_bus_speed_66, 290 e1000_bus_speed_100, 291 e1000_bus_speed_120, 292 e1000_bus_speed_133, 293 e1000_bus_speed_2500, 294 e1000_bus_speed_5000, 295 e1000_bus_speed_reserved 296}; 297 298enum e1000_bus_width { 299 e1000_bus_width_unknown = 0, 300 e1000_bus_width_pcie_x1, 301 e1000_bus_width_pcie_x2, 302 e1000_bus_width_pcie_x4 = 4, 303 e1000_bus_width_pcie_x8 = 8, 304 e1000_bus_width_32, 305 e1000_bus_width_64, 306 e1000_bus_width_reserved 307}; 308 309enum e1000_1000t_rx_status { 310 e1000_1000t_rx_status_not_ok = 0, 311 e1000_1000t_rx_status_ok, 312 e1000_1000t_rx_status_undefined = 0xFF 313}; 314 315enum e1000_rev_polarity { 316 e1000_rev_polarity_normal = 0, 317 e1000_rev_polarity_reversed, 318 e1000_rev_polarity_undefined = 0xFF 319}; 320 321enum e1000_fc_mode { 322 e1000_fc_none = 0, 323 e1000_fc_rx_pause, 324 e1000_fc_tx_pause, 325 e1000_fc_full, 326 e1000_fc_default = 0xFF 327}; 328 329enum e1000_ffe_config { 330 e1000_ffe_config_enabled = 0, 331 e1000_ffe_config_active, 332 e1000_ffe_config_blocked 333}; 334 335enum e1000_dsp_config { 336 e1000_dsp_config_disabled = 0, 337 e1000_dsp_config_enabled, 338 e1000_dsp_config_activated, 339 e1000_dsp_config_undefined = 0xFF 340}; 341 342enum e1000_ms_type { 343 e1000_ms_hw_default = 0, 344 e1000_ms_force_master, 345 e1000_ms_force_slave, 346 e1000_ms_auto 347}; 348 349enum e1000_smart_speed { 350 e1000_smart_speed_default = 0, 351 e1000_smart_speed_on, 352 e1000_smart_speed_off 353}; 354 355enum e1000_serdes_link_state { 356 e1000_serdes_link_down = 0, 357 e1000_serdes_link_autoneg_progress, 358 e1000_serdes_link_autoneg_complete, 359 e1000_serdes_link_forced_up 360}; 361 362#define __le16 u16 363#define __le32 u32 364#define __le64 u64 365/* Receive Descriptor */ 366struct e1000_rx_desc { 367 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 368 __le16 length; /* Length of data DMAed into data buffer */ 369 __le16 csum; /* Packet checksum */ 370 u8 status; /* Descriptor status */ 371 u8 errors; /* Descriptor Errors */ 372 __le16 special; 373}; 374 375/* Receive Descriptor - Extended */ 376union e1000_rx_desc_extended { 377 struct { 378 __le64 buffer_addr; 379 __le64 reserved; 380 } read; 381 struct { 382 struct { 383 __le32 mrq; /* Multiple Rx Queues */ 384 union { 385 __le32 rss; /* RSS Hash */ 386 struct { 387 __le16 ip_id; /* IP id */ 388 __le16 csum; /* Packet Checksum */ 389 } csum_ip; 390 } hi_dword; 391 } lower; 392 struct { 393 __le32 status_error; /* ext status/error */ 394 __le16 length; 395 __le16 vlan; /* VLAN tag */ 396 } upper; 397 } wb; /* writeback */ 398}; 399 400#define MAX_PS_BUFFERS 4 401 402/* Number of packet split data buffers (not including the header buffer) */ 403#define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1) 404 405/* Receive Descriptor - Packet Split */ 406union e1000_rx_desc_packet_split { 407 struct { 408 /* one buffer for protocol header(s), three data buffers */ 409 __le64 buffer_addr[MAX_PS_BUFFERS]; 410 } read; 411 struct { 412 struct { 413 __le32 mrq; /* Multiple Rx Queues */ 414 union { 415 __le32 rss; /* RSS Hash */ 416 struct { 417 __le16 ip_id; /* IP id */ 418 __le16 csum; /* Packet Checksum */ 419 } csum_ip; 420 } hi_dword; 421 } lower; 422 struct { 423 __le32 status_error; /* ext status/error */ 424 __le16 length0; /* length of buffer 0 */ 425 __le16 vlan; /* VLAN tag */ 426 } middle; 427 struct { 428 __le16 header_status; 429 /* length of buffers 1-3 */ 430 __le16 length[PS_PAGE_BUFFERS]; 431 } upper; 432 __le64 reserved; 433 } wb; /* writeback */ 434}; 435 436/* Transmit Descriptor */ 437struct e1000_tx_desc { 438 __le64 buffer_addr; /* Address of the descriptor's data buffer */ 439 union { 440 __le32 data; 441 struct { 442 __le16 length; /* Data buffer length */ 443 u8 cso; /* Checksum offset */ 444 u8 cmd; /* Descriptor control */ 445 } flags; 446 } lower; 447 union { 448 __le32 data; 449 struct { 450 u8 status; /* Descriptor status */ 451 u8 css; /* Checksum start */ 452 __le16 special; 453 } fields; 454 } upper; 455}; 456 457/* Offload Context Descriptor */ 458struct e1000_context_desc { 459 union { 460 __le32 ip_config; 461 struct { 462 u8 ipcss; /* IP checksum start */ 463 u8 ipcso; /* IP checksum offset */ 464 __le16 ipcse; /* IP checksum end */ 465 } ip_fields; 466 } lower_setup; 467 union { 468 __le32 tcp_config; 469 struct { 470 u8 tucss; /* TCP checksum start */ 471 u8 tucso; /* TCP checksum offset */ 472 __le16 tucse; /* TCP checksum end */ 473 } tcp_fields; 474 } upper_setup; 475 __le32 cmd_and_length; 476 union { 477 __le32 data; 478 struct { 479 u8 status; /* Descriptor status */ 480 u8 hdr_len; /* Header length */ 481 __le16 mss; /* Maximum segment size */ 482 } fields; 483 } tcp_seg_setup; 484}; 485 486/* Offload data descriptor */ 487struct e1000_data_desc { 488 __le64 buffer_addr; /* Address of the descriptor's buffer address */ 489 union { 490 __le32 data; 491 struct { 492 __le16 length; /* Data buffer length */ 493 u8 typ_len_ext; 494 u8 cmd; 495 } flags; 496 } lower; 497 union { 498 __le32 data; 499 struct { 500 u8 status; /* Descriptor status */ 501 u8 popts; /* Packet Options */ 502 __le16 special; 503 } fields; 504 } upper; 505}; 506 507/* Statistics counters collected by the MAC */ 508struct e1000_hw_stats { 509 u64 crcerrs; 510 u64 algnerrc; 511 u64 symerrs; 512 u64 rxerrc; 513 u64 mpc; 514 u64 scc; 515 u64 ecol; 516 u64 mcc; 517 u64 latecol; 518 u64 colc; 519 u64 dc; 520 u64 tncrs; 521 u64 sec; 522 u64 cexterr; 523 u64 rlec; 524 u64 xonrxc; 525 u64 xontxc; 526 u64 xoffrxc; 527 u64 xofftxc; 528 u64 fcruc; 529 u64 prc64; 530 u64 prc127; 531 u64 prc255; 532 u64 prc511; 533 u64 prc1023; 534 u64 prc1522; 535 u64 gprc; 536 u64 bprc; 537 u64 mprc; 538 u64 gptc; 539 u64 gorc; 540 u64 gotc; 541 u64 rnbc; 542 u64 ruc; 543 u64 rfc; 544 u64 roc; 545 u64 rjc; 546 u64 mgprc; 547 u64 mgpdc; 548 u64 mgptc; 549 u64 tor; 550 u64 tot; 551 u64 tpr; 552 u64 tpt; 553 u64 ptc64; 554 u64 ptc127; 555 u64 ptc255; 556 u64 ptc511; 557 u64 ptc1023; 558 u64 ptc1522; 559 u64 mptc; 560 u64 bptc; 561 u64 tsctc; 562 u64 tsctfc; 563 u64 iac; 564 u64 icrxptc; 565 u64 icrxatc; 566 u64 ictxptc; 567 u64 ictxatc; 568 u64 ictxqec; 569 u64 ictxqmtc; 570 u64 icrxdmtc; 571 u64 icrxoc; 572 u64 cbtmpc; 573 u64 htdpmc; 574 u64 cbrdpc; 575 u64 cbrmpc; 576 u64 rpthc; 577 u64 hgptc; 578 u64 htcbdpc; 579 u64 hgorc; 580 u64 hgotc; 581 u64 lenerrs; 582 u64 scvpc; 583 u64 hrmpc; 584 u64 doosync; 585 u64 o2bgptc; 586 u64 o2bspc; 587 u64 b2ospc; 588 u64 b2ogprc; 589}; 590 591struct e1000_vf_stats { 592 u64 base_gprc; 593 u64 base_gptc; 594 u64 base_gorc; 595 u64 base_gotc; 596 u64 base_mprc; 597 u64 base_gotlbc; 598 u64 base_gptlbc; 599 u64 base_gorlbc; 600 u64 base_gprlbc; 601 602 u32 last_gprc; 603 u32 last_gptc; 604 u32 last_gorc; 605 u32 last_gotc; 606 u32 last_mprc; 607 u32 last_gotlbc; 608 u32 last_gptlbc; 609 u32 last_gorlbc; 610 u32 last_gprlbc; 611 612 u64 gprc; 613 u64 gptc; 614 u64 gorc; 615 u64 gotc; 616 u64 mprc; 617 u64 gotlbc; 618 u64 gptlbc; 619 u64 gorlbc; 620 u64 gprlbc; 621}; 622 623struct e1000_phy_stats { 624 u32 idle_errors; 625 u32 receive_errors; 626}; 627 628struct e1000_host_mng_dhcp_cookie { 629 u32 signature; 630 u8 status; 631 u8 reserved0; 632 u16 vlan_id; 633 u32 reserved1; 634 u16 reserved2; 635 u8 reserved3; 636 u8 checksum; 637}; 638 639/* Host Interface "Rev 1" */ 640struct e1000_host_command_header { 641 u8 command_id; 642 u8 command_length; 643 u8 command_options; 644 u8 checksum; 645}; 646 647#define E1000_HI_MAX_DATA_LENGTH 252 648struct e1000_host_command_info { 649 struct e1000_host_command_header command_header; 650 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 651}; 652 653/* Host Interface "Rev 2" */ 654struct e1000_host_mng_command_header { 655 u8 command_id; 656 u8 checksum; 657 u16 reserved1; 658 u16 reserved2; 659 u16 command_length; 660}; 661 662#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 663struct e1000_host_mng_command_info { 664 struct e1000_host_mng_command_header command_header; 665 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 666}; 667 668#include "e1000_mac.h" 669#include "e1000_phy.h" 670#include "e1000_nvm.h" 671#include "e1000_manage.h" 672#include "e1000_mbx.h" 673 674/* Function pointers for the MAC. */ 675struct e1000_mac_operations { 676 s32 (*init_params)(struct e1000_hw *); 677 s32 (*id_led_init)(struct e1000_hw *); 678 s32 (*blink_led)(struct e1000_hw *); 679 bool (*check_mng_mode)(struct e1000_hw *); 680 s32 (*check_for_link)(struct e1000_hw *); 681 s32 (*cleanup_led)(struct e1000_hw *); 682 void (*clear_hw_cntrs)(struct e1000_hw *); 683 void (*clear_vfta)(struct e1000_hw *); 684 s32 (*get_bus_info)(struct e1000_hw *); 685 void (*set_lan_id)(struct e1000_hw *); 686 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *); 687 s32 (*led_on)(struct e1000_hw *); 688 s32 (*led_off)(struct e1000_hw *); 689 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32); 690 s32 (*reset_hw)(struct e1000_hw *); 691 s32 (*init_hw)(struct e1000_hw *); 692 void (*shutdown_serdes)(struct e1000_hw *); 693 void (*power_up_serdes)(struct e1000_hw *); 694 s32 (*setup_link)(struct e1000_hw *); 695 s32 (*setup_physical_interface)(struct e1000_hw *); 696 s32 (*setup_led)(struct e1000_hw *); 697 void (*write_vfta)(struct e1000_hw *, u32, u32); 698 void (*config_collision_dist)(struct e1000_hw *); 699 void (*rar_set)(struct e1000_hw *, u8*, u32); 700 s32 (*read_mac_addr)(struct e1000_hw *); 701 s32 (*validate_mdi_setting)(struct e1000_hw *); 702 s32 (*set_obff_timer)(struct e1000_hw *, u32); 703 s32 (*acquire_swfw_sync)(struct e1000_hw *, u16); 704 void (*release_swfw_sync)(struct e1000_hw *, u16); 705}; 706 707/* When to use various PHY register access functions: 708 * 709 * Func Caller 710 * Function Does Does When to use 711 * ~~~~~~~~~~~~ ~~~~~ ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 712 * X_reg L,P,A n/a for simple PHY reg accesses 713 * X_reg_locked P,A L for multiple accesses of different regs 714 * on different pages 715 * X_reg_page A L,P for multiple accesses of different regs 716 * on the same page 717 * 718 * Where X=[read|write], L=locking, P=sets page, A=register access 719 * 720 */ 721struct e1000_phy_operations { 722 s32 (*init_params)(struct e1000_hw *); 723 s32 (*acquire)(struct e1000_hw *); 724 s32 (*cfg_on_link_up)(struct e1000_hw *); 725 s32 (*check_polarity)(struct e1000_hw *); 726 s32 (*check_reset_block)(struct e1000_hw *); 727 s32 (*commit)(struct e1000_hw *); 728 s32 (*force_speed_duplex)(struct e1000_hw *); 729 s32 (*get_cfg_done)(struct e1000_hw *hw); 730 s32 (*get_cable_length)(struct e1000_hw *); 731 s32 (*get_info)(struct e1000_hw *); 732 s32 (*set_page)(struct e1000_hw *, u16); 733 s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 734 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *); 735 s32 (*read_reg_page)(struct e1000_hw *, u32, u16 *); 736 void (*release)(struct e1000_hw *); 737 s32 (*reset)(struct e1000_hw *); 738 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 739 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 740 s32 (*write_reg)(struct e1000_hw *, u32, u16); 741 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16); 742 s32 (*write_reg_page)(struct e1000_hw *, u32, u16); 743 void (*power_up)(struct e1000_hw *); 744 void (*power_down)(struct e1000_hw *); 745 s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *); 746 s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8); 747}; 748 749/* Function pointers for the NVM. */ 750struct e1000_nvm_operations { 751 s32 (*init_params)(struct e1000_hw *); 752 s32 (*acquire)(struct e1000_hw *); 753 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 754 void (*release)(struct e1000_hw *); 755 void (*reload)(struct e1000_hw *); 756 s32 (*update)(struct e1000_hw *); 757 s32 (*valid_led_default)(struct e1000_hw *, u16 *); 758 s32 (*validate)(struct e1000_hw *); 759 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 760}; 761 762struct e1000_mac_info { 763 struct e1000_mac_operations ops; 764 u8 addr[ETH_ADDR_LEN]; 765 u8 perm_addr[ETH_ADDR_LEN]; 766 767 enum e1000_mac_type type; 768 769 u32 collision_delta; 770 u32 ledctl_default; 771 u32 ledctl_mode1; 772 u32 ledctl_mode2; 773 u32 mc_filter_type; 774 u32 tx_packet_delta; 775 u32 txcw; 776 777 u16 current_ifs_val; 778 u16 ifs_max_val; 779 u16 ifs_min_val; 780 u16 ifs_ratio; 781 u16 ifs_step_size; 782 u16 mta_reg_count; 783 u16 uta_reg_count; 784 785 /* Maximum size of the MTA register table in all supported adapters */ 786 #define MAX_MTA_REG 128 787 u32 mta_shadow[MAX_MTA_REG]; 788 u16 rar_entry_count; 789 790 u8 forced_speed_duplex; 791 792 bool adaptive_ifs; 793 bool has_fwsm; 794 bool arc_subsystem_valid; 795 bool asf_firmware_present; 796 bool autoneg; 797 bool autoneg_failed; 798 bool get_link_status; 799 bool in_ifs_mode; 800 bool report_tx_early; 801 enum e1000_serdes_link_state serdes_link_state; 802 bool serdes_has_link; 803 bool tx_pkt_filtering; 804 u32 max_frame_size; 805}; 806 807struct e1000_phy_info { 808 struct e1000_phy_operations ops; 809 enum e1000_phy_type type; 810 811 enum e1000_1000t_rx_status local_rx; 812 enum e1000_1000t_rx_status remote_rx; 813 enum e1000_ms_type ms_type; 814 enum e1000_ms_type original_ms_type; 815 enum e1000_rev_polarity cable_polarity; 816 enum e1000_smart_speed smart_speed; 817 818 u32 addr; 819 u32 id; 820 u32 reset_delay_us; /* in usec */ 821 u32 revision; 822 823 enum e1000_media_type media_type; 824 825 u16 autoneg_advertised; 826 u16 autoneg_mask; 827 u16 cable_length; 828 u16 max_cable_length; 829 u16 min_cable_length; 830 831 u8 mdix; 832 833 bool disable_polarity_correction; 834 bool is_mdix; 835 bool polarity_correction; 836 bool speed_downgraded; 837 bool autoneg_wait_to_complete; 838}; 839 840struct e1000_nvm_info { 841 struct e1000_nvm_operations ops; 842 enum e1000_nvm_type type; 843 enum e1000_nvm_override override; 844 845 u32 flash_bank_size; 846 u32 flash_base_addr; 847 848 u16 word_size; 849 u16 delay_usec; 850 u16 address_bits; 851 u16 opcode_bits; 852 u16 page_size; 853}; 854 855struct e1000_bus_info { 856 enum e1000_bus_type type; 857 enum e1000_bus_speed speed; 858 enum e1000_bus_width width; 859 860 u16 func; 861 u16 pci_cmd_word; 862}; 863 864struct e1000_fc_info { 865 u32 high_water; /* Flow control high-water mark */ 866 u32 low_water; /* Flow control low-water mark */ 867 u16 pause_time; /* Flow control pause timer */ 868 u16 refresh_time; /* Flow control refresh timer */ 869 bool send_xon; /* Flow control send XON */ 870 bool strict_ieee; /* Strict IEEE mode */ 871 enum e1000_fc_mode current_mode; /* FC mode in effect */ 872 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */ 873}; 874 875struct e1000_mbx_operations { 876 s32 (*init_params)(struct e1000_hw *hw); 877 s32 (*read)(struct e1000_hw *, u32 *, u16, u16); 878 s32 (*write)(struct e1000_hw *, u32 *, u16, u16); 879 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16); 880 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16); 881 s32 (*check_for_msg)(struct e1000_hw *, u16); 882 s32 (*check_for_ack)(struct e1000_hw *, u16); 883 s32 (*check_for_rst)(struct e1000_hw *, u16); 884}; 885 886struct e1000_mbx_stats { 887 u32 msgs_tx; 888 u32 msgs_rx; 889 890 u32 acks; 891 u32 reqs; 892 u32 rsts; 893}; 894 895struct e1000_mbx_info { 896 struct e1000_mbx_operations ops; 897 struct e1000_mbx_stats stats; 898 u32 timeout; 899 u32 usec_delay; 900 u16 size; 901}; 902 903struct e1000_dev_spec_82541 { 904 enum e1000_dsp_config dsp_config; 905 enum e1000_ffe_config ffe_config; 906 u16 spd_default; 907 bool phy_init_script; 908}; 909 910struct e1000_dev_spec_82542 { 911 bool dma_fairness; 912}; 913 914struct e1000_dev_spec_82543 { 915 u32 tbi_compatibility; 916 bool dma_fairness; 917 bool init_phy_disabled; 918}; 919 920struct e1000_dev_spec_82571 { 921 bool laa_is_present; 922 u32 smb_counter; 923 E1000_MUTEX swflag_mutex; 924}; 925 926struct e1000_dev_spec_80003es2lan { 927 bool mdic_wa_enable; 928}; 929 930struct e1000_shadow_ram { 931 u16 value; 932 bool modified; 933}; 934 935#define E1000_SHADOW_RAM_WORDS 2048 936 937struct e1000_dev_spec_ich8lan { 938 bool kmrn_lock_loss_workaround_enabled; 939 struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS]; 940 E1000_MUTEX nvm_mutex; 941 E1000_MUTEX swflag_mutex; 942 bool nvm_k1_enabled; 943 bool eee_disable; 944 u16 eee_lp_ability; 945}; 946 947struct e1000_dev_spec_82575 { 948 bool sgmii_active; 949 bool global_device_reset; 950 bool eee_disable; 951 bool module_plugged; 952 bool clear_semaphore_once; 953 u32 mtu; 954 struct sfp_e1000_flags eth_flags; 955 u8 media_port; 956 bool media_changed; 957}; 958 959struct e1000_dev_spec_vf { 960 u32 vf_number; 961 u32 v2p_mailbox; 962}; 963 964struct e1000_hw { 965 void *back; 966 967 u8 *hw_addr; 968 u8 *flash_address; 969 unsigned long io_base; 970 971 struct e1000_mac_info mac; 972 struct e1000_fc_info fc; 973 struct e1000_phy_info phy; 974 struct e1000_nvm_info nvm; 975 struct e1000_bus_info bus; 976 struct e1000_mbx_info mbx; 977 struct e1000_host_mng_dhcp_cookie mng_cookie; 978 979 union { 980 struct e1000_dev_spec_82541 _82541; 981 struct e1000_dev_spec_82542 _82542; 982 struct e1000_dev_spec_82543 _82543; 983 struct e1000_dev_spec_82571 _82571; 984 struct e1000_dev_spec_80003es2lan _80003es2lan; 985 struct e1000_dev_spec_ich8lan ich8lan; 986 struct e1000_dev_spec_82575 _82575; 987 struct e1000_dev_spec_vf vf; 988 } dev_spec; 989 990 u16 device_id; 991 u16 subsystem_vendor_id; 992 u16 subsystem_device_id; 993 u16 vendor_id; 994 995 u8 revision_id; 996}; 997 998#include "e1000_82541.h" 999#include "e1000_82543.h" 1000#include "e1000_82571.h" 1001#include "e1000_80003es2lan.h" 1002#include "e1000_ich8lan.h" 1003#include "e1000_82575.h" 1004#include "e1000_i210.h" 1005 1006/* These functions must be implemented by drivers */ 1007void e1000_pci_clear_mwi(struct e1000_hw *hw); 1008void e1000_pci_set_mwi(struct e1000_hw *hw); 1009s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 1010s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 1011void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 1012void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value); 1013 1014#endif 1015