1#include <sys/cdefs.h> 2__FBSDID("$FreeBSD$"); 3 4#include <dev/drm2/drmP.h> 5#include <dev/drm2/drm_crtc_helper.h> 6#include "radeon.h" 7 8/* 9 * Integrated TV out support based on the GATOS code by 10 * Federico Ulivi <fulivi@lycos.com> 11 */ 12 13 14/* 15 * Limits of h/v positions (hPos & vPos) 16 */ 17#define MAX_H_POSITION 5 /* Range: [-5..5], negative is on the left, 0 is default, positive is on the right */ 18#define MAX_V_POSITION 5 /* Range: [-5..5], negative is up, 0 is default, positive is down */ 19 20/* 21 * Unit for hPos (in TV clock periods) 22 */ 23#define H_POS_UNIT 10 24 25/* 26 * Indexes in h. code timing table for horizontal line position adjustment 27 */ 28#define H_TABLE_POS1 6 29#define H_TABLE_POS2 8 30 31/* 32 * Limits of hor. size (hSize) 33 */ 34#define MAX_H_SIZE 5 /* Range: [-5..5], negative is smaller, positive is larger */ 35 36/* tv standard constants */ 37#define NTSC_TV_CLOCK_T 233 38#define NTSC_TV_VFTOTAL 1 39#define NTSC_TV_LINES_PER_FRAME 525 40#define NTSC_TV_ZERO_H_SIZE 479166 41#define NTSC_TV_H_SIZE_UNIT 9478 42 43#define PAL_TV_CLOCK_T 188 44#define PAL_TV_VFTOTAL 3 45#define PAL_TV_LINES_PER_FRAME 625 46#define PAL_TV_ZERO_H_SIZE 473200 47#define PAL_TV_H_SIZE_UNIT 9360 48 49/* tv pll setting for 27 mhz ref clk */ 50#define NTSC_TV_PLL_M_27 22 51#define NTSC_TV_PLL_N_27 175 52#define NTSC_TV_PLL_P_27 5 53 54#define PAL_TV_PLL_M_27 113 55#define PAL_TV_PLL_N_27 668 56#define PAL_TV_PLL_P_27 3 57 58/* tv pll setting for 14 mhz ref clk */ 59#define NTSC_TV_PLL_M_14 33 60#define NTSC_TV_PLL_N_14 693 61#define NTSC_TV_PLL_P_14 7 62 63#define PAL_TV_PLL_M_14 19 64#define PAL_TV_PLL_N_14 353 65#define PAL_TV_PLL_P_14 5 66 67#define VERT_LEAD_IN_LINES 2 68#define FRAC_BITS 0xe 69#define FRAC_MASK 0x3fff 70 71struct radeon_tv_mode_constants { 72 uint16_t hor_resolution; 73 uint16_t ver_resolution; 74 enum radeon_tv_std standard; 75 uint16_t hor_total; 76 uint16_t ver_total; 77 uint16_t hor_start; 78 uint16_t hor_syncstart; 79 uint16_t ver_syncstart; 80 unsigned def_restart; 81 uint16_t crtcPLL_N; 82 uint8_t crtcPLL_M; 83 uint8_t crtcPLL_post_div; 84 unsigned pix_to_tv; 85}; 86 87static const uint16_t hor_timing_NTSC[MAX_H_CODE_TIMING_LEN] = { 88 0x0007, 89 0x003f, 90 0x0263, 91 0x0a24, 92 0x2a6b, 93 0x0a36, 94 0x126d, /* H_TABLE_POS1 */ 95 0x1bfe, 96 0x1a8f, /* H_TABLE_POS2 */ 97 0x1ec7, 98 0x3863, 99 0x1bfe, 100 0x1bfe, 101 0x1a2a, 102 0x1e95, 103 0x0e31, 104 0x201b, 105 0 106}; 107 108static const uint16_t vert_timing_NTSC[MAX_V_CODE_TIMING_LEN] = { 109 0x2001, 110 0x200d, 111 0x1006, 112 0x0c06, 113 0x1006, 114 0x1818, 115 0x21e3, 116 0x1006, 117 0x0c06, 118 0x1006, 119 0x1817, 120 0x21d4, 121 0x0002, 122 0 123}; 124 125static const uint16_t hor_timing_PAL[MAX_H_CODE_TIMING_LEN] = { 126 0x0007, 127 0x0058, 128 0x027c, 129 0x0a31, 130 0x2a77, 131 0x0a95, 132 0x124f, /* H_TABLE_POS1 */ 133 0x1bfe, 134 0x1b22, /* H_TABLE_POS2 */ 135 0x1ef9, 136 0x387c, 137 0x1bfe, 138 0x1bfe, 139 0x1b31, 140 0x1eb5, 141 0x0e43, 142 0x201b, 143 0 144}; 145 146static const uint16_t vert_timing_PAL[MAX_V_CODE_TIMING_LEN] = { 147 0x2001, 148 0x200c, 149 0x1005, 150 0x0c05, 151 0x1005, 152 0x1401, 153 0x1821, 154 0x2240, 155 0x1005, 156 0x0c05, 157 0x1005, 158 0x1401, 159 0x1822, 160 0x2230, 161 0x0002, 162 0 163}; 164 165/********************************************************************** 166 * 167 * availableModes 168 * 169 * Table of all allowed modes for tv output 170 * 171 **********************************************************************/ 172static const struct radeon_tv_mode_constants available_tv_modes[] = { 173 { /* NTSC timing for 27 Mhz ref clk */ 174 800, /* horResolution */ 175 600, /* verResolution */ 176 TV_STD_NTSC, /* standard */ 177 990, /* horTotal */ 178 740, /* verTotal */ 179 813, /* horStart */ 180 824, /* horSyncStart */ 181 632, /* verSyncStart */ 182 625592, /* defRestart */ 183 592, /* crtcPLL_N */ 184 91, /* crtcPLL_M */ 185 4, /* crtcPLL_postDiv */ 186 1022, /* pixToTV */ 187 }, 188 { /* PAL timing for 27 Mhz ref clk */ 189 800, /* horResolution */ 190 600, /* verResolution */ 191 TV_STD_PAL, /* standard */ 192 1144, /* horTotal */ 193 706, /* verTotal */ 194 812, /* horStart */ 195 824, /* horSyncStart */ 196 669, /* verSyncStart */ 197 696700, /* defRestart */ 198 1382, /* crtcPLL_N */ 199 231, /* crtcPLL_M */ 200 4, /* crtcPLL_postDiv */ 201 759, /* pixToTV */ 202 }, 203 { /* NTSC timing for 14 Mhz ref clk */ 204 800, /* horResolution */ 205 600, /* verResolution */ 206 TV_STD_NTSC, /* standard */ 207 1018, /* horTotal */ 208 727, /* verTotal */ 209 813, /* horStart */ 210 840, /* horSyncStart */ 211 633, /* verSyncStart */ 212 630627, /* defRestart */ 213 347, /* crtcPLL_N */ 214 14, /* crtcPLL_M */ 215 8, /* crtcPLL_postDiv */ 216 1022, /* pixToTV */ 217 }, 218 { /* PAL timing for 14 Mhz ref clk */ 219 800, /* horResolution */ 220 600, /* verResolution */ 221 TV_STD_PAL, /* standard */ 222 1131, /* horTotal */ 223 742, /* verTotal */ 224 813, /* horStart */ 225 840, /* horSyncStart */ 226 633, /* verSyncStart */ 227 708369, /* defRestart */ 228 211, /* crtcPLL_N */ 229 9, /* crtcPLL_M */ 230 8, /* crtcPLL_postDiv */ 231 759, /* pixToTV */ 232 }, 233}; 234 235#define N_AVAILABLE_MODES DRM_ARRAY_SIZE(available_tv_modes) 236 237static const struct radeon_tv_mode_constants *radeon_legacy_tv_get_std_mode(struct radeon_encoder *radeon_encoder, 238 uint16_t *pll_ref_freq) 239{ 240 struct drm_device *dev = radeon_encoder->base.dev; 241 struct radeon_device *rdev = dev->dev_private; 242 struct radeon_crtc *radeon_crtc; 243 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; 244 const struct radeon_tv_mode_constants *const_ptr; 245 struct radeon_pll *pll; 246 247 radeon_crtc = to_radeon_crtc(radeon_encoder->base.crtc); 248 if (radeon_crtc->crtc_id == 1) 249 pll = &rdev->clock.p2pll; 250 else 251 pll = &rdev->clock.p1pll; 252 253 if (pll_ref_freq) 254 *pll_ref_freq = pll->reference_freq; 255 256 if (tv_dac->tv_std == TV_STD_NTSC || 257 tv_dac->tv_std == TV_STD_NTSC_J || 258 tv_dac->tv_std == TV_STD_PAL_M) { 259 if (pll->reference_freq == 2700) 260 const_ptr = &available_tv_modes[0]; 261 else 262 const_ptr = &available_tv_modes[2]; 263 } else { 264 if (pll->reference_freq == 2700) 265 const_ptr = &available_tv_modes[1]; 266 else 267 const_ptr = &available_tv_modes[3]; 268 } 269 return const_ptr; 270} 271 272static long YCOEF_value[5] = { 2, 2, 0, 4, 0 }; 273static long YCOEF_EN_value[5] = { 1, 1, 0, 1, 0 }; 274static long SLOPE_value[5] = { 1, 2, 2, 4, 8 }; 275static long SLOPE_limit[5] = { 6, 5, 4, 3, 2 }; 276 277static void radeon_wait_pll_lock(struct drm_encoder *encoder, unsigned n_tests, 278 unsigned n_wait_loops, unsigned cnt_threshold) 279{ 280 struct drm_device *dev = encoder->dev; 281 struct radeon_device *rdev = dev->dev_private; 282 uint32_t save_pll_test; 283 unsigned int i, j; 284 285 WREG32(RADEON_TEST_DEBUG_MUX, (RREG32(RADEON_TEST_DEBUG_MUX) & 0xffff60ff) | 0x100); 286 save_pll_test = RREG32_PLL(RADEON_PLL_TEST_CNTL); 287 WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test & ~RADEON_PLL_MASK_READ_B); 288 289 WREG8(RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_TEST_CNTL); 290 for (i = 0; i < n_tests; i++) { 291 WREG8(RADEON_CLOCK_CNTL_DATA + 3, 0); 292 for (j = 0; j < n_wait_loops; j++) 293 if (RREG8(RADEON_CLOCK_CNTL_DATA + 3) >= cnt_threshold) 294 break; 295 } 296 WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test); 297 WREG32(RADEON_TEST_DEBUG_MUX, RREG32(RADEON_TEST_DEBUG_MUX) & 0xffffe0ff); 298} 299 300 301static void radeon_legacy_tv_write_fifo(struct radeon_encoder *radeon_encoder, 302 uint16_t addr, uint32_t value) 303{ 304 struct drm_device *dev = radeon_encoder->base.dev; 305 struct radeon_device *rdev = dev->dev_private; 306 uint32_t tmp; 307 int i = 0; 308 309 WREG32(RADEON_TV_HOST_WRITE_DATA, value); 310 311 WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr); 312 WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_WT); 313 314 do { 315 tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL); 316 if ((tmp & RADEON_HOST_FIFO_WT_ACK) == 0) 317 break; 318 i++; 319 } while (i < 10000); 320 WREG32(RADEON_TV_HOST_RD_WT_CNTL, 0); 321} 322 323#if 0 /* included for completeness */ 324static uint32_t radeon_legacy_tv_read_fifo(struct radeon_encoder *radeon_encoder, uint16_t addr) 325{ 326 struct drm_device *dev = radeon_encoder->base.dev; 327 struct radeon_device *rdev = dev->dev_private; 328 uint32_t tmp; 329 int i = 0; 330 331 WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr); 332 WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_RD); 333 334 do { 335 tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL); 336 if ((tmp & RADEON_HOST_FIFO_RD_ACK) == 0) 337 break; 338 i++; 339 } while (i < 10000); 340 WREG32(RADEON_TV_HOST_RD_WT_CNTL, 0); 341 return RREG32(RADEON_TV_HOST_READ_DATA); 342} 343#endif 344 345static uint16_t radeon_get_htiming_tables_addr(uint32_t tv_uv_adr) 346{ 347 uint16_t h_table; 348 349 switch ((tv_uv_adr & RADEON_HCODE_TABLE_SEL_MASK) >> RADEON_HCODE_TABLE_SEL_SHIFT) { 350 case 0: 351 h_table = RADEON_TV_MAX_FIFO_ADDR_INTERNAL; 352 break; 353 case 1: 354 h_table = ((tv_uv_adr & RADEON_TABLE1_BOT_ADR_MASK) >> RADEON_TABLE1_BOT_ADR_SHIFT) * 2; 355 break; 356 case 2: 357 h_table = ((tv_uv_adr & RADEON_TABLE3_TOP_ADR_MASK) >> RADEON_TABLE3_TOP_ADR_SHIFT) * 2; 358 break; 359 default: 360 h_table = 0; 361 break; 362 } 363 return h_table; 364} 365 366static uint16_t radeon_get_vtiming_tables_addr(uint32_t tv_uv_adr) 367{ 368 uint16_t v_table; 369 370 switch ((tv_uv_adr & RADEON_VCODE_TABLE_SEL_MASK) >> RADEON_VCODE_TABLE_SEL_SHIFT) { 371 case 0: 372 v_table = ((tv_uv_adr & RADEON_MAX_UV_ADR_MASK) >> RADEON_MAX_UV_ADR_SHIFT) * 2 + 1; 373 break; 374 case 1: 375 v_table = ((tv_uv_adr & RADEON_TABLE1_BOT_ADR_MASK) >> RADEON_TABLE1_BOT_ADR_SHIFT) * 2 + 1; 376 break; 377 case 2: 378 v_table = ((tv_uv_adr & RADEON_TABLE3_TOP_ADR_MASK) >> RADEON_TABLE3_TOP_ADR_SHIFT) * 2 + 1; 379 break; 380 default: 381 v_table = 0; 382 break; 383 } 384 return v_table; 385} 386 387static void radeon_restore_tv_timing_tables(struct radeon_encoder *radeon_encoder) 388{ 389 struct drm_device *dev = radeon_encoder->base.dev; 390 struct radeon_device *rdev = dev->dev_private; 391 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; 392 uint16_t h_table, v_table; 393 uint32_t tmp; 394 int i; 395 396 WREG32(RADEON_TV_UV_ADR, tv_dac->tv.tv_uv_adr); 397 h_table = radeon_get_htiming_tables_addr(tv_dac->tv.tv_uv_adr); 398 v_table = radeon_get_vtiming_tables_addr(tv_dac->tv.tv_uv_adr); 399 400 for (i = 0; i < MAX_H_CODE_TIMING_LEN; i += 2, h_table--) { 401 tmp = ((uint32_t)tv_dac->tv.h_code_timing[i] << 14) | ((uint32_t)tv_dac->tv.h_code_timing[i+1]); 402 radeon_legacy_tv_write_fifo(radeon_encoder, h_table, tmp); 403 if (tv_dac->tv.h_code_timing[i] == 0 || tv_dac->tv.h_code_timing[i + 1] == 0) 404 break; 405 } 406 for (i = 0; i < MAX_V_CODE_TIMING_LEN; i += 2, v_table++) { 407 tmp = ((uint32_t)tv_dac->tv.v_code_timing[i+1] << 14) | ((uint32_t)tv_dac->tv.v_code_timing[i]); 408 radeon_legacy_tv_write_fifo(radeon_encoder, v_table, tmp); 409 if (tv_dac->tv.v_code_timing[i] == 0 || tv_dac->tv.v_code_timing[i + 1] == 0) 410 break; 411 } 412} 413 414static void radeon_legacy_write_tv_restarts(struct radeon_encoder *radeon_encoder) 415{ 416 struct drm_device *dev = radeon_encoder->base.dev; 417 struct radeon_device *rdev = dev->dev_private; 418 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; 419 WREG32(RADEON_TV_FRESTART, tv_dac->tv.frestart); 420 WREG32(RADEON_TV_HRESTART, tv_dac->tv.hrestart); 421 WREG32(RADEON_TV_VRESTART, tv_dac->tv.vrestart); 422} 423 424static bool radeon_legacy_tv_init_restarts(struct drm_encoder *encoder) 425{ 426 struct drm_device *dev = encoder->dev; 427 struct radeon_device *rdev = dev->dev_private; 428 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 429 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; 430 struct radeon_crtc *radeon_crtc; 431 int restart; 432 unsigned int h_total, v_total, f_total; 433 int v_offset, h_offset; 434 u16 p1, p2, h_inc; 435 bool h_changed; 436 const struct radeon_tv_mode_constants *const_ptr; 437 struct radeon_pll *pll; 438 439 radeon_crtc = to_radeon_crtc(radeon_encoder->base.crtc); 440 if (radeon_crtc->crtc_id == 1) 441 pll = &rdev->clock.p2pll; 442 else 443 pll = &rdev->clock.p1pll; 444 445 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL); 446 if (!const_ptr) 447 return false; 448 449 h_total = const_ptr->hor_total; 450 v_total = const_ptr->ver_total; 451 452 if (tv_dac->tv_std == TV_STD_NTSC || 453 tv_dac->tv_std == TV_STD_NTSC_J || 454 tv_dac->tv_std == TV_STD_PAL_M || 455 tv_dac->tv_std == TV_STD_PAL_60) 456 f_total = NTSC_TV_VFTOTAL + 1; 457 else 458 f_total = PAL_TV_VFTOTAL + 1; 459 460 /* adjust positions 1&2 in hor. cod timing table */ 461 h_offset = tv_dac->h_pos * H_POS_UNIT; 462 463 if (tv_dac->tv_std == TV_STD_NTSC || 464 tv_dac->tv_std == TV_STD_NTSC_J || 465 tv_dac->tv_std == TV_STD_PAL_M) { 466 h_offset -= 50; 467 p1 = hor_timing_NTSC[H_TABLE_POS1]; 468 p2 = hor_timing_NTSC[H_TABLE_POS2]; 469 } else { 470 p1 = hor_timing_PAL[H_TABLE_POS1]; 471 p2 = hor_timing_PAL[H_TABLE_POS2]; 472 } 473 474 p1 = (u16)((int)p1 + h_offset); 475 p2 = (u16)((int)p2 - h_offset); 476 477 h_changed = (p1 != tv_dac->tv.h_code_timing[H_TABLE_POS1] || 478 p2 != tv_dac->tv.h_code_timing[H_TABLE_POS2]); 479 480 tv_dac->tv.h_code_timing[H_TABLE_POS1] = p1; 481 tv_dac->tv.h_code_timing[H_TABLE_POS2] = p2; 482 483 /* Convert hOffset from n. of TV clock periods to n. of CRTC clock periods (CRTC pixels) */ 484 h_offset = (h_offset * (int)(const_ptr->pix_to_tv)) / 1000; 485 486 /* adjust restart */ 487 restart = const_ptr->def_restart; 488 489 /* 490 * convert v_pos TV lines to n. of CRTC pixels 491 */ 492 if (tv_dac->tv_std == TV_STD_NTSC || 493 tv_dac->tv_std == TV_STD_NTSC_J || 494 tv_dac->tv_std == TV_STD_PAL_M || 495 tv_dac->tv_std == TV_STD_PAL_60) 496 v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(NTSC_TV_LINES_PER_FRAME); 497 else 498 v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(PAL_TV_LINES_PER_FRAME); 499 500 restart -= v_offset + h_offset; 501 502 DRM_DEBUG_KMS("compute_restarts: def = %u h = %d v = %d, p1 = %04x, p2 = %04x, restart = %d\n", 503 const_ptr->def_restart, tv_dac->h_pos, tv_dac->v_pos, p1, p2, restart); 504 505 tv_dac->tv.hrestart = restart % h_total; 506 restart /= h_total; 507 tv_dac->tv.vrestart = restart % v_total; 508 restart /= v_total; 509 tv_dac->tv.frestart = restart % f_total; 510 511 DRM_DEBUG_KMS("compute_restart: F/H/V=%u,%u,%u\n", 512 (unsigned)tv_dac->tv.frestart, 513 (unsigned)tv_dac->tv.vrestart, 514 (unsigned)tv_dac->tv.hrestart); 515 516 /* compute h_inc from hsize */ 517 if (tv_dac->tv_std == TV_STD_NTSC || 518 tv_dac->tv_std == TV_STD_NTSC_J || 519 tv_dac->tv_std == TV_STD_PAL_M) 520 h_inc = (u16)((int)(const_ptr->hor_resolution * 4096 * NTSC_TV_CLOCK_T) / 521 (tv_dac->h_size * (int)(NTSC_TV_H_SIZE_UNIT) + (int)(NTSC_TV_ZERO_H_SIZE))); 522 else 523 h_inc = (u16)((int)(const_ptr->hor_resolution * 4096 * PAL_TV_CLOCK_T) / 524 (tv_dac->h_size * (int)(PAL_TV_H_SIZE_UNIT) + (int)(PAL_TV_ZERO_H_SIZE))); 525 526 tv_dac->tv.timing_cntl = (tv_dac->tv.timing_cntl & ~RADEON_H_INC_MASK) | 527 ((u32)h_inc << RADEON_H_INC_SHIFT); 528 529 DRM_DEBUG_KMS("compute_restart: h_size = %d h_inc = %d\n", tv_dac->h_size, h_inc); 530 531 return h_changed; 532} 533 534void radeon_legacy_tv_mode_set(struct drm_encoder *encoder, 535 struct drm_display_mode *mode, 536 struct drm_display_mode *adjusted_mode) 537{ 538 struct drm_device *dev = encoder->dev; 539 struct radeon_device *rdev = dev->dev_private; 540 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 541 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; 542 const struct radeon_tv_mode_constants *const_ptr; 543 struct radeon_crtc *radeon_crtc; 544 int i; 545 uint16_t pll_ref_freq; 546 uint32_t vert_space, flicker_removal, tmp; 547 uint32_t tv_master_cntl, tv_rgb_cntl, tv_dac_cntl; 548 uint32_t tv_modulator_cntl1, tv_modulator_cntl2; 549 uint32_t tv_vscaler_cntl1, tv_vscaler_cntl2; 550 uint32_t tv_pll_cntl, tv_pll_cntl1, tv_ftotal; 551 uint32_t tv_y_fall_cntl, tv_y_rise_cntl, tv_y_saw_tooth_cntl; 552 uint32_t m, n, p; 553 const uint16_t *hor_timing; 554 const uint16_t *vert_timing; 555 556 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, &pll_ref_freq); 557 if (!const_ptr) 558 return; 559 560 radeon_crtc = to_radeon_crtc(encoder->crtc); 561 562 tv_master_cntl = (RADEON_VIN_ASYNC_RST | 563 RADEON_CRT_FIFO_CE_EN | 564 RADEON_TV_FIFO_CE_EN | 565 RADEON_TV_ON); 566 567 if (!ASIC_IS_R300(rdev)) 568 tv_master_cntl |= RADEON_TVCLK_ALWAYS_ONb; 569 570 if (tv_dac->tv_std == TV_STD_NTSC || 571 tv_dac->tv_std == TV_STD_NTSC_J) 572 tv_master_cntl |= RADEON_RESTART_PHASE_FIX; 573 574 tv_modulator_cntl1 = (RADEON_SLEW_RATE_LIMIT | 575 RADEON_SYNC_TIP_LEVEL | 576 RADEON_YFLT_EN | 577 RADEON_UVFLT_EN | 578 (6 << RADEON_CY_FILT_BLEND_SHIFT)); 579 580 if (tv_dac->tv_std == TV_STD_NTSC || 581 tv_dac->tv_std == TV_STD_NTSC_J) { 582 tv_modulator_cntl1 |= (0x46 << RADEON_SET_UP_LEVEL_SHIFT) | 583 (0x3b << RADEON_BLANK_LEVEL_SHIFT); 584 tv_modulator_cntl2 = (-111 & RADEON_TV_U_BURST_LEVEL_MASK) | 585 ((0 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT); 586 } else if (tv_dac->tv_std == TV_STD_SCART_PAL) { 587 tv_modulator_cntl1 |= RADEON_ALT_PHASE_EN; 588 tv_modulator_cntl2 = (0 & RADEON_TV_U_BURST_LEVEL_MASK) | 589 ((0 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT); 590 } else { 591 tv_modulator_cntl1 |= RADEON_ALT_PHASE_EN | 592 (0x3b << RADEON_SET_UP_LEVEL_SHIFT) | 593 (0x3b << RADEON_BLANK_LEVEL_SHIFT); 594 tv_modulator_cntl2 = (-78 & RADEON_TV_U_BURST_LEVEL_MASK) | 595 ((62 & RADEON_TV_V_BURST_LEVEL_MASK) << RADEON_TV_V_BURST_LEVEL_SHIFT); 596 } 597 598 599 tv_rgb_cntl = (RADEON_RGB_DITHER_EN 600 | RADEON_TVOUT_SCALE_EN 601 | (0x0b << RADEON_UVRAM_READ_MARGIN_SHIFT) 602 | (0x07 << RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT) 603 | RADEON_RGB_ATTEN_SEL(0x3) 604 | RADEON_RGB_ATTEN_VAL(0xc)); 605 606 if (radeon_crtc->crtc_id == 1) 607 tv_rgb_cntl |= RADEON_RGB_SRC_SEL_CRTC2; 608 else { 609 if (radeon_crtc->rmx_type != RMX_OFF) 610 tv_rgb_cntl |= RADEON_RGB_SRC_SEL_RMX; 611 else 612 tv_rgb_cntl |= RADEON_RGB_SRC_SEL_CRTC1; 613 } 614 615 if (tv_dac->tv_std == TV_STD_NTSC || 616 tv_dac->tv_std == TV_STD_NTSC_J || 617 tv_dac->tv_std == TV_STD_PAL_M || 618 tv_dac->tv_std == TV_STD_PAL_60) 619 vert_space = const_ptr->ver_total * 2 * 10000 / NTSC_TV_LINES_PER_FRAME; 620 else 621 vert_space = const_ptr->ver_total * 2 * 10000 / PAL_TV_LINES_PER_FRAME; 622 623 tmp = RREG32(RADEON_TV_VSCALER_CNTL1); 624 tmp &= 0xe3ff0000; 625 tmp |= (vert_space * (1 << FRAC_BITS) / 10000); 626 tv_vscaler_cntl1 = tmp; 627 628 if (pll_ref_freq == 2700) 629 tv_vscaler_cntl1 |= RADEON_RESTART_FIELD; 630 631 if (const_ptr->hor_resolution == 1024) 632 tv_vscaler_cntl1 |= (4 << RADEON_Y_DEL_W_SIG_SHIFT); 633 else 634 tv_vscaler_cntl1 |= (2 << RADEON_Y_DEL_W_SIG_SHIFT); 635 636 /* scale up for int divide */ 637 tmp = const_ptr->ver_total * 2 * 1000; 638 if (tv_dac->tv_std == TV_STD_NTSC || 639 tv_dac->tv_std == TV_STD_NTSC_J || 640 tv_dac->tv_std == TV_STD_PAL_M || 641 tv_dac->tv_std == TV_STD_PAL_60) { 642 tmp /= NTSC_TV_LINES_PER_FRAME; 643 } else { 644 tmp /= PAL_TV_LINES_PER_FRAME; 645 } 646 flicker_removal = (tmp + 500) / 1000; 647 648 if (flicker_removal < 3) 649 flicker_removal = 3; 650 for (i = 0; i < DRM_ARRAY_SIZE(SLOPE_limit); ++i) { 651 if (flicker_removal == SLOPE_limit[i]) 652 break; 653 } 654 655 tv_y_saw_tooth_cntl = (vert_space * SLOPE_value[i] * (1 << (FRAC_BITS - 1)) + 656 5001) / 10000 / 8 | ((SLOPE_value[i] * 657 (1 << (FRAC_BITS - 1)) / 8) << 16); 658 tv_y_fall_cntl = 659 (YCOEF_EN_value[i] << 17) | ((YCOEF_value[i] * (1 << 8) / 8) << 24) | 660 RADEON_Y_FALL_PING_PONG | (272 * SLOPE_value[i] / 8) * (1 << (FRAC_BITS - 1)) / 661 1024; 662 tv_y_rise_cntl = RADEON_Y_RISE_PING_PONG| 663 (flicker_removal * 1024 - 272) * SLOPE_value[i] / 8 * (1 << (FRAC_BITS - 1)) / 1024; 664 665 tv_vscaler_cntl2 = RREG32(RADEON_TV_VSCALER_CNTL2) & 0x00fffff0; 666 tv_vscaler_cntl2 |= (0x10 << 24) | 667 RADEON_DITHER_MODE | 668 RADEON_Y_OUTPUT_DITHER_EN | 669 RADEON_UV_OUTPUT_DITHER_EN | 670 RADEON_UV_TO_BUF_DITHER_EN; 671 672 tmp = (tv_vscaler_cntl1 >> RADEON_UV_INC_SHIFT) & RADEON_UV_INC_MASK; 673 tmp = ((16384 * 256 * 10) / tmp + 5) / 10; 674 tmp = (tmp << RADEON_UV_OUTPUT_POST_SCALE_SHIFT) | 0x000b0000; 675 tv_dac->tv.timing_cntl = tmp; 676 677 if (tv_dac->tv_std == TV_STD_NTSC || 678 tv_dac->tv_std == TV_STD_NTSC_J || 679 tv_dac->tv_std == TV_STD_PAL_M || 680 tv_dac->tv_std == TV_STD_PAL_60) 681 tv_dac_cntl = tv_dac->ntsc_tvdac_adj; 682 else 683 tv_dac_cntl = tv_dac->pal_tvdac_adj; 684 685 tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD; 686 687 if (tv_dac->tv_std == TV_STD_NTSC || 688 tv_dac->tv_std == TV_STD_NTSC_J) 689 tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC; 690 else 691 tv_dac_cntl |= RADEON_TV_DAC_STD_PAL; 692 693 if (tv_dac->tv_std == TV_STD_NTSC || 694 tv_dac->tv_std == TV_STD_NTSC_J) { 695 if (pll_ref_freq == 2700) { 696 m = NTSC_TV_PLL_M_27; 697 n = NTSC_TV_PLL_N_27; 698 p = NTSC_TV_PLL_P_27; 699 } else { 700 m = NTSC_TV_PLL_M_14; 701 n = NTSC_TV_PLL_N_14; 702 p = NTSC_TV_PLL_P_14; 703 } 704 } else { 705 if (pll_ref_freq == 2700) { 706 m = PAL_TV_PLL_M_27; 707 n = PAL_TV_PLL_N_27; 708 p = PAL_TV_PLL_P_27; 709 } else { 710 m = PAL_TV_PLL_M_14; 711 n = PAL_TV_PLL_N_14; 712 p = PAL_TV_PLL_P_14; 713 } 714 } 715 716 tv_pll_cntl = (m & RADEON_TV_M0LO_MASK) | 717 (((m >> 8) & RADEON_TV_M0HI_MASK) << RADEON_TV_M0HI_SHIFT) | 718 ((n & RADEON_TV_N0LO_MASK) << RADEON_TV_N0LO_SHIFT) | 719 (((n >> 9) & RADEON_TV_N0HI_MASK) << RADEON_TV_N0HI_SHIFT) | 720 ((p & RADEON_TV_P_MASK) << RADEON_TV_P_SHIFT); 721 722 tv_pll_cntl1 = (((4 & RADEON_TVPCP_MASK) << RADEON_TVPCP_SHIFT) | 723 ((4 & RADEON_TVPVG_MASK) << RADEON_TVPVG_SHIFT) | 724 ((1 & RADEON_TVPDC_MASK) << RADEON_TVPDC_SHIFT) | 725 RADEON_TVCLK_SRC_SEL_TVPLL | 726 RADEON_TVPLL_TEST_DIS); 727 728 tv_dac->tv.tv_uv_adr = 0xc8; 729 730 if (tv_dac->tv_std == TV_STD_NTSC || 731 tv_dac->tv_std == TV_STD_NTSC_J || 732 tv_dac->tv_std == TV_STD_PAL_M || 733 tv_dac->tv_std == TV_STD_PAL_60) { 734 tv_ftotal = NTSC_TV_VFTOTAL; 735 hor_timing = hor_timing_NTSC; 736 vert_timing = vert_timing_NTSC; 737 } else { 738 hor_timing = hor_timing_PAL; 739 vert_timing = vert_timing_PAL; 740 tv_ftotal = PAL_TV_VFTOTAL; 741 } 742 743 for (i = 0; i < MAX_H_CODE_TIMING_LEN; i++) { 744 if ((tv_dac->tv.h_code_timing[i] = hor_timing[i]) == 0) 745 break; 746 } 747 748 for (i = 0; i < MAX_V_CODE_TIMING_LEN; i++) { 749 if ((tv_dac->tv.v_code_timing[i] = vert_timing[i]) == 0) 750 break; 751 } 752 753 radeon_legacy_tv_init_restarts(encoder); 754 755 /* play with DAC_CNTL */ 756 /* play with GPIOPAD_A */ 757 /* DISP_OUTPUT_CNTL */ 758 /* use reference freq */ 759 760 /* program the TV registers */ 761 WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST | 762 RADEON_CRT_ASYNC_RST | RADEON_TV_FIFO_ASYNC_RST)); 763 764 tmp = RREG32(RADEON_TV_DAC_CNTL); 765 tmp &= ~RADEON_TV_DAC_NBLANK; 766 tmp |= RADEON_TV_DAC_BGSLEEP | 767 RADEON_TV_DAC_RDACPD | 768 RADEON_TV_DAC_GDACPD | 769 RADEON_TV_DAC_BDACPD; 770 WREG32(RADEON_TV_DAC_CNTL, tmp); 771 772 /* TV PLL */ 773 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVCLK_SRC_SEL_TVPLL); 774 WREG32_PLL(RADEON_TV_PLL_CNTL, tv_pll_cntl); 775 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVPLL_RESET, ~RADEON_TVPLL_RESET); 776 777 radeon_wait_pll_lock(encoder, 200, 800, 135); 778 779 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_RESET); 780 781 radeon_wait_pll_lock(encoder, 300, 160, 27); 782 radeon_wait_pll_lock(encoder, 200, 800, 135); 783 784 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~0xf); 785 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, RADEON_TVCLK_SRC_SEL_TVPLL, ~RADEON_TVCLK_SRC_SEL_TVPLL); 786 787 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, (1 << RADEON_TVPDC_SHIFT), ~RADEON_TVPDC_MASK); 788 WREG32_PLL_P(RADEON_TV_PLL_CNTL1, 0, ~RADEON_TVPLL_SLEEP); 789 790 /* TV HV */ 791 WREG32(RADEON_TV_RGB_CNTL, tv_rgb_cntl); 792 WREG32(RADEON_TV_HTOTAL, const_ptr->hor_total - 1); 793 WREG32(RADEON_TV_HDISP, const_ptr->hor_resolution - 1); 794 WREG32(RADEON_TV_HSTART, const_ptr->hor_start); 795 796 WREG32(RADEON_TV_VTOTAL, const_ptr->ver_total - 1); 797 WREG32(RADEON_TV_VDISP, const_ptr->ver_resolution - 1); 798 WREG32(RADEON_TV_FTOTAL, tv_ftotal); 799 WREG32(RADEON_TV_VSCALER_CNTL1, tv_vscaler_cntl1); 800 WREG32(RADEON_TV_VSCALER_CNTL2, tv_vscaler_cntl2); 801 802 WREG32(RADEON_TV_Y_FALL_CNTL, tv_y_fall_cntl); 803 WREG32(RADEON_TV_Y_RISE_CNTL, tv_y_rise_cntl); 804 WREG32(RADEON_TV_Y_SAW_TOOTH_CNTL, tv_y_saw_tooth_cntl); 805 806 WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST | 807 RADEON_CRT_ASYNC_RST)); 808 809 /* TV restarts */ 810 radeon_legacy_write_tv_restarts(radeon_encoder); 811 812 /* tv timings */ 813 radeon_restore_tv_timing_tables(radeon_encoder); 814 815 WREG32(RADEON_TV_MASTER_CNTL, (tv_master_cntl | RADEON_TV_ASYNC_RST)); 816 817 /* tv std */ 818 WREG32(RADEON_TV_SYNC_CNTL, (RADEON_SYNC_PUB | RADEON_TV_SYNC_IO_DRIVE)); 819 WREG32(RADEON_TV_TIMING_CNTL, tv_dac->tv.timing_cntl); 820 WREG32(RADEON_TV_MODULATOR_CNTL1, tv_modulator_cntl1); 821 WREG32(RADEON_TV_MODULATOR_CNTL2, tv_modulator_cntl2); 822 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, (RADEON_Y_RED_EN | 823 RADEON_C_GRN_EN | 824 RADEON_CMP_BLU_EN | 825 RADEON_DAC_DITHER_EN)); 826 827 WREG32(RADEON_TV_CRC_CNTL, 0); 828 829 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); 830 831 WREG32(RADEON_TV_GAIN_LIMIT_SETTINGS, ((0x17f << RADEON_UV_GAIN_LIMIT_SHIFT) | 832 (0x5ff << RADEON_Y_GAIN_LIMIT_SHIFT))); 833 WREG32(RADEON_TV_LINEAR_GAIN_SETTINGS, ((0x100 << RADEON_UV_GAIN_SHIFT) | 834 (0x100 << RADEON_Y_GAIN_SHIFT))); 835 836 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 837 838} 839 840void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder, 841 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid, 842 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid) 843{ 844 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 845 const struct radeon_tv_mode_constants *const_ptr; 846 uint32_t tmp; 847 848 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL); 849 if (!const_ptr) 850 return; 851 852 *h_total_disp = (((const_ptr->hor_resolution / 8) - 1) << RADEON_CRTC_H_DISP_SHIFT) | 853 (((const_ptr->hor_total / 8) - 1) << RADEON_CRTC_H_TOTAL_SHIFT); 854 855 tmp = *h_sync_strt_wid; 856 tmp &= ~(RADEON_CRTC_H_SYNC_STRT_PIX | RADEON_CRTC_H_SYNC_STRT_CHAR); 857 tmp |= (((const_ptr->hor_syncstart / 8) - 1) << RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT) | 858 (const_ptr->hor_syncstart & 7); 859 *h_sync_strt_wid = tmp; 860 861 *v_total_disp = ((const_ptr->ver_resolution - 1) << RADEON_CRTC_V_DISP_SHIFT) | 862 ((const_ptr->ver_total - 1) << RADEON_CRTC_V_TOTAL_SHIFT); 863 864 tmp = *v_sync_strt_wid; 865 tmp &= ~RADEON_CRTC_V_SYNC_STRT; 866 tmp |= ((const_ptr->ver_syncstart - 1) << RADEON_CRTC_V_SYNC_STRT_SHIFT); 867 *v_sync_strt_wid = tmp; 868} 869 870static int get_post_div(int value) 871{ 872 int post_div; 873 switch (value) { 874 case 1: post_div = 0; break; 875 case 2: post_div = 1; break; 876 case 3: post_div = 4; break; 877 case 4: post_div = 2; break; 878 case 6: post_div = 6; break; 879 case 8: post_div = 3; break; 880 case 12: post_div = 7; break; 881 case 16: 882 default: post_div = 5; break; 883 } 884 return post_div; 885} 886 887void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder, 888 uint32_t *htotal_cntl, uint32_t *ppll_ref_div, 889 uint32_t *ppll_div_3, uint32_t *pixclks_cntl) 890{ 891 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 892 const struct radeon_tv_mode_constants *const_ptr; 893 894 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL); 895 if (!const_ptr) 896 return; 897 898 *htotal_cntl = (const_ptr->hor_total & 0x7) | RADEON_HTOT_CNTL_VGA_EN; 899 900 *ppll_ref_div = const_ptr->crtcPLL_M; 901 902 *ppll_div_3 = (const_ptr->crtcPLL_N & 0x7ff) | (get_post_div(const_ptr->crtcPLL_post_div) << 16); 903 *pixclks_cntl &= ~(RADEON_PIX2CLK_SRC_SEL_MASK | RADEON_PIXCLK_TV_SRC_SEL); 904 *pixclks_cntl |= RADEON_PIX2CLK_SRC_SEL_P2PLLCLK; 905} 906 907void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder, 908 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div, 909 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl) 910{ 911 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 912 const struct radeon_tv_mode_constants *const_ptr; 913 914 const_ptr = radeon_legacy_tv_get_std_mode(radeon_encoder, NULL); 915 if (!const_ptr) 916 return; 917 918 *htotal2_cntl = (const_ptr->hor_total & 0x7); 919 920 *p2pll_ref_div = const_ptr->crtcPLL_M; 921 922 *p2pll_div_0 = (const_ptr->crtcPLL_N & 0x7ff) | (get_post_div(const_ptr->crtcPLL_post_div) << 16); 923 *pixclks_cntl &= ~RADEON_PIX2CLK_SRC_SEL_MASK; 924 *pixclks_cntl |= RADEON_PIX2CLK_SRC_SEL_P2PLLCLK | RADEON_PIXCLK_TV_SRC_SEL; 925} 926 927