1218792Snp/*- 2218792Snp * Copyright (c) 2011 Chelsio Communications, Inc. 3218792Snp * All rights reserved. 4218792Snp * Written by: Navdeep Parhar <np@FreeBSD.org> 5218792Snp * 6218792Snp * Redistribution and use in source and binary forms, with or without 7218792Snp * modification, are permitted provided that the following conditions 8218792Snp * are met: 9218792Snp * 1. Redistributions of source code must retain the above copyright 10218792Snp * notice, this list of conditions and the following disclaimer. 11218792Snp * 2. Redistributions in binary form must reproduce the above copyright 12218792Snp * notice, this list of conditions and the following disclaimer in the 13218792Snp * documentation and/or other materials provided with the distribution. 14218792Snp * 15218792Snp * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16218792Snp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17218792Snp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18218792Snp * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19218792Snp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20218792Snp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21218792Snp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22218792Snp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23218792Snp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24218792Snp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25218792Snp * SUCH DAMAGE. 26218792Snp * 27218792Snp * $FreeBSD$ 28218792Snp * 29218792Snp */ 30218792Snp 31218792Snp#ifndef __T4_IOCTL_H__ 32218792Snp#define __T4_IOCTL_H__ 33218792Snp 34221474Snp#include <sys/types.h> 35221474Snp#include <net/ethernet.h> 36221474Snp 37218792Snp/* 38218792Snp * Ioctl commands specific to this driver. 39218792Snp */ 40218792Snpenum { 41220410Snp T4_GETREG = 0x40, /* read register */ 42220410Snp T4_SETREG, /* write register */ 43218792Snp T4_REGDUMP, /* dump of all registers */ 44221474Snp T4_GET_FILTER_MODE, /* get global filter mode */ 45221474Snp T4_SET_FILTER_MODE, /* set global filter mode */ 46221474Snp T4_GET_FILTER, /* get information about a filter */ 47221474Snp T4_SET_FILTER, /* program a filter */ 48221474Snp T4_DEL_FILTER, /* delete a filter */ 49222973Snp T4_GET_SGE_CONTEXT, /* get SGE context for a queue */ 50228561Snp T4_LOAD_FW, /* flash firmware */ 51228561Snp T4_GET_MEM, /* read memory */ 52241399Snp T4_GET_I2C, /* read from i2c addressible device */ 53241409Snp T4_CLEAR_STATS, /* clear a port's MAC statistics */ 54253688Snp T4_SET_OFLD_POLICY, /* Set offload policy */ 55253688Snp T4_SET_SCHED_CLASS, /* set sched class */ 56253688Snp T4_SET_SCHED_QUEUE, /* set queue class */ 57253691Snp T4_GET_TRACER, /* get information about a tracer */ 58253691Snp T4_SET_TRACER, /* program a tracer */ 59218792Snp}; 60218792Snp 61220410Snpstruct t4_reg { 62218792Snp uint32_t addr; 63220410Snp uint32_t size; 64220410Snp uint64_t val; 65218792Snp}; 66218792Snp 67218792Snp#define T4_REGDUMP_SIZE (160 * 1024) 68248925Snp#define T5_REGDUMP_SIZE (332 * 1024) 69218792Snpstruct t4_regdump { 70220410Snp uint32_t version; 71220410Snp uint32_t len; /* bytes */ 72220410Snp uint32_t *data; 73218792Snp}; 74218792Snp 75228561Snpstruct t4_data { 76228561Snp uint32_t len; 77228561Snp uint8_t *data; 78228561Snp}; 79228561Snp 80241399Snpstruct t4_i2c_data { 81241399Snp uint8_t port_id; 82241399Snp uint8_t dev_addr; 83241399Snp uint8_t offset; 84241399Snp uint8_t len; 85241399Snp uint8_t data[8]; 86241399Snp}; 87241399Snp 88221474Snp/* 89221474Snp * A hardware filter is some valid combination of these. 90221474Snp */ 91221474Snp#define T4_FILTER_IPv4 0x1 /* IPv4 packet */ 92221474Snp#define T4_FILTER_IPv6 0x2 /* IPv6 packet */ 93221474Snp#define T4_FILTER_IP_SADDR 0x4 /* Source IP address or network */ 94221474Snp#define T4_FILTER_IP_DADDR 0x8 /* Destination IP address or network */ 95221474Snp#define T4_FILTER_IP_SPORT 0x10 /* Source IP port */ 96221474Snp#define T4_FILTER_IP_DPORT 0x20 /* Destination IP port */ 97221474Snp#define T4_FILTER_FCoE 0x40 /* Fibre Channel over Ethernet packet */ 98221474Snp#define T4_FILTER_PORT 0x80 /* Physical ingress port */ 99228561Snp#define T4_FILTER_VNIC 0x100 /* VNIC id or outer VLAN */ 100228561Snp#define T4_FILTER_VLAN 0x200 /* VLAN ID */ 101221474Snp#define T4_FILTER_IP_TOS 0x400 /* IPv4 TOS/IPv6 Traffic Class */ 102221474Snp#define T4_FILTER_IP_PROTO 0x800 /* IP protocol */ 103221474Snp#define T4_FILTER_ETH_TYPE 0x1000 /* Ethernet Type */ 104221474Snp#define T4_FILTER_MAC_IDX 0x2000 /* MPS MAC address match index */ 105221474Snp#define T4_FILTER_MPS_HIT_TYPE 0x4000 /* MPS match type */ 106221474Snp#define T4_FILTER_IP_FRAGMENT 0x8000 /* IP fragment */ 107221474Snp 108221474Snp/* Filter action */ 109221474Snpenum { 110221474Snp FILTER_PASS = 0, /* default */ 111221474Snp FILTER_DROP, 112221474Snp FILTER_SWITCH 113221474Snp}; 114221474Snp 115221474Snp/* 802.1q manipulation on FILTER_SWITCH */ 116221474Snpenum { 117221474Snp VLAN_NOCHANGE = 0, /* default */ 118221474Snp VLAN_REMOVE, 119221474Snp VLAN_INSERT, 120221474Snp VLAN_REWRITE 121221474Snp}; 122221474Snp 123221474Snp/* MPS match type */ 124221474Snpenum { 125221474Snp UCAST_EXACT = 0, /* exact unicast match */ 126221474Snp UCAST_HASH = 1, /* inexact (hashed) unicast match */ 127221474Snp MCAST_EXACT = 2, /* exact multicast match */ 128221474Snp MCAST_HASH = 3, /* inexact (hashed) multicast match */ 129221474Snp PROMISC = 4, /* no match but port is promiscuous */ 130221474Snp HYPPROMISC = 5, /* port is hypervisor-promisuous + not bcast */ 131221474Snp BCAST = 6, /* broadcast packet */ 132221474Snp}; 133221474Snp 134221474Snp/* Rx steering */ 135221474Snpenum { 136221474Snp DST_MODE_QUEUE, /* queue is directly specified by filter */ 137221474Snp DST_MODE_RSS_QUEUE, /* filter specifies RSS entry containing queue */ 138221474Snp DST_MODE_RSS, /* queue selected by default RSS hash lookup */ 139221474Snp DST_MODE_FILT_RSS /* queue selected by hashing in filter-specified 140221474Snp RSS subtable */ 141221474Snp}; 142221474Snp 143221474Snpstruct t4_filter_tuple { 144221474Snp /* 145221474Snp * These are always available. 146221474Snp */ 147221474Snp uint8_t sip[16]; /* source IP address (IPv4 in [3:0]) */ 148221474Snp uint8_t dip[16]; /* destinatin IP address (IPv4 in [3:0]) */ 149221474Snp uint16_t sport; /* source port */ 150221474Snp uint16_t dport; /* destination port */ 151221474Snp 152221474Snp /* 153221474Snp * A combination of these (upto 36 bits) is available. TP_VLAN_PRI_MAP 154221474Snp * is used to select the global mode and all filters are limited to the 155221474Snp * set of fields allowed by the global mode. 156221474Snp */ 157228561Snp uint16_t vnic; /* VNIC id or outer VLAN tag */ 158228561Snp uint16_t vlan; /* VLAN tag */ 159221474Snp uint16_t ethtype; /* Ethernet type */ 160221474Snp uint8_t tos; /* TOS/Traffic Type */ 161221474Snp uint8_t proto; /* protocol type */ 162221474Snp uint32_t fcoe:1; /* FCoE packet */ 163221474Snp uint32_t iport:3; /* ingress port */ 164221474Snp uint32_t matchtype:3; /* MPS match type */ 165221474Snp uint32_t frag:1; /* fragmentation extension header */ 166221474Snp uint32_t macidx:9; /* exact match MAC index */ 167228561Snp uint32_t vlan_vld:1; /* VLAN valid */ 168228561Snp uint32_t vnic_vld:1; /* VNIC id/outer VLAN tag valid */ 169221474Snp}; 170221474Snp 171221474Snpstruct t4_filter_specification { 172221474Snp uint32_t hitcnts:1; /* count filter hits in TCB */ 173221474Snp uint32_t prio:1; /* filter has priority over active/server */ 174221474Snp uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 175221474Snp uint32_t action:2; /* drop, pass, switch */ 176221474Snp uint32_t rpttid:1; /* report TID in RSS hash field */ 177221474Snp uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 178221474Snp uint32_t iq:10; /* ingress queue */ 179221474Snp uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 180221474Snp uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 181221474Snp /* 1 => TCB contains IQ ID */ 182221474Snp 183221474Snp /* 184221474Snp * Switch proxy/rewrite fields. An ingress packet which matches a 185221474Snp * filter with "switch" set will be looped back out as an egress 186221474Snp * packet -- potentially with some Ethernet header rewriting. 187221474Snp */ 188221474Snp uint32_t eport:2; /* egress port to switch packet out */ 189221474Snp uint32_t newdmac:1; /* rewrite destination MAC address */ 190221474Snp uint32_t newsmac:1; /* rewrite source MAC address */ 191221474Snp uint32_t newvlan:2; /* rewrite VLAN Tag */ 192221474Snp uint8_t dmac[ETHER_ADDR_LEN]; /* new destination MAC address */ 193221474Snp uint8_t smac[ETHER_ADDR_LEN]; /* new source MAC address */ 194221474Snp uint16_t vlan; /* VLAN Tag to insert */ 195221474Snp 196221474Snp /* 197221474Snp * Filter rule value/mask pairs. 198221474Snp */ 199221474Snp struct t4_filter_tuple val; 200221474Snp struct t4_filter_tuple mask; 201221474Snp}; 202221474Snp 203221474Snpstruct t4_filter { 204221474Snp uint32_t idx; 205222509Snp uint16_t l2tidx; 206222509Snp uint16_t smtidx; 207221474Snp uint64_t hits; 208221474Snp struct t4_filter_specification fs; 209221474Snp}; 210221474Snp 211222973Snp#define T4_SGE_CONTEXT_SIZE 24 212222973Snpenum { 213222973Snp SGE_CONTEXT_EGRESS, 214222973Snp SGE_CONTEXT_INGRESS, 215222973Snp SGE_CONTEXT_FLM, 216222973Snp SGE_CONTEXT_CNM 217222973Snp}; 218222973Snp 219222973Snpstruct t4_sge_context { 220222973Snp uint32_t mem_id; 221222973Snp uint32_t cid; 222222973Snp uint32_t data[T4_SGE_CONTEXT_SIZE / 4]; 223222973Snp}; 224222973Snp 225228561Snpstruct t4_mem_range { 226228561Snp uint32_t addr; 227228561Snp uint32_t len; 228228561Snp uint32_t *data; 229228561Snp}; 230228561Snp 231253691Snp#define T4_TRACE_LEN 112 232253691Snpstruct t4_trace_params { 233253691Snp uint32_t data[T4_TRACE_LEN / 4]; 234253691Snp uint32_t mask[T4_TRACE_LEN / 4]; 235253691Snp uint16_t snap_len; 236253691Snp uint16_t min_len; 237253691Snp uint8_t skip_ofst; 238253691Snp uint8_t skip_len; 239253691Snp uint8_t invert; 240253691Snp uint8_t port; 241253691Snp}; 242253691Snp 243253691Snpstruct t4_tracer { 244253691Snp uint8_t idx; 245253691Snp uint8_t enabled; 246253691Snp uint8_t valid; 247253691Snp struct t4_trace_params tp; 248253691Snp}; 249253691Snp 250220410Snp#define CHELSIO_T4_GETREG _IOWR('f', T4_GETREG, struct t4_reg) 251220410Snp#define CHELSIO_T4_SETREG _IOW('f', T4_SETREG, struct t4_reg) 252218792Snp#define CHELSIO_T4_REGDUMP _IOWR('f', T4_REGDUMP, struct t4_regdump) 253221474Snp#define CHELSIO_T4_GET_FILTER_MODE _IOWR('f', T4_GET_FILTER_MODE, uint32_t) 254221474Snp#define CHELSIO_T4_SET_FILTER_MODE _IOW('f', T4_SET_FILTER_MODE, uint32_t) 255221474Snp#define CHELSIO_T4_GET_FILTER _IOWR('f', T4_GET_FILTER, struct t4_filter) 256221474Snp#define CHELSIO_T4_SET_FILTER _IOW('f', T4_SET_FILTER, struct t4_filter) 257221474Snp#define CHELSIO_T4_DEL_FILTER _IOW('f', T4_DEL_FILTER, struct t4_filter) 258222973Snp#define CHELSIO_T4_GET_SGE_CONTEXT _IOWR('f', T4_GET_SGE_CONTEXT, \ 259222973Snp struct t4_sge_context) 260228561Snp#define CHELSIO_T4_LOAD_FW _IOW('f', T4_LOAD_FW, struct t4_data) 261228561Snp#define CHELSIO_T4_GET_MEM _IOW('f', T4_GET_MEM, struct t4_mem_range) 262241399Snp#define CHELSIO_T4_GET_I2C _IOWR('f', T4_GET_I2C, struct t4_i2c_data) 263241409Snp#define CHELSIO_T4_CLEAR_STATS _IOW('f', T4_CLEAR_STATS, uint32_t) 264253691Snp#define CHELSIO_T4_GET_TRACER _IOWR('f', T4_GET_TRACER, struct t4_tracer) 265253691Snp#define CHELSIO_T4_SET_TRACER _IOW('f', T4_SET_TRACER, struct t4_tracer) 266218792Snp#endif 267