1/*- 2 * Copyright (c) 2011 Chelsio Communications, Inc. 3 * All rights reserved. 4 * Written by: Navdeep Parhar <np@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 * 29 */ 30 31#ifndef __T4_IOCTL_H__ 32#define __T4_IOCTL_H__ 33 34#include <sys/types.h> 35#include <net/ethernet.h> 36 37/* 38 * Ioctl commands specific to this driver. 39 */ 40enum { 41 T4_GETREG = 0x40, /* read register */ 42 T4_SETREG, /* write register */ 43 T4_REGDUMP, /* dump of all registers */ 44 T4_GET_FILTER_MODE, /* get global filter mode */ 45 T4_SET_FILTER_MODE, /* set global filter mode */ 46 T4_GET_FILTER, /* get information about a filter */ 47 T4_SET_FILTER, /* program a filter */ 48 T4_DEL_FILTER, /* delete a filter */ 49 T4_GET_SGE_CONTEXT, /* get SGE context for a queue */ 50 T4_LOAD_FW, /* flash firmware */ 51 T4_GET_MEM, /* read memory */ 52 T4_GET_I2C, /* read from i2c addressible device */ 53 T4_CLEAR_STATS, /* clear a port's MAC statistics */ 54 T4_SET_OFLD_POLICY, /* Set offload policy */ 55 T4_SET_SCHED_CLASS, /* set sched class */ 56 T4_SET_SCHED_QUEUE, /* set queue class */ 57 T4_GET_TRACER, /* get information about a tracer */ 58 T4_SET_TRACER, /* program a tracer */ 59}; 60 61struct t4_reg { 62 uint32_t addr; 63 uint32_t size; 64 uint64_t val; 65}; 66 67#define T4_REGDUMP_SIZE (160 * 1024) 68#define T5_REGDUMP_SIZE (332 * 1024) 69struct t4_regdump { 70 uint32_t version; 71 uint32_t len; /* bytes */ 72 uint32_t *data; 73}; 74 75struct t4_data { 76 uint32_t len; 77 uint8_t *data; 78}; 79 80struct t4_i2c_data { 81 uint8_t port_id; 82 uint8_t dev_addr; 83 uint8_t offset; 84 uint8_t len; 85 uint8_t data[8]; 86}; 87 88/* 89 * A hardware filter is some valid combination of these. 90 */ 91#define T4_FILTER_IPv4 0x1 /* IPv4 packet */ 92#define T4_FILTER_IPv6 0x2 /* IPv6 packet */ 93#define T4_FILTER_IP_SADDR 0x4 /* Source IP address or network */ 94#define T4_FILTER_IP_DADDR 0x8 /* Destination IP address or network */ 95#define T4_FILTER_IP_SPORT 0x10 /* Source IP port */ 96#define T4_FILTER_IP_DPORT 0x20 /* Destination IP port */ 97#define T4_FILTER_FCoE 0x40 /* Fibre Channel over Ethernet packet */ 98#define T4_FILTER_PORT 0x80 /* Physical ingress port */ 99#define T4_FILTER_VNIC 0x100 /* VNIC id or outer VLAN */ 100#define T4_FILTER_VLAN 0x200 /* VLAN ID */ 101#define T4_FILTER_IP_TOS 0x400 /* IPv4 TOS/IPv6 Traffic Class */ 102#define T4_FILTER_IP_PROTO 0x800 /* IP protocol */ 103#define T4_FILTER_ETH_TYPE 0x1000 /* Ethernet Type */ 104#define T4_FILTER_MAC_IDX 0x2000 /* MPS MAC address match index */ 105#define T4_FILTER_MPS_HIT_TYPE 0x4000 /* MPS match type */ 106#define T4_FILTER_IP_FRAGMENT 0x8000 /* IP fragment */ 107 108/* Filter action */ 109enum { 110 FILTER_PASS = 0, /* default */ 111 FILTER_DROP, 112 FILTER_SWITCH 113}; 114 115/* 802.1q manipulation on FILTER_SWITCH */ 116enum { 117 VLAN_NOCHANGE = 0, /* default */ 118 VLAN_REMOVE, 119 VLAN_INSERT, 120 VLAN_REWRITE 121}; 122 123/* MPS match type */ 124enum { 125 UCAST_EXACT = 0, /* exact unicast match */ 126 UCAST_HASH = 1, /* inexact (hashed) unicast match */ 127 MCAST_EXACT = 2, /* exact multicast match */ 128 MCAST_HASH = 3, /* inexact (hashed) multicast match */ 129 PROMISC = 4, /* no match but port is promiscuous */ 130 HYPPROMISC = 5, /* port is hypervisor-promisuous + not bcast */ 131 BCAST = 6, /* broadcast packet */ 132}; 133 134/* Rx steering */ 135enum { 136 DST_MODE_QUEUE, /* queue is directly specified by filter */ 137 DST_MODE_RSS_QUEUE, /* filter specifies RSS entry containing queue */ 138 DST_MODE_RSS, /* queue selected by default RSS hash lookup */ 139 DST_MODE_FILT_RSS /* queue selected by hashing in filter-specified 140 RSS subtable */ 141}; 142 143struct t4_filter_tuple { 144 /* 145 * These are always available. 146 */ 147 uint8_t sip[16]; /* source IP address (IPv4 in [3:0]) */ 148 uint8_t dip[16]; /* destinatin IP address (IPv4 in [3:0]) */ 149 uint16_t sport; /* source port */ 150 uint16_t dport; /* destination port */ 151 152 /* 153 * A combination of these (upto 36 bits) is available. TP_VLAN_PRI_MAP 154 * is used to select the global mode and all filters are limited to the 155 * set of fields allowed by the global mode. 156 */ 157 uint16_t vnic; /* VNIC id or outer VLAN tag */ 158 uint16_t vlan; /* VLAN tag */ 159 uint16_t ethtype; /* Ethernet type */ 160 uint8_t tos; /* TOS/Traffic Type */ 161 uint8_t proto; /* protocol type */ 162 uint32_t fcoe:1; /* FCoE packet */ 163 uint32_t iport:3; /* ingress port */ 164 uint32_t matchtype:3; /* MPS match type */ 165 uint32_t frag:1; /* fragmentation extension header */ 166 uint32_t macidx:9; /* exact match MAC index */ 167 uint32_t vlan_vld:1; /* VLAN valid */ 168 uint32_t vnic_vld:1; /* VNIC id/outer VLAN tag valid */ 169}; 170 171struct t4_filter_specification { 172 uint32_t hitcnts:1; /* count filter hits in TCB */ 173 uint32_t prio:1; /* filter has priority over active/server */ 174 uint32_t type:1; /* 0 => IPv4, 1 => IPv6 */ 175 uint32_t action:2; /* drop, pass, switch */ 176 uint32_t rpttid:1; /* report TID in RSS hash field */ 177 uint32_t dirsteer:1; /* 0 => RSS, 1 => steer to iq */ 178 uint32_t iq:10; /* ingress queue */ 179 uint32_t maskhash:1; /* dirsteer=0: store RSS hash in TCB */ 180 uint32_t dirsteerhash:1;/* dirsteer=1: 0 => TCB contains RSS hash */ 181 /* 1 => TCB contains IQ ID */ 182 183 /* 184 * Switch proxy/rewrite fields. An ingress packet which matches a 185 * filter with "switch" set will be looped back out as an egress 186 * packet -- potentially with some Ethernet header rewriting. 187 */ 188 uint32_t eport:2; /* egress port to switch packet out */ 189 uint32_t newdmac:1; /* rewrite destination MAC address */ 190 uint32_t newsmac:1; /* rewrite source MAC address */ 191 uint32_t newvlan:2; /* rewrite VLAN Tag */ 192 uint8_t dmac[ETHER_ADDR_LEN]; /* new destination MAC address */ 193 uint8_t smac[ETHER_ADDR_LEN]; /* new source MAC address */ 194 uint16_t vlan; /* VLAN Tag to insert */ 195 196 /* 197 * Filter rule value/mask pairs. 198 */ 199 struct t4_filter_tuple val; 200 struct t4_filter_tuple mask; 201}; 202 203struct t4_filter { 204 uint32_t idx; 205 uint16_t l2tidx; 206 uint16_t smtidx; 207 uint64_t hits; 208 struct t4_filter_specification fs; 209}; 210 211#define T4_SGE_CONTEXT_SIZE 24 212enum { 213 SGE_CONTEXT_EGRESS, 214 SGE_CONTEXT_INGRESS, 215 SGE_CONTEXT_FLM, 216 SGE_CONTEXT_CNM 217}; 218 219struct t4_sge_context { 220 uint32_t mem_id; 221 uint32_t cid; 222 uint32_t data[T4_SGE_CONTEXT_SIZE / 4]; 223}; 224 225struct t4_mem_range { 226 uint32_t addr; 227 uint32_t len; 228 uint32_t *data; 229}; 230 231#define T4_TRACE_LEN 112 232struct t4_trace_params { 233 uint32_t data[T4_TRACE_LEN / 4]; 234 uint32_t mask[T4_TRACE_LEN / 4]; 235 uint16_t snap_len; 236 uint16_t min_len; 237 uint8_t skip_ofst; 238 uint8_t skip_len; 239 uint8_t invert; 240 uint8_t port; 241}; 242 243struct t4_tracer { 244 uint8_t idx; 245 uint8_t enabled; 246 uint8_t valid; 247 struct t4_trace_params tp; 248}; 249 250#define CHELSIO_T4_GETREG _IOWR('f', T4_GETREG, struct t4_reg) 251#define CHELSIO_T4_SETREG _IOW('f', T4_SETREG, struct t4_reg) 252#define CHELSIO_T4_REGDUMP _IOWR('f', T4_REGDUMP, struct t4_regdump) 253#define CHELSIO_T4_GET_FILTER_MODE _IOWR('f', T4_GET_FILTER_MODE, uint32_t) 254#define CHELSIO_T4_SET_FILTER_MODE _IOW('f', T4_SET_FILTER_MODE, uint32_t) 255#define CHELSIO_T4_GET_FILTER _IOWR('f', T4_GET_FILTER, struct t4_filter) 256#define CHELSIO_T4_SET_FILTER _IOW('f', T4_SET_FILTER, struct t4_filter) 257#define CHELSIO_T4_DEL_FILTER _IOW('f', T4_DEL_FILTER, struct t4_filter) 258#define CHELSIO_T4_GET_SGE_CONTEXT _IOWR('f', T4_GET_SGE_CONTEXT, \ 259 struct t4_sge_context) 260#define CHELSIO_T4_LOAD_FW _IOW('f', T4_LOAD_FW, struct t4_data) 261#define CHELSIO_T4_GET_MEM _IOW('f', T4_GET_MEM, struct t4_mem_range) 262#define CHELSIO_T4_GET_I2C _IOWR('f', T4_GET_I2C, struct t4_i2c_data) 263#define CHELSIO_T4_CLEAR_STATS _IOW('f', T4_CLEAR_STATS, uint32_t) 264#define CHELSIO_T4_GET_TRACER _IOWR('f', T4_GET_TRACER, struct t4_tracer) 265#define CHELSIO_T4_SET_TRACER _IOW('f', T4_SET_TRACER, struct t4_tracer) 266#endif 267