1/*- 2 * Defines for Cronyx-Tau adapter driver. 3 * 4 * Copyright (C) 1994-2003 Cronyx Engineering. 5 * Author: Serge Vakulenko, <vak@cronyx.ru> 6 * 7 * This software is distributed with NO WARRANTIES, not even the implied 8 * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 9 * 10 * Authors grant any other persons or organisations permission to use 11 * or modify this software as long as this message is kept with the software, 12 * all derivative works or modified versions. 13 * 14 * Cronyx Id: ctddk.h,v 1.1.2.3 2003/12/11 17:33:44 rik Exp $ 15 * $FreeBSD$ 16 */ 17#define NBRD 3 /* the maximum number of installed boards */ 18#define NPORT 32 /* the number of i/o ports per board */ 19#define NCHAN 2 /* the number of channels on the board */ 20#define NBUF 4 /* the number of buffers per direction */ 21#define DMABUFSZ 1600 /* buffer size */ 22#define SCCBUFSZ 50 23 24#ifndef port_t 25# ifdef _M_ALPHA /* port address on Alpha under */ 26# define port_t unsigned long /* Windows NT is 32 bit long */ 27# else 28# define port_t unsigned short /* all other architectures */ 29# endif /* have 16-bit port addresses */ 30#endif 31 32/* 33 * There are tree models of Tau adapters. 34 * Each of two channels of the adapter is assigned a type: 35 * 36 * Channel 0 Channel 1 37 * ------------------------------------------ 38 * Tau T_SERIAL T_SERIAL 39 * Tau/E1 T_E1 T_E1_SERIAL 40 * Tau/G703 T_G703 T_G703_SERIAL 41 * 42 * Each channel could work in one of several modes: 43 * 44 * Channel 0 Channel 1 45 * ------------------------------------------ 46 * Tau M_ASYNC, M_ASYNC, 47 * M_HDLC M_HDLC 48 * ------------------------------------------ 49 * Tau/E1 M_E1, M_E1, 50 * M_E1 & CFG_D, M_E1 & CFG_D, 51 * M_ASYNC, 52 * M_HDLC 53 * ------------------------------------------ 54 * Tau/G703 M_G703, M_G703, 55 * M_ASYNC, 56 * M_HDLC 57 * ------------------------------------------ 58 */ 59#define B_TAU 0 /* Tau - basic model */ 60#define B_TAU_E1 1 /* Tau/E1 */ 61#define B_TAU_G703 2 /* Tau/G.703 */ 62#define B_TAU_E1C 3 /* Tau/E1 revision C */ 63#define B_TAU_E1D 4 /* Tau/E1 revision C with phony mode support */ 64#define B_TAU_G703C 5 /* Tau/G.703 revision C */ 65#define B_TAU2 6 /* Tau2 - basic model */ 66#define B_TAU2_E1 7 /* Tau2/E1 */ 67#define B_TAU2_E1D 8 /* Tau2/E1 with phony mode support */ 68#define B_TAU2_G703 9 /* Tau2/G.703 */ 69 70#define T_SERIAL 1 71#define T_E1 2 72#define T_G703 4 73#define T_E1_SERIAL (T_E1 | T_SERIAL) 74#define T_G703_SERIAL (T_G703 | T_SERIAL) 75 76#define M_ASYNC 0 /* asynchronous mode */ 77#define M_HDLC 1 /* bit-sync mode (HDLC) */ 78#define M_G703 2 79#define M_E1 3 80 81#define CFG_A 0 82#define CFG_B 1 83#define CFG_C 2 84#define CFG_D 3 85 86/* E1/G.703 interfaces - i0, i1 87 * Digital interface - d0 88 * 89 * 90 * Configuration 91 * --------------------------------------------------- 92 * CFG_A | i0<->ct0 i1<->ct1 93 * --------------------------------------------------- 94 * CFG_B | i0<->ct0 d0<->ct1 95 * | ^ 96 * | | 97 * | v 98 * | i1 99 * --------------------------------------------------- 100 * CFG_C | ct0<->i0<->ct1 101 * | ^ 102 * | | 103 * | v 104 * | i1 105 * --------------------------------------------------- 106 * CFG_D | i0(e1)<->hdlc<->hdlc<->ct0(e1) 107 * ONLY TAU/E1 | i1(e1)<->hdlc<->hdlc<->ct1(e1) 108 * | 109 */ 110 111/* 112 * Mode register 0 (MD0) bits. 113 */ 114#define MD0_STOPB_1 0 /* 1 stop bit */ 115#define MD0_STOPB_15 1 /* 1.5 stop bits */ 116#define MD0_STOPB_2 2 /* 2 stop bits */ 117 118#define MD0_MODE_ASYNC 0 /* asynchronous mode */ 119#define MD0_MODE_EXTSYNC 3 /* external byte-sync mode */ 120#define MD0_MODE_HDLC 4 /* HDLC mode */ 121 122typedef struct { 123 unsigned stopb : 2; /* stop bit length */ 124 unsigned : 2; 125 unsigned cts_rts_dcd : 1; /* auto-enable CTS/DCD/RTS */ 126 unsigned mode : 3; /* protocol mode */ 127} ct_md0_async_t; 128 129typedef struct { 130 unsigned crcpre : 1; /* CRC preset 1s / 0s */ 131 unsigned ccitt : 1; /* CRC-CCITT / CRC-16 */ 132 unsigned crc : 1; /* CRC enable */ 133 unsigned : 1; 134 unsigned cts_dcd : 1; /* auto-enable CTS/DCD */ 135 unsigned mode : 3; /* protocol mode */ 136} ct_md0_hdlc_t; 137 138/* 139 * Mode register 1 (MD1) bits. 140 */ 141#define MD1_PAR_NO 0 /* no parity */ 142#define MD1_PAR_CMD 1 /* parity bit appended by command */ 143#define MD1_PAR_EVEN 2 /* even parity */ 144#define MD1_PAR_ODD 3 /* odd parity */ 145 146#define MD1_CLEN_8 0 /* 8 bits/character */ 147#define MD1_CLEN_7 1 /* 7 bits/character */ 148#define MD1_CLEN_6 2 /* 6 bits/character */ 149#define MD1_CLEN_5 3 /* 5 bits/character */ 150 151#define MD1_CLK_1 0 /* 1/1 clock rate */ 152#define MD1_CLK_16 1 /* 1/16 clock rate */ 153#define MD1_CLK_32 2 /* 1/32 clock rate */ 154#define MD1_CLK_64 3 /* 1/64 clock rate */ 155 156#define MD1_ADDR_NOCHK 0 /* do not check address field */ 157#define MD1_ADDR_SNGLE1 1 /* single address 1 */ 158#define MD1_ADDR_SNGLE2 2 /* single address 2 */ 159#define MD1_ADDR_DUAL 3 /* dual address */ 160 161typedef struct { 162 unsigned parmode : 2; /* parity mode */ 163 unsigned rxclen : 2; /* receive character length */ 164 unsigned txclen : 2; /* transmit character length */ 165 unsigned clk : 2; /* clock rate */ 166} ct_md1_async_t; 167 168typedef struct { 169 unsigned : 6; 170 unsigned addr : 2; /* address field check */ 171} ct_md1_hdlc_t; 172 173/* 174 * Mode register 2 (MD2) bits. 175 */ 176#define MD2_FDX 0 /* full duplex communication */ 177#define MD2_RLOOP 1 /* remote loopback (auto echo) */ 178#define MD2_LLOOP 3 /* local+remote loopback */ 179 180#define MD2_DPLL_CLK_8 0 /* x8 ADPLL clock rate */ 181#define MD2_DPLL_CLK_16 1 /* x16 ADPLL clock rate */ 182#define MD2_DPLL_CLK_32 2 /* x32 ADPLL clock rate */ 183 184#define MD2_ENCOD_NRZ 0 /* NRZ encoding */ 185#define MD2_ENCOD_NRZI 1 /* NRZI encoding */ 186#define MD2_ENCOD_MANCHESTER 4 /* Manchester encoding */ 187#define MD2_ENCOD_FM0 5 /* FM0 encoding */ 188#define MD2_ENCOD_FM1 6 /* FM1 encoding */ 189 190typedef struct { 191 unsigned loop : 2; /* loopback mode */ 192 unsigned : 1; 193 unsigned dpll_clk : 2; /* ADPLL clock rate */ 194 unsigned encod : 3; /* signal encoding NRZ/NRZI/etc. */ 195} ct_md2_t; 196 197/* 198 * DMA priority control register (PCR) values. 199 */ 200#define PCR_PRIO_0_1 0 /* priority c0r > c0t > c1r > c1t */ 201#define PCR_PRIO_1_0 1 /* priority c1r > c1t > c0r > c0t */ 202#define PCR_PRIO_RX_TX 2 /* priority c0r > c1r > c0t > c1t */ 203#define PCR_PRIO_TX_RX 3 /* priority c0t > c1t > c0r > c1r */ 204#define PCR_PRIO_ROTATE 4 /* rotation priority -c0r-c0t-c1r-c1t- */ 205 206typedef struct { 207 unsigned prio : 3; /* priority of channels */ 208 unsigned noshare : 1; /* 1 - chan holds the bus until end of data */ 209 /* 0 - all channels share the bus hold */ 210 unsigned release : 1; /* 1 - release the bus between transfers */ 211 /* 0 - hold the bus until all transfers done */ 212} ct_pcr_t; 213 214typedef struct { /* hdlc channel options */ 215 ct_md0_hdlc_t md0; /* mode register 0 */ 216 ct_md1_hdlc_t md1; /* mode register 1 */ 217 unsigned char ctl; /* control register */ 218 unsigned char sa0; /* sync/address register 0 */ 219 unsigned char sa1; /* sync/address register 1 */ 220 unsigned char rxs; /* receive clock source */ 221 unsigned char txs; /* transmit clock source */ 222} ct_opt_hdlc_t; 223 224typedef struct { 225 ct_md2_t md2; /* mode register 2 */ 226 unsigned char dma_rrc; /* DMA mode receive FIFO ready level */ 227 unsigned char dma_trc0; /* DMA mode transmit FIFO empty mark */ 228 unsigned char dma_trc1; /* DMA mode transmit FIFO full mark */ 229 unsigned char pio_rrc; /* port i/o mode receive FIFO ready level */ 230 unsigned char pio_trc0; /* port i/o transmit FIFO empty mark */ 231 unsigned char pio_trc1; /* port i/o transmit FIFO full mark */ 232} ct_chan_opt_t; 233 234/* 235 * Option CLK is valid for both E1 and G.703 models. 236 * Options RATE, PCE, TEST are for G.703 only. 237 */ 238#define GCLK_INT 0 /* internal transmit clock source */ 239#define GCLK_RCV 1 /* transmit clock source = receive */ 240#define GCLK_RCLKO 2 /* tclk = receive clock of another channel */ 241 242#define GTEST_DIS 0 /* test disabled, normal operation */ 243#define GTEST_0 1 /* test "all zeros" */ 244#define GTEST_1 2 /* test "all ones" */ 245#define GTEST_01 3 /* test "0/1" */ 246 247typedef struct { /* E1/G.703 channel options */ 248 unsigned char hdb3; /* encoding HDB3/AMI */ 249 unsigned char pce; /* precoder enable */ 250 unsigned char test; /* test mode 0/1/01/disable */ 251 unsigned char crc4; /* E1 CRC4 enable */ 252 unsigned char cas; /* E1 signalling mode CAS/CCS */ 253 unsigned char higain; /* E1 high gain amplifier (30 dB) */ 254 unsigned char phony; /* E1 phony mode */ 255 unsigned char pce2; /* old PCM2 precoder compatibility */ 256 unsigned long rate; /* data rate 2048/1024/512/256/128/64 kbit/s */ 257 unsigned short level; /* G.703 input signal level, -cB */ 258} ct_opt_g703_t; 259 260typedef struct { 261 unsigned char bcr2; /* board control register 2 */ 262 ct_pcr_t pcr; /* DMA priority control register */ 263 unsigned char clk0; /* E1/G.703 chan 0 txclk src int/rcv/rclki */ 264 unsigned char clk1; /* E1/G.703 chan 1 txclk src int/rcv/rclki */ 265 unsigned char cfg; /* E1 configuration II/HI/K */ 266 unsigned long s0; /* E1 channel 0 timeslot mask */ 267 unsigned long s1; /* E1 channel 1 timeslot mask */ 268 unsigned long s2; /* E1 subchannel pass-through timeslot mask */ 269} ct_board_opt_t; 270 271/* 272 * Board control register 2 bits. 273 */ 274#define BCR2_INVTXC0 0x10 /* channel 0 invert transmit clock */ 275#define BCR2_INVTXC1 0x20 /* channel 1 invert transmit clock */ 276#define BCR2_INVRXC0 0x40 /* channel 0 invert receive clock */ 277#define BCR2_INVRXC1 0x80 /* channel 1 invert receive clock */ 278 279#define BCR2_BUS_UNLIM 0x01 /* unlimited DMA master burst length */ 280#define BCR2_BUS_RFST 0x02 /* fast read cycle bus timing */ 281#define BCR2_BUS_WFST 0x04 /* fast write cycle bus timing */ 282 283/* 284 * Receive/transmit clock source register (RXS/TXS) bits - from hdc64570.h. 285 */ 286#define CLK_MASK 0x70 /* RXC/TXC clock input mask */ 287#define CLK_LINE 0x00 /* RXC/TXC line input */ 288#define CLK_INT 0x40 /* internal baud rate generator */ 289 290#define CLK_RXS_LINE_NS 0x20 /* RXC line with noise suppression */ 291#define CLK_RXS_DPLL_INT 0x60 /* ADPLL based on internal BRG */ 292#define CLK_RXS_DPLL_LINE 0x70 /* ADPLL based on RXC line */ 293 294#define CLK_TXS_RECV 0x60 /* receive clock */ 295 296/* 297 * Control register (CTL) bits - from hdc64570.h. 298 */ 299#define CTL_RTS_INV 0x01 /* RTS control bit (inverted) */ 300#define CTL_SYNCLD 0x04 /* load SYN characters */ 301#define CTL_BRK 0x08 /* async: send break */ 302#define CTL_IDLE_MARK 0 /* HDLC: when idle, transmit mark */ 303#define CTL_IDLE_PTRN 0x10 /* HDLC: when idle, transmit an idle pattern */ 304#define CTL_UDRN_ABORT 0 /* HDLC: on underrun - abort */ 305#define CTL_UDRN_FCS 0x20 /* HDLC: on underrun - send FCS/flag */ 306 307typedef struct { 308 unsigned long bpv; /* bipolar violations */ 309 unsigned long fse; /* frame sync errors */ 310 unsigned long crce; /* CRC errors */ 311 unsigned long rcrce; /* remote CRC errors (E-bit) */ 312 unsigned long uas; /* unavailable seconds */ 313 unsigned long les; /* line errored seconds */ 314 unsigned long es; /* errored seconds */ 315 unsigned long bes; /* bursty errored seconds */ 316 unsigned long ses; /* severely errored seconds */ 317 unsigned long oofs; /* out of frame seconds */ 318 unsigned long css; /* controlled slip seconds */ 319 unsigned long dm; /* degraded minutes */ 320} ct_gstat_t; 321 322#define ESTS_NOALARM 0x0001 /* no alarm present */ 323#define ESTS_FARLOF 0x0002 /* receiving far loss of framing */ 324#define ESTS_AIS 0x0008 /* receiving all ones */ 325#define ESTS_LOF 0x0020 /* loss of framing */ 326#define ESTS_LOS 0x0040 /* loss of signal */ 327#define ESTS_AIS16 0x0100 /* receiving all ones in timeslot 16 */ 328#define ESTS_FARLOMF 0x0200 /* receiving alarm in timeslot 16 */ 329#define ESTS_LOMF 0x0400 /* loss of multiframe sync */ 330#define ESTS_TSTREQ 0x0800 /* test code detected */ 331#define ESTS_TSTERR 0x1000 /* test error */ 332 333typedef struct { 334 unsigned char data[10]; 335} ct_desc_t; 336 337typedef struct { 338 unsigned char tbuffer [NBUF] [DMABUFSZ]; /* transmit buffers */ 339 unsigned char rbuffer [NBUF] [DMABUFSZ]; /* receive buffers */ 340 ct_desc_t descbuf [4*NBUF]; /* descriptors */ 341 /* double size for alignment */ 342} ct_buf_t; 343 344#define B_NEXT(b) (*(unsigned short*)(b).data) /* next descriptor ptr */ 345#define B_PTR(b) (*(unsigned long*) ((b).data+2)) /* ptr to data buffer */ 346#define B_LEN(b) (*(unsigned short*)((b).data+6)) /* data buffer length */ 347#define B_STATUS(b) (*(unsigned short*)((b).data+8)) /* buf status, see FST */ 348 349typedef struct { 350 port_t DAR, DARB, SAR, SARB, CDA, EDA, BFL, BCR, DSR, 351 DMR, FCT, DIR, DCR, TCNT, TCONR, TCSR, TEPR; 352} ct_dmareg_t; 353 354#ifdef NDIS_MINIPORT_DRIVER 355typedef struct _ct_queue_t { /* packet queue */ 356 PNDIS_WAN_PACKET head; /* first packet in queue */ 357 PNDIS_WAN_PACKET tail; /* last packet in queue */ 358} ct_queue_t; 359#endif 360 361typedef struct _ct_chan_t { 362 port_t MD0, MD1, MD2, CTL, RXS, TXS, TMC, CMD, ST0, 363 ST1, ST2, ST3, FST, IE0, IE1, IE2, FIE, SA0, 364 SA1, IDL, TRB, RRC, TRC0, TRC1, CST; 365 ct_dmareg_t RX; /* RX DMA/timer registers */ 366 ct_dmareg_t TX; /* TX DMA/timer registers */ 367 368 unsigned char num; /* channel number, 0..1 */ 369 struct _ct_board_t *board; /* board pointer */ 370 unsigned long baud; /* data rate */ 371 unsigned char type; /* channel type */ 372 unsigned char mode; /* channel mode */ 373 ct_chan_opt_t opt; /* common channel options */ 374 ct_opt_hdlc_t hopt; /* hdlc mode options */ 375 ct_opt_g703_t gopt; /* E1/G.703 options */ 376 unsigned char dtr; /* DTR signal value */ 377 unsigned char rts; /* RTS signal value */ 378 unsigned char lx; /* LXT input bit settings */ 379 380 unsigned char *tbuf [NBUF]; /* transmit buffer */ 381 ct_desc_t *tdesc; /* transmit buffer descriptors */ 382 unsigned long tphys [NBUF]; /* transmit buffer phys address */ 383 unsigned long tdphys [NBUF]; /* transmit descr phys addresses */ 384 int tn; /* first active transmit buffer */ 385 int te; /* first active transmit buffer */ 386 387 unsigned char *rbuf [NBUF]; /* receive buffers */ 388 ct_desc_t *rdesc; /* receive buffer descriptors */ 389 unsigned long rphys [NBUF]; /* receive buffer phys address */ 390 unsigned long rdphys [NBUF]; /* receive descr phys addresses */ 391 int rn; /* first active receive buffer */ 392 393 unsigned long rintr; /* receive interrupts */ 394 unsigned long tintr; /* transmit interrupts */ 395 unsigned long mintr; /* modem interrupts */ 396 unsigned long ibytes; /* input bytes */ 397 unsigned long ipkts; /* input packets */ 398 unsigned long ierrs; /* input errors */ 399 unsigned long obytes; /* output bytes */ 400 unsigned long opkts; /* output packets */ 401 unsigned long oerrs; /* output errors */ 402 403 unsigned short status; /* line status bit mask */ 404 unsigned long totsec; /* total seconds elapsed */ 405 unsigned long cursec; /* total seconds elapsed */ 406 unsigned long degsec; /* degraded seconds */ 407 unsigned long degerr; /* errors during degraded seconds */ 408 ct_gstat_t currnt; /* current 15-min interval data */ 409 ct_gstat_t total; /* total statistics data */ 410 ct_gstat_t interval [48]; /* 12 hour period data */ 411 412 void *attach [NBUF]; /* system dependent data per buffer */ 413 void *sys; /* system dependent data per channel */ 414 int debug; 415 int debug_shadow; 416 417 int e1_first_int; 418 unsigned char *sccrx, *scctx; /* pointers to SCC rx and tx buffers */ 419 int sccrx_empty, scctx_empty; /* flags : set when buffer is empty */ 420 int sccrx_b, scctx_b; /* first byte in queue */ 421 int sccrx_e, scctx_e; /* first free byte in queue */ 422 423 /* pointers to callback functions */ 424 void (*call_on_tx) (struct _ct_chan_t*, void*, int); 425 void (*call_on_rx) (struct _ct_chan_t*, char*, int); 426 void (*call_on_msig) (struct _ct_chan_t*); 427 void (*call_on_scc) (struct _ct_chan_t*); 428 void (*call_on_err) (struct _ct_chan_t*, int); 429 430#ifdef NDIS_MINIPORT_DRIVER /* NDIS 3 - WinNT/Win95 */ 431 HTAPI_LINE htline; /* TAPI line descriptor */ 432 HTAPI_CALL htcall; /* TAPI call descriptor */ 433 NDIS_HANDLE connect; /* WAN connection context */ 434 ct_queue_t sendq; /* packets to transmit queue */ 435 ct_queue_t busyq; /* transmit busy queue */ 436 UINT state; /* line state mask */ 437 int timo; /* state timeout counter */ 438#endif 439} ct_chan_t; 440 441typedef struct _ct_board_t { 442 port_t port; /* base board port, 200..3e0 */ 443 unsigned short num; /* board number, 0..2 */ 444 unsigned char irq; /* intterupt request {3 5 7 10 11 12 15} */ 445 unsigned char dma; /* DMA request {5 6 7} */ 446 unsigned long osc; /* oscillator frequency: 10MHz or 8.192 */ 447 unsigned char type; /* board type Tau/TauE1/TauG703 */ 448 char name[16]; /* board version name */ 449 unsigned char bcr0; /* BCR0 image */ 450 unsigned char bcr1; /* BCR1 image */ 451 unsigned char bcr2; /* BCR2 image */ 452 unsigned char gmd0; /* G.703 MD0 register image */ 453 unsigned char gmd1; /* G.703 MD1 register image */ 454 unsigned char gmd2; /* G.703 MD2 register image */ 455 unsigned char e1cfg; /* E1 CFG register image */ 456 unsigned char e1syn; /* E1 SYN register image */ 457 ct_board_opt_t opt; /* board options */ 458 ct_chan_t chan[NCHAN]; /* channel structures */ 459#ifdef NDIS_MINIPORT_DRIVER /* NDIS 3 - WinNT/Win95 */ 460 PVOID ioaddr; /* mapped i/o port address */ 461 NDIS_HANDLE mh; /* miniport adapter handler */ 462 NDIS_MINIPORT_INTERRUPT irqh; /* interrupt handler */ 463 NDIS_HANDLE dmah; /* dma channel handler */ 464 ULONG bufsz; /* size of shared memory buffer */ 465 PVOID buf; /* shared memory for adapter */ 466 NDIS_PHYSICAL_ADDRESS bphys; /* shared memory phys address */ 467 NDIS_SPIN_LOCK lock; /* lock descriptor */ 468 ULONG debug; /* debug flags */ 469 ULONG idbase; /* TAPI device identifier base number */ 470 ULONG anum; /* adapter number, from inf setup script */ 471 NDIS_MINIPORT_TIMER timer; /* periodic timer structure */ 472#endif 473} ct_board_t; 474 475extern long ct_baud; 476extern unsigned char ct_chan_mode; 477 478extern ct_board_opt_t ct_board_opt_dflt; /* default board options */ 479extern ct_chan_opt_t ct_chan_opt_dflt; /* default channel options */ 480extern ct_opt_hdlc_t ct_opt_hdlc_dflt; /* default hdlc mode options */ 481extern ct_opt_g703_t ct_opt_g703_dflt; /* default E1/G.703 options */ 482 483struct _cr_dat_tst; 484int ct_probe_board (port_t port, int irq, int dma); 485void ct_init (ct_board_t *b, int num, port_t port, int irq, int dma, 486 const unsigned char *firmware, long bits, 487 const struct _cr_dat_tst *tst, const unsigned char *firmware2); 488void ct_init_board (ct_board_t *b, int num, port_t port, int irq, int dma, 489 int type, long osc); 490int ct_download (port_t port, const unsigned char *firmware, long bits, 491 const struct _cr_dat_tst *tst); 492int ct_download2 (port_t port, const unsigned char *firmware); 493int ct_setup_board (ct_board_t *b, const unsigned char *firmware, 494 long bits, const struct _cr_dat_tst *tst); 495void ct_setup_e1 (ct_board_t *b); 496void ct_setup_g703 (ct_board_t *b); 497void ct_setup_chan (ct_chan_t *c); 498void ct_update_chan (ct_chan_t *c); 499void ct_start_receiver (ct_chan_t *c, int dma, unsigned long buf1, 500 unsigned len, unsigned long buf, unsigned long lim); 501void ct_start_transmitter (ct_chan_t *c, int dma, unsigned long buf1, 502 unsigned len, unsigned long buf, unsigned long lim); 503void ct_set_dtr (ct_chan_t *c, int on); 504void ct_set_rts (ct_chan_t *c, int on); 505void ct_set_brk (ct_chan_t *c, int on); 506void ct_led (ct_board_t *b, int on); 507void ct_cmd (port_t base, int cmd); 508void ct_disable_dma (ct_board_t *b); 509void ct_reinit_board (ct_board_t *b); 510void ct_reinit_chan (ct_chan_t *c); 511int ct_get_dsr (ct_chan_t *c); 512int ct_get_cd (ct_chan_t *c); 513int ct_get_cts (ct_chan_t *c); 514int ct_get_lq (ct_chan_t *c); 515void ct_compute_clock (long hz, long baud, int *txbr, int *tmc); 516unsigned char cte_in (port_t base, unsigned char reg); 517void cte_out (port_t base, unsigned char reg, unsigned char val); 518unsigned char cte_ins (port_t base, unsigned char reg, 519 unsigned char mask); 520unsigned char cte_in2 (port_t base, unsigned char reg); 521void cte_out2 (port_t base, unsigned char reg, unsigned char val); 522void ctg_outx (ct_chan_t *c, unsigned char reg, unsigned char val); 523unsigned char ctg_inx (ct_chan_t *c, unsigned char reg); 524unsigned char cte_in2d (ct_chan_t *c); 525void cte_out2d (ct_chan_t *c, unsigned char val); 526void cte_out2c (ct_chan_t *c, unsigned char val); 527 528/* functions dealing with interrupt vector in DOS */ 529#if defined (MSDOS) || defined (__MSDOS__) 530int ddk_int_alloc (int irq, void (*func)(), void *arg); 531int ddk_int_restore (int irq); 532#endif 533 534int ct_probe_irq (ct_board_t *b, int irq); 535void ct_int_handler (ct_board_t *b); 536void ct_g703_timer (ct_chan_t *c); 537 538/* DDK errors */ 539#define CT_FRAME 1 540#define CT_CRC 2 541#define CT_OVERRUN 3 542#define CT_OVERFLOW 4 543#define CT_UNDERRUN 5 544#define CT_SCC_OVERRUN 6 545#define CT_SCC_FRAME 7 546#define CT_SCC_OVERFLOW 8 547 548int ct_open_board (ct_board_t *b, int num, port_t port, int irq, int dma); 549void ct_close_board (ct_board_t *b); 550int ct_find (port_t *board_ports); 551 552int ct_set_config (ct_board_t *b, int cfg); 553int ct_set_clk (ct_chan_t *c, int clk); 554int ct_set_ts (ct_chan_t *c, unsigned long ts); 555int ct_set_subchan (ct_board_t *b, unsigned long ts); 556int ct_set_higain (ct_chan_t *c, int on); 557void ct_set_phony (ct_chan_t *c, int on); 558 559#define ct_get_config(b) ((b)->opt.cfg) 560#define ct_get_subchan(b) ((b)->opt.s2) 561#define ct_get_higain(c) ((c)->gopt.higain) 562#define ct_get_phony(c) ((c)->gopt.phony) 563int ct_get_clk (ct_chan_t *c); 564unsigned long ct_get_ts (ct_chan_t *c); 565 566void ct_start_chan (ct_chan_t *c, ct_buf_t *cb, unsigned long phys); 567void ct_enable_receive (ct_chan_t *c, int on); 568void ct_enable_transmit (ct_chan_t *c, int on); 569int ct_receive_enabled (ct_chan_t *c); 570int ct_transmit_enabled (ct_chan_t *c); 571 572void ct_set_baud (ct_chan_t *c, unsigned long baud); 573unsigned long ct_get_baud (ct_chan_t *c); 574 575void ct_set_dpll (ct_chan_t *c, int on); 576int ct_get_dpll (ct_chan_t *c); 577 578void ct_set_nrzi (ct_chan_t *c, int on); 579int ct_get_nrzi (ct_chan_t *c); 580 581void ct_set_loop (ct_chan_t *c, int on); 582int ct_get_loop (ct_chan_t *c); 583 584void ct_set_invtxc (ct_chan_t *c, int on); 585int ct_get_invtxc (ct_chan_t *c); 586void ct_set_invrxc (ct_chan_t *c, int on); 587int ct_get_invrxc (ct_chan_t *c); 588 589int ct_buf_free (ct_chan_t *c); 590int ct_send_packet (ct_chan_t *c, unsigned char *data, int len, 591 void *attachment); 592 593void ct_start_scc (ct_chan_t *c, char *rxbuf, char * txbuf); 594int sccrx_check (ct_chan_t *c); 595int scc_read (ct_chan_t *c, unsigned char *d, int len); 596int scc_write (ct_chan_t *c, unsigned char *d, int len); 597int scc_read_byte (ct_chan_t *c); 598int scc_write_byte (ct_chan_t *c, unsigned char b); 599 600void ct_register_transmit (ct_chan_t *c, 601 void (*func) (ct_chan_t*, void *attachment, int len)); 602void ct_register_receive (ct_chan_t *c, 603 void (*func) (ct_chan_t*, char *data, int len)); 604void ct_register_error (ct_chan_t *c, 605 void (*func) (ct_chan_t *c, int data)); 606void ct_register_modem (ct_chan_t *c, void (*func) (ct_chan_t *c)); 607void ct_register_scc (ct_chan_t *c, void (*func) (ct_chan_t *c)); 608