1/*- 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD$"); 32 33/* 34 * Driver for the Atheros Wireless LAN controller. 35 * 36 * This software is derived from work of Atsushi Onoe; his contribution 37 * is greatly appreciated. 38 */ 39 40#include "opt_inet.h" 41#include "opt_ath.h" 42/* 43 * This is needed for register operations which are performed 44 * by the driver - eg, calls to ath_hal_gettsf32(). 45 * 46 * It's also required for any AH_DEBUG checks in here, eg the 47 * module dependencies. 48 */ 49#include "opt_ah.h" 50#include "opt_wlan.h" 51 52#include <sys/param.h> 53#include <sys/systm.h> 54#include <sys/sysctl.h> 55#include <sys/mbuf.h> 56#include <sys/malloc.h> 57#include <sys/lock.h> 58#include <sys/mutex.h> 59#include <sys/kernel.h> 60#include <sys/socket.h> 61#include <sys/sockio.h> 62#include <sys/errno.h> 63#include <sys/callout.h> 64#include <sys/bus.h> 65#include <sys/endian.h> 66#include <sys/kthread.h> 67#include <sys/taskqueue.h> 68#include <sys/priv.h> 69#include <sys/module.h> 70#include <sys/ktr.h> 71#include <sys/smp.h> /* for mp_ncpus */ 72 73#include <machine/bus.h> 74 75#include <net/if.h> 76#include <net/if_dl.h> 77#include <net/if_media.h> 78#include <net/if_types.h> 79#include <net/if_arp.h> 80#include <net/ethernet.h> 81#include <net/if_llc.h> 82 83#include <net80211/ieee80211_var.h> 84#include <net80211/ieee80211_regdomain.h> 85#ifdef IEEE80211_SUPPORT_SUPERG 86#include <net80211/ieee80211_superg.h> 87#endif 88#ifdef IEEE80211_SUPPORT_TDMA 89#include <net80211/ieee80211_tdma.h> 90#endif 91 92#include <net/bpf.h> 93 94#ifdef INET 95#include <netinet/in.h> 96#include <netinet/if_ether.h> 97#endif 98 99#include <dev/ath/if_athvar.h> 100#include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */ 101#include <dev/ath/ath_hal/ah_diagcodes.h> 102 103#include <dev/ath/if_ath_debug.h> 104#include <dev/ath/if_ath_misc.h> 105#include <dev/ath/if_ath_tsf.h> 106#include <dev/ath/if_ath_tx.h> 107#include <dev/ath/if_ath_sysctl.h> 108#include <dev/ath/if_ath_led.h> 109#include <dev/ath/if_ath_keycache.h> 110#include <dev/ath/if_ath_rx.h> 111#include <dev/ath/if_ath_beacon.h> 112#include <dev/ath/if_athdfs.h> 113 114#ifdef ATH_TX99_DIAG 115#include <dev/ath/ath_tx99/ath_tx99.h> 116#endif 117 118#ifdef ATH_DEBUG_ALQ 119#include <dev/ath/if_ath_alq.h> 120#endif 121 122#include <dev/ath/if_ath_lna_div.h> 123 124/* 125 * Calculate the receive filter according to the 126 * operating mode and state: 127 * 128 * o always accept unicast, broadcast, and multicast traffic 129 * o accept PHY error frames when hardware doesn't have MIB support 130 * to count and we need them for ANI (sta mode only until recently) 131 * and we are not scanning (ANI is disabled) 132 * NB: older hal's add rx filter bits out of sight and we need to 133 * blindly preserve them 134 * o probe request frames are accepted only when operating in 135 * hostap, adhoc, mesh, or monitor modes 136 * o enable promiscuous mode 137 * - when in monitor mode 138 * - if interface marked PROMISC (assumes bridge setting is filtered) 139 * o accept beacons: 140 * - when operating in station mode for collecting rssi data when 141 * the station is otherwise quiet, or 142 * - when operating in adhoc mode so the 802.11 layer creates 143 * node table entries for peers, 144 * - when scanning 145 * - when doing s/w beacon miss (e.g. for ap+sta) 146 * - when operating in ap mode in 11g to detect overlapping bss that 147 * require protection 148 * - when operating in mesh mode to detect neighbors 149 * o accept control frames: 150 * - when in monitor mode 151 * XXX HT protection for 11n 152 */ 153u_int32_t 154ath_calcrxfilter(struct ath_softc *sc) 155{ 156 struct ifnet *ifp = sc->sc_ifp; 157 struct ieee80211com *ic = ifp->if_l2com; 158 u_int32_t rfilt; 159 160 rfilt = HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 161 if (!sc->sc_needmib && !sc->sc_scanning) 162 rfilt |= HAL_RX_FILTER_PHYERR; 163 if (ic->ic_opmode != IEEE80211_M_STA) 164 rfilt |= HAL_RX_FILTER_PROBEREQ; 165 /* XXX ic->ic_monvaps != 0? */ 166 if (ic->ic_opmode == IEEE80211_M_MONITOR || (ifp->if_flags & IFF_PROMISC)) 167 rfilt |= HAL_RX_FILTER_PROM; 168 if (ic->ic_opmode == IEEE80211_M_STA || 169 ic->ic_opmode == IEEE80211_M_IBSS || 170 sc->sc_swbmiss || sc->sc_scanning) 171 rfilt |= HAL_RX_FILTER_BEACON; 172 /* 173 * NB: We don't recalculate the rx filter when 174 * ic_protmode changes; otherwise we could do 175 * this only when ic_protmode != NONE. 176 */ 177 if (ic->ic_opmode == IEEE80211_M_HOSTAP && 178 IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) 179 rfilt |= HAL_RX_FILTER_BEACON; 180 181 /* 182 * Enable hardware PS-POLL RX only for hostap mode; 183 * STA mode sends PS-POLL frames but never 184 * receives them. 185 */ 186 if (ath_hal_getcapability(sc->sc_ah, HAL_CAP_PSPOLL, 187 0, NULL) == HAL_OK && 188 ic->ic_opmode == IEEE80211_M_HOSTAP) 189 rfilt |= HAL_RX_FILTER_PSPOLL; 190 191 if (sc->sc_nmeshvaps) { 192 rfilt |= HAL_RX_FILTER_BEACON; 193 if (sc->sc_hasbmatch) 194 rfilt |= HAL_RX_FILTER_BSSID; 195 else 196 rfilt |= HAL_RX_FILTER_PROM; 197 } 198 if (ic->ic_opmode == IEEE80211_M_MONITOR) 199 rfilt |= HAL_RX_FILTER_CONTROL; 200 201 /* 202 * Enable RX of compressed BAR frames only when doing 203 * 802.11n. Required for A-MPDU. 204 */ 205 if (IEEE80211_IS_CHAN_HT(ic->ic_curchan)) 206 rfilt |= HAL_RX_FILTER_COMPBAR; 207 208 /* 209 * Enable radar PHY errors if requested by the 210 * DFS module. 211 */ 212 if (sc->sc_dodfs) 213 rfilt |= HAL_RX_FILTER_PHYRADAR; 214 215 /* 216 * Enable spectral PHY errors if requested by the 217 * spectral module. 218 */ 219 if (sc->sc_dospectral) 220 rfilt |= HAL_RX_FILTER_PHYRADAR; 221 222 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, %s if_flags 0x%x\n", 223 __func__, rfilt, ieee80211_opmode_name[ic->ic_opmode], ifp->if_flags); 224 return rfilt; 225} 226 227static int 228ath_legacy_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 229{ 230 struct ath_hal *ah = sc->sc_ah; 231 int error; 232 struct mbuf *m; 233 struct ath_desc *ds; 234 235 m = bf->bf_m; 236 if (m == NULL) { 237 /* 238 * NB: by assigning a page to the rx dma buffer we 239 * implicitly satisfy the Atheros requirement that 240 * this buffer be cache-line-aligned and sized to be 241 * multiple of the cache line size. Not doing this 242 * causes weird stuff to happen (for the 5210 at least). 243 */ 244 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 245 if (m == NULL) { 246 DPRINTF(sc, ATH_DEBUG_ANY, 247 "%s: no mbuf/cluster\n", __func__); 248 sc->sc_stats.ast_rx_nombuf++; 249 return ENOMEM; 250 } 251 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 252 253 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, 254 bf->bf_dmamap, m, 255 bf->bf_segs, &bf->bf_nseg, 256 BUS_DMA_NOWAIT); 257 if (error != 0) { 258 DPRINTF(sc, ATH_DEBUG_ANY, 259 "%s: bus_dmamap_load_mbuf_sg failed; error %d\n", 260 __func__, error); 261 sc->sc_stats.ast_rx_busdma++; 262 m_freem(m); 263 return error; 264 } 265 KASSERT(bf->bf_nseg == 1, 266 ("multi-segment packet; nseg %u", bf->bf_nseg)); 267 bf->bf_m = m; 268 } 269 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD); 270 271 /* 272 * Setup descriptors. For receive we always terminate 273 * the descriptor list with a self-linked entry so we'll 274 * not get overrun under high load (as can happen with a 275 * 5212 when ANI processing enables PHY error frames). 276 * 277 * To insure the last descriptor is self-linked we create 278 * each descriptor as self-linked and add it to the end. As 279 * each additional descriptor is added the previous self-linked 280 * entry is ``fixed'' naturally. This should be safe even 281 * if DMA is happening. When processing RX interrupts we 282 * never remove/process the last, self-linked, entry on the 283 * descriptor list. This insures the hardware always has 284 * someplace to write a new frame. 285 */ 286 /* 287 * 11N: we can no longer afford to self link the last descriptor. 288 * MAC acknowledges BA status as long as it copies frames to host 289 * buffer (or rx fifo). This can incorrectly acknowledge packets 290 * to a sender if last desc is self-linked. 291 */ 292 ds = bf->bf_desc; 293 if (sc->sc_rxslink) 294 ds->ds_link = bf->bf_daddr; /* link to self */ 295 else 296 ds->ds_link = 0; /* terminate the list */ 297 ds->ds_data = bf->bf_segs[0].ds_addr; 298 ath_hal_setuprxdesc(ah, ds 299 , m->m_len /* buffer size */ 300 , 0 301 ); 302 303 if (sc->sc_rxlink != NULL) 304 *sc->sc_rxlink = bf->bf_daddr; 305 sc->sc_rxlink = &ds->ds_link; 306 return 0; 307} 308 309/* 310 * Intercept management frames to collect beacon rssi data 311 * and to do ibss merges. 312 */ 313void 314ath_recv_mgmt(struct ieee80211_node *ni, struct mbuf *m, 315 int subtype, int rssi, int nf) 316{ 317 struct ieee80211vap *vap = ni->ni_vap; 318 struct ath_softc *sc = vap->iv_ic->ic_ifp->if_softc; 319 320 /* 321 * Call up first so subsequent work can use information 322 * potentially stored in the node (e.g. for ibss merge). 323 */ 324 ATH_VAP(vap)->av_recv_mgmt(ni, m, subtype, rssi, nf); 325 switch (subtype) { 326 case IEEE80211_FC0_SUBTYPE_BEACON: 327 /* update rssi statistics for use by the hal */ 328 /* XXX unlocked check against vap->iv_bss? */ 329 ATH_RSSI_LPF(sc->sc_halstats.ns_avgbrssi, rssi); 330 if (sc->sc_syncbeacon && 331 ni == vap->iv_bss && vap->iv_state == IEEE80211_S_RUN) { 332 /* 333 * Resync beacon timers using the tsf of the beacon 334 * frame we just received. 335 */ 336 ath_beacon_config(sc, vap); 337 } 338 /* fall thru... */ 339 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 340 if (vap->iv_opmode == IEEE80211_M_IBSS && 341 vap->iv_state == IEEE80211_S_RUN) { 342 uint32_t rstamp = sc->sc_lastrs->rs_tstamp; 343 uint64_t tsf = ath_extend_tsf(sc, rstamp, 344 ath_hal_gettsf64(sc->sc_ah)); 345 /* 346 * Handle ibss merge as needed; check the tsf on the 347 * frame before attempting the merge. The 802.11 spec 348 * says the station should change it's bssid to match 349 * the oldest station with the same ssid, where oldest 350 * is determined by the tsf. Note that hardware 351 * reconfiguration happens through callback to 352 * ath_newstate as the state machine will go from 353 * RUN -> RUN when this happens. 354 */ 355 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 356 DPRINTF(sc, ATH_DEBUG_STATE, 357 "ibss merge, rstamp %u tsf %ju " 358 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 359 (uintmax_t)ni->ni_tstamp.tsf); 360 (void) ieee80211_ibss_merge(ni); 361 } 362 } 363 break; 364 } 365} 366 367#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 368static void 369ath_rx_tap_vendor(struct ifnet *ifp, struct mbuf *m, 370 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf) 371{ 372 struct ath_softc *sc = ifp->if_softc; 373 374 /* Fill in the extension bitmap */ 375 sc->sc_rx_th.wr_ext_bitmap = htole32(1 << ATH_RADIOTAP_VENDOR_HEADER); 376 377 /* Fill in the vendor header */ 378 sc->sc_rx_th.wr_vh.vh_oui[0] = 0x7f; 379 sc->sc_rx_th.wr_vh.vh_oui[1] = 0x03; 380 sc->sc_rx_th.wr_vh.vh_oui[2] = 0x00; 381 382 /* XXX what should this be? */ 383 sc->sc_rx_th.wr_vh.vh_sub_ns = 0; 384 sc->sc_rx_th.wr_vh.vh_skip_len = 385 htole16(sizeof(struct ath_radiotap_vendor_hdr)); 386 387 /* General version info */ 388 sc->sc_rx_th.wr_v.vh_version = 1; 389 390 sc->sc_rx_th.wr_v.vh_rx_chainmask = sc->sc_rxchainmask; 391 392 /* rssi */ 393 sc->sc_rx_th.wr_v.rssi_ctl[0] = rs->rs_rssi_ctl[0]; 394 sc->sc_rx_th.wr_v.rssi_ctl[1] = rs->rs_rssi_ctl[1]; 395 sc->sc_rx_th.wr_v.rssi_ctl[2] = rs->rs_rssi_ctl[2]; 396 sc->sc_rx_th.wr_v.rssi_ext[0] = rs->rs_rssi_ext[0]; 397 sc->sc_rx_th.wr_v.rssi_ext[1] = rs->rs_rssi_ext[1]; 398 sc->sc_rx_th.wr_v.rssi_ext[2] = rs->rs_rssi_ext[2]; 399 400 /* evm */ 401 sc->sc_rx_th.wr_v.evm[0] = rs->rs_evm0; 402 sc->sc_rx_th.wr_v.evm[1] = rs->rs_evm1; 403 sc->sc_rx_th.wr_v.evm[2] = rs->rs_evm2; 404 /* These are only populated from the AR9300 or later */ 405 sc->sc_rx_th.wr_v.evm[3] = rs->rs_evm3; 406 sc->sc_rx_th.wr_v.evm[4] = rs->rs_evm4; 407 408 /* direction */ 409 sc->sc_rx_th.wr_v.vh_flags = ATH_VENDOR_PKT_RX; 410 411 /* RX rate */ 412 sc->sc_rx_th.wr_v.vh_rx_hwrate = rs->rs_rate; 413 414 /* RX flags */ 415 sc->sc_rx_th.wr_v.vh_rs_flags = rs->rs_flags; 416 417 if (rs->rs_isaggr) 418 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_ISAGGR; 419 if (rs->rs_moreaggr) 420 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_MOREAGGR; 421 422 /* phyerr info */ 423 if (rs->rs_status & HAL_RXERR_PHY) { 424 sc->sc_rx_th.wr_v.vh_phyerr_code = rs->rs_phyerr; 425 sc->sc_rx_th.wr_v.vh_flags |= ATH_VENDOR_PKT_RXPHYERR; 426 } else { 427 sc->sc_rx_th.wr_v.vh_phyerr_code = 0xff; 428 } 429 sc->sc_rx_th.wr_v.vh_rs_status = rs->rs_status; 430 sc->sc_rx_th.wr_v.vh_rssi = rs->rs_rssi; 431} 432#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 433 434static void 435ath_rx_tap(struct ifnet *ifp, struct mbuf *m, 436 const struct ath_rx_status *rs, u_int64_t tsf, int16_t nf) 437{ 438#define CHAN_HT20 htole32(IEEE80211_CHAN_HT20) 439#define CHAN_HT40U htole32(IEEE80211_CHAN_HT40U) 440#define CHAN_HT40D htole32(IEEE80211_CHAN_HT40D) 441#define CHAN_HT (CHAN_HT20|CHAN_HT40U|CHAN_HT40D) 442 struct ath_softc *sc = ifp->if_softc; 443 const HAL_RATE_TABLE *rt; 444 uint8_t rix; 445 446 rt = sc->sc_currates; 447 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 448 rix = rt->rateCodeToIndex[rs->rs_rate]; 449 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 450 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 451#ifdef AH_SUPPORT_AR5416 452 sc->sc_rx_th.wr_chan_flags &= ~CHAN_HT; 453 if (rs->rs_status & HAL_RXERR_PHY) { 454 /* 455 * PHY error - make sure the channel flags 456 * reflect the actual channel configuration, 457 * not the received frame. 458 */ 459 if (IEEE80211_IS_CHAN_HT40U(sc->sc_curchan)) 460 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U; 461 else if (IEEE80211_IS_CHAN_HT40D(sc->sc_curchan)) 462 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D; 463 else if (IEEE80211_IS_CHAN_HT20(sc->sc_curchan)) 464 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20; 465 } else if (sc->sc_rx_th.wr_rate & IEEE80211_RATE_MCS) { /* HT rate */ 466 struct ieee80211com *ic = ifp->if_l2com; 467 468 if ((rs->rs_flags & HAL_RX_2040) == 0) 469 sc->sc_rx_th.wr_chan_flags |= CHAN_HT20; 470 else if (IEEE80211_IS_CHAN_HT40U(ic->ic_curchan)) 471 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40U; 472 else 473 sc->sc_rx_th.wr_chan_flags |= CHAN_HT40D; 474 if ((rs->rs_flags & HAL_RX_GI) == 0) 475 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTGI; 476 } 477 478#endif 479 sc->sc_rx_th.wr_tsf = htole64(ath_extend_tsf(sc, rs->rs_tstamp, tsf)); 480 if (rs->rs_status & HAL_RXERR_CRC) 481 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS; 482 /* XXX propagate other error flags from descriptor */ 483 sc->sc_rx_th.wr_antnoise = nf; 484 sc->sc_rx_th.wr_antsignal = nf + rs->rs_rssi; 485 sc->sc_rx_th.wr_antenna = rs->rs_antenna; 486#undef CHAN_HT 487#undef CHAN_HT20 488#undef CHAN_HT40U 489#undef CHAN_HT40D 490} 491 492static void 493ath_handle_micerror(struct ieee80211com *ic, 494 struct ieee80211_frame *wh, int keyix) 495{ 496 struct ieee80211_node *ni; 497 498 /* XXX recheck MIC to deal w/ chips that lie */ 499 /* XXX discard MIC errors on !data frames */ 500 ni = ieee80211_find_rxnode(ic, (const struct ieee80211_frame_min *) wh); 501 if (ni != NULL) { 502 ieee80211_notify_michael_failure(ni->ni_vap, wh, keyix); 503 ieee80211_free_node(ni); 504 } 505} 506 507/* 508 * Process a single packet. 509 * 510 * The mbuf must already be synced, unmapped and removed from bf->bf_m 511 * by this stage. 512 * 513 * The mbuf must be consumed by this routine - either passed up the 514 * net80211 stack, put on the holding queue, or freed. 515 */ 516int 517ath_rx_pkt(struct ath_softc *sc, struct ath_rx_status *rs, HAL_STATUS status, 518 uint64_t tsf, int nf, HAL_RX_QUEUE qtype, struct ath_buf *bf, 519 struct mbuf *m) 520{ 521 uint64_t rstamp; 522 int len, type; 523 struct ifnet *ifp = sc->sc_ifp; 524 struct ieee80211com *ic = ifp->if_l2com; 525 struct ieee80211_node *ni; 526 int is_good = 0; 527 struct ath_rx_edma *re = &sc->sc_rxedma[qtype]; 528 529 /* 530 * Calculate the correct 64 bit TSF given 531 * the TSF64 register value and rs_tstamp. 532 */ 533 rstamp = ath_extend_tsf(sc, rs->rs_tstamp, tsf); 534 535 /* These aren't specifically errors */ 536#ifdef AH_SUPPORT_AR5416 537 if (rs->rs_flags & HAL_RX_GI) 538 sc->sc_stats.ast_rx_halfgi++; 539 if (rs->rs_flags & HAL_RX_2040) 540 sc->sc_stats.ast_rx_2040++; 541 if (rs->rs_flags & HAL_RX_DELIM_CRC_PRE) 542 sc->sc_stats.ast_rx_pre_crc_err++; 543 if (rs->rs_flags & HAL_RX_DELIM_CRC_POST) 544 sc->sc_stats.ast_rx_post_crc_err++; 545 if (rs->rs_flags & HAL_RX_DECRYPT_BUSY) 546 sc->sc_stats.ast_rx_decrypt_busy_err++; 547 if (rs->rs_flags & HAL_RX_HI_RX_CHAIN) 548 sc->sc_stats.ast_rx_hi_rx_chain++; 549 if (rs->rs_flags & HAL_RX_STBC) 550 sc->sc_stats.ast_rx_stbc++; 551#endif /* AH_SUPPORT_AR5416 */ 552 553 if (rs->rs_status != 0) { 554 if (rs->rs_status & HAL_RXERR_CRC) 555 sc->sc_stats.ast_rx_crcerr++; 556 if (rs->rs_status & HAL_RXERR_FIFO) 557 sc->sc_stats.ast_rx_fifoerr++; 558 if (rs->rs_status & HAL_RXERR_PHY) { 559 sc->sc_stats.ast_rx_phyerr++; 560 /* Process DFS radar events */ 561 if ((rs->rs_phyerr == HAL_PHYERR_RADAR) || 562 (rs->rs_phyerr == HAL_PHYERR_FALSE_RADAR_EXT)) { 563 /* Now pass it to the radar processing code */ 564 ath_dfs_process_phy_err(sc, m, rstamp, rs); 565 } 566 567 /* Be suitably paranoid about receiving phy errors out of the stats array bounds */ 568 if (rs->rs_phyerr < 64) 569 sc->sc_stats.ast_rx_phy[rs->rs_phyerr]++; 570 goto rx_error; /* NB: don't count in ierrors */ 571 } 572 if (rs->rs_status & HAL_RXERR_DECRYPT) { 573 /* 574 * Decrypt error. If the error occurred 575 * because there was no hardware key, then 576 * let the frame through so the upper layers 577 * can process it. This is necessary for 5210 578 * parts which have no way to setup a ``clear'' 579 * key cache entry. 580 * 581 * XXX do key cache faulting 582 */ 583 if (rs->rs_keyix == HAL_RXKEYIX_INVALID) 584 goto rx_accept; 585 sc->sc_stats.ast_rx_badcrypt++; 586 } 587 /* 588 * Similar as above - if the failure was a keymiss 589 * just punt it up to the upper layers for now. 590 */ 591 if (rs->rs_status & HAL_RXERR_KEYMISS) { 592 sc->sc_stats.ast_rx_keymiss++; 593 goto rx_accept; 594 } 595 if (rs->rs_status & HAL_RXERR_MIC) { 596 sc->sc_stats.ast_rx_badmic++; 597 /* 598 * Do minimal work required to hand off 599 * the 802.11 header for notification. 600 */ 601 /* XXX frag's and qos frames */ 602 len = rs->rs_datalen; 603 if (len >= sizeof (struct ieee80211_frame)) { 604 ath_handle_micerror(ic, 605 mtod(m, struct ieee80211_frame *), 606 sc->sc_splitmic ? 607 rs->rs_keyix-32 : rs->rs_keyix); 608 } 609 } 610 ifp->if_ierrors++; 611rx_error: 612 /* 613 * Cleanup any pending partial frame. 614 */ 615 if (re->m_rxpending != NULL) { 616 m_freem(re->m_rxpending); 617 re->m_rxpending = NULL; 618 } 619 /* 620 * When a tap is present pass error frames 621 * that have been requested. By default we 622 * pass decrypt+mic errors but others may be 623 * interesting (e.g. crc). 624 */ 625 if (ieee80211_radiotap_active(ic) && 626 (rs->rs_status & sc->sc_monpass)) { 627 /* NB: bpf needs the mbuf length setup */ 628 len = rs->rs_datalen; 629 m->m_pkthdr.len = m->m_len = len; 630 ath_rx_tap(ifp, m, rs, rstamp, nf); 631#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 632 ath_rx_tap_vendor(ifp, m, rs, rstamp, nf); 633#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 634 ieee80211_radiotap_rx_all(ic, m); 635 } 636 /* XXX pass MIC errors up for s/w reclaculation */ 637 m_freem(m); m = NULL; 638 goto rx_next; 639 } 640rx_accept: 641 len = rs->rs_datalen; 642 m->m_len = len; 643 644 if (rs->rs_more) { 645 /* 646 * Frame spans multiple descriptors; save 647 * it for the next completed descriptor, it 648 * will be used to construct a jumbogram. 649 */ 650 if (re->m_rxpending != NULL) { 651 /* NB: max frame size is currently 2 clusters */ 652 sc->sc_stats.ast_rx_toobig++; 653 m_freem(re->m_rxpending); 654 } 655 m->m_pkthdr.rcvif = ifp; 656 m->m_pkthdr.len = len; 657 re->m_rxpending = m; 658 m = NULL; 659 goto rx_next; 660 } else if (re->m_rxpending != NULL) { 661 /* 662 * This is the second part of a jumbogram, 663 * chain it to the first mbuf, adjust the 664 * frame length, and clear the rxpending state. 665 */ 666 re->m_rxpending->m_next = m; 667 re->m_rxpending->m_pkthdr.len += len; 668 m = re->m_rxpending; 669 re->m_rxpending = NULL; 670 } else { 671 /* 672 * Normal single-descriptor receive; setup 673 * the rcvif and packet length. 674 */ 675 m->m_pkthdr.rcvif = ifp; 676 m->m_pkthdr.len = len; 677 } 678 679 /* 680 * Validate rs->rs_antenna. 681 * 682 * Some users w/ AR9285 NICs have reported crashes 683 * here because rs_antenna field is bogusly large. 684 * Let's enforce the maximum antenna limit of 8 685 * (and it shouldn't be hard coded, but that's a 686 * separate problem) and if there's an issue, print 687 * out an error and adjust rs_antenna to something 688 * sensible. 689 * 690 * This code should be removed once the actual 691 * root cause of the issue has been identified. 692 * For example, it may be that the rs_antenna 693 * field is only valid for the lsat frame of 694 * an aggregate and it just happens that it is 695 * "mostly" right. (This is a general statement - 696 * the majority of the statistics are only valid 697 * for the last frame in an aggregate. 698 */ 699 if (rs->rs_antenna > 7) { 700 device_printf(sc->sc_dev, "%s: rs_antenna > 7 (%d)\n", 701 __func__, rs->rs_antenna); 702#ifdef ATH_DEBUG 703 ath_printrxbuf(sc, bf, 0, status == HAL_OK); 704#endif /* ATH_DEBUG */ 705 rs->rs_antenna = 0; /* XXX better than nothing */ 706 } 707 708 /* 709 * If this is an AR9285/AR9485, then the receive and LNA 710 * configuration is stored in RSSI[2] / EXTRSSI[2]. 711 * We can extract this out to build a much better 712 * receive antenna profile. 713 * 714 * Yes, this just blurts over the above RX antenna field 715 * for now. It's fine, the AR9285 doesn't really use 716 * that. 717 * 718 * Later on we should store away the fine grained LNA 719 * information and keep separate counters just for 720 * that. It'll help when debugging the AR9285/AR9485 721 * combined diversity code. 722 */ 723 if (sc->sc_rx_lnamixer) { 724 rs->rs_antenna = 0; 725 726 /* Bits 0:1 - the LNA configuration used */ 727 rs->rs_antenna |= 728 ((rs->rs_rssi_ctl[2] & HAL_RX_LNA_CFG_USED) 729 >> HAL_RX_LNA_CFG_USED_S); 730 731 /* Bit 2 - the external RX antenna switch */ 732 if (rs->rs_rssi_ctl[2] & HAL_RX_LNA_EXTCFG) 733 rs->rs_antenna |= 0x4; 734 } 735 736 ifp->if_ipackets++; 737 sc->sc_stats.ast_ant_rx[rs->rs_antenna]++; 738 739 /* 740 * Populate the rx status block. When there are bpf 741 * listeners we do the additional work to provide 742 * complete status. Otherwise we fill in only the 743 * material required by ieee80211_input. Note that 744 * noise setting is filled in above. 745 */ 746 if (ieee80211_radiotap_active(ic)) { 747 ath_rx_tap(ifp, m, rs, rstamp, nf); 748#ifdef ATH_ENABLE_RADIOTAP_VENDOR_EXT 749 ath_rx_tap_vendor(ifp, m, rs, rstamp, nf); 750#endif /* ATH_ENABLE_RADIOTAP_VENDOR_EXT */ 751 } 752 753 /* 754 * From this point on we assume the frame is at least 755 * as large as ieee80211_frame_min; verify that. 756 */ 757 if (len < IEEE80211_MIN_LEN) { 758 if (!ieee80211_radiotap_active(ic)) { 759 DPRINTF(sc, ATH_DEBUG_RECV, 760 "%s: short packet %d\n", __func__, len); 761 sc->sc_stats.ast_rx_tooshort++; 762 } else { 763 /* NB: in particular this captures ack's */ 764 ieee80211_radiotap_rx_all(ic, m); 765 } 766 m_freem(m); m = NULL; 767 goto rx_next; 768 } 769 770 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 771 const HAL_RATE_TABLE *rt = sc->sc_currates; 772 uint8_t rix = rt->rateCodeToIndex[rs->rs_rate]; 773 774 ieee80211_dump_pkt(ic, mtod(m, caddr_t), len, 775 sc->sc_hwmap[rix].ieeerate, rs->rs_rssi); 776 } 777 778 m_adj(m, -IEEE80211_CRC_LEN); 779 780 /* 781 * Locate the node for sender, track state, and then 782 * pass the (referenced) node up to the 802.11 layer 783 * for its use. 784 */ 785 ni = ieee80211_find_rxnode_withkey(ic, 786 mtod(m, const struct ieee80211_frame_min *), 787 rs->rs_keyix == HAL_RXKEYIX_INVALID ? 788 IEEE80211_KEYIX_NONE : rs->rs_keyix); 789 sc->sc_lastrs = rs; 790 791#ifdef AH_SUPPORT_AR5416 792 if (rs->rs_isaggr) 793 sc->sc_stats.ast_rx_agg++; 794#endif /* AH_SUPPORT_AR5416 */ 795 796 if (ni != NULL) { 797 /* 798 * Only punt packets for ampdu reorder processing for 799 * 11n nodes; net80211 enforces that M_AMPDU is only 800 * set for 11n nodes. 801 */ 802 if (ni->ni_flags & IEEE80211_NODE_HT) 803 m->m_flags |= M_AMPDU; 804 805 /* 806 * Sending station is known, dispatch directly. 807 */ 808 type = ieee80211_input(ni, m, rs->rs_rssi, nf); 809 ieee80211_free_node(ni); 810 m = NULL; 811 /* 812 * Arrange to update the last rx timestamp only for 813 * frames from our ap when operating in station mode. 814 * This assumes the rx key is always setup when 815 * associated. 816 */ 817 if (ic->ic_opmode == IEEE80211_M_STA && 818 rs->rs_keyix != HAL_RXKEYIX_INVALID) 819 is_good = 1; 820 } else { 821 type = ieee80211_input_all(ic, m, rs->rs_rssi, nf); 822 m = NULL; 823 } 824 825 /* 826 * At this point we have passed the frame up the stack; thus 827 * the mbuf is no longer ours. 828 */ 829 830 /* 831 * Track rx rssi and do any rx antenna management. 832 */ 833 ATH_RSSI_LPF(sc->sc_halstats.ns_avgrssi, rs->rs_rssi); 834 if (sc->sc_diversity) { 835 /* 836 * When using fast diversity, change the default rx 837 * antenna if diversity chooses the other antenna 3 838 * times in a row. 839 */ 840 if (sc->sc_defant != rs->rs_antenna) { 841 if (++sc->sc_rxotherant >= 3) 842 ath_setdefantenna(sc, rs->rs_antenna); 843 } else 844 sc->sc_rxotherant = 0; 845 } 846 847 /* Handle slow diversity if enabled */ 848 if (sc->sc_dolnadiv) { 849 ath_lna_rx_comb_scan(sc, rs, ticks, hz); 850 } 851 852 if (sc->sc_softled) { 853 /* 854 * Blink for any data frame. Otherwise do a 855 * heartbeat-style blink when idle. The latter 856 * is mainly for station mode where we depend on 857 * periodic beacon frames to trigger the poll event. 858 */ 859 if (type == IEEE80211_FC0_TYPE_DATA) { 860 const HAL_RATE_TABLE *rt = sc->sc_currates; 861 ath_led_event(sc, 862 rt->rateCodeToIndex[rs->rs_rate]); 863 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 864 ath_led_event(sc, 0); 865 } 866rx_next: 867 /* 868 * Debugging - complain if we didn't NULL the mbuf pointer 869 * here. 870 */ 871 if (m != NULL) { 872 device_printf(sc->sc_dev, 873 "%s: mbuf %p should've been freed!\n", 874 __func__, 875 m); 876 } 877 return (is_good); 878} 879 880#define ATH_RX_MAX 128 881 882static void 883ath_rx_proc(struct ath_softc *sc, int resched) 884{ 885#define PA2DESC(_sc, _pa) \ 886 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 887 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 888 struct ath_buf *bf; 889 struct ifnet *ifp = sc->sc_ifp; 890 struct ath_hal *ah = sc->sc_ah; 891#ifdef IEEE80211_SUPPORT_SUPERG 892 struct ieee80211com *ic = ifp->if_l2com; 893#endif 894 struct ath_desc *ds; 895 struct ath_rx_status *rs; 896 struct mbuf *m; 897 int ngood; 898 HAL_STATUS status; 899 int16_t nf; 900 u_int64_t tsf; 901 int npkts = 0; 902 int kickpcu = 0; 903 904 /* XXX we must not hold the ATH_LOCK here */ 905 ATH_UNLOCK_ASSERT(sc); 906 ATH_PCU_UNLOCK_ASSERT(sc); 907 908 ATH_PCU_LOCK(sc); 909 sc->sc_rxproc_cnt++; 910 kickpcu = sc->sc_kickpcu; 911 ATH_PCU_UNLOCK(sc); 912 913 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: called\n", __func__); 914 ngood = 0; 915 nf = ath_hal_getchannoise(ah, sc->sc_curchan); 916 sc->sc_stats.ast_rx_noise = nf; 917 tsf = ath_hal_gettsf64(ah); 918 do { 919 /* 920 * Don't process too many packets at a time; give the 921 * TX thread time to also run - otherwise the TX 922 * latency can jump by quite a bit, causing throughput 923 * degredation. 924 */ 925 if (!kickpcu && npkts >= ATH_RX_MAX) 926 break; 927 928 bf = TAILQ_FIRST(&sc->sc_rxbuf); 929 if (sc->sc_rxslink && bf == NULL) { /* NB: shouldn't happen */ 930 if_printf(ifp, "%s: no buffer!\n", __func__); 931 break; 932 } else if (bf == NULL) { 933 /* 934 * End of List: 935 * this can happen for non-self-linked RX chains 936 */ 937 sc->sc_stats.ast_rx_hitqueueend++; 938 break; 939 } 940 m = bf->bf_m; 941 if (m == NULL) { /* NB: shouldn't happen */ 942 /* 943 * If mbuf allocation failed previously there 944 * will be no mbuf; try again to re-populate it. 945 */ 946 /* XXX make debug msg */ 947 if_printf(ifp, "%s: no mbuf!\n", __func__); 948 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list); 949 goto rx_proc_next; 950 } 951 ds = bf->bf_desc; 952 if (ds->ds_link == bf->bf_daddr) { 953 /* NB: never process the self-linked entry at the end */ 954 sc->sc_stats.ast_rx_hitqueueend++; 955 break; 956 } 957 /* XXX sync descriptor memory */ 958 /* 959 * Must provide the virtual address of the current 960 * descriptor, the physical address, and the virtual 961 * address of the next descriptor in the h/w chain. 962 * This allows the HAL to look ahead to see if the 963 * hardware is done with a descriptor by checking the 964 * done bit in the following descriptor and the address 965 * of the current descriptor the DMA engine is working 966 * on. All this is necessary because of our use of 967 * a self-linked list to avoid rx overruns. 968 */ 969 rs = &bf->bf_status.ds_rxstat; 970 status = ath_hal_rxprocdesc(ah, ds, 971 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 972#ifdef ATH_DEBUG 973 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 974 ath_printrxbuf(sc, bf, 0, status == HAL_OK); 975#endif 976 977#ifdef ATH_DEBUG_ALQ 978 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS)) 979 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_RXSTATUS, 980 sc->sc_rx_statuslen, (char *) ds); 981#endif /* ATH_DEBUG_ALQ */ 982 983 if (status == HAL_EINPROGRESS) 984 break; 985 986 TAILQ_REMOVE(&sc->sc_rxbuf, bf, bf_list); 987 npkts++; 988 989 /* 990 * Process a single frame. 991 */ 992 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_POSTREAD); 993 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 994 bf->bf_m = NULL; 995 if (ath_rx_pkt(sc, rs, status, tsf, nf, HAL_RX_QUEUE_HP, bf, m)) 996 ngood++; 997rx_proc_next: 998 TAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 999 } while (ath_rxbuf_init(sc, bf) == 0); 1000 1001 /* rx signal state monitoring */ 1002 ath_hal_rxmonitor(ah, &sc->sc_halstats, sc->sc_curchan); 1003 if (ngood) 1004 sc->sc_lastrx = tsf; 1005 1006 ATH_KTR(sc, ATH_KTR_RXPROC, 2, "ath_rx_proc: npkts=%d, ngood=%d", npkts, ngood); 1007 /* Queue DFS tasklet if needed */ 1008 if (resched && ath_dfs_tasklet_needed(sc, sc->sc_curchan)) 1009 taskqueue_enqueue(sc->sc_tq, &sc->sc_dfstask); 1010 1011 /* 1012 * Now that all the RX frames were handled that 1013 * need to be handled, kick the PCU if there's 1014 * been an RXEOL condition. 1015 */ 1016 if (resched && kickpcu) { 1017 ATH_PCU_LOCK(sc); 1018 ATH_KTR(sc, ATH_KTR_ERROR, 0, "ath_rx_proc: kickpcu"); 1019 device_printf(sc->sc_dev, "%s: kickpcu; handled %d packets\n", 1020 __func__, npkts); 1021 1022 /* 1023 * Go through the process of fully tearing down 1024 * the RX buffers and reinitialising them. 1025 * 1026 * There's a hardware bug that causes the RX FIFO 1027 * to get confused under certain conditions and 1028 * constantly write over the same frame, leading 1029 * the RX driver code here to get heavily confused. 1030 */ 1031#if 1 1032 ath_startrecv(sc); 1033#else 1034 /* 1035 * Disabled for now - it'd be nice to be able to do 1036 * this in order to limit the amount of CPU time spent 1037 * reinitialising the RX side (and thus minimise RX 1038 * drops) however there's a hardware issue that 1039 * causes things to get too far out of whack. 1040 */ 1041 /* 1042 * XXX can we hold the PCU lock here? 1043 * Are there any net80211 buffer calls involved? 1044 */ 1045 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1046 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP); 1047 ath_hal_rxena(ah); /* enable recv descriptors */ 1048 ath_mode_init(sc); /* set filters, etc. */ 1049 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 1050#endif 1051 1052 ath_hal_intrset(ah, sc->sc_imask); 1053 sc->sc_kickpcu = 0; 1054 ATH_PCU_UNLOCK(sc); 1055 } 1056 1057 /* XXX check this inside of IF_LOCK? */ 1058 if (resched && (ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) { 1059#ifdef IEEE80211_SUPPORT_SUPERG 1060 ieee80211_ff_age_all(ic, 100); 1061#endif 1062 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 1063 ath_tx_kick(sc); 1064 } 1065#undef PA2DESC 1066 1067 /* 1068 * If we hit the maximum number of frames in this round, 1069 * reschedule for another immediate pass. This gives 1070 * the TX and TX completion routines time to run, which 1071 * will reduce latency. 1072 */ 1073 if (npkts >= ATH_RX_MAX) 1074 sc->sc_rx.recv_sched(sc, resched); 1075 1076 ATH_PCU_LOCK(sc); 1077 sc->sc_rxproc_cnt--; 1078 ATH_PCU_UNLOCK(sc); 1079} 1080 1081#undef ATH_RX_MAX 1082 1083/* 1084 * Only run the RX proc if it's not already running. 1085 * Since this may get run as part of the reset/flush path, 1086 * the task can't clash with an existing, running tasklet. 1087 */ 1088static void 1089ath_legacy_rx_tasklet(void *arg, int npending) 1090{ 1091 struct ath_softc *sc = arg; 1092 1093 ATH_KTR(sc, ATH_KTR_RXPROC, 1, "ath_rx_proc: pending=%d", npending); 1094 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 1095 ATH_PCU_LOCK(sc); 1096 if (sc->sc_inreset_cnt > 0) { 1097 device_printf(sc->sc_dev, 1098 "%s: sc_inreset_cnt > 0; skipping\n", __func__); 1099 ATH_PCU_UNLOCK(sc); 1100 return; 1101 } 1102 ATH_PCU_UNLOCK(sc); 1103 1104 ath_rx_proc(sc, 1); 1105} 1106 1107static void 1108ath_legacy_flushrecv(struct ath_softc *sc) 1109{ 1110 1111 ath_rx_proc(sc, 0); 1112} 1113 1114/* 1115 * Disable the receive h/w in preparation for a reset. 1116 */ 1117static void 1118ath_legacy_stoprecv(struct ath_softc *sc, int dodelay) 1119{ 1120#define PA2DESC(_sc, _pa) \ 1121 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 1122 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 1123 struct ath_hal *ah = sc->sc_ah; 1124 1125 ath_hal_stoppcurecv(ah); /* disable PCU */ 1126 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 1127 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 1128 /* 1129 * TODO: see if this particular DELAY() is required; it may be 1130 * masking some missing FIFO flush or DMA sync. 1131 */ 1132#if 0 1133 if (dodelay) 1134#endif 1135 DELAY(3000); /* 3ms is long enough for 1 frame */ 1136#ifdef ATH_DEBUG 1137 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 1138 struct ath_buf *bf; 1139 u_int ix; 1140 1141 device_printf(sc->sc_dev, 1142 "%s: rx queue %p, link %p\n", 1143 __func__, 1144 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah, HAL_RX_QUEUE_HP), 1145 sc->sc_rxlink); 1146 ix = 0; 1147 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 1148 struct ath_desc *ds = bf->bf_desc; 1149 struct ath_rx_status *rs = &bf->bf_status.ds_rxstat; 1150 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 1151 bf->bf_daddr, PA2DESC(sc, ds->ds_link), rs); 1152 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 1153 ath_printrxbuf(sc, bf, ix, status == HAL_OK); 1154 ix++; 1155 } 1156 } 1157#endif 1158 /* 1159 * Free both high/low RX pending, just in case. 1160 */ 1161 if (sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending != NULL) { 1162 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending); 1163 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL; 1164 } 1165 if (sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending != NULL) { 1166 m_freem(sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending); 1167 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL; 1168 } 1169 sc->sc_rxlink = NULL; /* just in case */ 1170#undef PA2DESC 1171} 1172 1173/* 1174 * Enable the receive h/w following a reset. 1175 */ 1176static int 1177ath_legacy_startrecv(struct ath_softc *sc) 1178{ 1179 struct ath_hal *ah = sc->sc_ah; 1180 struct ath_buf *bf; 1181 1182 sc->sc_rxlink = NULL; 1183 sc->sc_rxedma[HAL_RX_QUEUE_LP].m_rxpending = NULL; 1184 sc->sc_rxedma[HAL_RX_QUEUE_HP].m_rxpending = NULL; 1185 TAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 1186 int error = ath_rxbuf_init(sc, bf); 1187 if (error != 0) { 1188 DPRINTF(sc, ATH_DEBUG_RECV, 1189 "%s: ath_rxbuf_init failed %d\n", 1190 __func__, error); 1191 return error; 1192 } 1193 } 1194 1195 bf = TAILQ_FIRST(&sc->sc_rxbuf); 1196 ath_hal_putrxbuf(ah, bf->bf_daddr, HAL_RX_QUEUE_HP); 1197 ath_hal_rxena(ah); /* enable recv descriptors */ 1198 ath_mode_init(sc); /* set filters, etc. */ 1199 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 1200 return 0; 1201} 1202 1203static int 1204ath_legacy_dma_rxsetup(struct ath_softc *sc) 1205{ 1206 int error; 1207 1208 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 1209 "rx", sizeof(struct ath_desc), ath_rxbuf, 1); 1210 if (error != 0) 1211 return (error); 1212 1213 return (0); 1214} 1215 1216static int 1217ath_legacy_dma_rxteardown(struct ath_softc *sc) 1218{ 1219 1220 if (sc->sc_rxdma.dd_desc_len != 0) 1221 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 1222 return (0); 1223} 1224 1225static void 1226ath_legacy_recv_sched(struct ath_softc *sc, int dosched) 1227{ 1228 1229 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1230} 1231 1232static void 1233ath_legacy_recv_sched_queue(struct ath_softc *sc, HAL_RX_QUEUE q, 1234 int dosched) 1235{ 1236 1237 taskqueue_enqueue(sc->sc_tq, &sc->sc_rxtask); 1238} 1239 1240void 1241ath_recv_setup_legacy(struct ath_softc *sc) 1242{ 1243 1244 /* Sensible legacy defaults */ 1245 /* 1246 * XXX this should be changed to properly support the 1247 * exact RX descriptor size for each HAL. 1248 */ 1249 sc->sc_rx_statuslen = sizeof(struct ath_desc); 1250 1251 sc->sc_rx.recv_start = ath_legacy_startrecv; 1252 sc->sc_rx.recv_stop = ath_legacy_stoprecv; 1253 sc->sc_rx.recv_flush = ath_legacy_flushrecv; 1254 sc->sc_rx.recv_tasklet = ath_legacy_rx_tasklet; 1255 sc->sc_rx.recv_rxbuf_init = ath_legacy_rxbuf_init; 1256 1257 sc->sc_rx.recv_setup = ath_legacy_dma_rxsetup; 1258 sc->sc_rx.recv_teardown = ath_legacy_dma_rxteardown; 1259 sc->sc_rx.recv_sched = ath_legacy_recv_sched; 1260 sc->sc_rx.recv_sched_queue = ath_legacy_recv_sched_queue; 1261} 1262