ar5416_reset.c revision 191909
1/* 2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c 191909 2009-05-08 00:23:00Z sam $ 18 */ 19#include "opt_ah.h" 20 21#include "ah.h" 22#include "ah_internal.h" 23#include "ah_devid.h" 24 25#include "ah_eeprom_v14.h" 26 27#include "ar5416/ar5416.h" 28#include "ar5416/ar5416reg.h" 29#include "ar5416/ar5416phy.h" 30 31/* Eeprom versioning macros. Returns true if the version is equal or newer than the ver specified */ 32#define EEP_MINOR(_ah) \ 33 (AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK) 34#define IS_EEP_MINOR_V2(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_2) 35#define IS_EEP_MINOR_V3(_ah) (EEP_MINOR(_ah) >= AR5416_EEP_MINOR_VER_3) 36 37/* Additional Time delay to wait after activiting the Base band */ 38#define BASE_ACTIVATE_DELAY 100 /* 100 usec */ 39#define PLL_SETTLE_DELAY 300 /* 300 usec */ 40#define RTC_PLL_SETTLE_DELAY 1000 /* 1 ms */ 41 42static void ar5416InitDMA(struct ath_hal *ah); 43static void ar5416InitBB(struct ath_hal *ah, const struct ieee80211_channel *); 44static void ar5416InitIMR(struct ath_hal *ah, HAL_OPMODE opmode); 45static void ar5416InitQoS(struct ath_hal *ah); 46static void ar5416InitUserSettings(struct ath_hal *ah); 47 48static HAL_BOOL ar5416SetTransmitPower(struct ath_hal *ah, 49 const struct ieee80211_channel *chan, uint16_t *rfXpdGain); 50 51#if 0 52static HAL_BOOL ar5416ChannelChange(struct ath_hal *, const struct ieee80211_channel *); 53#endif 54static void ar5416SetDeltaSlope(struct ath_hal *, const struct ieee80211_channel *); 55 56static HAL_BOOL ar5416SetResetPowerOn(struct ath_hal *ah); 57static HAL_BOOL ar5416SetReset(struct ath_hal *ah, int type); 58static void ar5416InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan); 59static HAL_BOOL ar5416SetBoardValues(struct ath_hal *, const struct ieee80211_channel *); 60static HAL_BOOL ar5416SetPowerPerRateTable(struct ath_hal *ah, 61 struct ar5416eeprom *pEepData, 62 const struct ieee80211_channel *chan, int16_t *ratesArray, 63 uint16_t cfgCtl, uint16_t AntennaReduction, 64 uint16_t twiceMaxRegulatoryPower, 65 uint16_t powerLimit); 66static HAL_BOOL ar5416SetPowerCalTable(struct ath_hal *ah, 67 struct ar5416eeprom *pEepData, 68 const struct ieee80211_channel *chan, 69 int16_t *pTxPowerIndexOffset); 70static uint16_t ar5416GetMaxEdgePower(uint16_t freq, 71 CAL_CTL_EDGES *pRdEdgesPower, HAL_BOOL is2GHz); 72static void ar5416GetTargetPowers(struct ath_hal *ah, 73 const struct ieee80211_channel *chan, CAL_TARGET_POWER_HT *powInfo, 74 uint16_t numChannels, CAL_TARGET_POWER_HT *pNewPower, 75 uint16_t numRates, HAL_BOOL isHt40Target); 76static void ar5416GetTargetPowersLeg(struct ath_hal *ah, 77 const struct ieee80211_channel *chan, CAL_TARGET_POWER_LEG *powInfo, 78 uint16_t numChannels, CAL_TARGET_POWER_LEG *pNewPower, 79 uint16_t numRates, HAL_BOOL isExtTarget); 80 81static int16_t interpolate(uint16_t target, uint16_t srcLeft, 82 uint16_t srcRight, int16_t targetLeft, int16_t targetRight); 83static void ar5416Set11nRegs(struct ath_hal *ah, const struct ieee80211_channel *chan); 84static void ar5416GetGainBoundariesAndPdadcs(struct ath_hal *ah, 85 const struct ieee80211_channel *chan, CAL_DATA_PER_FREQ *pRawDataSet, 86 uint8_t * bChans, uint16_t availPiers, 87 uint16_t tPdGainOverlap, int16_t *pMinCalPower, 88 uint16_t * pPdGainBoundaries, uint8_t * pPDADCValues, 89 uint16_t numXpdGains); 90static HAL_BOOL getLowerUpperIndex(uint8_t target, uint8_t *pList, 91 uint16_t listSize, uint16_t *indexL, uint16_t *indexR); 92static HAL_BOOL ar5416FillVpdTable(uint8_t pwrMin, uint8_t pwrMax, 93 uint8_t *pPwrList, uint8_t *pVpdList, 94 uint16_t numIntercepts, uint8_t *pRetVpdList); 95 96/* 97 * Places the device in and out of reset and then places sane 98 * values in the registers based on EEPROM config, initialization 99 * vectors (as determined by the mode), and station configuration 100 * 101 * bChannelChange is used to preserve DMA/PCU registers across 102 * a HW Reset during channel change. 103 */ 104HAL_BOOL 105ar5416Reset(struct ath_hal *ah, HAL_OPMODE opmode, 106 struct ieee80211_channel *chan, 107 HAL_BOOL bChannelChange, HAL_STATUS *status) 108{ 109#define N(a) (sizeof (a) / sizeof (a[0])) 110#define FAIL(_code) do { ecode = _code; goto bad; } while (0) 111 struct ath_hal_5212 *ahp = AH5212(ah); 112 HAL_CHANNEL_INTERNAL *ichan; 113 uint32_t saveDefAntenna, saveLedState; 114 uint32_t macStaId1; 115 uint16_t rfXpdGain[2]; 116 HAL_STATUS ecode; 117 uint32_t powerVal, rssiThrReg; 118 uint32_t ackTpcPow, ctsTpcPow, chirpTpcPow; 119 int i; 120 121 OS_MARK(ah, AH_MARK_RESET, bChannelChange); 122 123 /* Bring out of sleep mode */ 124 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 125 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip did not wakeup\n", 126 __func__); 127 FAIL(HAL_EIO); 128 } 129 130 /* 131 * Map public channel to private. 132 */ 133 ichan = ath_hal_checkchannel(ah, chan); 134 if (ichan == AH_NULL) 135 FAIL(HAL_EINVAL); 136 switch (opmode) { 137 case HAL_M_STA: 138 case HAL_M_IBSS: 139 case HAL_M_HOSTAP: 140 case HAL_M_MONITOR: 141 break; 142 default: 143 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid operating mode %u\n", 144 __func__, opmode); 145 FAIL(HAL_EINVAL); 146 break; 147 } 148 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1); 149 150 /* XXX Turn on fast channel change for 5416 */ 151 /* 152 * Preserve the bmiss rssi threshold and count threshold 153 * across resets 154 */ 155 rssiThrReg = OS_REG_READ(ah, AR_RSSI_THR); 156 /* If reg is zero, first time thru set to default val */ 157 if (rssiThrReg == 0) 158 rssiThrReg = INIT_RSSI_THR; 159 160 /* 161 * Preserve the antenna on a channel change 162 */ 163 saveDefAntenna = OS_REG_READ(ah, AR_DEF_ANTENNA); 164 if (saveDefAntenna == 0) /* XXX magic constants */ 165 saveDefAntenna = 1; 166 167 /* Save hardware flag before chip reset clears the register */ 168 macStaId1 = OS_REG_READ(ah, AR_STA_ID1) & 169 (AR_STA_ID1_BASE_RATE_11B | AR_STA_ID1_USE_DEFANT); 170 171 /* Save led state from pci config register */ 172 saveLedState = OS_REG_READ(ah, AR_MAC_LED) & 173 (AR_MAC_LED_ASSOC | AR_MAC_LED_MODE | 174 AR_MAC_LED_BLINK_THRESH_SEL | AR_MAC_LED_BLINK_SLOW); 175 176 if (!ar5416ChipReset(ah, chan)) { 177 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 178 FAIL(HAL_EIO); 179 } 180 181 /* Restore bmiss rssi & count thresholds */ 182 OS_REG_WRITE(ah, AR_RSSI_THR, rssiThrReg); 183 184 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 185 186 AH5416(ah)->ah_writeIni(ah, chan); 187 188 /* Setup 11n MAC/Phy mode registers */ 189 ar5416Set11nRegs(ah, chan); 190 191 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 192 193 HALDEBUG(ah, HAL_DEBUG_RESET, ">>>2 %s: AR_PHY_DAG_CTRLCCK=0x%x\n", 194 __func__, OS_REG_READ(ah,AR_PHY_DAG_CTRLCCK)); 195 HALDEBUG(ah, HAL_DEBUG_RESET, ">>>2 %s: AR_PHY_ADC_CTL=0x%x\n", 196 __func__, OS_REG_READ(ah,AR_PHY_ADC_CTL)); 197 198 /* Set the mute mask to the correct default */ 199 if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_2) 200 OS_REG_WRITE(ah, AR_SEQ_MASK, 0x0000000F); 201 202 if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_3) { 203 /* Clear reg to alllow RX_CLEAR line debug */ 204 OS_REG_WRITE(ah, AR_PHY_BLUETOOTH, 0); 205 } 206 if (AH_PRIVATE(ah)->ah_phyRev >= AR_PHY_CHIP_ID_REV_4) { 207#ifdef notyet 208 /* Enable burst prefetch for the data queues */ 209 OS_REG_RMW_FIELD(ah, AR_D_FPCTL, ... ); 210 /* Enable double-buffering */ 211 OS_REG_CLR_BIT(ah, AR_TXCFG, AR_TXCFG_DBL_BUF_DIS); 212#endif 213 } 214 215 /* Set ADC/DAC select values */ 216 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e); 217 218 if (AH5416(ah)->ah_rx_chainmask == 0x5 || 219 AH5416(ah)->ah_tx_chainmask == 0x5) 220 OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP, AR_PHY_SWAP_ALT_CHAIN); 221 /* Setup Chain Masks */ 222 OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, AH5416(ah)->ah_rx_chainmask); 223 OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, AH5416(ah)->ah_rx_chainmask); 224 OS_REG_WRITE(ah, AR_SELFGEN_MASK, AH5416(ah)->ah_tx_chainmask); 225 226 /* Setup the transmit power values. */ 227 if (!ar5416SetTransmitPower(ah, chan, rfXpdGain)) { 228 HALDEBUG(ah, HAL_DEBUG_ANY, 229 "%s: error init'ing transmit power\n", __func__); 230 FAIL(HAL_EIO); 231 } 232 233 /* Write the analog registers */ 234 if (!ahp->ah_rfHal->setRfRegs(ah, chan, 235 IEEE80211_IS_CHAN_2GHZ(chan) ? 2: 1, rfXpdGain)) { 236 HALDEBUG(ah, HAL_DEBUG_ANY, 237 "%s: ar5212SetRfRegs failed\n", __func__); 238 FAIL(HAL_EIO); 239 } 240 241 /* Write delta slope for OFDM enabled modes (A, G, Turbo) */ 242 if (IEEE80211_IS_CHAN_OFDM(chan)|| IEEE80211_IS_CHAN_HT(chan)) 243 ar5416SetDeltaSlope(ah, chan); 244 245 AH5416(ah)->ah_spurMitigate(ah, chan); 246 247 /* Setup board specific options for EEPROM version 3 */ 248 if (!ar5416SetBoardValues(ah, chan)) { 249 HALDEBUG(ah, HAL_DEBUG_ANY, 250 "%s: error setting board options\n", __func__); 251 FAIL(HAL_EIO); 252 } 253 254 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 255 256 OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr)); 257 OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4) 258 | macStaId1 259 | AR_STA_ID1_RTS_USE_DEF 260 | ahp->ah_staId1Defaults 261 ); 262 ar5212SetOperatingMode(ah, opmode); 263 264 /* Set Venice BSSID mask according to current state */ 265 OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssidmask)); 266 OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssidmask + 4)); 267 268 /* Restore previous led state */ 269 OS_REG_WRITE(ah, AR_MAC_LED, OS_REG_READ(ah, AR_MAC_LED) | saveLedState); 270 271 /* Restore previous antenna */ 272 OS_REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna); 273 274 /* then our BSSID */ 275 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid)); 276 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4)); 277 278 /* Restore bmiss rssi & count thresholds */ 279 OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr); 280 281 OS_REG_WRITE(ah, AR_ISR, ~0); /* cleared on write */ 282 283 if (!ar5212SetChannel(ah, chan)) 284 FAIL(HAL_EIO); 285 286 OS_MARK(ah, AH_MARK_RESET_LINE, __LINE__); 287 288 /* Set 1:1 QCU to DCU mapping for all queues */ 289 for (i = 0; i < AR_NUM_DCU; i++) 290 OS_REG_WRITE(ah, AR_DQCUMASK(i), 1 << i); 291 292 ahp->ah_intrTxqs = 0; 293 for (i = 0; i < AH_PRIVATE(ah)->ah_caps.halTotalQueues; i++) 294 ar5212ResetTxQueue(ah, i); 295 296 ar5416InitIMR(ah, opmode); 297 ar5212SetCoverageClass(ah, AH_PRIVATE(ah)->ah_coverageClass, 1); 298 ar5416InitQoS(ah); 299 ar5416InitUserSettings(ah); 300 301 /* 302 * disable seq number generation in hw 303 */ 304 OS_REG_WRITE(ah, AR_STA_ID1, 305 OS_REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM); 306 307 ar5416InitDMA(ah); 308 309 /* 310 * program OBS bus to see MAC interrupts 311 */ 312 OS_REG_WRITE(ah, AR_OBS, 8); 313 314#ifdef AR5416_INT_MITIGATION 315 OS_REG_WRITE(ah, AR_MIRT, 0); 316 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500); 317 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000); 318#endif 319 320 ar5416InitBB(ah, chan); 321 322 /* Setup compression registers */ 323 ar5212SetCompRegs(ah); /* XXX not needed? */ 324 325 /* 326 * 5416 baseband will check the per rate power table 327 * and select the lower of the two 328 */ 329 ackTpcPow = 63; 330 ctsTpcPow = 63; 331 chirpTpcPow = 63; 332 powerVal = SM(ackTpcPow, AR_TPC_ACK) | 333 SM(ctsTpcPow, AR_TPC_CTS) | 334 SM(chirpTpcPow, AR_TPC_CHIRP); 335 OS_REG_WRITE(ah, AR_TPC, powerVal); 336 337 if (!ar5416InitCal(ah, chan)) 338 FAIL(HAL_ESELFTEST); 339 340 AH_PRIVATE(ah)->ah_opmode = opmode; /* record operating mode */ 341 342 if (bChannelChange && !IEEE80211_IS_CHAN_DFS(chan)) 343 chan->ic_state &= ~IEEE80211_CHANSTATE_CWINT; 344 345 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n", __func__); 346 347 OS_MARK(ah, AH_MARK_RESET_DONE, 0); 348 349 return AH_TRUE; 350bad: 351 OS_MARK(ah, AH_MARK_RESET_DONE, ecode); 352 if (status != AH_NULL) 353 *status = ecode; 354 return AH_FALSE; 355#undef FAIL 356#undef N 357} 358 359#if 0 360/* 361 * This channel change evaluates whether the selected hardware can 362 * perform a synthesizer-only channel change (no reset). If the 363 * TX is not stopped, or the RFBus cannot be granted in the given 364 * time, the function returns false as a reset is necessary 365 */ 366HAL_BOOL 367ar5416ChannelChange(struct ath_hal *ah, const structu ieee80211_channel *chan) 368{ 369 uint32_t ulCount; 370 uint32_t data, synthDelay, qnum; 371 uint16_t rfXpdGain[4]; 372 struct ath_hal_5212 *ahp = AH5212(ah); 373 HAL_CHANNEL_INTERNAL *ichan; 374 375 /* 376 * Map public channel to private. 377 */ 378 ichan = ath_hal_checkchannel(ah, chan); 379 380 /* TX must be stopped or RF Bus grant will not work */ 381 for (qnum = 0; qnum < AH_PRIVATE(ah)->ah_caps.halTotalQueues; qnum++) { 382 if (ar5212NumTxPending(ah, qnum)) { 383 HALDEBUG(ah, HAL_DEBUG_ANY, 384 "%s: frames pending on queue %d\n", __func__, qnum); 385 return AH_FALSE; 386 } 387 } 388 389 /* 390 * Kill last Baseband Rx Frame - Request analog bus grant 391 */ 392 OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_REQUEST); 393 if (!ath_hal_wait(ah, AR_PHY_RFBUS_GNT, AR_PHY_RFBUS_GRANT_EN, AR_PHY_RFBUS_GRANT_EN)) { 394 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: could not kill baseband rx\n", 395 __func__); 396 return AH_FALSE; 397 } 398 399 ar5416Set11nRegs(ah, chan); /* NB: setup 5416-specific regs */ 400 401 /* Change the synth */ 402 if (!ar5212SetChannel(ah, chan)) 403 return AH_FALSE; 404 405 /* Setup the transmit power values. */ 406 if (!ar5416SetTransmitPower(ah, chan, rfXpdGain)) { 407 HALDEBUG(ah, HAL_DEBUG_ANY, 408 "%s: error init'ing transmit power\n", __func__); 409 return AH_FALSE; 410 } 411 412 /* 413 * Wait for the frequency synth to settle (synth goes on 414 * via PHY_ACTIVE_EN). Read the phy active delay register. 415 * Value is in 100ns increments. 416 */ 417 data = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 418 if (IS_CHAN_CCK(ichan)) { 419 synthDelay = (4 * data) / 22; 420 } else { 421 synthDelay = data / 10; 422 } 423 424 OS_DELAY(synthDelay + BASE_ACTIVATE_DELAY); 425 426 /* Release the RFBus Grant */ 427 OS_REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); 428 429 /* Write delta slope for OFDM enabled modes (A, G, Turbo) */ 430 if (IEEE80211_IS_CHAN_OFDM(ichan)|| IEEE80211_IS_CHAN_HT(chan)) { 431 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER5_3); 432 ar5212SetSpurMitigation(ah, chan); 433 ar5416SetDeltaSlope(ah, chan); 434 } 435 436 /* XXX spur mitigation for Melin */ 437 438 if (!IEEE80211_IS_CHAN_DFS(chan)) 439 chan->ic_state &= ~IEEE80211_CHANSTATE_CWINT; 440 441 ichan->channel_time = 0; 442 ichan->tsf_last = ar5212GetTsf64(ah); 443 ar5212TxEnable(ah, AH_TRUE); 444 return AH_TRUE; 445} 446#endif 447 448static void 449ar5416InitDMA(struct ath_hal *ah) 450{ 451 452 /* 453 * set AHB_MODE not to do cacheline prefetches 454 */ 455 OS_REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); 456 457 /* 458 * let mac dma reads be in 128 byte chunks 459 */ 460 OS_REG_WRITE(ah, AR_TXCFG, 461 (OS_REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK) | AR_TXCFG_DMASZ_128B); 462 463 /* 464 * let mac dma writes be in 128 byte chunks 465 */ 466 OS_REG_WRITE(ah, AR_RXCFG, 467 (OS_REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK) | AR_RXCFG_DMASZ_128B); 468 469 /* XXX restore TX trigger level */ 470 471 /* 472 * Setup receive FIFO threshold to hold off TX activities 473 */ 474 OS_REG_WRITE(ah, AR_RXFIFO_CFG, 0x200); 475 476 /* 477 * reduce the number of usable entries in PCU TXBUF to avoid 478 * wrap around. 479 */ 480 OS_REG_WRITE(ah, AR_PCU_TXBUF_CTRL, AR_PCU_TXBUF_CTRL_USABLE_SIZE); 481} 482 483static void 484ar5416InitBB(struct ath_hal *ah, const struct ieee80211_channel *chan) 485{ 486 uint32_t synthDelay; 487 488 /* 489 * Wait for the frequency synth to settle (synth goes on 490 * via AR_PHY_ACTIVE_EN). Read the phy active delay register. 491 * Value is in 100ns increments. 492 */ 493 synthDelay = OS_REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 494 if (IEEE80211_IS_CHAN_CCK(chan)) { 495 synthDelay = (4 * synthDelay) / 22; 496 } else { 497 synthDelay /= 10; 498 } 499 500 /* Turn on PLL on 5416 */ 501 HALDEBUG(ah, HAL_DEBUG_RESET, "%s %s channel\n", 502 __func__, IEEE80211_IS_CHAN_5GHZ(chan) ? "5GHz" : "2GHz"); 503 ar5416InitPLL(ah, chan); 504 505 /* Activate the PHY (includes baseband activate and synthesizer on) */ 506 OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 507 508 /* 509 * If the AP starts the calibration before the base band timeout 510 * completes we could get rx_clear false triggering. Add an 511 * extra BASE_ACTIVATE_DELAY usecs to ensure this condition 512 * does not happen. 513 */ 514 if (IEEE80211_IS_CHAN_HALF(chan)) { 515 OS_DELAY((synthDelay << 1) + BASE_ACTIVATE_DELAY); 516 } else if (IEEE80211_IS_CHAN_QUARTER(chan)) { 517 OS_DELAY((synthDelay << 2) + BASE_ACTIVATE_DELAY); 518 } else { 519 OS_DELAY(synthDelay + BASE_ACTIVATE_DELAY); 520 } 521} 522 523static void 524ar5416InitIMR(struct ath_hal *ah, HAL_OPMODE opmode) 525{ 526 struct ath_hal_5212 *ahp = AH5212(ah); 527 528 /* 529 * Setup interrupt handling. Note that ar5212ResetTxQueue 530 * manipulates the secondary IMR's as queues are enabled 531 * and disabled. This is done with RMW ops to insure the 532 * settings we make here are preserved. 533 */ 534 ahp->ah_maskReg = AR_IMR_TXERR | AR_IMR_TXURN 535 | AR_IMR_RXERR | AR_IMR_RXORN 536 | AR_IMR_BCNMISC; 537 538#ifdef AR5416_INT_MITIGATION 539 ahp->ah_maskReg |= AR_IMR_TXINTM | AR_IMR_RXINTM 540 | AR_IMR_TXMINTR | AR_IMR_RXMINTR; 541#else 542 ahp->ah_maskReg |= AR_IMR_TXOK | AR_IMR_RXOK; 543#endif 544 if (opmode == HAL_M_HOSTAP) 545 ahp->ah_maskReg |= AR_IMR_MIB; 546 OS_REG_WRITE(ah, AR_IMR, ahp->ah_maskReg); 547 /* Enable bus errors that are OR'd to set the HIUERR bit */ 548#if 0 549 OS_REG_WRITE(ah, AR_IMR_S2, 550 OS_REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT | AR_IMR_S2_CST); 551#endif 552} 553 554static void 555ar5416InitQoS(struct ath_hal *ah) 556{ 557 /* QoS support */ 558 OS_REG_WRITE(ah, AR_QOS_CONTROL, 0x100aa); /* XXX magic */ 559 OS_REG_WRITE(ah, AR_QOS_SELECT, 0x3210); /* XXX magic */ 560 561 /* Turn on NOACK Support for QoS packets */ 562 OS_REG_WRITE(ah, AR_NOACK, 563 SM(2, AR_NOACK_2BIT_VALUE) | 564 SM(5, AR_NOACK_BIT_OFFSET) | 565 SM(0, AR_NOACK_BYTE_OFFSET)); 566 567 /* 568 * initialize TXOP for all TIDs 569 */ 570 OS_REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL); 571 OS_REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF); 572 OS_REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF); 573 OS_REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF); 574 OS_REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF); 575} 576 577static void 578ar5416InitUserSettings(struct ath_hal *ah) 579{ 580 struct ath_hal_5212 *ahp = AH5212(ah); 581 582 /* Restore user-specified settings */ 583 if (ahp->ah_miscMode != 0) 584 OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode); 585 if (ahp->ah_sifstime != (u_int) -1) 586 ar5212SetSifsTime(ah, ahp->ah_sifstime); 587 if (ahp->ah_slottime != (u_int) -1) 588 ar5212SetSlotTime(ah, ahp->ah_slottime); 589 if (ahp->ah_acktimeout != (u_int) -1) 590 ar5212SetAckTimeout(ah, ahp->ah_acktimeout); 591 if (ahp->ah_ctstimeout != (u_int) -1) 592 ar5212SetCTSTimeout(ah, ahp->ah_ctstimeout); 593 if (AH_PRIVATE(ah)->ah_diagreg != 0) 594 OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg); 595#if 0 /* XXX Todo */ 596 if (ahp->ah_globaltxtimeout != (u_int) -1) 597 ar5416SetGlobalTxTimeout(ah, ahp->ah_globaltxtimeout); 598#endif 599} 600 601/* 602 * Places the hardware into reset and then pulls it out of reset 603 */ 604HAL_BOOL 605ar5416ChipReset(struct ath_hal *ah, const struct ieee80211_channel *chan) 606{ 607 OS_MARK(ah, AH_MARK_CHIPRESET, chan ? chan->ic_freq : 0); 608 /* 609 * Warm reset is optimistic. 610 */ 611 if (AR_SREV_MERLIN_20_OR_LATER(ah) && 612 ath_hal_eepromGetFlag(ah, AR_EEP_OL_PWRCTRL)) { 613 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) 614 return AH_FALSE; 615 } else { 616 if (!ar5416SetResetReg(ah, HAL_RESET_WARM)) 617 return AH_FALSE; 618 } 619 620 /* Bring out of sleep mode (AGAIN) */ 621 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 622 return AH_FALSE; 623 624 ar5416InitPLL(ah, chan); 625 626 /* 627 * Perform warm reset before the mode/PLL/turbo registers 628 * are changed in order to deactivate the radio. Mode changes 629 * with an active radio can result in corrupted shifts to the 630 * radio device. 631 */ 632 if (chan != AH_NULL) { 633 uint32_t rfMode; 634 635 /* treat channel B as channel G , no B mode suport in owl */ 636 rfMode = IEEE80211_IS_CHAN_CCK(chan) ? 637 AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM; 638 if (AR_SREV_MERLIN_20(ah) && IS_5GHZ_FAST_CLOCK_EN(ah, chan)) { 639 /* phy mode bits for 5GHz channels require Fast Clock */ 640 rfMode |= AR_PHY_MODE_DYNAMIC 641 | AR_PHY_MODE_DYN_CCK_DISABLE; 642 } else if (!AR_SREV_MERLIN_10_OR_LATER(ah)) { 643 rfMode |= IEEE80211_IS_CHAN_5GHZ(chan) ? 644 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ; 645 } 646 OS_REG_WRITE(ah, AR_PHY_MODE, rfMode); 647 } 648 return AH_TRUE; 649} 650 651/* 652 * Delta slope coefficient computation. 653 * Required for OFDM operation. 654 */ 655static void 656ar5416GetDeltaSlopeValues(struct ath_hal *ah, uint32_t coef_scaled, 657 uint32_t *coef_mantissa, uint32_t *coef_exponent) 658{ 659#define COEF_SCALE_S 24 660 uint32_t coef_exp, coef_man; 661 /* 662 * ALGO -> coef_exp = 14-floor(log2(coef)); 663 * floor(log2(x)) is the highest set bit position 664 */ 665 for (coef_exp = 31; coef_exp > 0; coef_exp--) 666 if ((coef_scaled >> coef_exp) & 0x1) 667 break; 668 /* A coef_exp of 0 is a legal bit position but an unexpected coef_exp */ 669 HALASSERT(coef_exp); 670 coef_exp = 14 - (coef_exp - COEF_SCALE_S); 671 672 /* 673 * ALGO -> coef_man = floor(coef* 2^coef_exp+0.5); 674 * The coefficient is already shifted up for scaling 675 */ 676 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1)); 677 678 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp); 679 *coef_exponent = coef_exp - 16; 680 681#undef COEF_SCALE_S 682} 683 684void 685ar5416SetDeltaSlope(struct ath_hal *ah, const struct ieee80211_channel *chan) 686{ 687#define INIT_CLOCKMHZSCALED 0x64000000 688 uint32_t coef_scaled, ds_coef_exp, ds_coef_man; 689 uint32_t clockMhzScaled; 690 691 CHAN_CENTERS centers; 692 693 /* half and quarter rate can divide the scaled clock by 2 or 4 respectively */ 694 /* scale for selected channel bandwidth */ 695 clockMhzScaled = INIT_CLOCKMHZSCALED; 696 if (IEEE80211_IS_CHAN_TURBO(chan)) 697 clockMhzScaled <<= 1; 698 else if (IEEE80211_IS_CHAN_HALF(chan)) 699 clockMhzScaled >>= 1; 700 else if (IEEE80211_IS_CHAN_QUARTER(chan)) 701 clockMhzScaled >>= 2; 702 703 /* 704 * ALGO -> coef = 1e8/fcarrier*fclock/40; 705 * scaled coef to provide precision for this floating calculation 706 */ 707 ar5416GetChannelCenters(ah, chan, ¢ers); 708 coef_scaled = clockMhzScaled / centers.synth_center; 709 710 ar5416GetDeltaSlopeValues(ah, coef_scaled, &ds_coef_man, &ds_coef_exp); 711 712 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3, 713 AR_PHY_TIMING3_DSC_MAN, ds_coef_man); 714 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3, 715 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp); 716 717 /* 718 * For Short GI, 719 * scaled coeff is 9/10 that of normal coeff 720 */ 721 coef_scaled = (9 * coef_scaled)/10; 722 723 ar5416GetDeltaSlopeValues(ah, coef_scaled, &ds_coef_man, &ds_coef_exp); 724 725 /* for short gi */ 726 OS_REG_RMW_FIELD(ah, AR_PHY_HALFGI, 727 AR_PHY_HALFGI_DSC_MAN, ds_coef_man); 728 OS_REG_RMW_FIELD(ah, AR_PHY_HALFGI, 729 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp); 730#undef INIT_CLOCKMHZSCALED 731} 732 733/* 734 * Set a limit on the overall output power. Used for dynamic 735 * transmit power control and the like. 736 * 737 * NB: limit is in units of 0.5 dbM. 738 */ 739HAL_BOOL 740ar5416SetTxPowerLimit(struct ath_hal *ah, uint32_t limit) 741{ 742 uint16_t dummyXpdGains[2]; 743 744 AH_PRIVATE(ah)->ah_powerLimit = AH_MIN(limit, MAX_RATE_POWER); 745 return ar5416SetTransmitPower(ah, AH_PRIVATE(ah)->ah_curchan, 746 dummyXpdGains); 747} 748 749HAL_BOOL 750ar5416GetChipPowerLimits(struct ath_hal *ah, 751 struct ieee80211_channel *chan) 752{ 753 struct ath_hal_5212 *ahp = AH5212(ah); 754 int16_t minPower, maxPower; 755 756 /* 757 * Get Pier table max and min powers. 758 */ 759 if (ahp->ah_rfHal->getChannelMaxMinPower(ah, chan, &maxPower, &minPower)) { 760 /* NB: rf code returns 1/4 dBm units, convert */ 761 chan->ic_maxpower = maxPower / 2; 762 chan->ic_minpower = minPower / 2; 763 } else { 764 HALDEBUG(ah, HAL_DEBUG_ANY, 765 "%s: no min/max power for %u/0x%x\n", 766 __func__, chan->ic_freq, chan->ic_flags); 767 chan->ic_maxpower = AR5416_MAX_RATE_POWER; 768 chan->ic_minpower = 0; 769 } 770 HALDEBUG(ah, HAL_DEBUG_RESET, 771 "Chan %d: MaxPow = %d MinPow = %d\n", 772 chan->ic_freq, chan->ic_maxpower, chan->ic_minpower); 773 return AH_TRUE; 774} 775 776/* XXX gag, this is sick */ 777typedef enum Ar5416_Rates { 778 rate6mb, rate9mb, rate12mb, rate18mb, 779 rate24mb, rate36mb, rate48mb, rate54mb, 780 rate1l, rate2l, rate2s, rate5_5l, 781 rate5_5s, rate11l, rate11s, rateXr, 782 rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3, 783 rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7, 784 rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3, 785 rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7, 786 rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm, 787 Ar5416RateSize 788} AR5416_RATES; 789 790/************************************************************** 791 * ar5416SetTransmitPower 792 * 793 * Set the transmit power in the baseband for the given 794 * operating channel and mode. 795 */ 796static HAL_BOOL 797ar5416SetTransmitPower(struct ath_hal *ah, 798 const struct ieee80211_channel *chan, uint16_t *rfXpdGain) 799{ 800#define POW_SM(_r, _s) (((_r) & 0x3f) << (_s)) 801#define N(a) (sizeof (a) / sizeof (a[0])) 802 803 MODAL_EEP_HEADER *pModal; 804 struct ath_hal_5212 *ahp = AH5212(ah); 805 int16_t ratesArray[Ar5416RateSize]; 806 int16_t txPowerIndexOffset = 0; 807 uint8_t ht40PowerIncForPdadc = 2; 808 int i; 809 810 uint16_t cfgCtl; 811 uint16_t powerLimit; 812 uint16_t twiceAntennaReduction; 813 uint16_t twiceMaxRegulatoryPower; 814 int16_t maxPower; 815 HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom; 816 struct ar5416eeprom *pEepData = &ee->ee_base; 817 818 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1); 819 820 /* Setup info for the actual eeprom */ 821 OS_MEMZERO(ratesArray, sizeof(ratesArray)); 822 cfgCtl = ath_hal_getctl(ah, chan); 823 powerLimit = chan->ic_maxregpower * 2; 824 twiceAntennaReduction = chan->ic_maxantgain; 825 twiceMaxRegulatoryPower = AH_MIN(MAX_RATE_POWER, AH_PRIVATE(ah)->ah_powerLimit); 826 pModal = &pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)]; 827 HALDEBUG(ah, HAL_DEBUG_RESET, "%s Channel=%u CfgCtl=%u\n", 828 __func__,chan->ic_freq, cfgCtl ); 829 830 if (IS_EEP_MINOR_V2(ah)) { 831 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc; 832 } 833 834 if (!ar5416SetPowerPerRateTable(ah, pEepData, chan, 835 &ratesArray[0],cfgCtl, 836 twiceAntennaReduction, 837 twiceMaxRegulatoryPower, powerLimit)) { 838 HALDEBUG(ah, HAL_DEBUG_ANY, 839 "%s: unable to set tx power per rate table\n", __func__); 840 return AH_FALSE; 841 } 842 843 if (!ar5416SetPowerCalTable(ah, pEepData, chan, &txPowerIndexOffset)) { 844 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set power table\n", 845 __func__); 846 return AH_FALSE; 847 } 848 849 maxPower = AH_MAX(ratesArray[rate6mb], ratesArray[rateHt20_0]); 850 851 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 852 maxPower = AH_MAX(maxPower, ratesArray[rate1l]); 853 } 854 855 if (IEEE80211_IS_CHAN_HT40(chan)) { 856 maxPower = AH_MAX(maxPower, ratesArray[rateHt40_0]); 857 } 858 859 ahp->ah_tx6PowerInHalfDbm = maxPower; 860 AH_PRIVATE(ah)->ah_maxPowerLevel = maxPower; 861 ahp->ah_txPowerIndexOffset = txPowerIndexOffset; 862 863 /* 864 * txPowerIndexOffset is set by the SetPowerTable() call - 865 * adjust the rate table (0 offset if rates EEPROM not loaded) 866 */ 867 for (i = 0; i < N(ratesArray); i++) { 868 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); 869 if (ratesArray[i] > AR5416_MAX_RATE_POWER) 870 ratesArray[i] = AR5416_MAX_RATE_POWER; 871 } 872 873#ifdef AH_EEPROM_DUMP 874 ar5416PrintPowerPerRate(ah, ratesArray); 875#endif 876 877 /* Write the OFDM power per rate set */ 878 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE1, 879 POW_SM(ratesArray[rate18mb], 24) 880 | POW_SM(ratesArray[rate12mb], 16) 881 | POW_SM(ratesArray[rate9mb], 8) 882 | POW_SM(ratesArray[rate6mb], 0) 883 ); 884 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE2, 885 POW_SM(ratesArray[rate54mb], 24) 886 | POW_SM(ratesArray[rate48mb], 16) 887 | POW_SM(ratesArray[rate36mb], 8) 888 | POW_SM(ratesArray[rate24mb], 0) 889 ); 890 891 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 892 /* Write the CCK power per rate set */ 893 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE3, 894 POW_SM(ratesArray[rate2s], 24) 895 | POW_SM(ratesArray[rate2l], 16) 896 | POW_SM(ratesArray[rateXr], 8) /* XR target power */ 897 | POW_SM(ratesArray[rate1l], 0) 898 ); 899 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE4, 900 POW_SM(ratesArray[rate11s], 24) 901 | POW_SM(ratesArray[rate11l], 16) 902 | POW_SM(ratesArray[rate5_5s], 8) 903 | POW_SM(ratesArray[rate5_5l], 0) 904 ); 905 HALDEBUG(ah, HAL_DEBUG_RESET, 906 "%s AR_PHY_POWER_TX_RATE3=0x%x AR_PHY_POWER_TX_RATE4=0x%x\n", 907 __func__, OS_REG_READ(ah,AR_PHY_POWER_TX_RATE3), 908 OS_REG_READ(ah,AR_PHY_POWER_TX_RATE4)); 909 } 910 911 /* Write the HT20 power per rate set */ 912 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE5, 913 POW_SM(ratesArray[rateHt20_3], 24) 914 | POW_SM(ratesArray[rateHt20_2], 16) 915 | POW_SM(ratesArray[rateHt20_1], 8) 916 | POW_SM(ratesArray[rateHt20_0], 0) 917 ); 918 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE6, 919 POW_SM(ratesArray[rateHt20_7], 24) 920 | POW_SM(ratesArray[rateHt20_6], 16) 921 | POW_SM(ratesArray[rateHt20_5], 8) 922 | POW_SM(ratesArray[rateHt20_4], 0) 923 ); 924 925 if (IEEE80211_IS_CHAN_HT40(chan)) { 926 /* Write the HT40 power per rate set */ 927 /* Correct PAR difference between HT40 and HT20/LEGACY */ 928 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE7, 929 POW_SM(ratesArray[rateHt40_3] + ht40PowerIncForPdadc, 24) 930 | POW_SM(ratesArray[rateHt40_2] + ht40PowerIncForPdadc, 16) 931 | POW_SM(ratesArray[rateHt40_1] + ht40PowerIncForPdadc, 8) 932 | POW_SM(ratesArray[rateHt40_0] + ht40PowerIncForPdadc, 0) 933 ); 934 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE8, 935 POW_SM(ratesArray[rateHt40_7] + ht40PowerIncForPdadc, 24) 936 | POW_SM(ratesArray[rateHt40_6] + ht40PowerIncForPdadc, 16) 937 | POW_SM(ratesArray[rateHt40_5] + ht40PowerIncForPdadc, 8) 938 | POW_SM(ratesArray[rateHt40_4] + ht40PowerIncForPdadc, 0) 939 ); 940 /* Write the Dup/Ext 40 power per rate set */ 941 OS_REG_WRITE(ah, AR_PHY_POWER_TX_RATE9, 942 POW_SM(ratesArray[rateExtOfdm], 24) 943 | POW_SM(ratesArray[rateExtCck], 16) 944 | POW_SM(ratesArray[rateDupOfdm], 8) 945 | POW_SM(ratesArray[rateDupCck], 0) 946 ); 947 } 948 949 /* Write the Power subtraction for dynamic chain changing, for per-packet powertx */ 950 OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB, 951 POW_SM(pModal->pwrDecreaseFor3Chain, 6) 952 | POW_SM(pModal->pwrDecreaseFor2Chain, 0) 953 ); 954 return AH_TRUE; 955#undef POW_SM 956#undef N 957} 958 959/* 960 * Exported call to check for a recent gain reading and return 961 * the current state of the thermal calibration gain engine. 962 */ 963HAL_RFGAIN 964ar5416GetRfgain(struct ath_hal *ah) 965{ 966 return HAL_RFGAIN_INACTIVE; 967} 968 969/* 970 * Places all of hardware into reset 971 */ 972HAL_BOOL 973ar5416Disable(struct ath_hal *ah) 974{ 975 if (!ar5212SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 976 return AH_FALSE; 977 return ar5416SetResetReg(ah, HAL_RESET_COLD); 978} 979 980/* 981 * Places the PHY and Radio chips into reset. A full reset 982 * must be called to leave this state. The PCI/MAC/PCU are 983 * not placed into reset as we must receive interrupt to 984 * re-enable the hardware. 985 */ 986HAL_BOOL 987ar5416PhyDisable(struct ath_hal *ah) 988{ 989 return ar5416SetResetReg(ah, HAL_RESET_WARM); 990} 991 992/* 993 * Write the given reset bit mask into the reset register 994 */ 995HAL_BOOL 996ar5416SetResetReg(struct ath_hal *ah, uint32_t type) 997{ 998 switch (type) { 999 case HAL_RESET_POWER_ON: 1000 return ar5416SetResetPowerOn(ah); 1001 case HAL_RESET_WARM: 1002 case HAL_RESET_COLD: 1003 return ar5416SetReset(ah, type); 1004 default: 1005 HALASSERT(AH_FALSE); 1006 return AH_FALSE; 1007 } 1008} 1009 1010static HAL_BOOL 1011ar5416SetResetPowerOn(struct ath_hal *ah) 1012{ 1013 /* Power On Reset (Hard Reset) */ 1014 1015 /* 1016 * Set force wake 1017 * 1018 * If the MAC was running, previously calling 1019 * reset will wake up the MAC but it may go back to sleep 1020 * before we can start polling. 1021 * Set force wake stops that 1022 * This must be called before initiating a hard reset. 1023 */ 1024 OS_REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1025 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1026 1027 /* 1028 * RTC reset and clear 1029 */ 1030 OS_REG_WRITE(ah, AR_RTC_RESET, 0); 1031 OS_DELAY(20); 1032 OS_REG_WRITE(ah, AR_RTC_RESET, 1); 1033 1034 /* 1035 * Poll till RTC is ON 1036 */ 1037 if (!ath_hal_wait(ah, AR_RTC_STATUS, AR_RTC_PM_STATUS_M, AR_RTC_STATUS_ON)) { 1038 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RTC not waking up\n", __func__); 1039 return AH_FALSE; 1040 } 1041 1042 return ar5416SetReset(ah, HAL_RESET_COLD); 1043} 1044 1045static HAL_BOOL 1046ar5416SetReset(struct ath_hal *ah, int type) 1047{ 1048 uint32_t tmpReg; 1049 1050 /* 1051 * Force wake 1052 */ 1053 OS_REG_WRITE(ah, AR_RTC_FORCE_WAKE, 1054 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT); 1055 1056 /* 1057 * Reset AHB 1058 */ 1059 tmpReg = OS_REG_READ(ah, AR_INTR_SYNC_CAUSE); 1060 if (tmpReg & (AR_INTR_SYNC_LOCAL_TIMEOUT|AR_INTR_SYNC_RADM_CPL_TIMEOUT)) { 1061 OS_REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0); 1062 OS_REG_WRITE(ah, AR_RC, AR_RC_AHB|AR_RC_HOSTIF); 1063 } else { 1064 OS_REG_WRITE(ah, AR_RC, AR_RC_AHB); 1065 } 1066 1067 /* 1068 * Set Mac(BB,Phy) Warm Reset 1069 */ 1070 switch (type) { 1071 case HAL_RESET_WARM: 1072 OS_REG_WRITE(ah, AR_RTC_RC, AR_RTC_RC_MAC_WARM); 1073 break; 1074 case HAL_RESET_COLD: 1075 OS_REG_WRITE(ah, AR_RTC_RC, AR_RTC_RC_MAC_WARM|AR_RTC_RC_MAC_COLD); 1076 break; 1077 default: 1078 HALASSERT(AH_FALSE); 1079 break; 1080 } 1081 1082 /* 1083 * Clear resets and force wakeup 1084 */ 1085 OS_REG_WRITE(ah, AR_RTC_RC, 0); 1086 if (!ath_hal_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0)) { 1087 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RTC stuck in MAC reset\n", __func__); 1088 return AH_FALSE; 1089 } 1090 1091 /* Clear AHB reset */ 1092 OS_REG_WRITE(ah, AR_RC, 0); 1093 1094 /* Set register and descriptor swapping on 1095 * Bigendian platforms on cold reset 1096 */ 1097#ifdef __BIG_ENDIAN__ 1098 if (type == HAL_RESET_COLD) { 1099 uint32_t mask; 1100 1101 HALDEBUG(ah, HAL_DEBUG_RESET, 1102 "%s Applying descriptor swap\n", __func__); 1103 1104 mask = INIT_CONFIG_STATUS | AR_CFG_SWRD | AR_CFG_SWRG; 1105#ifndef AH_NEED_DESC_SWAP 1106 mask |= AR_CFG_SWTD; 1107#endif 1108 OS_REG_WRITE(ah, AR_CFG, LE_READ_4(&mask)); 1109 } 1110#endif 1111 1112 ar5416InitPLL(ah, AH_NULL); 1113 1114 return AH_TRUE; 1115} 1116 1117#ifndef IS_5GHZ_FAST_CLOCK_EN 1118#define IS_5GHZ_FAST_CLOCK_EN(ah, chan) AH_FALSE 1119#endif 1120 1121static void 1122ar5416InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan) 1123{ 1124 uint32_t pll; 1125 1126 if (AR_SREV_MERLIN_20(ah) && 1127 chan != AH_NULL && IEEE80211_IS_CHAN_5GHZ(chan)) { 1128 /* 1129 * PLL WAR for Merlin 2.0/2.1 1130 * When doing fast clock, set PLL to 0x142c 1131 * Else, set PLL to 0x2850 to prevent reset-to-reset variation 1132 */ 1133 pll = IS_5GHZ_FAST_CLOCK_EN(ah, chan) ? 0x142c : 0x2850; 1134 } else if (AR_SREV_MERLIN_10_OR_LATER(ah)) { 1135 pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV); 1136 if (chan != AH_NULL) { 1137 if (IEEE80211_IS_CHAN_HALF(chan)) 1138 pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL); 1139 else if (IEEE80211_IS_CHAN_QUARTER(chan)) 1140 pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL); 1141 else if (IEEE80211_IS_CHAN_5GHZ(chan)) 1142 pll |= SM(0x28, AR_RTC_SOWL_PLL_DIV); 1143 else 1144 pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV); 1145 } else 1146 pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV); 1147 } else if (AR_SREV_SOWL_10_OR_LATER(ah)) { 1148 pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV); 1149 if (chan != AH_NULL) { 1150 if (IEEE80211_IS_CHAN_HALF(chan)) 1151 pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL); 1152 else if (IEEE80211_IS_CHAN_QUARTER(chan)) 1153 pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL); 1154 else if (IEEE80211_IS_CHAN_5GHZ(chan)) 1155 pll |= SM(0x50, AR_RTC_SOWL_PLL_DIV); 1156 else 1157 pll |= SM(0x58, AR_RTC_SOWL_PLL_DIV); 1158 } else 1159 pll |= SM(0x58, AR_RTC_SOWL_PLL_DIV); 1160 } else { 1161 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2; 1162 if (chan != AH_NULL) { 1163 if (IEEE80211_IS_CHAN_HALF(chan)) 1164 pll |= SM(0x1, AR_RTC_PLL_CLKSEL); 1165 else if (IEEE80211_IS_CHAN_QUARTER(chan)) 1166 pll |= SM(0x2, AR_RTC_PLL_CLKSEL); 1167 else if (IEEE80211_IS_CHAN_5GHZ(chan)) 1168 pll |= SM(0xa, AR_RTC_PLL_DIV); 1169 else 1170 pll |= SM(0xb, AR_RTC_PLL_DIV); 1171 } else 1172 pll |= SM(0xb, AR_RTC_PLL_DIV); 1173 } 1174 OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 1175 1176 /* TODO: 1177 * For multi-band owl, switch between bands by reiniting the PLL. 1178 */ 1179 1180 OS_DELAY(RTC_PLL_SETTLE_DELAY); 1181 1182 OS_REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_SLEEP_DERIVED_CLK); 1183} 1184 1185/* 1186 * Read EEPROM header info and program the device for correct operation 1187 * given the channel value. 1188 */ 1189static HAL_BOOL 1190ar5416SetBoardValues(struct ath_hal *ah, const struct ieee80211_channel *chan) 1191{ 1192 const HAL_EEPROM_v14 *ee = AH_PRIVATE(ah)->ah_eeprom; 1193 const struct ar5416eeprom *eep = &ee->ee_base; 1194 const MODAL_EEP_HEADER *pModal; 1195 int i, regChainOffset; 1196 uint8_t txRxAttenLocal; /* workaround for eeprom versions <= 14.2 */ 1197 1198 HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1); 1199 pModal = &eep->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)]; 1200 1201 /* NB: workaround for eeprom versions <= 14.2 */ 1202 txRxAttenLocal = IEEE80211_IS_CHAN_2GHZ(chan) ? 23 : 44; 1203 1204 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon); 1205 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 1206 if (AR_SREV_MERLIN(ah)) { 1207 if (i >= 2) break; 1208 } 1209 if (AR_SREV_OWL_20_OR_LATER(ah) && 1210 (AH5416(ah)->ah_rx_chainmask == 0x5 || 1211 AH5416(ah)->ah_tx_chainmask == 0x5) && i != 0) { 1212 /* Regs are swapped from chain 2 to 1 for 5416 2_0 with 1213 * only chains 0 and 2 populated 1214 */ 1215 regChainOffset = (i == 1) ? 0x2000 : 0x1000; 1216 } else { 1217 regChainOffset = i * 0x1000; 1218 } 1219 1220 OS_REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset, pModal->antCtrlChain[i]); 1221 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4 + regChainOffset, 1222 (OS_REG_READ(ah, AR_PHY_TIMING_CTRL4 + regChainOffset) & 1223 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF | AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) | 1224 SM(pModal->iqCalICh[i], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) | 1225 SM(pModal->iqCalQCh[i], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF)); 1226 1227 /* 1228 * Large signal upgrade. 1229 * XXX update 1230 */ 1231 1232 if ((i == 0) || AR_SREV_OWL_20_OR_LATER(ah)) { 1233 OS_REG_WRITE(ah, AR_PHY_RXGAIN + regChainOffset, 1234 (OS_REG_READ(ah, AR_PHY_RXGAIN + regChainOffset) & ~AR_PHY_RXGAIN_TXRX_ATTEN) | 1235 SM(IS_EEP_MINOR_V3(ah) ? pModal->txRxAttenCh[i] : txRxAttenLocal, 1236 AR_PHY_RXGAIN_TXRX_ATTEN)); 1237 1238 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset, 1239 (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) & ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) | 1240 SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN)); 1241 } 1242 } 1243 1244 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, pModal->switchSettling); 1245 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC, pModal->adcDesiredSize); 1246 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_PGA, pModal->pgaDesiredSize); 1247 OS_REG_WRITE(ah, AR_PHY_RF_CTL4, 1248 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) 1249 | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) 1250 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON) 1251 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON)); 1252 1253 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON, pModal->txEndToRxOn); 1254 1255 if (AR_SREV_MERLIN_10_OR_LATER(ah)) { 1256 OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62, 1257 pModal->thresh62); 1258 OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62, 1259 pModal->thresh62); 1260 } else { 1261 OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62, 1262 pModal->thresh62); 1263 OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA_THRESH62, 1264 pModal->thresh62); 1265 } 1266 1267 /* Minor Version Specific application */ 1268 if (IS_EEP_MINOR_V2(ah)) { 1269 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_DATA_START, pModal->txFrameToDataStart); 1270 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_FRAME_TO_PA_ON, pModal->txFrameToPaOn); 1271 } 1272 1273 if (IS_EEP_MINOR_V3(ah)) { 1274 if (IEEE80211_IS_CHAN_HT40(chan)) { 1275 /* Overwrite switch settling with HT40 value */ 1276 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH, pModal->swSettleHt40); 1277 } 1278 1279 if ((AR_SREV_OWL_20_OR_LATER(ah)) && 1280 ( AH5416(ah)->ah_rx_chainmask == 0x5 || AH5416(ah)->ah_tx_chainmask == 0x5)){ 1281 /* Reg Offsets are swapped for logical mapping */ 1282 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) | 1283 SM(pModal->bswMargin[2], AR_PHY_GAIN_2GHZ_BSW_MARGIN)); 1284 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) | 1285 SM(pModal->bswAtten[2], AR_PHY_GAIN_2GHZ_BSW_ATTEN)); 1286 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) | 1287 SM(pModal->bswMargin[1], AR_PHY_GAIN_2GHZ_BSW_MARGIN)); 1288 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) | 1289 SM(pModal->bswAtten[1], AR_PHY_GAIN_2GHZ_BSW_ATTEN)); 1290 } else { 1291 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) | 1292 SM(pModal->bswMargin[1], AR_PHY_GAIN_2GHZ_BSW_MARGIN)); 1293 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) | 1294 SM(pModal->bswAtten[1], AR_PHY_GAIN_2GHZ_BSW_ATTEN)); 1295 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) | 1296 SM(pModal->bswMargin[2],AR_PHY_GAIN_2GHZ_BSW_MARGIN)); 1297 OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) | 1298 SM(pModal->bswAtten[2], AR_PHY_GAIN_2GHZ_BSW_ATTEN)); 1299 } 1300 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_BSW_MARGIN, pModal->bswMargin[0]); 1301 OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_BSW_ATTEN, pModal->bswAtten[0]); 1302 } 1303 return AH_TRUE; 1304} 1305 1306/* 1307 * Helper functions common for AP/CB/XB 1308 */ 1309 1310/* 1311 * ar5416SetPowerPerRateTable 1312 * 1313 * Sets the transmit power in the baseband for the given 1314 * operating channel and mode. 1315 */ 1316static HAL_BOOL 1317ar5416SetPowerPerRateTable(struct ath_hal *ah, struct ar5416eeprom *pEepData, 1318 const struct ieee80211_channel *chan, 1319 int16_t *ratesArray, uint16_t cfgCtl, 1320 uint16_t AntennaReduction, 1321 uint16_t twiceMaxRegulatoryPower, 1322 uint16_t powerLimit) 1323{ 1324#define N(a) (sizeof(a)/sizeof(a[0])) 1325/* Local defines to distinguish between extension and control CTL's */ 1326#define EXT_ADDITIVE (0x8000) 1327#define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE) 1328#define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE) 1329#define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE) 1330 1331 uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 1332 int i; 1333 int16_t twiceLargestAntenna; 1334 CAL_CTL_DATA *rep; 1335 CAL_TARGET_POWER_LEG targetPowerOfdm, targetPowerCck = {0, {0, 0, 0, 0}}; 1336 CAL_TARGET_POWER_LEG targetPowerOfdmExt = {0, {0, 0, 0, 0}}, targetPowerCckExt = {0, {0, 0, 0, 0}}; 1337 CAL_TARGET_POWER_HT targetPowerHt20, targetPowerHt40 = {0, {0, 0, 0, 0}}; 1338 int16_t scaledPower, minCtlPower; 1339 1340#define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */ 1341#define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */ 1342 static const uint16_t ctlModesFor11a[] = { 1343 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 1344 }; 1345 static const uint16_t ctlModesFor11g[] = { 1346 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40 1347 }; 1348 const uint16_t *pCtlMode; 1349 uint16_t numCtlModes, ctlMode, freq; 1350 CHAN_CENTERS centers; 1351 1352 ar5416GetChannelCenters(ah, chan, ¢ers); 1353 1354 /* Compute TxPower reduction due to Antenna Gain */ 1355 1356 twiceLargestAntenna = AH_MAX(AH_MAX( 1357 pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[0], 1358 pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[1]), 1359 pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[2]); 1360#if 0 1361 /* Turn it back on if we need to calculate per chain antenna gain reduction */ 1362 /* Use only if the expected gain > 6dbi */ 1363 /* Chain 0 is always used */ 1364 twiceLargestAntenna = pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[0]; 1365 1366 /* Look at antenna gains of Chains 1 and 2 if the TX mask is set */ 1367 if (ahp->ah_tx_chainmask & 0x2) 1368 twiceLargestAntenna = AH_MAX(twiceLargestAntenna, 1369 pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[1]); 1370 1371 if (ahp->ah_tx_chainmask & 0x4) 1372 twiceLargestAntenna = AH_MAX(twiceLargestAntenna, 1373 pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[2]); 1374#endif 1375 twiceLargestAntenna = (int16_t)AH_MIN((AntennaReduction) - twiceLargestAntenna, 0); 1376 1377 /* XXX setup for 5212 use (really used?) */ 1378 ath_hal_eepromSet(ah, 1379 IEEE80211_IS_CHAN_2GHZ(chan) ? AR_EEP_ANTGAINMAX_2 : AR_EEP_ANTGAINMAX_5, 1380 twiceLargestAntenna); 1381 1382 /* 1383 * scaledPower is the minimum of the user input power level and 1384 * the regulatory allowed power level 1385 */ 1386 scaledPower = AH_MIN(powerLimit, twiceMaxRegulatoryPower + twiceLargestAntenna); 1387 1388 /* Reduce scaled Power by number of chains active to get to per chain tx power level */ 1389 /* TODO: better value than these? */ 1390 switch (owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask)) { 1391 case 1: 1392 break; 1393 case 2: 1394 scaledPower -= pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pwrDecreaseFor2Chain; 1395 break; 1396 case 3: 1397 scaledPower -= pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pwrDecreaseFor3Chain; 1398 break; 1399 default: 1400 return AH_FALSE; /* Unsupported number of chains */ 1401 } 1402 1403 scaledPower = AH_MAX(0, scaledPower); 1404 1405 /* Get target powers from EEPROM - our baseline for TX Power */ 1406 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 1407 /* Setup for CTL modes */ 1408 numCtlModes = N(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40; /* CTL_11B, CTL_11G, CTL_2GHT20 */ 1409 pCtlMode = ctlModesFor11g; 1410 1411 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck, 1412 AR5416_NUM_2G_CCK_TARGET_POWERS, &targetPowerCck, 4, AH_FALSE); 1413 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G, 1414 AR5416_NUM_2G_20_TARGET_POWERS, &targetPowerOfdm, 4, AH_FALSE); 1415 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT20, 1416 AR5416_NUM_2G_20_TARGET_POWERS, &targetPowerHt20, 8, AH_FALSE); 1417 1418 if (IEEE80211_IS_CHAN_HT40(chan)) { 1419 numCtlModes = N(ctlModesFor11g); /* All 2G CTL's */ 1420 1421 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower2GHT40, 1422 AR5416_NUM_2G_40_TARGET_POWERS, &targetPowerHt40, 8, AH_TRUE); 1423 /* Get target powers for extension channels */ 1424 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPowerCck, 1425 AR5416_NUM_2G_CCK_TARGET_POWERS, &targetPowerCckExt, 4, AH_TRUE); 1426 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower2G, 1427 AR5416_NUM_2G_20_TARGET_POWERS, &targetPowerOfdmExt, 4, AH_TRUE); 1428 } 1429 } else { 1430 /* Setup for CTL modes */ 1431 numCtlModes = N(ctlModesFor11a) - SUB_NUM_CTL_MODES_AT_5G_40; /* CTL_11A, CTL_5GHT20 */ 1432 pCtlMode = ctlModesFor11a; 1433 1434 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower5G, 1435 AR5416_NUM_5G_20_TARGET_POWERS, &targetPowerOfdm, 4, AH_FALSE); 1436 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower5GHT20, 1437 AR5416_NUM_5G_20_TARGET_POWERS, &targetPowerHt20, 8, AH_FALSE); 1438 1439 if (IEEE80211_IS_CHAN_HT40(chan)) { 1440 numCtlModes = N(ctlModesFor11a); /* All 5G CTL's */ 1441 1442 ar5416GetTargetPowers(ah, chan, pEepData->calTargetPower5GHT40, 1443 AR5416_NUM_5G_40_TARGET_POWERS, &targetPowerHt40, 8, AH_TRUE); 1444 ar5416GetTargetPowersLeg(ah, chan, pEepData->calTargetPower5G, 1445 AR5416_NUM_5G_20_TARGET_POWERS, &targetPowerOfdmExt, 4, AH_TRUE); 1446 } 1447 } 1448 1449 /* 1450 * For MIMO, need to apply regulatory caps individually across dynamically 1451 * running modes: CCK, OFDM, HT20, HT40 1452 * 1453 * The outer loop walks through each possible applicable runtime mode. 1454 * The inner loop walks through each ctlIndex entry in EEPROM. 1455 * The ctl value is encoded as [7:4] == test group, [3:0] == test mode. 1456 * 1457 */ 1458 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) { 1459 HAL_BOOL isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) || 1460 (pCtlMode[ctlMode] == CTL_2GHT40); 1461 if (isHt40CtlMode) { 1462 freq = centers.ctl_center; 1463 } else if (pCtlMode[ctlMode] & EXT_ADDITIVE) { 1464 freq = centers.ext_center; 1465 } else { 1466 freq = centers.ctl_center; 1467 } 1468 1469 /* walk through each CTL index stored in EEPROM */ 1470 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) { 1471 uint16_t twiceMinEdgePower; 1472 1473 /* compare test group from regulatory channel list with test mode from pCtlMode list */ 1474 if ((((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == pEepData->ctlIndex[i]) || 1475 (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == 1476 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) { 1477 rep = &(pEepData->ctlData[i]); 1478 twiceMinEdgePower = ar5416GetMaxEdgePower(freq, 1479 rep->ctlEdges[owl_get_ntxchains(AH5416(ah)->ah_tx_chainmask) - 1], 1480 IEEE80211_IS_CHAN_2GHZ(chan)); 1481 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) { 1482 /* Find the minimum of all CTL edge powers that apply to this channel */ 1483 twiceMaxEdgePower = AH_MIN(twiceMaxEdgePower, twiceMinEdgePower); 1484 } else { 1485 /* specific */ 1486 twiceMaxEdgePower = twiceMinEdgePower; 1487 break; 1488 } 1489 } 1490 } 1491 minCtlPower = (uint8_t)AH_MIN(twiceMaxEdgePower, scaledPower); 1492 /* Apply ctl mode to correct target power set */ 1493 switch(pCtlMode[ctlMode]) { 1494 case CTL_11B: 1495 for (i = 0; i < N(targetPowerCck.tPow2x); i++) { 1496 targetPowerCck.tPow2x[i] = (uint8_t)AH_MIN(targetPowerCck.tPow2x[i], minCtlPower); 1497 } 1498 break; 1499 case CTL_11A: 1500 case CTL_11G: 1501 for (i = 0; i < N(targetPowerOfdm.tPow2x); i++) { 1502 targetPowerOfdm.tPow2x[i] = (uint8_t)AH_MIN(targetPowerOfdm.tPow2x[i], minCtlPower); 1503 } 1504 break; 1505 case CTL_5GHT20: 1506 case CTL_2GHT20: 1507 for (i = 0; i < N(targetPowerHt20.tPow2x); i++) { 1508 targetPowerHt20.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt20.tPow2x[i], minCtlPower); 1509 } 1510 break; 1511 case CTL_11B_EXT: 1512 targetPowerCckExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerCckExt.tPow2x[0], minCtlPower); 1513 break; 1514 case CTL_11A_EXT: 1515 case CTL_11G_EXT: 1516 targetPowerOfdmExt.tPow2x[0] = (uint8_t)AH_MIN(targetPowerOfdmExt.tPow2x[0], minCtlPower); 1517 break; 1518 case CTL_5GHT40: 1519 case CTL_2GHT40: 1520 for (i = 0; i < N(targetPowerHt40.tPow2x); i++) { 1521 targetPowerHt40.tPow2x[i] = (uint8_t)AH_MIN(targetPowerHt40.tPow2x[i], minCtlPower); 1522 } 1523 break; 1524 default: 1525 return AH_FALSE; 1526 break; 1527 } 1528 } /* end ctl mode checking */ 1529 1530 /* Set rates Array from collected data */ 1531 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] = ratesArray[rate18mb] = ratesArray[rate24mb] = targetPowerOfdm.tPow2x[0]; 1532 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1]; 1533 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2]; 1534 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3]; 1535 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0]; 1536 1537 for (i = 0; i < N(targetPowerHt20.tPow2x); i++) { 1538 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i]; 1539 } 1540 1541 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 1542 ratesArray[rate1l] = targetPowerCck.tPow2x[0]; 1543 ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1]; 1544 ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2]; 1545 ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3]; 1546 } 1547 if (IEEE80211_IS_CHAN_HT40(chan)) { 1548 for (i = 0; i < N(targetPowerHt40.tPow2x); i++) { 1549 ratesArray[rateHt40_0 + i] = targetPowerHt40.tPow2x[i]; 1550 } 1551 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0]; 1552 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0]; 1553 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0]; 1554 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 1555 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0]; 1556 } 1557 } 1558 return AH_TRUE; 1559#undef EXT_ADDITIVE 1560#undef CTL_11A_EXT 1561#undef CTL_11G_EXT 1562#undef CTL_11B_EXT 1563#undef SUB_NUM_CTL_MODES_AT_5G_40 1564#undef SUB_NUM_CTL_MODES_AT_2G_40 1565#undef N 1566} 1567 1568/************************************************************************** 1569 * fbin2freq 1570 * 1571 * Get channel value from binary representation held in eeprom 1572 * RETURNS: the frequency in MHz 1573 */ 1574static uint16_t 1575fbin2freq(uint8_t fbin, HAL_BOOL is2GHz) 1576{ 1577 /* 1578 * Reserved value 0xFF provides an empty definition both as 1579 * an fbin and as a frequency - do not convert 1580 */ 1581 if (fbin == AR5416_BCHAN_UNUSED) { 1582 return fbin; 1583 } 1584 1585 return (uint16_t)((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin)); 1586} 1587 1588/* 1589 * ar5416GetMaxEdgePower 1590 * 1591 * Find the maximum conformance test limit for the given channel and CTL info 1592 */ 1593static uint16_t 1594ar5416GetMaxEdgePower(uint16_t freq, CAL_CTL_EDGES *pRdEdgesPower, HAL_BOOL is2GHz) 1595{ 1596 uint16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER; 1597 int i; 1598 1599 /* Get the edge power */ 1600 for (i = 0; (i < AR5416_NUM_BAND_EDGES) && (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED) ; i++) { 1601 /* 1602 * If there's an exact channel match or an inband flag set 1603 * on the lower channel use the given rdEdgePower 1604 */ 1605 if (freq == fbin2freq(pRdEdgesPower[i].bChannel, is2GHz)) { 1606 twiceMaxEdgePower = MS(pRdEdgesPower[i].tPowerFlag, CAL_CTL_EDGES_POWER); 1607 break; 1608 } else if ((i > 0) && (freq < fbin2freq(pRdEdgesPower[i].bChannel, is2GHz))) { 1609 if (fbin2freq(pRdEdgesPower[i - 1].bChannel, is2GHz) < freq && (pRdEdgesPower[i - 1].tPowerFlag & CAL_CTL_EDGES_FLAG) != 0) { 1610 twiceMaxEdgePower = MS(pRdEdgesPower[i - 1].tPowerFlag, CAL_CTL_EDGES_POWER); 1611 } 1612 /* Leave loop - no more affecting edges possible in this monotonic increasing list */ 1613 break; 1614 } 1615 } 1616 HALASSERT(twiceMaxEdgePower > 0); 1617 return twiceMaxEdgePower; 1618} 1619 1620/************************************************************** 1621 * ar5416GetTargetPowers 1622 * 1623 * Return the rates of target power for the given target power table 1624 * channel, and number of channels 1625 */ 1626static void 1627ar5416GetTargetPowers(struct ath_hal *ah, const struct ieee80211_channel *chan, 1628 CAL_TARGET_POWER_HT *powInfo, uint16_t numChannels, 1629 CAL_TARGET_POWER_HT *pNewPower, uint16_t numRates, 1630 HAL_BOOL isHt40Target) 1631{ 1632 uint16_t clo, chi; 1633 int i; 1634 int matchIndex = -1, lowIndex = -1; 1635 uint16_t freq; 1636 CHAN_CENTERS centers; 1637 1638 ar5416GetChannelCenters(ah, chan, ¢ers); 1639 freq = isHt40Target ? centers.synth_center : centers.ctl_center; 1640 1641 /* Copy the target powers into the temp channel list */ 1642 if (freq <= fbin2freq(powInfo[0].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) { 1643 matchIndex = 0; 1644 } else { 1645 for (i = 0; (i < numChannels) && (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) { 1646 if (freq == fbin2freq(powInfo[i].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) { 1647 matchIndex = i; 1648 break; 1649 } else if ((freq < fbin2freq(powInfo[i].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) && 1650 (freq > fbin2freq(powInfo[i - 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan)))) 1651 { 1652 lowIndex = i - 1; 1653 break; 1654 } 1655 } 1656 if ((matchIndex == -1) && (lowIndex == -1)) { 1657 HALASSERT(freq > fbin2freq(powInfo[i - 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))); 1658 matchIndex = i - 1; 1659 } 1660 } 1661 1662 if (matchIndex != -1) { 1663 OS_MEMCPY(pNewPower, &powInfo[matchIndex], sizeof(*pNewPower)); 1664 } else { 1665 HALASSERT(lowIndex != -1); 1666 /* 1667 * Get the lower and upper channels, target powers, 1668 * and interpolate between them. 1669 */ 1670 clo = fbin2freq(powInfo[lowIndex].bChannel, IEEE80211_IS_CHAN_2GHZ(chan)); 1671 chi = fbin2freq(powInfo[lowIndex + 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan)); 1672 1673 for (i = 0; i < numRates; i++) { 1674 pNewPower->tPow2x[i] = (uint8_t)interpolate(freq, clo, chi, 1675 powInfo[lowIndex].tPow2x[i], powInfo[lowIndex + 1].tPow2x[i]); 1676 } 1677 } 1678} 1679/************************************************************** 1680 * ar5416GetTargetPowersLeg 1681 * 1682 * Return the four rates of target power for the given target power table 1683 * channel, and number of channels 1684 */ 1685static void 1686ar5416GetTargetPowersLeg(struct ath_hal *ah, 1687 const struct ieee80211_channel *chan, 1688 CAL_TARGET_POWER_LEG *powInfo, uint16_t numChannels, 1689 CAL_TARGET_POWER_LEG *pNewPower, uint16_t numRates, 1690 HAL_BOOL isExtTarget) 1691{ 1692 uint16_t clo, chi; 1693 int i; 1694 int matchIndex = -1, lowIndex = -1; 1695 uint16_t freq; 1696 CHAN_CENTERS centers; 1697 1698 ar5416GetChannelCenters(ah, chan, ¢ers); 1699 freq = (isExtTarget) ? centers.ext_center :centers.ctl_center; 1700 1701 /* Copy the target powers into the temp channel list */ 1702 if (freq <= fbin2freq(powInfo[0].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) { 1703 matchIndex = 0; 1704 } else { 1705 for (i = 0; (i < numChannels) && (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) { 1706 if (freq == fbin2freq(powInfo[i].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) { 1707 matchIndex = i; 1708 break; 1709 } else if ((freq < fbin2freq(powInfo[i].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))) && 1710 (freq > fbin2freq(powInfo[i - 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan)))) 1711 { 1712 lowIndex = i - 1; 1713 break; 1714 } 1715 } 1716 if ((matchIndex == -1) && (lowIndex == -1)) { 1717 HALASSERT(freq > fbin2freq(powInfo[i - 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan))); 1718 matchIndex = i - 1; 1719 } 1720 } 1721 1722 if (matchIndex != -1) { 1723 OS_MEMCPY(pNewPower, &powInfo[matchIndex], sizeof(*pNewPower)); 1724 } else { 1725 HALASSERT(lowIndex != -1); 1726 /* 1727 * Get the lower and upper channels, target powers, 1728 * and interpolate between them. 1729 */ 1730 clo = fbin2freq(powInfo[lowIndex].bChannel, IEEE80211_IS_CHAN_2GHZ(chan)); 1731 chi = fbin2freq(powInfo[lowIndex + 1].bChannel, IEEE80211_IS_CHAN_2GHZ(chan)); 1732 1733 for (i = 0; i < numRates; i++) { 1734 pNewPower->tPow2x[i] = (uint8_t)interpolate(freq, clo, chi, 1735 powInfo[lowIndex].tPow2x[i], powInfo[lowIndex + 1].tPow2x[i]); 1736 } 1737 } 1738} 1739 1740/************************************************************** 1741 * ar5416SetPowerCalTable 1742 * 1743 * Pull the PDADC piers from cal data and interpolate them across the given 1744 * points as well as from the nearest pier(s) to get a power detector 1745 * linear voltage to power level table. 1746 */ 1747static HAL_BOOL 1748ar5416SetPowerCalTable(struct ath_hal *ah, struct ar5416eeprom *pEepData, 1749 const struct ieee80211_channel *chan, int16_t *pTxPowerIndexOffset) 1750{ 1751 CAL_DATA_PER_FREQ *pRawDataset; 1752 uint8_t *pCalBChans = AH_NULL; 1753 uint16_t pdGainOverlap_t2; 1754 static uint8_t pdadcValues[AR5416_NUM_PDADC_VALUES]; 1755 uint16_t gainBoundaries[AR5416_PD_GAINS_IN_MASK]; 1756 uint16_t numPiers, i, j; 1757 int16_t tMinCalPower; 1758 uint16_t numXpdGain, xpdMask; 1759 uint16_t xpdGainValues[AR5416_NUM_PD_GAINS]; 1760 uint32_t reg32, regOffset, regChainOffset; 1761 1762 OS_MEMZERO(xpdGainValues, sizeof(xpdGainValues)); 1763 1764 xpdMask = pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].xpdGain; 1765 1766 if (IS_EEP_MINOR_V2(ah)) { 1767 pdGainOverlap_t2 = pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].pdGainOverlap; 1768 } else { 1769 pdGainOverlap_t2 = (uint16_t)(MS(OS_REG_READ(ah, AR_PHY_TPCRG5), AR_PHY_TPCRG5_PD_GAIN_OVERLAP)); 1770 } 1771 1772 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 1773 pCalBChans = pEepData->calFreqPier2G; 1774 numPiers = AR5416_NUM_2G_CAL_PIERS; 1775 } else { 1776 pCalBChans = pEepData->calFreqPier5G; 1777 numPiers = AR5416_NUM_5G_CAL_PIERS; 1778 } 1779 1780 numXpdGain = 0; 1781 /* Calculate the value of xpdgains from the xpdGain Mask */ 1782 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) { 1783 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) { 1784 if (numXpdGain >= AR5416_NUM_PD_GAINS) { 1785 HALASSERT(0); 1786 break; 1787 } 1788 xpdGainValues[numXpdGain] = (uint16_t)(AR5416_PD_GAINS_IN_MASK - i); 1789 numXpdGain++; 1790 } 1791 } 1792 1793 /* Write the detector gain biases and their number */ 1794 OS_REG_WRITE(ah, AR_PHY_TPCRG1, (OS_REG_READ(ah, AR_PHY_TPCRG1) & 1795 ~(AR_PHY_TPCRG1_NUM_PD_GAIN | AR_PHY_TPCRG1_PD_GAIN_1 | AR_PHY_TPCRG1_PD_GAIN_2 | AR_PHY_TPCRG1_PD_GAIN_3)) | 1796 SM(numXpdGain - 1, AR_PHY_TPCRG1_NUM_PD_GAIN) | SM(xpdGainValues[0], AR_PHY_TPCRG1_PD_GAIN_1 ) | 1797 SM(xpdGainValues[1], AR_PHY_TPCRG1_PD_GAIN_2) | SM(xpdGainValues[2], AR_PHY_TPCRG1_PD_GAIN_3)); 1798 1799 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 1800 1801 if (AR_SREV_OWL_20_OR_LATER(ah) && 1802 ( AH5416(ah)->ah_rx_chainmask == 0x5 || AH5416(ah)->ah_tx_chainmask == 0x5) && (i != 0)) { 1803 /* Regs are swapped from chain 2 to 1 for 5416 2_0 with 1804 * only chains 0 and 2 populated 1805 */ 1806 regChainOffset = (i == 1) ? 0x2000 : 0x1000; 1807 } else { 1808 regChainOffset = i * 0x1000; 1809 } 1810 1811 if (pEepData->baseEepHeader.txMask & (1 << i)) { 1812 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 1813 pRawDataset = pEepData->calPierData2G[i]; 1814 } else { 1815 pRawDataset = pEepData->calPierData5G[i]; 1816 } 1817 1818 ar5416GetGainBoundariesAndPdadcs(ah, chan, pRawDataset, 1819 pCalBChans, numPiers, 1820 pdGainOverlap_t2, 1821 &tMinCalPower, gainBoundaries, 1822 pdadcValues, numXpdGain); 1823 1824 if ((i == 0) || AR_SREV_OWL_20_OR_LATER(ah)) { 1825 /* 1826 * Note the pdadc table may not start at 0 dBm power, could be 1827 * negative or greater than 0. Need to offset the power 1828 * values by the amount of minPower for griffin 1829 */ 1830 1831 OS_REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset, 1832 SM(pdGainOverlap_t2, AR_PHY_TPCRG5_PD_GAIN_OVERLAP) | 1833 SM(gainBoundaries[0], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) | 1834 SM(gainBoundaries[1], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2) | 1835 SM(gainBoundaries[2], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3) | 1836 SM(gainBoundaries[3], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4)); 1837 } 1838 1839 /* Write the power values into the baseband power table */ 1840 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset; 1841 1842 for (j = 0; j < 32; j++) { 1843 reg32 = ((pdadcValues[4*j + 0] & 0xFF) << 0) | 1844 ((pdadcValues[4*j + 1] & 0xFF) << 8) | 1845 ((pdadcValues[4*j + 2] & 0xFF) << 16) | 1846 ((pdadcValues[4*j + 3] & 0xFF) << 24) ; 1847 OS_REG_WRITE(ah, regOffset, reg32); 1848 1849#ifdef PDADC_DUMP 1850 ath_hal_printf(ah, "PDADC: Chain %d | PDADC %3d Value %3d | PDADC %3d Value %3d | PDADC %3d Value %3d | PDADC %3d Value %3d |\n", 1851 i, 1852 4*j, pdadcValues[4*j], 1853 4*j+1, pdadcValues[4*j + 1], 1854 4*j+2, pdadcValues[4*j + 2], 1855 4*j+3, pdadcValues[4*j + 3]); 1856#endif 1857 regOffset += 4; 1858 } 1859 } 1860 } 1861 *pTxPowerIndexOffset = 0; 1862 1863 return AH_TRUE; 1864} 1865 1866/************************************************************** 1867 * ar5416GetGainBoundariesAndPdadcs 1868 * 1869 * Uses the data points read from EEPROM to reconstruct the pdadc power table 1870 * Called by ar5416SetPowerCalTable only. 1871 */ 1872static void 1873ar5416GetGainBoundariesAndPdadcs(struct ath_hal *ah, 1874 const struct ieee80211_channel *chan, 1875 CAL_DATA_PER_FREQ *pRawDataSet, 1876 uint8_t * bChans, uint16_t availPiers, 1877 uint16_t tPdGainOverlap, int16_t *pMinCalPower, uint16_t * pPdGainBoundaries, 1878 uint8_t * pPDADCValues, uint16_t numXpdGains) 1879{ 1880 1881 int i, j, k; 1882 int16_t ss; /* potentially -ve index for taking care of pdGainOverlap */ 1883 uint16_t idxL, idxR, numPiers; /* Pier indexes */ 1884 1885 /* filled out Vpd table for all pdGains (chanL) */ 1886 static uint8_t vpdTableL[AR5416_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 1887 1888 /* filled out Vpd table for all pdGains (chanR) */ 1889 static uint8_t vpdTableR[AR5416_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 1890 1891 /* filled out Vpd table for all pdGains (interpolated) */ 1892 static uint8_t vpdTableI[AR5416_NUM_PD_GAINS][AR5416_MAX_PWR_RANGE_IN_HALF_DB]; 1893 1894 uint8_t *pVpdL, *pVpdR, *pPwrL, *pPwrR; 1895 uint8_t minPwrT4[AR5416_NUM_PD_GAINS]; 1896 uint8_t maxPwrT4[AR5416_NUM_PD_GAINS]; 1897 int16_t vpdStep; 1898 int16_t tmpVal; 1899 uint16_t sizeCurrVpdTable, maxIndex, tgtIndex; 1900 HAL_BOOL match; 1901 int16_t minDelta = 0; 1902 CHAN_CENTERS centers; 1903 1904 ar5416GetChannelCenters(ah, chan, ¢ers); 1905 1906 /* Trim numPiers for the number of populated channel Piers */ 1907 for (numPiers = 0; numPiers < availPiers; numPiers++) { 1908 if (bChans[numPiers] == AR5416_BCHAN_UNUSED) { 1909 break; 1910 } 1911 } 1912 1913 /* Find pier indexes around the current channel */ 1914 match = getLowerUpperIndex((uint8_t)FREQ2FBIN(centers.synth_center, IEEE80211_IS_CHAN_2GHZ(chan)), 1915 bChans, numPiers, &idxL, &idxR); 1916 1917 if (match) { 1918 /* Directly fill both vpd tables from the matching index */ 1919 for (i = 0; i < numXpdGains; i++) { 1920 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0]; 1921 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4]; 1922 ar5416FillVpdTable(minPwrT4[i], maxPwrT4[i], pRawDataSet[idxL].pwrPdg[i], 1923 pRawDataSet[idxL].vpdPdg[i], AR5416_PD_GAIN_ICEPTS, vpdTableI[i]); 1924 } 1925 } else { 1926 for (i = 0; i < numXpdGains; i++) { 1927 pVpdL = pRawDataSet[idxL].vpdPdg[i]; 1928 pPwrL = pRawDataSet[idxL].pwrPdg[i]; 1929 pVpdR = pRawDataSet[idxR].vpdPdg[i]; 1930 pPwrR = pRawDataSet[idxR].pwrPdg[i]; 1931 1932 /* Start Vpd interpolation from the max of the minimum powers */ 1933 minPwrT4[i] = AH_MAX(pPwrL[0], pPwrR[0]); 1934 1935 /* End Vpd interpolation from the min of the max powers */ 1936 maxPwrT4[i] = AH_MIN(pPwrL[AR5416_PD_GAIN_ICEPTS - 1], pPwrR[AR5416_PD_GAIN_ICEPTS - 1]); 1937 HALASSERT(maxPwrT4[i] > minPwrT4[i]); 1938 1939 /* Fill pier Vpds */ 1940 ar5416FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrL, pVpdL, AR5416_PD_GAIN_ICEPTS, vpdTableL[i]); 1941 ar5416FillVpdTable(minPwrT4[i], maxPwrT4[i], pPwrR, pVpdR, AR5416_PD_GAIN_ICEPTS, vpdTableR[i]); 1942 1943 /* Interpolate the final vpd */ 1944 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) { 1945 vpdTableI[i][j] = (uint8_t)(interpolate((uint16_t)FREQ2FBIN(centers.synth_center, IEEE80211_IS_CHAN_2GHZ(chan)), 1946 bChans[idxL], bChans[idxR], vpdTableL[i][j], vpdTableR[i][j])); 1947 } 1948 } 1949 } 1950 *pMinCalPower = (int16_t)(minPwrT4[0] / 2); 1951 1952 k = 0; /* index for the final table */ 1953 for (i = 0; i < numXpdGains; i++) { 1954 if (i == (numXpdGains - 1)) { 1955 pPdGainBoundaries[i] = (uint16_t)(maxPwrT4[i] / 2); 1956 } else { 1957 pPdGainBoundaries[i] = (uint16_t)((maxPwrT4[i] + minPwrT4[i+1]) / 4); 1958 } 1959 1960 pPdGainBoundaries[i] = (uint16_t)AH_MIN(AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]); 1961 1962 /* NB: only applies to owl 1.0 */ 1963 if ((i == 0) && !AR_SREV_OWL_20_OR_LATER(ah) ) { 1964 /* 1965 * fix the gain delta, but get a delta that can be applied to min to 1966 * keep the upper power values accurate, don't think max needs to 1967 * be adjusted because should not be at that area of the table? 1968 */ 1969 minDelta = pPdGainBoundaries[0] - 23; 1970 pPdGainBoundaries[0] = 23; 1971 } 1972 else { 1973 minDelta = 0; 1974 } 1975 1976 /* Find starting index for this pdGain */ 1977 if (i == 0) { 1978 ss = 0; /* for the first pdGain, start from index 0 */ 1979 } else { 1980 /* need overlap entries extrapolated below. */ 1981 ss = (int16_t)((pPdGainBoundaries[i-1] - (minPwrT4[i] / 2)) - tPdGainOverlap + 1 + minDelta); 1982 } 1983 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]); 1984 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); 1985 /* 1986 *-ve ss indicates need to extrapolate data below for this pdGain 1987 */ 1988 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { 1989 tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep); 1990 pPDADCValues[k++] = (uint8_t)((tmpVal < 0) ? 0 : tmpVal); 1991 ss++; 1992 } 1993 1994 sizeCurrVpdTable = (uint8_t)((maxPwrT4[i] - minPwrT4[i]) / 2 +1); 1995 tgtIndex = (uint8_t)(pPdGainBoundaries[i] + tPdGainOverlap - (minPwrT4[i] / 2)); 1996 maxIndex = (tgtIndex < sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable; 1997 1998 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { 1999 pPDADCValues[k++] = vpdTableI[i][ss++]; 2000 } 2001 2002 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] - vpdTableI[i][sizeCurrVpdTable - 2]); 2003 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep); 2004 /* 2005 * for last gain, pdGainBoundary == Pmax_t2, so will 2006 * have to extrapolate 2007 */ 2008 if (tgtIndex > maxIndex) { /* need to extrapolate above */ 2009 while ((ss <= tgtIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) { 2010 tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] + 2011 (ss - maxIndex +1) * vpdStep)); 2012 pPDADCValues[k++] = (uint8_t)((tmpVal > 255) ? 255 : tmpVal); 2013 ss++; 2014 } 2015 } /* extrapolated above */ 2016 } /* for all pdGainUsed */ 2017 2018 /* Fill out pdGainBoundaries - only up to 2 allowed here, but hardware allows up to 4 */ 2019 while (i < AR5416_PD_GAINS_IN_MASK) { 2020 pPdGainBoundaries[i] = pPdGainBoundaries[i-1]; 2021 i++; 2022 } 2023 2024 while (k < AR5416_NUM_PDADC_VALUES) { 2025 pPDADCValues[k] = pPDADCValues[k-1]; 2026 k++; 2027 } 2028 return; 2029} 2030 2031/************************************************************** 2032 * getLowerUppderIndex 2033 * 2034 * Return indices surrounding the value in sorted integer lists. 2035 * Requirement: the input list must be monotonically increasing 2036 * and populated up to the list size 2037 * Returns: match is set if an index in the array matches exactly 2038 * or a the target is before or after the range of the array. 2039 */ 2040HAL_BOOL 2041getLowerUpperIndex(uint8_t target, uint8_t *pList, uint16_t listSize, 2042 uint16_t *indexL, uint16_t *indexR) 2043{ 2044 uint16_t i; 2045 2046 /* 2047 * Check first and last elements for beyond ordered array cases. 2048 */ 2049 if (target <= pList[0]) { 2050 *indexL = *indexR = 0; 2051 return AH_TRUE; 2052 } 2053 if (target >= pList[listSize-1]) { 2054 *indexL = *indexR = (uint16_t)(listSize - 1); 2055 return AH_TRUE; 2056 } 2057 2058 /* look for value being near or between 2 values in list */ 2059 for (i = 0; i < listSize - 1; i++) { 2060 /* 2061 * If value is close to the current value of the list 2062 * then target is not between values, it is one of the values 2063 */ 2064 if (pList[i] == target) { 2065 *indexL = *indexR = i; 2066 return AH_TRUE; 2067 } 2068 /* 2069 * Look for value being between current value and next value 2070 * if so return these 2 values 2071 */ 2072 if (target < pList[i + 1]) { 2073 *indexL = i; 2074 *indexR = (uint16_t)(i + 1); 2075 return AH_FALSE; 2076 } 2077 } 2078 HALASSERT(0); 2079 *indexL = *indexR = 0; 2080 return AH_FALSE; 2081} 2082 2083/************************************************************** 2084 * ar5416FillVpdTable 2085 * 2086 * Fill the Vpdlist for indices Pmax-Pmin 2087 * Note: pwrMin, pwrMax and Vpdlist are all in dBm * 4 2088 */ 2089static HAL_BOOL 2090ar5416FillVpdTable(uint8_t pwrMin, uint8_t pwrMax, uint8_t *pPwrList, 2091 uint8_t *pVpdList, uint16_t numIntercepts, uint8_t *pRetVpdList) 2092{ 2093 uint16_t i, k; 2094 uint8_t currPwr = pwrMin; 2095 uint16_t idxL, idxR; 2096 2097 HALASSERT(pwrMax > pwrMin); 2098 for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) { 2099 getLowerUpperIndex(currPwr, pPwrList, numIntercepts, 2100 &(idxL), &(idxR)); 2101 if (idxR < 1) 2102 idxR = 1; /* extrapolate below */ 2103 if (idxL == numIntercepts - 1) 2104 idxL = (uint16_t)(numIntercepts - 2); /* extrapolate above */ 2105 if (pPwrList[idxL] == pPwrList[idxR]) 2106 k = pVpdList[idxL]; 2107 else 2108 k = (uint16_t)( ((currPwr - pPwrList[idxL]) * pVpdList[idxR] + (pPwrList[idxR] - currPwr) * pVpdList[idxL]) / 2109 (pPwrList[idxR] - pPwrList[idxL]) ); 2110 HALASSERT(k < 256); 2111 pRetVpdList[i] = (uint8_t)k; 2112 currPwr += 2; /* half dB steps */ 2113 } 2114 2115 return AH_TRUE; 2116} 2117 2118/************************************************************************** 2119 * interpolate 2120 * 2121 * Returns signed interpolated or the scaled up interpolated value 2122 */ 2123static int16_t 2124interpolate(uint16_t target, uint16_t srcLeft, uint16_t srcRight, 2125 int16_t targetLeft, int16_t targetRight) 2126{ 2127 int16_t rv; 2128 2129 if (srcRight == srcLeft) { 2130 rv = targetLeft; 2131 } else { 2132 rv = (int16_t)( ((target - srcLeft) * targetRight + 2133 (srcRight - target) * targetLeft) / (srcRight - srcLeft) ); 2134 } 2135 return rv; 2136} 2137 2138static void 2139ar5416Set11nRegs(struct ath_hal *ah, const struct ieee80211_channel *chan) 2140{ 2141 uint32_t phymode; 2142 HAL_HT_MACMODE macmode; /* MAC - 20/40 mode */ 2143 2144 if (!IEEE80211_IS_CHAN_HT(chan)) 2145 return; 2146 2147 /* Enable 11n HT, 20 MHz */ 2148 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40 2149 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH; 2150 2151 /* Configure baseband for dynamic 20/40 operation */ 2152 if (IEEE80211_IS_CHAN_HT40(chan)) { 2153 phymode |= AR_PHY_FC_DYN2040_EN | AR_PHY_FC_SHORT_GI_40; 2154 2155 /* Configure control (primary) channel at +-10MHz */ 2156 if (IEEE80211_IS_CHAN_HT40U(chan)) 2157 phymode |= AR_PHY_FC_DYN2040_PRI_CH; 2158#if 0 2159 /* Configure 20/25 spacing */ 2160 if (ht->ht_extprotspacing == HAL_HT_EXTPROTSPACING_25) 2161 phymode |= AR_PHY_FC_DYN2040_EXT_CH; 2162#endif 2163 macmode = HAL_HT_MACMODE_2040; 2164 } else 2165 macmode = HAL_HT_MACMODE_20; 2166 OS_REG_WRITE(ah, AR_PHY_TURBO, phymode); 2167 2168 /* Configure MAC for 20/40 operation */ 2169 ar5416Set11nMac2040(ah, macmode); 2170 2171 /* global transmit timeout (25 TUs default)*/ 2172 /* XXX - put this elsewhere??? */ 2173 OS_REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S) ; 2174 2175 /* carrier sense timeout */ 2176 OS_REG_SET_BIT(ah, AR_GTTM, AR_GTTM_CST_USEC); 2177 OS_REG_WRITE(ah, AR_CST, 1 << AR_CST_TIMEOUT_LIMIT_S); 2178} 2179 2180void 2181ar5416GetChannelCenters(struct ath_hal *ah, 2182 const struct ieee80211_channel *chan, CHAN_CENTERS *centers) 2183{ 2184 uint16_t freq = ath_hal_gethwchannel(ah, chan); 2185 2186 centers->ctl_center = freq; 2187 centers->synth_center = freq; 2188 /* 2189 * In 20/40 phy mode, the center frequency is 2190 * "between" the control and extension channels. 2191 */ 2192 if (IEEE80211_IS_CHAN_HT40U(chan)) { 2193 centers->synth_center += HT40_CHANNEL_CENTER_SHIFT; 2194 centers->ext_center = 2195 centers->synth_center + HT40_CHANNEL_CENTER_SHIFT; 2196 } else if (IEEE80211_IS_CHAN_HT40D(chan)) { 2197 centers->synth_center -= HT40_CHANNEL_CENTER_SHIFT; 2198 centers->ext_center = 2199 centers->synth_center - HT40_CHANNEL_CENTER_SHIFT; 2200 } else { 2201 centers->ext_center = freq; 2202 } 2203} 2204