1/*- 2 * Copyright (c) 2012,2013 Bjoern A. Zeeb 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-11-C-0249) 7 * ("MRC2"), as part of the DARPA MRC research programme. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30/* 31 * Altera Triple-Speed Ethernet MegaCore, Function User Guide 32 * UG-01008-3.0, Software Version: 12.0, June 2012. 33 * Available at the time of writing at: 34 * http://www.altera.com/literature/ug/ug_ethernet.pdf 35 * 36 * We are using an Marvell E1111 (Alaska) PHY on the DE4. See mii/e1000phy.c. 37 */ 38/* 39 * XXX-BZ NOTES: 40 * - ifOutBroadcastPkts are only counted if both ether dst and src are all-1s; 41 * seems an IP core bug, they count ether broadcasts as multicast. Is this 42 * still the case? 43 * - figure out why the TX FIFO fill status and intr did not work as expected. 44 * - test 100Mbit/s and 10Mbit/s 45 * - blacklist the one special factory programmed ethernet address (for now 46 * hardcoded, later from loader?) 47 * - resolve all XXX, left as reminders to shake out details later 48 * - Jumbo frame support 49 */ 50 51#include <sys/cdefs.h> 52__FBSDID("$FreeBSD$"); 53 54#include "opt_device_polling.h" 55 56#include <sys/param.h> 57#include <sys/systm.h> 58#include <sys/kernel.h> 59#include <sys/bus.h> 60#include <sys/endian.h> 61#include <sys/jail.h> 62#include <sys/lock.h> 63#include <sys/module.h> 64#include <sys/mutex.h> 65#include <sys/proc.h> 66#include <sys/socket.h> 67#include <sys/sockio.h> 68#include <sys/types.h> 69 70#include <net/ethernet.h> 71#include <net/if.h> 72#include <net/if_var.h> 73#include <net/if_dl.h> 74#include <net/if_media.h> 75#include <net/if_types.h> 76#include <net/if_vlan_var.h> 77 78#include <net/bpf.h> 79 80#include <machine/bus.h> 81#include <machine/resource.h> 82#include <sys/rman.h> 83 84#include <dev/mii/mii.h> 85#include <dev/mii/miivar.h> 86 87#include <dev/altera/atse/if_atsereg.h> 88#include <dev/altera/atse/a_api.h> 89 90MODULE_DEPEND(atse, ether, 1, 1, 1); 91MODULE_DEPEND(atse, miibus, 1, 1, 1); 92 93 94#define ATSE_WATCHDOG_TIME 5 95 96#ifdef DEVICE_POLLING 97static poll_handler_t atse_poll; 98#endif 99 100/* XXX once we'd do parallel attach, we need a global lock for this. */ 101#define ATSE_ETHERNET_OPTION_BITS_UNDEF 0 102#define ATSE_ETHERNET_OPTION_BITS_READ 1 103static int atse_ethernet_option_bits_flag = ATSE_ETHERNET_OPTION_BITS_UNDEF; 104static uint8_t atse_ethernet_option_bits[ALTERA_ETHERNET_OPTION_BITS_LEN]; 105 106/* 107 * Softc and critical resource locking. 108 */ 109#define ATSE_LOCK(_sc) mtx_lock(&(_sc)->atse_mtx) 110#define ATSE_UNLOCK(_sc) mtx_unlock(&(_sc)->atse_mtx) 111#define ATSE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->atse_mtx, MA_OWNED) 112 113#ifdef DEBUG 114#define DPRINTF(format, ...) printf(format, __VA_ARGS__) 115#else 116#define DPRINTF(format, ...) 117#endif 118 119/* a_api.c functions; factor out? */ 120static inline void 121a_onchip_fifo_mem_core_write(struct resource *res, uint32_t off, 122 uint32_t val4, const char *desc, const char *f, const int l) 123{ 124 125 val4 = htole32(val4); 126 DPRINTF("[%s:%d] FIFOW %s 0x%08x = 0x%08x\n", f, l, desc, off, val4); 127 bus_write_4(res, off, val4); 128} 129static inline uint32_t 130a_onchip_fifo_mem_core_read(struct resource *res, uint32_t off, 131 const char *desc, const char *f, const int l) 132{ 133 uint32_t val4; 134 135 val4 = le32toh(bus_read_4(res, off)); 136 DPRINTF("[%s:%d] FIFOR %s 0x%08x = 0x%08x\n", f, l, desc, off, val4); 137 return (val4); 138} 139 140/* The FIFO does an endian convertion, so we must not do it as well. */ 141/* XXX-BZ in fact we should do a htobe32 so le would be fine as well? */ 142#define ATSE_TX_DATA_WRITE(sc, val4) \ 143 bus_write_4((sc)->atse_tx_mem_res, A_ONCHIP_FIFO_MEM_CORE_DATA, val4) 144 145#define ATSE_TX_META_WRITE(sc, val4) \ 146 a_onchip_fifo_mem_core_write((sc)->atse_tx_mem_res, \ 147 A_ONCHIP_FIFO_MEM_CORE_METADATA, \ 148 (val4), "TXM", __func__, __LINE__) 149#define ATSE_TX_META_READ(sc) \ 150 a_onchip_fifo_mem_core_read((sc)->atse_tx_mem_res, \ 151 A_ONCHIP_FIFO_MEM_CORE_METADATA, \ 152 "TXM", __func__, __LINE__) 153 154#define ATSE_TX_READ_FILL_LEVEL(sc) \ 155 a_onchip_fifo_mem_core_read((sc)->atse_txc_mem_res, \ 156 A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_FILL_LEVEL, \ 157 "TX_FILL", __func__, __LINE__) 158#define ATSE_RX_READ_FILL_LEVEL(sc) \ 159 a_onchip_fifo_mem_core_read((sc)->atse_rxc_mem_res, \ 160 A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_FILL_LEVEL, \ 161 "RX_FILL", __func__, __LINE__) 162 163/* The FIFO does an endian convertion, so we must not do it as well. */ 164/* XXX-BZ in fact we shoudl do a htobe32 so le would be fine as well? */ 165#define ATSE_RX_DATA_READ(sc) \ 166 bus_read_4((sc)->atse_rx_mem_res, A_ONCHIP_FIFO_MEM_CORE_DATA) 167#define ATSE_RX_META_READ(sc) \ 168 a_onchip_fifo_mem_core_read((sc)->atse_rx_mem_res, \ 169 A_ONCHIP_FIFO_MEM_CORE_METADATA, \ 170 "RXM", __func__, __LINE__) 171 172#define ATSE_RX_EVENT_READ(sc) \ 173 a_onchip_fifo_mem_core_read((sc)->atse_rxc_mem_res, \ 174 A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_EVENT, \ 175 "RX_EVENT", __func__, __LINE__) 176 177#define ATSE_TX_EVENT_READ(sc) \ 178 a_onchip_fifo_mem_core_read((sc)->atse_txc_mem_res, \ 179 A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_EVENT, \ 180 "TX_EVENT", __func__, __LINE__) 181 182#define ATSE_RX_EVENT_CLEAR(sc) \ 183 do { \ 184 uint32_t val4; \ 185 \ 186 val4 = a_onchip_fifo_mem_core_read( \ 187 (sc)->atse_rxc_mem_res, \ 188 A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_EVENT, \ 189 "RX_EVENT", __func__, __LINE__); \ 190 if (val4 != 0x00) \ 191 a_onchip_fifo_mem_core_write( \ 192 (sc)->atse_rxc_mem_res, \ 193 A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_EVENT, \ 194 val4, "RX_EVENT", __func__, __LINE__); \ 195 } while(0) 196#define ATSE_TX_EVENT_CLEAR(sc) \ 197 do { \ 198 uint32_t val4; \ 199 \ 200 val4 = a_onchip_fifo_mem_core_read( \ 201 (sc)->atse_txc_mem_res, \ 202 A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_EVENT, \ 203 "TX_EVENT", __func__, __LINE__); \ 204 if (val4 != 0x00) \ 205 a_onchip_fifo_mem_core_write( \ 206 (sc)->atse_txc_mem_res, \ 207 A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_EVENT, \ 208 val4, "TX_EVENT", __func__, __LINE__); \ 209 } while(0) 210 211#define ATSE_RX_INTR_ENABLE(sc) \ 212 a_onchip_fifo_mem_core_write((sc)->atse_rxc_mem_res, \ 213 A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_INT_ENABLE, \ 214 A_ONCHIP_FIFO_MEM_CORE_INTR_ALL, \ 215 "RX_INTR", __func__, __LINE__) /* XXX-BZ review later. */ 216#define ATSE_RX_INTR_DISABLE(sc) \ 217 a_onchip_fifo_mem_core_write((sc)->atse_rxc_mem_res, \ 218 A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_INT_ENABLE, 0, \ 219 "RX_INTR", __func__, __LINE__) 220#define ATSE_TX_INTR_ENABLE(sc) \ 221 a_onchip_fifo_mem_core_write((sc)->atse_txc_mem_res, \ 222 A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_INT_ENABLE, \ 223 A_ONCHIP_FIFO_MEM_CORE_INTR_ALL, \ 224 "TX_INTR", __func__, __LINE__) /* XXX-BZ review later. */ 225#define ATSE_TX_INTR_DISABLE(sc) \ 226 a_onchip_fifo_mem_core_write((sc)->atse_txc_mem_res, \ 227 A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_INT_ENABLE, 0, \ 228 "TX_INTR", __func__, __LINE__) 229 230/* 231 * Register space access macros. 232 */ 233static inline void 234csr_write_4(struct atse_softc *sc, uint32_t reg, uint32_t val4, 235 const char *f, const int l) 236{ 237 238 val4 = htole32(val4); 239 DPRINTF("[%s:%d] CSR W %s 0x%08x (0x%08x) = 0x%08x\n", f, l, 240 "atse_mem_res", reg, reg * 4, val4); 241 bus_write_4(sc->atse_mem_res, reg * 4, val4); 242} 243 244static inline uint32_t 245csr_read_4(struct atse_softc *sc, uint32_t reg, const char *f, const int l) 246{ 247 uint32_t val4; 248 249 val4 = le32toh(bus_read_4(sc->atse_mem_res, reg * 4)); 250 DPRINTF("[%s:%d] CSR R %s 0x%08x (0x%08x) = 0x%08x\n", f, l, 251 "atse_mem_res", reg, reg * 4, val4); 252 return (val4); 253} 254 255/* 256 * See page 5-2 that it's all dword offsets and the MS 16 bits need to be zero 257 * on write and ignored on read. 258 */ 259static inline void 260pxx_write_2(struct atse_softc *sc, bus_addr_t bmcr, uint32_t reg, uint16_t val, 261 const char *f, const int l, const char *s) 262{ 263 uint32_t val4; 264 265 val4 = htole32(val & 0x0000ffff); 266 DPRINTF("[%s:%d] %s W %s 0x%08x (0x%08jx) = 0x%08x\n", f, l, s, 267 "atse_mem_res", reg, (bmcr + reg) * 4, val4); 268 bus_write_4(sc->atse_mem_res, (bmcr + reg) * 4, val4); 269} 270 271static inline uint16_t 272pxx_read_2(struct atse_softc *sc, bus_addr_t bmcr, uint32_t reg, const char *f, 273 const int l, const char *s) 274{ 275 uint32_t val4; 276 uint16_t val; 277 278 val4 = bus_read_4(sc->atse_mem_res, (bmcr + reg) * 4); 279 val = le32toh(val4) & 0x0000ffff; 280 DPRINTF("[%s:%d] %s R %s 0x%08x (0x%08jx) = 0x%04x\n", f, l, s, 281 "atse_mem_res", reg, (bmcr + reg) * 4, val); 282 return (val); 283} 284 285#define CSR_WRITE_4(sc, reg, val) \ 286 csr_write_4((sc), (reg), (val), __func__, __LINE__) 287#define CSR_READ_4(sc, reg) \ 288 csr_read_4((sc), (reg), __func__, __LINE__) 289#define PCS_WRITE_2(sc, reg, val) \ 290 pxx_write_2((sc), sc->atse_bmcr0, (reg), (val), __func__, __LINE__, \ 291 "PCS") 292#define PCS_READ_2(sc, reg) \ 293 pxx_read_2((sc), sc->atse_bmcr0, (reg), __func__, __LINE__, "PCS") 294#define PHY_WRITE_2(sc, reg, val) \ 295 pxx_write_2((sc), sc->atse_bmcr1, (reg), (val), __func__, __LINE__, \ 296 "PHY") 297#define PHY_READ_2(sc, reg) \ 298 pxx_read_2((sc), sc->atse_bmcr1, (reg), __func__, __LINE__, "PHY") 299 300static void atse_tick(void *); 301static int atse_detach(device_t); 302 303devclass_t atse_devclass; 304 305static int 306atse_tx_locked(struct atse_softc *sc, int *sent) 307{ 308 struct mbuf *m; 309 uint32_t val4, fill_level; 310 int c; 311 312 ATSE_LOCK_ASSERT(sc); 313 314 m = sc->atse_tx_m; 315 KASSERT(m != NULL, ("%s: m is null: sc=%p", __func__, sc)); 316 KASSERT(m->m_flags & M_PKTHDR, ("%s: not a pkthdr: m=%p", __func__, m)); 317 318 /* 319 * Copy to buffer to minimize our pain as we can only store 320 * double words which, after the first mbuf gets out of alignment 321 * quite quickly. 322 */ 323 if (sc->atse_tx_m_offset == 0) { 324 m_copydata(m, 0, m->m_pkthdr.len, sc->atse_tx_buf); 325 sc->atse_tx_buf_len = m->m_pkthdr.len; 326 } 327 328 fill_level = ATSE_TX_READ_FILL_LEVEL(sc); 329#if 0 /* Returns 0xdeadc0de. */ 330 val4 = ATSE_TX_META_READ(sc); 331#endif 332 if (sc->atse_tx_m_offset == 0) { 333 /* Write start of packet. */ 334 val4 = A_ONCHIP_FIFO_MEM_CORE_SOP; 335 val4 &= ~A_ONCHIP_FIFO_MEM_CORE_EOP; 336 ATSE_TX_META_WRITE(sc, val4); 337 } 338 339 /* TX FIFO is single clock mode, so we have the full FIFO. */ 340 c = 0; 341 while ((sc->atse_tx_buf_len - sc->atse_tx_m_offset) > 4 && 342 fill_level < AVALON_FIFO_TX_BASIC_OPTS_DEPTH) { 343 344 bcopy(&sc->atse_tx_buf[sc->atse_tx_m_offset], &val4, 345 sizeof(val4)); 346 ATSE_TX_DATA_WRITE(sc, val4); 347 sc->atse_tx_m_offset += sizeof(val4); 348 c += sizeof(val4); 349 350 fill_level++; 351 if (fill_level == AVALON_FIFO_TX_BASIC_OPTS_DEPTH) 352 fill_level = ATSE_TX_READ_FILL_LEVEL(sc); 353 } 354 if (sent != NULL) 355 *sent += c; 356 357 /* Set EOP *before* writing the last symbol. */ 358 if (sc->atse_tx_m_offset >= (sc->atse_tx_buf_len - 4) && 359 fill_level < AVALON_FIFO_TX_BASIC_OPTS_DEPTH) { 360 int leftm; 361 uint32_t x; 362 363 /* Set EndOfPacket. */ 364 val4 = A_ONCHIP_FIFO_MEM_CORE_EOP; 365 /* Set EMPTY. */ 366 leftm = sc->atse_tx_buf_len - sc->atse_tx_m_offset; 367 val4 |= ((4 - leftm) << A_ONCHIP_FIFO_MEM_CORE_EMPTY_SHIFT); 368 x = val4; 369 ATSE_TX_META_WRITE(sc, val4); 370 371 /* Write last symbol. */ 372 val4 = 0; 373 bcopy(sc->atse_tx_buf + sc->atse_tx_m_offset, &val4, leftm); 374 ATSE_TX_DATA_WRITE(sc, val4); 375 376 if (sent != NULL) 377 *sent += leftm; 378 379 /* OK, the packet is gone. */ 380 sc->atse_tx_m = NULL; 381 sc->atse_tx_m_offset = 0; 382 383 /* If anyone is interested give them a copy. */ 384 BPF_MTAP(sc->atse_ifp, m); 385 386 m_freem(m); 387 return (0); 388 } 389 390 return (EBUSY); 391} 392 393static void 394atse_start_locked(struct ifnet *ifp) 395{ 396 struct atse_softc *sc; 397 int error, sent; 398 399 sc = ifp->if_softc; 400 ATSE_LOCK_ASSERT(sc); 401 402 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 403 IFF_DRV_RUNNING || (sc->atse_flags & ATSE_FLAGS_LINK) == 0) 404 return; 405 406#if 1 407 /* 408 * Disable the watchdog while sending, we are batching packets. 409 * Though we should never reach 5 seconds, and are holding the lock, 410 * but who knows. 411 */ 412 sc->atse_watchdog_timer = 0; 413#endif 414 415 if (sc->atse_tx_m != NULL) { 416 error = atse_tx_locked(sc, &sent); 417 if (error != 0) 418 goto done; 419 } 420 /* We have more space to send so continue ... */ 421 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 422 423 IFQ_DRV_DEQUEUE(&ifp->if_snd, sc->atse_tx_m); 424 sc->atse_tx_m_offset = 0; 425 if (sc->atse_tx_m == NULL) 426 break; 427 error = atse_tx_locked(sc, &sent); 428 if (error != 0) 429 goto done; 430 } 431 432done: 433 /* If the IP core walks into Nekromanteion try to bail out. */ 434 if (sent > 0) 435 sc->atse_watchdog_timer = ATSE_WATCHDOG_TIME; 436} 437 438static void 439atse_start(struct ifnet *ifp) 440{ 441 struct atse_softc *sc; 442 443 sc = ifp->if_softc; 444 ATSE_LOCK(sc); 445 atse_start_locked(ifp); 446 ATSE_UNLOCK(sc); 447} 448 449static int 450atse_stop_locked(struct atse_softc *sc) 451{ 452 struct ifnet *ifp; 453 uint32_t mask, val4; 454 int i; 455 456 ATSE_LOCK_ASSERT(sc); 457 458 sc->atse_watchdog_timer = 0; 459 callout_stop(&sc->atse_tick); 460 461 ifp = sc->atse_ifp; 462 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 463 ATSE_RX_INTR_DISABLE(sc); 464 ATSE_TX_INTR_DISABLE(sc); 465 ATSE_RX_EVENT_CLEAR(sc); 466 ATSE_TX_EVENT_CLEAR(sc); 467 468 /* Disable MAC transmit and receive datapath. */ 469 mask = BASE_CFG_COMMAND_CONFIG_TX_ENA|BASE_CFG_COMMAND_CONFIG_RX_ENA; 470 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); 471 val4 &= ~mask; 472 CSR_WRITE_4(sc, BASE_CFG_COMMAND_CONFIG, val4); 473 /* Wait for bits to be cleared; i=100 is excessive. */ 474 for (i = 0; i < 100; i++) { 475 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); 476 if ((val4 & mask) == 0) 477 break; 478 DELAY(10); 479 } 480 if ((val4 & mask) != 0) 481 device_printf(sc->atse_dev, "Disabling MAC TX/RX timed out.\n"); 482 /* Punt. */ 483 484 sc->atse_flags &= ~ATSE_FLAGS_LINK; 485 486 /* XXX-BZ free the RX/TX rings. */ 487 488 return (0); 489} 490 491static uint8_t 492atse_mchash(struct atse_softc *sc __unused, const uint8_t *addr) 493{ 494 int i, j; 495 uint8_t x, y; 496 497 x = 0; 498 for (i = 0; i < ETHER_ADDR_LEN; i++) { 499 y = addr[i] & 0x01; 500 for (j = 1; j < 8; j++) 501 y ^= (addr[i] >> j) & 0x01; 502 x |= (y << i); 503 } 504 return (x); 505} 506 507static int 508atse_rxfilter_locked(struct atse_softc *sc) 509{ 510 struct ifnet *ifp; 511 struct ifmultiaddr *ifma; 512 uint32_t val4; 513 int i; 514 515 /* XXX-BZ can we find out if we have the MHASH synthesized? */ 516 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); 517 /* For simplicity always hash full 48 bits of addresses. */ 518 if ((val4 & BASE_CFG_COMMAND_CONFIG_MHASH_SEL) != 0) 519 val4 &= ~BASE_CFG_COMMAND_CONFIG_MHASH_SEL; 520 521 ifp = sc->atse_ifp; 522 if (ifp->if_flags & IFF_PROMISC) 523 val4 |= BASE_CFG_COMMAND_CONFIG_PROMIS_EN; 524 else 525 val4 &= ~BASE_CFG_COMMAND_CONFIG_PROMIS_EN; 526 527 CSR_WRITE_4(sc, BASE_CFG_COMMAND_CONFIG, val4); 528 529 if (ifp->if_flags & IFF_ALLMULTI) { 530 /* Accept all multicast addresses. */ 531 for (i = 0; i <= MHASH_LEN; i++) 532 CSR_WRITE_4(sc, MHASH_START + i, 0x1); 533 } else { 534 /* 535 * Can hold MHASH_LEN entries. 536 * XXX-BZ bitstring.h would be more general. 537 */ 538 uint64_t h; 539 540 h = 0; 541 /* 542 * Re-build and re-program hash table. First build the 543 * bit-field "yes" or "no" for each slot per address, then 544 * do all the programming afterwards. 545 */ 546 if_maddr_rlock(ifp); 547 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 548 if (ifma->ifma_addr->sa_family != AF_LINK) 549 continue; 550 551 h |= (1 << atse_mchash(sc, 552 LLADDR((struct sockaddr_dl *)ifma->ifma_addr))); 553 } 554 if_maddr_runlock(ifp); 555 for (i = 0; i <= MHASH_LEN; i++) 556 CSR_WRITE_4(sc, MHASH_START + i, 557 (h & (1 << i)) ? 0x01 : 0x00); 558 } 559 560 return (0); 561} 562 563static int 564atse_ethernet_option_bits_read_fdt(device_t dev) 565{ 566 struct resource *res; 567 device_t fdev; 568 int i, rid; 569 570 if (atse_ethernet_option_bits_flag & ATSE_ETHERNET_OPTION_BITS_READ) 571 return (0); 572 573 fdev = device_find_child(device_get_parent(dev), "cfi", 0); 574 if (fdev == NULL) 575 return (ENOENT); 576 577 rid = 0; 578 res = bus_alloc_resource_any(fdev, SYS_RES_MEMORY, &rid, 579 RF_ACTIVE | RF_SHAREABLE); 580 if (res == NULL) 581 return (ENXIO); 582 583 for (i = 0; i < ALTERA_ETHERNET_OPTION_BITS_LEN; i++) 584 atse_ethernet_option_bits[i] = bus_read_1(res, 585 ALTERA_ETHERNET_OPTION_BITS_OFF + i); 586 587 bus_release_resource(fdev, SYS_RES_MEMORY, rid, res); 588 atse_ethernet_option_bits_flag |= ATSE_ETHERNET_OPTION_BITS_READ; 589 590 return (0); 591} 592 593static int 594atse_ethernet_option_bits_read(device_t dev) 595{ 596 int error; 597 598 error = atse_ethernet_option_bits_read_fdt(dev); 599 if (error == 0) 600 return (0); 601 602 device_printf(dev, "Cannot read Ethernet addresses from flash.\n"); 603 return (error); 604} 605 606static int 607atse_get_eth_address(struct atse_softc *sc) 608{ 609 unsigned long hostid; 610 uint32_t val4; 611 int unit; 612 613 /* 614 * Make sure to only ever do this once. Otherwise a reset would 615 * possibly change our ethernet address, which is not good at all. 616 */ 617 if (sc->atse_eth_addr[0] != 0x00 || sc->atse_eth_addr[1] != 0x00 || 618 sc->atse_eth_addr[2] != 0x00) 619 return (0); 620 621 if ((atse_ethernet_option_bits_flag & 622 ATSE_ETHERNET_OPTION_BITS_READ) == 0) 623 goto get_random; 624 625 val4 = atse_ethernet_option_bits[0] << 24; 626 val4 |= atse_ethernet_option_bits[1] << 16; 627 val4 |= atse_ethernet_option_bits[2] << 8; 628 val4 |= atse_ethernet_option_bits[3]; 629 /* They chose "safe". */ 630 if (val4 != le32toh(0x00005afe)) { 631 device_printf(sc->atse_dev, "Magic '5afe' is not safe: 0x%08x. " 632 "Falling back to random numbers for hardware address.\n", 633 val4); 634 goto get_random; 635 } 636 637 sc->atse_eth_addr[0] = atse_ethernet_option_bits[4]; 638 sc->atse_eth_addr[1] = atse_ethernet_option_bits[5]; 639 sc->atse_eth_addr[2] = atse_ethernet_option_bits[6]; 640 sc->atse_eth_addr[3] = atse_ethernet_option_bits[7]; 641 sc->atse_eth_addr[4] = atse_ethernet_option_bits[8]; 642 sc->atse_eth_addr[5] = atse_ethernet_option_bits[9]; 643 644 /* Handle factory default ethernet addresss: 00:07:ed:ff:ed:15 */ 645 if (sc->atse_eth_addr[0] == 0x00 && sc->atse_eth_addr[1] == 0x07 && 646 sc->atse_eth_addr[2] == 0xed && sc->atse_eth_addr[3] == 0xff && 647 sc->atse_eth_addr[4] == 0xed && sc->atse_eth_addr[5] == 0x15) { 648 649 device_printf(sc->atse_dev, "Factory programmed Ethernet " 650 "hardware address blacklisted. Falling back to random " 651 "address to avoid collisions.\n"); 652 device_printf(sc->atse_dev, "Please re-program your flash.\n"); 653 goto get_random; 654 } 655 656 if (sc->atse_eth_addr[0] == 0x00 && sc->atse_eth_addr[1] == 0x00 && 657 sc->atse_eth_addr[2] == 0x00 && sc->atse_eth_addr[3] == 0x00 && 658 sc->atse_eth_addr[4] == 0x00 && sc->atse_eth_addr[5] == 0x00) { 659 device_printf(sc->atse_dev, "All zero's Ethernet hardware " 660 "address blacklisted. Falling back to random address.\n"); 661 device_printf(sc->atse_dev, "Please re-program your flash.\n"); 662 goto get_random; 663 } 664 665 if (ETHER_IS_MULTICAST(sc->atse_eth_addr)) { 666 device_printf(sc->atse_dev, "Multicast Ethernet hardware " 667 "address blacklisted. Falling back to random address.\n"); 668 device_printf(sc->atse_dev, "Please re-program your flash.\n"); 669 goto get_random; 670 } 671 672 /* 673 * If we find an Altera prefixed address with a 0x0 ending 674 * adjust by device unit. If not and this is not the first 675 * Ethernet, go to random. 676 */ 677 unit = device_get_unit(sc->atse_dev); 678 if (unit == 0x00) 679 return (0); 680 681 if (unit > 0x0f) { 682 device_printf(sc->atse_dev, "We do not support Ethernet " 683 "addresses for more than 16 MACs. Falling back to " 684 "random hadware address.\n"); 685 goto get_random; 686 } 687 if ((sc->atse_eth_addr[0] & ~0x2) != 0 || 688 sc->atse_eth_addr[1] != 0x07 || sc->atse_eth_addr[2] != 0xed || 689 (sc->atse_eth_addr[5] & 0x0f) != 0x0) { 690 device_printf(sc->atse_dev, "Ethernet address not meeting our " 691 "multi-MAC standards. Falling back to random hadware " 692 "address.\n"); 693 goto get_random; 694 } 695 sc->atse_eth_addr[5] |= (unit & 0x0f); 696 697 return (0); 698 699get_random: 700 /* 701 * Fall back to random code we also use on bridge(4). 702 */ 703 getcredhostid(curthread->td_ucred, &hostid); 704 if (hostid == 0) { 705 arc4rand(sc->atse_eth_addr, ETHER_ADDR_LEN, 1); 706 sc->atse_eth_addr[0] &= ~1;/* clear multicast bit */ 707 sc->atse_eth_addr[0] |= 2; /* set the LAA bit */ 708 } else { 709 sc->atse_eth_addr[0] = 0x2; 710 sc->atse_eth_addr[1] = (hostid >> 24) & 0xff; 711 sc->atse_eth_addr[2] = (hostid >> 16) & 0xff; 712 sc->atse_eth_addr[3] = (hostid >> 8 ) & 0xff; 713 sc->atse_eth_addr[4] = hostid & 0xff; 714 sc->atse_eth_addr[5] = sc->atse_unit & 0xff; 715 } 716 717 return (0); 718} 719 720static int 721atse_set_eth_address(struct atse_softc *sc, int n) 722{ 723 uint32_t v0, v1; 724 725 v0 = (sc->atse_eth_addr[3] << 24) | (sc->atse_eth_addr[2] << 16) | 726 (sc->atse_eth_addr[1] << 8) | sc->atse_eth_addr[0]; 727 v1 = (sc->atse_eth_addr[5] << 8) | sc->atse_eth_addr[4]; 728 729 if (n & ATSE_ETH_ADDR_DEF) { 730 CSR_WRITE_4(sc, BASE_CFG_MAC_0, v0); 731 CSR_WRITE_4(sc, BASE_CFG_MAC_1, v1); 732 } 733 if (n & ATSE_ETH_ADDR_SUPP1) { 734 CSR_WRITE_4(sc, SUPPL_ADDR_SMAC_0_0, v0); 735 CSR_WRITE_4(sc, SUPPL_ADDR_SMAC_0_1, v1); 736 } 737 if (n & ATSE_ETH_ADDR_SUPP2) { 738 CSR_WRITE_4(sc, SUPPL_ADDR_SMAC_1_0, v0); 739 CSR_WRITE_4(sc, SUPPL_ADDR_SMAC_1_1, v1); 740 } 741 if (n & ATSE_ETH_ADDR_SUPP3) { 742 CSR_WRITE_4(sc, SUPPL_ADDR_SMAC_2_0, v0); 743 CSR_WRITE_4(sc, SUPPL_ADDR_SMAC_2_1, v1); 744 } 745 if (n & ATSE_ETH_ADDR_SUPP4) { 746 CSR_WRITE_4(sc, SUPPL_ADDR_SMAC_3_0, v0); 747 CSR_WRITE_4(sc, SUPPL_ADDR_SMAC_3_1, v1); 748 } 749 750 return (0); 751} 752 753static int 754atse_reset(struct atse_softc *sc) 755{ 756 int i; 757 uint32_t val4, mask; 758 uint16_t val; 759 760 /* 1. External PHY Initialization using MDIO. */ 761 /* 762 * We select the right MDIO space in atse_attach() and let MII do 763 * anything else. 764 */ 765 766 /* 2. PCS Configuration Register Initialization. */ 767 /* a. Set auto negotiation link timer to 1.6ms for SGMII. */ 768 PCS_WRITE_2(sc, PCS_EXT_LINK_TIMER_0, 0x0D40); 769 PCS_WRITE_2(sc, PCS_EXT_LINK_TIMER_1, 0x0003); 770 771 /* b. Configure SGMII. */ 772 val = PCS_EXT_IF_MODE_SGMII_ENA|PCS_EXT_IF_MODE_USE_SGMII_AN; 773 PCS_WRITE_2(sc, PCS_EXT_IF_MODE, val); 774 775 /* c. Enable auto negotiation. */ 776 /* Ignore Bits 6,8,13; should be set,set,unset. */ 777 val = PCS_READ_2(sc, PCS_CONTROL); 778 val &= ~(PCS_CONTROL_ISOLATE|PCS_CONTROL_POWERDOWN); 779 val &= ~PCS_CONTROL_LOOPBACK; /* Make this a -link1 option? */ 780 val |= PCS_CONTROL_AUTO_NEGOTIATION_ENABLE; 781 PCS_WRITE_2(sc, PCS_CONTROL, val); 782 783 /* d. PCS reset. */ 784 val = PCS_READ_2(sc, PCS_CONTROL); 785 val |= PCS_CONTROL_RESET; 786 PCS_WRITE_2(sc, PCS_CONTROL, val); 787 /* Wait for reset bit to clear; i=100 is excessive. */ 788 for (i = 0; i < 100; i++) { 789 val = PCS_READ_2(sc, PCS_CONTROL); 790 if ((val & PCS_CONTROL_RESET) == 0) 791 break; 792 DELAY(10); 793 } 794 if ((val & PCS_CONTROL_RESET) != 0) { 795 device_printf(sc->atse_dev, "PCS reset timed out.\n"); 796 return (ENXIO); 797 } 798 799 /* 3. MAC Configuration Register Initialization. */ 800 /* a. Disable MAC transmit and receive datapath. */ 801 mask = BASE_CFG_COMMAND_CONFIG_TX_ENA|BASE_CFG_COMMAND_CONFIG_RX_ENA; 802 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); 803 val4 &= ~mask; 804 /* Samples in the manual do have the SW_RESET bit set here, why? */ 805 CSR_WRITE_4(sc, BASE_CFG_COMMAND_CONFIG, val4); 806 /* Wait for bits to be cleared; i=100 is excessive. */ 807 for (i = 0; i < 100; i++) { 808 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); 809 if ((val4 & mask) == 0) 810 break; 811 DELAY(10); 812 } 813 if ((val4 & mask) != 0) { 814 device_printf(sc->atse_dev, "Disabling MAC TX/RX timed out.\n"); 815 return (ENXIO); 816 } 817 /* b. MAC FIFO configuration. */ 818 CSR_WRITE_4(sc, BASE_CFG_TX_SECTION_EMPTY, FIFO_DEPTH_TX - 16); 819 CSR_WRITE_4(sc, BASE_CFG_TX_ALMOST_FULL, 3); 820 CSR_WRITE_4(sc, BASE_CFG_TX_ALMOST_EMPTY, 8); 821 CSR_WRITE_4(sc, BASE_CFG_RX_SECTION_EMPTY, FIFO_DEPTH_RX - 16); 822 CSR_WRITE_4(sc, BASE_CFG_RX_ALMOST_FULL, 8); 823 CSR_WRITE_4(sc, BASE_CFG_RX_ALMOST_EMPTY, 8); 824#if 0 825 CSR_WRITE_4(sc, BASE_CFG_TX_SECTION_FULL, 16); 826 CSR_WRITE_4(sc, BASE_CFG_RX_SECTION_FULL, 16); 827#else 828 /* For store-and-forward mode, set this threshold to 0. */ 829 CSR_WRITE_4(sc, BASE_CFG_TX_SECTION_FULL, 0); 830 CSR_WRITE_4(sc, BASE_CFG_RX_SECTION_FULL, 0); 831#endif 832 /* c. MAC address configuration. */ 833 /* Also intialize supplementary addresses to our primary one. */ 834 /* XXX-BZ FreeBSD really needs to grow and API for using these. */ 835 atse_get_eth_address(sc); 836 atse_set_eth_address(sc, ATSE_ETH_ADDR_ALL); 837 838 /* d. MAC function configuration. */ 839 CSR_WRITE_4(sc, BASE_CFG_FRM_LENGTH, 1518); /* Default. */ 840 CSR_WRITE_4(sc, BASE_CFG_TX_IPG_LENGTH, 12); 841 CSR_WRITE_4(sc, BASE_CFG_PAUSE_QUANT, 0xFFFF); 842 843 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); 844 /* 845 * If 1000BASE-X/SGMII PCS is initialized, set the ETH_SPEED (bit 3) 846 * and ENA_10 (bit 25) in command_config register to 0. If half duplex 847 * is reported in the PHY/PCS status register, set the HD_ENA (bit 10) 848 * to 1 in command_config register. 849 * BZ: We shoot for 1000 instead. 850 */ 851#if 0 852 val4 |= BASE_CFG_COMMAND_CONFIG_ETH_SPEED; 853#else 854 val4 &= ~BASE_CFG_COMMAND_CONFIG_ETH_SPEED; 855#endif 856 val4 &= ~BASE_CFG_COMMAND_CONFIG_ENA_10; 857#if 0 858 /* 859 * We do not want to set this, otherwise, we could not even send 860 * random raw ethernet frames for various other research. By default 861 * FreeBSD will use the right ether source address. 862 */ 863 val4 |= BASE_CFG_COMMAND_CONFIG_TX_ADDR_INS; 864#endif 865 val4 |= BASE_CFG_COMMAND_CONFIG_PAD_EN; 866 val4 &= ~BASE_CFG_COMMAND_CONFIG_CRC_FWD; 867#if 0 868 val4 |= BASE_CFG_COMMAND_CONFIG_CNTL_FRM_ENA; 869#endif 870#if 1 871 val4 |= BASE_CFG_COMMAND_CONFIG_RX_ERR_DISC; 872#endif 873 val &= ~BASE_CFG_COMMAND_CONFIG_LOOP_ENA; /* link0? */ 874 CSR_WRITE_4(sc, BASE_CFG_COMMAND_CONFIG, val4); 875 876 /* 877 * Make sure we do not enable 32bit alignment; FreeBSD cannot 878 * cope with the additional padding (though we should!?). 879 * Also make sure we get the CRC appended. 880 */ 881 val4 = CSR_READ_4(sc, TX_CMD_STAT); 882 val4 &= ~(TX_CMD_STAT_OMIT_CRC|TX_CMD_STAT_TX_SHIFT16); 883 CSR_WRITE_4(sc, TX_CMD_STAT, val4); 884 val4 = CSR_READ_4(sc, RX_CMD_STAT); 885 val4 &= ~RX_CMD_STAT_RX_SHIFT16; 886 CSR_WRITE_4(sc, RX_CMD_STAT, val4); 887 888 /* e. Reset MAC. */ 889 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); 890 val4 |= BASE_CFG_COMMAND_CONFIG_SW_RESET; 891 CSR_WRITE_4(sc, BASE_CFG_COMMAND_CONFIG, val4); 892 /* Wait for bits to be cleared; i=100 is excessive. */ 893 for (i = 0; i < 100; i++) { 894 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); 895 if ((val4 & BASE_CFG_COMMAND_CONFIG_SW_RESET) == 0) 896 break; 897 DELAY(10); 898 } 899 if ((val4 & BASE_CFG_COMMAND_CONFIG_SW_RESET) != 0) { 900 device_printf(sc->atse_dev, "MAC reset timed out.\n"); 901 return (ENXIO); 902 } 903 904 /* f. Enable MAC transmit and receive datapath. */ 905 mask = BASE_CFG_COMMAND_CONFIG_TX_ENA|BASE_CFG_COMMAND_CONFIG_RX_ENA; 906 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); 907 val4 |= mask; 908 CSR_WRITE_4(sc, BASE_CFG_COMMAND_CONFIG, val4); 909 /* Wait for bits to be cleared; i=100 is excessive. */ 910 for (i = 0; i < 100; i++) { 911 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); 912 if ((val4 & mask) == mask) 913 break; 914 DELAY(10); 915 } 916 if ((val4 & mask) != mask) { 917 device_printf(sc->atse_dev, "Enabling MAC TX/RX timed out.\n"); 918 return (ENXIO); 919 } 920 921 return (0); 922} 923 924static void 925atse_init_locked(struct atse_softc *sc) 926{ 927 struct ifnet *ifp; 928 struct mii_data *mii; 929 uint8_t *eaddr; 930 931 ATSE_LOCK_ASSERT(sc); 932 ifp = sc->atse_ifp; 933 934 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 935 return; 936 937 /* 938 * Must update the ether address if changed. Given we do not handle 939 * in atse_ioctl() but it's in the general framework, just always 940 * do it here before atse_reset(). 941 */ 942 eaddr = IF_LLADDR(sc->atse_ifp); 943 bcopy(eaddr, &sc->atse_eth_addr, ETHER_ADDR_LEN); 944 945 /* Make things frind to halt, cleanup, ... */ 946 atse_stop_locked(sc); 947 /* ... reset, ... */ 948 atse_reset(sc); 949 950 /* ... and fire up the engine again. */ 951 atse_rxfilter_locked(sc); 952 953 /* Memory rings? DMA engine? */ 954 955 sc->atse_rx_buf_len = 0; 956 sc->atse_flags &= ATSE_FLAGS_LINK; /* Preserve. */ 957 958#ifdef DEVICE_POLLING 959 /* Only enable interrupts if we are not polling. */ 960 if (ifp->if_capenable & IFCAP_POLLING) { 961 ATSE_RX_INTR_DISABLE(sc); 962 ATSE_TX_INTR_DISABLE(sc); 963 ATSE_RX_EVENT_CLEAR(sc); 964 ATSE_TX_EVENT_CLEAR(sc); 965 } else 966#endif 967 { 968 ATSE_RX_INTR_ENABLE(sc); 969 ATSE_TX_INTR_ENABLE(sc); 970 } 971 972 mii = device_get_softc(sc->atse_miibus); 973 974 sc->atse_flags &= ~ATSE_FLAGS_LINK; 975 mii_mediachg(mii); 976 977 ifp->if_drv_flags |= IFF_DRV_RUNNING; 978 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 979 980 callout_reset(&sc->atse_tick, hz, atse_tick, sc); 981} 982 983static void 984atse_init(void *xsc) 985{ 986 struct atse_softc *sc; 987 988 sc = (struct atse_softc *)xsc; 989 ATSE_LOCK(sc); 990 atse_init_locked(sc); 991 ATSE_UNLOCK(sc); 992} 993 994static int 995atse_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 996{ 997 struct atse_softc *sc; 998 struct ifreq *ifr; 999 int error, mask; 1000 1001 1002 error = 0; 1003 sc = ifp->if_softc; 1004 ifr = (struct ifreq *)data; 1005 1006 switch (command) { 1007 case SIOCSIFFLAGS: 1008 ATSE_LOCK(sc); 1009 if (ifp->if_flags & IFF_UP) { 1010 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 1011 ((ifp->if_flags ^ sc->atse_if_flags) & 1012 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1013 atse_rxfilter_locked(sc); 1014 else 1015 atse_init_locked(sc); 1016 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1017 atse_stop_locked(sc); 1018 sc->atse_if_flags = ifp->if_flags; 1019 ATSE_UNLOCK(sc); 1020 break; 1021 case SIOCSIFCAP: 1022 ATSE_LOCK(sc); 1023 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1024#ifdef DEVICE_POLLING 1025 if ((mask & IFCAP_POLLING) != 0 && 1026 (IFCAP_POLLING & ifp->if_capabilities) != 0) { 1027 ifp->if_capenable ^= IFCAP_POLLING; 1028 if ((IFCAP_POLLING & ifp->if_capenable) != 0) { 1029 1030 error = ether_poll_register(atse_poll, ifp); 1031 if (error != 0) { 1032 ATSE_UNLOCK(sc); 1033 break; 1034 } 1035 /* Disable interrupts. */ 1036 ATSE_RX_INTR_DISABLE(sc); 1037 ATSE_TX_INTR_DISABLE(sc); 1038 ATSE_RX_EVENT_CLEAR(sc); 1039 ATSE_TX_EVENT_CLEAR(sc); 1040 1041 /* 1042 * Do not allow disabling of polling if we do 1043 * not have interrupts. 1044 */ 1045 } else if (sc->atse_rx_irq_res != NULL || 1046 sc->atse_tx_irq_res != NULL) { 1047 error = ether_poll_deregister(ifp); 1048 /* Enable interrupts. */ 1049 ATSE_RX_INTR_ENABLE(sc); 1050 ATSE_TX_INTR_ENABLE(sc); 1051 } else { 1052 ifp->if_capenable ^= IFCAP_POLLING; 1053 error = EINVAL; 1054 } 1055 } 1056#endif /* DEVICE_POLLING */ 1057 ATSE_UNLOCK(sc); 1058 break; 1059 case SIOCADDMULTI: 1060 case SIOCDELMULTI: 1061 ATSE_LOCK(sc); 1062 atse_rxfilter_locked(sc); 1063 ATSE_UNLOCK(sc); 1064 break; 1065 case SIOCGIFMEDIA: 1066 case SIOCSIFMEDIA: 1067 { 1068 struct mii_data *mii; 1069 struct ifreq *ifr; 1070 1071 mii = device_get_softc(sc->atse_miibus); 1072 ifr = (struct ifreq *)data; 1073 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1074 break; 1075 } 1076 default: 1077 error = ether_ioctl(ifp, command, data); 1078 break; 1079 } 1080 1081 return (error); 1082} 1083 1084static void 1085atse_watchdog(struct atse_softc *sc) 1086{ 1087 1088 ATSE_LOCK_ASSERT(sc); 1089 1090 if (sc->atse_watchdog_timer == 0 || --sc->atse_watchdog_timer > 0) 1091 return; 1092 1093 device_printf(sc->atse_dev, "watchdog timeout\n"); 1094 sc->atse_ifp->if_oerrors++; 1095 1096 sc->atse_ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1097 atse_init_locked(sc); 1098 1099 if (!IFQ_DRV_IS_EMPTY(&sc->atse_ifp->if_snd)) 1100 atse_start_locked(sc->atse_ifp); 1101} 1102 1103static void 1104atse_tick(void *xsc) 1105{ 1106 struct atse_softc *sc; 1107 struct mii_data *mii; 1108 struct ifnet *ifp; 1109 1110 sc = (struct atse_softc *)xsc; 1111 ATSE_LOCK_ASSERT(sc); 1112 ifp = sc->atse_ifp; 1113 1114 mii = device_get_softc(sc->atse_miibus); 1115 mii_tick(mii); 1116 atse_watchdog(sc); 1117 if ((sc->atse_flags & ATSE_FLAGS_LINK) == 0) 1118 atse_miibus_statchg(sc->atse_dev); 1119 callout_reset(&sc->atse_tick, hz, atse_tick, sc); 1120} 1121 1122/* 1123 * Set media options. 1124 */ 1125static int 1126atse_ifmedia_upd(struct ifnet *ifp) 1127{ 1128 struct atse_softc *sc; 1129 struct mii_data *mii; 1130 struct mii_softc *miisc; 1131 int error; 1132 1133 sc = ifp->if_softc; 1134 1135 ATSE_LOCK(sc); 1136 mii = device_get_softc(sc->atse_miibus); 1137 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1138 PHY_RESET(miisc); 1139 error = mii_mediachg(mii); 1140 ATSE_UNLOCK(sc); 1141 1142 return (error); 1143} 1144 1145static void 1146atse_update_rx_err(struct atse_softc *sc, uint32_t mask) 1147{ 1148 int i; 1149 1150 /* RX error are 6 bits, we only know 4 of them. */ 1151 for (i = 0; i < ATSE_RX_ERR_MAX; i++) 1152 if ((mask & (1 << i)) != 0) 1153 sc->atse_rx_err[i]++; 1154} 1155 1156static int 1157atse_rx_locked(struct atse_softc *sc) 1158{ 1159 struct ifnet *ifp; 1160 struct mbuf *m; 1161 uint32_t fill, i, j; 1162 uint32_t data, meta; 1163 int rx_npkts = 0; 1164 1165 ATSE_LOCK_ASSERT(sc); 1166 1167 ifp = sc->atse_ifp; 1168 j = 0; 1169 meta = 0; 1170 do { 1171outer: 1172 if (sc->atse_rx_cycles <= 0) 1173 return (rx_npkts); 1174 sc->atse_rx_cycles--; 1175 1176 if (sc->atse_rx_m == NULL) { 1177 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1178 if (m == NULL) 1179 return (rx_npkts); 1180 m->m_len = m->m_pkthdr.len = MCLBYTES; 1181 /* Make sure upper layers will be aligned. */ 1182 m_adj(m, 2); 1183 sc->atse_rx_m = m; 1184 } 1185 1186 fill = ATSE_RX_READ_FILL_LEVEL(sc); 1187 for (i = 0; i < fill; i++) { 1188 /* 1189 * XXX-BZ for whatever reason the FIFO requires the 1190 * the data read before we can access the meta data. 1191 */ 1192 data = ATSE_RX_DATA_READ(sc); 1193 meta = ATSE_RX_META_READ(sc); 1194 if (meta & A_ONCHIP_FIFO_MEM_CORE_ERROR_MASK) { 1195 /* XXX-BZ evaluate error. */ 1196 atse_update_rx_err(sc, ((meta & 1197 A_ONCHIP_FIFO_MEM_CORE_ERROR_MASK) >> 1198 A_ONCHIP_FIFO_MEM_CORE_ERROR_SHIFT) & 0xff); 1199 ifp->if_ierrors++; 1200 sc->atse_rx_buf_len = 0; 1201 /* 1202 * Should still read till EOP or next SOP. 1203 * 1204 * XXX-BZ might also depend on 1205 * BASE_CFG_COMMAND_CONFIG_RX_ERR_DISC 1206 */ 1207 sc->atse_flags |= ATSE_FLAGS_ERROR; 1208 return (rx_npkts); 1209 } 1210 if ((meta & A_ONCHIP_FIFO_MEM_CORE_CHANNEL_MASK) != 0) 1211 device_printf(sc->atse_dev, "%s: unexpected " 1212 "channel %u\n", __func__, (meta & 1213 A_ONCHIP_FIFO_MEM_CORE_CHANNEL_MASK) >> 1214 A_ONCHIP_FIFO_MEM_CORE_CHANNEL_SHIFT); 1215 1216 if (meta & A_ONCHIP_FIFO_MEM_CORE_SOP) { 1217 /* 1218 * There is no need to clear SOP between 1st 1219 * and subsequent packet data junks. 1220 */ 1221 if (sc->atse_rx_buf_len != 0 && 1222 (sc->atse_flags & ATSE_FLAGS_SOP_SEEN) == 0) 1223 { 1224 device_printf(sc->atse_dev, "%s: SOP " 1225 "without empty buffer: %u\n", 1226 __func__, sc->atse_rx_buf_len); 1227 /* XXX-BZ any better counter? */ 1228 ifp->if_ierrors++; 1229 } 1230 1231 if ((sc->atse_flags & ATSE_FLAGS_SOP_SEEN) == 0) 1232 { 1233 sc->atse_flags |= ATSE_FLAGS_SOP_SEEN; 1234 sc->atse_rx_buf_len = 0; 1235 } 1236 } 1237#if 0 /* We had to read the data before we could access meta data. See above. */ 1238 data = ATSE_RX_DATA_READ(sc); 1239#endif 1240 /* Make sure to not overflow the mbuf data size. */ 1241 if (sc->atse_rx_buf_len >= sc->atse_rx_m->m_len - 4) { 1242 /* 1243 * XXX-BZ Error. We need more mbufs and are 1244 * not setup for this yet. 1245 */ 1246 ifp->if_ierrors++; 1247 sc->atse_flags |= ATSE_FLAGS_ERROR; 1248 } 1249 if ((sc->atse_flags & ATSE_FLAGS_ERROR) == 0) 1250 /* 1251 * MUST keep this bcopy as m_data after m_adj 1252 * for IP header aligment is on half-word 1253 * and not word alignment. 1254 */ 1255 bcopy(&data, (uint8_t *)(sc->atse_rx_m->m_data + 1256 sc->atse_rx_buf_len), sizeof(data)); 1257 if (meta & A_ONCHIP_FIFO_MEM_CORE_EOP) { 1258 uint8_t empty; 1259 1260 empty = (meta & 1261 A_ONCHIP_FIFO_MEM_CORE_EMPTY_MASK) >> 1262 A_ONCHIP_FIFO_MEM_CORE_EMPTY_SHIFT; 1263 sc->atse_rx_buf_len += (4 - empty); 1264 1265 ifp->if_ipackets++; 1266 rx_npkts++; 1267 1268 m = sc->atse_rx_m; 1269 m->m_pkthdr.len = m->m_len = 1270 sc->atse_rx_buf_len; 1271 sc->atse_rx_m = NULL; 1272 1273 sc->atse_rx_buf_len = 0; 1274 sc->atse_flags &= ~ATSE_FLAGS_SOP_SEEN; 1275 if (sc->atse_flags & ATSE_FLAGS_ERROR) { 1276 sc->atse_flags &= ~ATSE_FLAGS_ERROR; 1277 m_freem(m); 1278 /* Need to start with a new packet. */ 1279 goto outer; 1280 } 1281 1282 m->m_pkthdr.rcvif = ifp; 1283 1284 ATSE_UNLOCK(sc); 1285 (*ifp->if_input)(ifp, m); 1286 ATSE_LOCK(sc); 1287 goto outer; /* Need a new mbuf. */ 1288 } else { 1289 sc->atse_rx_buf_len += sizeof(data); 1290 } 1291 } /* for */ 1292 1293 /* XXX-BZ could optimize in case of another packet waiting. */ 1294 } while ((meta & A_ONCHIP_FIFO_MEM_CORE_EOP) == 0 || fill > 0); 1295 1296 return (rx_npkts); 1297} 1298 1299 1300/* 1301 * Report current media status. 1302 */ 1303static void 1304atse_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1305{ 1306 struct atse_softc *sc; 1307 struct mii_data *mii; 1308 1309 sc = ifp->if_softc; 1310 1311 ATSE_LOCK(sc); 1312 mii = device_get_softc(sc->atse_miibus); 1313 mii_pollstat(mii); 1314 ifmr->ifm_active = mii->mii_media_active; 1315 ifmr->ifm_status = mii->mii_media_status; 1316 ATSE_UNLOCK(sc); 1317} 1318 1319static void 1320atse_intr(void *arg) 1321{ 1322 struct atse_softc *sc; 1323 struct ifnet *ifp; 1324 uint32_t rx, tx; 1325 1326 sc = (struct atse_softc *)arg; 1327 ifp = sc->atse_ifp; 1328 1329 ATSE_LOCK(sc); 1330#ifdef DEVICE_POLLING 1331 if (ifp->if_capenable & IFCAP_POLLING) { 1332 ATSE_UNLOCK(sc); 1333 return; 1334 } 1335#endif 1336 1337 ATSE_RX_INTR_DISABLE(sc); 1338 ATSE_TX_INTR_DISABLE(sc); 1339 1340 rx = ATSE_RX_EVENT_READ(sc); 1341 tx = ATSE_TX_EVENT_READ(sc); 1342 if (rx != 0) { 1343 if (rx & (A_ONCHIP_FIFO_MEM_CORE_EVENT_OVERFLOW| 1344 A_ONCHIP_FIFO_MEM_CORE_EVENT_UNDERFLOW)) { 1345 /* XXX-BZ ERROR HANDLING. */ 1346 atse_update_rx_err(sc, ((rx & 1347 A_ONCHIP_FIFO_MEM_CORE_ERROR_MASK) >> 1348 A_ONCHIP_FIFO_MEM_CORE_ERROR_SHIFT) & 0xff); 1349 ifp->if_ierrors++; 1350 } 1351 if ((rx & A_ONCHIP_FIFO_MEM_CORE_EVENT_EMPTY) != 0) { 1352 sc->atse_rx_cycles = RX_CYCLES_IN_INTR; 1353 atse_rx_locked(sc); 1354 } 1355 } 1356 if (tx != 0) { 1357 /* XXX-BZ build histogram. */ 1358 if (tx & (A_ONCHIP_FIFO_MEM_CORE_EVENT_OVERFLOW| 1359 A_ONCHIP_FIFO_MEM_CORE_EVENT_UNDERFLOW)) { 1360 /* XXX-BZ ERROR HANDLING. */ 1361 ifp->if_oerrors++; 1362 } 1363 if (tx & A_ONCHIP_FIFO_MEM_CORE_EVENT_EMPTY) 1364 sc->atse_watchdog_timer = 0; 1365#if 0 1366 if (tx & (A_ONCHIP_FIFO_MEM_CORE_EVENT_EMPTY| 1367 A_ONCHIP_FIFO_MEM_CORE_EVENT_ALMOSTEMPTY)) 1368 atse_start_locked(ifp); 1369#endif 1370 } 1371 1372 /* Clear events before re-enabling intrs. */ 1373 ATSE_TX_EVENT_CLEAR(sc); 1374 ATSE_RX_EVENT_CLEAR(sc); 1375 1376 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1377 /* Re-enable interrupts. */ 1378 ATSE_RX_INTR_ENABLE(sc); 1379 ATSE_TX_INTR_ENABLE(sc); 1380 1381 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1382 atse_start_locked(ifp); 1383 } 1384 1385 ATSE_UNLOCK(sc); 1386} 1387 1388#ifdef DEVICE_POLLING 1389static int 1390atse_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1391{ 1392 struct atse_softc *sc; 1393 int rx_npkts = 0; 1394 1395 sc = ifp->if_softc; 1396 ATSE_LOCK(sc); 1397 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1398 ATSE_UNLOCK(sc); 1399 return (rx_npkts); 1400 } 1401 1402 sc->atse_rx_cycles = count; 1403 rx_npkts = atse_rx_locked(sc); 1404 atse_start_locked(ifp); 1405 1406 if (sc->atse_rx_cycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1407 uint32_t rx, tx; 1408 1409 rx = ATSE_RX_EVENT_READ(sc); 1410 tx = ATSE_TX_EVENT_READ(sc); 1411 1412 if (rx & (A_ONCHIP_FIFO_MEM_CORE_EVENT_OVERFLOW| 1413 A_ONCHIP_FIFO_MEM_CORE_EVENT_UNDERFLOW)) { 1414 /* XXX-BZ ERROR HANDLING. */ 1415 atse_update_rx_err(sc, ((rx & 1416 A_ONCHIP_FIFO_MEM_CORE_ERROR_MASK) >> 1417 A_ONCHIP_FIFO_MEM_CORE_ERROR_SHIFT) & 0xff); 1418 ifp->if_ierrors++; 1419 } 1420 if (tx & (A_ONCHIP_FIFO_MEM_CORE_EVENT_OVERFLOW| 1421 A_ONCHIP_FIFO_MEM_CORE_EVENT_UNDERFLOW)) { 1422 /* XXX-BZ ERROR HANDLING. */ 1423 ifp->if_oerrors++; 1424 } 1425 if (tx & A_ONCHIP_FIFO_MEM_CORE_EVENT_EMPTY) 1426 sc->atse_watchdog_timer = 0; 1427 1428#if 0 1429 if (/* Severe error; if only we could find out. */) { 1430 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1431 atse_init_locked(sc); 1432 } 1433#endif 1434 } 1435 1436 ATSE_UNLOCK(sc); 1437 return (rx_npkts); 1438} 1439#endif /* DEVICE_POLLING */ 1440 1441static struct atse_mac_stats_regs { 1442 const char *name; 1443 const char *descr; /* Mostly copied from Altera datasheet. */ 1444} atse_mac_stats_regs[] = { 1445 [0x1a] = 1446 { "aFramesTransmittedOK", 1447 "The number of frames that are successfully transmitted including " 1448 "the pause frames." }, 1449 { "aFramesReceivedOK", 1450 "The number of frames that are successfully received including the " 1451 "pause frames." }, 1452 { "aFrameCheckSequenceErrors", 1453 "The number of receive frames with CRC error." }, 1454 { "aAlignmentErrors", 1455 "The number of receive frames with alignment error." }, 1456 { "aOctetsTransmittedOK", 1457 "The lower 32 bits of the number of data and padding octets that " 1458 "are successfully transmitted." }, 1459 { "aOctetsReceivedOK", 1460 "The lower 32 bits of the number of data and padding octets that " 1461 " are successfully received." }, 1462 { "aTxPAUSEMACCtrlFrames", 1463 "The number of pause frames transmitted." }, 1464 { "aRxPAUSEMACCtrlFrames", 1465 "The number received pause frames received." }, 1466 { "ifInErrors", 1467 "The number of errored frames received." }, 1468 { "ifOutErrors", 1469 "The number of transmit frames with either a FIFO overflow error, " 1470 "a FIFO underflow error, or a error defined by the user " 1471 "application." }, 1472 { "ifInUcastPkts", 1473 "The number of valid unicast frames received." }, 1474 { "ifInMulticastPkts", 1475 "The number of valid multicast frames received. The count does " 1476 "not include pause frames." }, 1477 { "ifInBroadcastPkts", 1478 "The number of valid broadcast frames received." }, 1479 { "ifOutDiscards", 1480 "This statistics counter is not in use. The MAC function does not " 1481 "discard frames that are written to the FIFO buffer by the user " 1482 "application." }, 1483 { "ifOutUcastPkts", 1484 "The number of valid unicast frames transmitted." }, 1485 { "ifOutMulticastPkts", 1486 "The number of valid multicast frames transmitted, excluding pause " 1487 "frames." }, 1488 { "ifOutBroadcastPkts", 1489 "The number of valid broadcast frames transmitted." }, 1490 { "etherStatsDropEvents", 1491 "The number of frames that are dropped due to MAC internal errors " 1492 "when FIFO buffer overflow persists." }, 1493 { "etherStatsOctets", 1494 "The lower 32 bits of the total number of octets received. This " 1495 "count includes both good and errored frames." }, 1496 { "etherStatsPkts", 1497 "The total number of good and errored frames received." }, 1498 { "etherStatsUndersizePkts", 1499 "The number of frames received with length less than 64 bytes. " 1500 "This count does not include errored frames." }, 1501 { "etherStatsOversizePkts", 1502 "The number of frames received that are longer than the value " 1503 "configured in the frm_length register. This count does not " 1504 "include errored frames." }, 1505 { "etherStatsPkts64Octets", 1506 "The number of 64-byte frames received. This count includes good " 1507 "and errored frames." }, 1508 { "etherStatsPkts65to127Octets", 1509 "The number of received good and errored frames between the length " 1510 "of 65 and 127 bytes." }, 1511 { "etherStatsPkts128to255Octets", 1512 "The number of received good and errored frames between the length " 1513 "of 128 and 255 bytes." }, 1514 { "etherStatsPkts256to511Octets", 1515 "The number of received good and errored frames between the length " 1516 "of 256 and 511 bytes." }, 1517 { "etherStatsPkts512to1023Octets", 1518 "The number of received good and errored frames between the length " 1519 "of 512 and 1023 bytes." }, 1520 { "etherStatsPkts1024to1518Octets", 1521 "The number of received good and errored frames between the length " 1522 "of 1024 and 1518 bytes." }, 1523 { "etherStatsPkts1519toXOctets", 1524 "The number of received good and errored frames between the length " 1525 "of 1519 and the maximum frame length configured in the frm_length " 1526 "register." }, 1527 { "etherStatsJabbers", 1528 "Too long frames with CRC error." }, 1529 { "etherStatsFragments", 1530 "Too short frames with CRC error." }, 1531 /* 0x39 unused, 0x3a/b non-stats. */ 1532 [0x3c] = 1533 /* Extended Statistics Counters */ 1534 { "msb_aOctetsTransmittedOK", 1535 "Upper 32 bits of the number of data and padding octets that are " 1536 "successfully transmitted." }, 1537 { "msb_aOctetsReceivedOK", 1538 "Upper 32 bits of the number of data and padding octets that are " 1539 "successfully received." }, 1540 { "msb_etherStatsOctets", 1541 "Upper 32 bits of the total number of octets received. This count " 1542 "includes both good and errored frames." } 1543}; 1544 1545static int 1546sysctl_atse_mac_stats_proc(SYSCTL_HANDLER_ARGS) 1547{ 1548 struct atse_softc *sc; 1549 int error, offset, s; 1550 1551 sc = arg1; 1552 offset = arg2; 1553 1554 s = CSR_READ_4(sc, offset); 1555 error = sysctl_handle_int(oidp, &s, 0, req); 1556 if (error || !req->newptr) 1557 return (error); 1558 1559 return (0); 1560} 1561 1562static struct atse_rx_err_stats_regs { 1563 const char *name; 1564 const char *descr; 1565} atse_rx_err_stats_regs[] = { 1566 1567#define ATSE_RX_ERR_FIFO_THRES_EOP 0 /* FIFO threshold reached, on EOP. */ 1568#define ATSE_RX_ERR_ELEN 1 /* Frame/payload length not valid. */ 1569#define ATSE_RX_ERR_CRC32 2 /* CRC-32 error. */ 1570#define ATSE_RX_ERR_FIFO_THRES_TRUNC 3 /* FIFO thresh., truncated frame. */ 1571#define ATSE_RX_ERR_4 4 /* ? */ 1572#define ATSE_RX_ERR_5 5 /* / */ 1573 1574 { "rx_err_fifo_thres_eop", 1575 "FIFO threshold reached, reported on EOP." }, 1576 { "rx_err_fifo_elen", 1577 "Frame or payload length not valid." }, 1578 { "rx_err_fifo_crc32", 1579 "CRC-32 error." }, 1580 { "rx_err_fifo_thres_trunc", 1581 "FIFO threshold reached, truncated frame" }, 1582 { "rx_err_4", 1583 "?" }, 1584 { "rx_err_5", 1585 "?" }, 1586}; 1587 1588static int 1589sysctl_atse_rx_err_stats_proc(SYSCTL_HANDLER_ARGS) 1590{ 1591 struct atse_softc *sc; 1592 int error, offset, s; 1593 1594 sc = arg1; 1595 offset = arg2; 1596 1597 s = sc->atse_rx_err[offset]; 1598 error = sysctl_handle_int(oidp, &s, 0, req); 1599 if (error || !req->newptr) 1600 return (error); 1601 1602 return (0); 1603} 1604 1605static void 1606atse_sysctl_stats_attach(device_t dev) 1607{ 1608 struct sysctl_ctx_list *sctx; 1609 struct sysctl_oid *soid; 1610 struct atse_softc *sc; 1611 int i; 1612 1613 sc = device_get_softc(dev); 1614 sctx = device_get_sysctl_ctx(dev); 1615 soid = device_get_sysctl_tree(dev); 1616 1617 /* MAC statistics. */ 1618 for (i = 0; i < sizeof(atse_mac_stats_regs) / 1619 sizeof(*atse_mac_stats_regs); i++) { 1620 if (atse_mac_stats_regs[i].name == NULL || 1621 atse_mac_stats_regs[i].descr == NULL) 1622 continue; 1623 1624 SYSCTL_ADD_PROC(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, 1625 atse_mac_stats_regs[i].name, CTLTYPE_UINT|CTLFLAG_RD, 1626 sc, i, sysctl_atse_mac_stats_proc, "IU", 1627 atse_mac_stats_regs[i].descr); 1628 } 1629 1630 /* rx_err[]. */ 1631 for (i = 0; i < ATSE_RX_ERR_MAX; i++) { 1632 if (atse_rx_err_stats_regs[i].name == NULL || 1633 atse_rx_err_stats_regs[i].descr == NULL) 1634 continue; 1635 1636 SYSCTL_ADD_PROC(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, 1637 atse_rx_err_stats_regs[i].name, CTLTYPE_UINT|CTLFLAG_RD, 1638 sc, i, sysctl_atse_rx_err_stats_proc, "IU", 1639 atse_rx_err_stats_regs[i].descr); 1640 } 1641} 1642 1643/* 1644 * Generic device handling routines. 1645 */ 1646int 1647atse_attach(device_t dev) 1648{ 1649 struct atse_softc *sc; 1650 struct ifnet *ifp; 1651 int error; 1652 1653 sc = device_get_softc(dev); 1654 1655 atse_ethernet_option_bits_read(dev); 1656 1657 mtx_init(&sc->atse_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1658 MTX_DEF); 1659 1660 callout_init_mtx(&sc->atse_tick, &sc->atse_mtx, 0); 1661 1662 sc->atse_tx_buf = malloc(ETHER_MAX_LEN_JUMBO, M_DEVBUF, M_WAITOK); 1663 1664 /* 1665 * We are only doing single-PHY with this driver currently. The 1666 * defaults would be right so that BASE_CFG_MDIO_ADDR0 points to the 1667 * 1st PHY address (0) apart from the fact that BMCR0 is always 1668 * the PCS mapping, so we always use BMCR1. See Table 5-1 0xA0-0xBF. 1669 */ 1670#if 0 /* Always PCS. */ 1671 sc->atse_bmcr0 = MDIO_0_START; 1672 CSR_WRITE_4(sc, BASE_CFG_MDIO_ADDR0, 0x00); 1673#endif 1674 /* Always use matching PHY for atse[0..]. */ 1675 sc->atse_phy_addr = device_get_unit(dev); 1676 sc->atse_bmcr1 = MDIO_1_START; 1677 CSR_WRITE_4(sc, BASE_CFG_MDIO_ADDR1, sc->atse_phy_addr); 1678 1679 /* Reset the adapter. */ 1680 atse_reset(sc); 1681 1682 /* Setup interface. */ 1683 ifp = sc->atse_ifp = if_alloc(IFT_ETHER); 1684 if (ifp == NULL) { 1685 device_printf(dev, "if_alloc() failed\n"); 1686 error = ENOSPC; 1687 goto err; 1688 } 1689 ifp->if_softc = sc; 1690 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1691 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1692 ifp->if_ioctl = atse_ioctl; 1693 ifp->if_start = atse_start; 1694 ifp->if_init = atse_init; 1695 IFQ_SET_MAXLEN(&ifp->if_snd, ATSE_TX_LIST_CNT - 1); 1696 ifp->if_snd.ifq_drv_maxlen = ATSE_TX_LIST_CNT - 1; 1697 IFQ_SET_READY(&ifp->if_snd); 1698 1699 /* MII setup. */ 1700 error = mii_attach(dev, &sc->atse_miibus, ifp, atse_ifmedia_upd, 1701 atse_ifmedia_sts, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 1702 if (error != 0) { 1703 device_printf(dev, "attaching PHY failed: %d\n", error); 1704 goto err; 1705 } 1706 1707 /* Call media-indepedent attach routine. */ 1708 ether_ifattach(ifp, sc->atse_eth_addr); 1709 1710 /* Tell the upper layer(s) about vlan mtu support. */ 1711 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1712 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1713 ifp->if_capenable = ifp->if_capabilities; 1714#ifdef DEVICE_POLLING 1715 /* We will enable polling by default if no irqs available. See below. */ 1716 ifp->if_capabilities |= IFCAP_POLLING; 1717#endif 1718 1719 /* Hook up interrupts. */ 1720 if (sc->atse_rx_irq_res != NULL) { 1721 error = bus_setup_intr(dev, sc->atse_rx_irq_res, INTR_TYPE_NET | 1722 INTR_MPSAFE, NULL, atse_intr, sc, &sc->atse_rx_intrhand); 1723 if (error != 0) { 1724 device_printf(dev, "enabling RX IRQ failed\n"); 1725 ether_ifdetach(ifp); 1726 goto err; 1727 } 1728 } 1729 1730 if (sc->atse_tx_irq_res != NULL) { 1731 error = bus_setup_intr(dev, sc->atse_tx_irq_res, INTR_TYPE_NET | 1732 INTR_MPSAFE, NULL, atse_intr, sc, &sc->atse_tx_intrhand); 1733 if (error != 0) { 1734 bus_teardown_intr(dev, sc->atse_rx_irq_res, 1735 sc->atse_rx_intrhand); 1736 device_printf(dev, "enabling TX IRQ failed\n"); 1737 ether_ifdetach(ifp); 1738 goto err; 1739 } 1740 } 1741 1742 if ((ifp->if_capenable & IFCAP_POLLING) != 0 || 1743 (sc->atse_rx_irq_res == NULL && sc->atse_tx_irq_res == NULL)) { 1744#ifdef DEVICE_POLLING 1745 /* If not on and no IRQs force it on. */ 1746 if (sc->atse_rx_irq_res == NULL && sc->atse_tx_irq_res == NULL){ 1747 ifp->if_capenable |= IFCAP_POLLING; 1748 device_printf(dev, "forcing to polling due to no " 1749 "interrupts\n"); 1750 } 1751 error = ether_poll_register(atse_poll, ifp); 1752 if (error != 0) 1753 goto err; 1754#else 1755 device_printf(dev, "no DEVICE_POLLING in kernel and no IRQs\n"); 1756 error = ENXIO; 1757#endif 1758 } else { 1759 ATSE_RX_INTR_ENABLE(sc); 1760 ATSE_TX_INTR_ENABLE(sc); 1761 } 1762 1763err: 1764 if (error != 0) 1765 atse_detach(dev); 1766 1767 if (error == 0) 1768 atse_sysctl_stats_attach(dev); 1769 1770 return (error); 1771} 1772 1773static int 1774atse_detach(device_t dev) 1775{ 1776 struct atse_softc *sc; 1777 struct ifnet *ifp; 1778 1779 sc = device_get_softc(dev); 1780 KASSERT(mtx_initialized(&sc->atse_mtx), ("%s: mutex not initialized", 1781 device_get_nameunit(dev))); 1782 ifp = sc->atse_ifp; 1783 1784#ifdef DEVICE_POLLING 1785 if (ifp->if_capenable & IFCAP_POLLING) 1786 ether_poll_deregister(ifp); 1787#endif 1788 1789 /* Only cleanup if attach succeeded. */ 1790 if (device_is_attached(dev)) { 1791 ATSE_LOCK(sc); 1792 atse_stop_locked(sc); 1793 ATSE_UNLOCK(sc); 1794 callout_drain(&sc->atse_tick); 1795 ether_ifdetach(ifp); 1796 } 1797 if (sc->atse_miibus != NULL) 1798 device_delete_child(dev, sc->atse_miibus); 1799 1800 if (sc->atse_tx_intrhand) 1801 bus_teardown_intr(dev, sc->atse_tx_irq_res, 1802 sc->atse_tx_intrhand); 1803 if (sc->atse_rx_intrhand) 1804 bus_teardown_intr(dev, sc->atse_rx_irq_res, 1805 sc->atse_rx_intrhand); 1806 1807 if (ifp != NULL) 1808 if_free(ifp); 1809 1810 if (sc->atse_tx_buf != NULL) 1811 free(sc->atse_tx_buf, M_DEVBUF); 1812 1813 mtx_destroy(&sc->atse_mtx); 1814 1815 return (0); 1816} 1817 1818/* Shared between nexus anf fdt implementation. */ 1819void 1820atse_detach_resources(device_t dev) 1821{ 1822 struct atse_softc *sc; 1823 1824 sc = device_get_softc(dev); 1825 1826 if (sc->atse_txc_mem_res != NULL) { 1827 bus_release_resource(dev, SYS_RES_MEMORY, sc->atse_txc_mem_rid, 1828 sc->atse_txc_mem_res); 1829 sc->atse_txc_mem_res = NULL; 1830 } 1831 if (sc->atse_tx_mem_res != NULL) { 1832 bus_release_resource(dev, SYS_RES_MEMORY, sc->atse_tx_mem_rid, 1833 sc->atse_tx_mem_res); 1834 sc->atse_tx_mem_res = NULL; 1835 } 1836 if (sc->atse_tx_irq_res != NULL) { 1837 bus_release_resource(dev, SYS_RES_IRQ, sc->atse_tx_irq_rid, 1838 sc->atse_tx_irq_res); 1839 sc->atse_tx_irq_res = NULL; 1840 } 1841 if (sc->atse_rxc_mem_res != NULL) { 1842 bus_release_resource(dev, SYS_RES_MEMORY, sc->atse_rxc_mem_rid, 1843 sc->atse_rxc_mem_res); 1844 sc->atse_rxc_mem_res = NULL; 1845 } 1846 if (sc->atse_rx_mem_res != NULL) { 1847 bus_release_resource(dev, SYS_RES_MEMORY, sc->atse_rx_mem_rid, 1848 sc->atse_rx_mem_res); 1849 sc->atse_rx_mem_res = NULL; 1850 } 1851 if (sc->atse_rx_irq_res != NULL) { 1852 bus_release_resource(dev, SYS_RES_IRQ, sc->atse_rx_irq_rid, 1853 sc->atse_rx_irq_res); 1854 sc->atse_rx_irq_res = NULL; 1855 } 1856 if (sc->atse_mem_res != NULL) { 1857 bus_release_resource(dev, SYS_RES_MEMORY, sc->atse_mem_rid, 1858 sc->atse_mem_res); 1859 sc->atse_mem_res = NULL; 1860 } 1861} 1862 1863int 1864atse_detach_dev(device_t dev) 1865{ 1866 int error; 1867 1868 error = atse_detach(dev); 1869 if (error) { 1870 /* We are basically in undefined state now. */ 1871 device_printf(dev, "atse_detach() failed: %d\n", error); 1872 return (error); 1873 } 1874 1875 atse_detach_resources(dev); 1876 1877 return (0); 1878} 1879 1880int 1881atse_miibus_readreg(device_t dev, int phy, int reg) 1882{ 1883 struct atse_softc *sc; 1884 1885 sc = device_get_softc(dev); 1886 1887 /* 1888 * We currently do not support re-mapping of MDIO space on-the-fly 1889 * but de-facto hard-code the phy#. 1890 */ 1891 if (phy != sc->atse_phy_addr) 1892 return (0); 1893 1894 return (PHY_READ_2(sc, reg)); 1895} 1896 1897int 1898atse_miibus_writereg(device_t dev, int phy, int reg, int data) 1899{ 1900 struct atse_softc *sc; 1901 1902 sc = device_get_softc(dev); 1903 1904 /* 1905 * We currently do not support re-mapping of MDIO space on-the-fly 1906 * but de-facto hard-code the phy#. 1907 */ 1908 if (phy != sc->atse_phy_addr) 1909 return (0); 1910 1911 PHY_WRITE_2(sc, reg, data); 1912 return (0); 1913} 1914 1915void 1916atse_miibus_statchg(device_t dev) 1917{ 1918 struct atse_softc *sc; 1919 struct mii_data *mii; 1920 struct ifnet *ifp; 1921 uint32_t val4; 1922 1923 sc = device_get_softc(dev); 1924 ATSE_LOCK_ASSERT(sc); 1925 1926 mii = device_get_softc(sc->atse_miibus); 1927 ifp = sc->atse_ifp; 1928 if (mii == NULL || ifp == NULL || 1929 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1930 return; 1931 1932 val4 = CSR_READ_4(sc, BASE_CFG_COMMAND_CONFIG); 1933 1934 /* Assume no link. */ 1935 sc->atse_flags &= ~ATSE_FLAGS_LINK; 1936 1937 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1938 (IFM_ACTIVE | IFM_AVALID)) { 1939 1940 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1941 case IFM_10_T: 1942 val4 |= BASE_CFG_COMMAND_CONFIG_ENA_10; 1943 val4 &= ~BASE_CFG_COMMAND_CONFIG_ETH_SPEED; 1944 sc->atse_flags |= ATSE_FLAGS_LINK; 1945 break; 1946 case IFM_100_TX: 1947 val4 &= ~BASE_CFG_COMMAND_CONFIG_ENA_10; 1948 val4 &= ~BASE_CFG_COMMAND_CONFIG_ETH_SPEED; 1949 sc->atse_flags |= ATSE_FLAGS_LINK; 1950 break; 1951 case IFM_1000_T: 1952 val4 &= ~BASE_CFG_COMMAND_CONFIG_ENA_10; 1953 val4 |= BASE_CFG_COMMAND_CONFIG_ETH_SPEED; 1954 sc->atse_flags |= ATSE_FLAGS_LINK; 1955 break; 1956 default: 1957 break; 1958 } 1959 } 1960 1961 if ((sc->atse_flags & ATSE_FLAGS_LINK) == 0) { 1962 /* XXX-BZ need to stop the MAC? */ 1963 return; 1964 } 1965 1966 if (IFM_OPTIONS(mii->mii_media_active & IFM_FDX) != 0) 1967 val4 &= ~BASE_CFG_COMMAND_CONFIG_HD_ENA; 1968 else 1969 val4 |= BASE_CFG_COMMAND_CONFIG_HD_ENA; 1970 /* XXX-BZ flow control? */ 1971 1972 /* Make sure the MAC is activated. */ 1973 val4 |= BASE_CFG_COMMAND_CONFIG_TX_ENA; 1974 val4 |= BASE_CFG_COMMAND_CONFIG_RX_ENA; 1975 1976 CSR_WRITE_4(sc, BASE_CFG_COMMAND_CONFIG, val4); 1977} 1978 1979/* end */ 1980