1/*- 2 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28/* Driver for Atheros AR813x/AR815x PCIe Ethernet. */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD$"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/bus.h> 36#include <sys/endian.h> 37#include <sys/kernel.h> 38#include <sys/lock.h> 39#include <sys/malloc.h> 40#include <sys/mbuf.h> 41#include <sys/module.h> 42#include <sys/mutex.h> 43#include <sys/rman.h> 44#include <sys/queue.h> 45#include <sys/socket.h> 46#include <sys/sockio.h> 47#include <sys/sysctl.h> 48#include <sys/taskqueue.h> 49 50#include <net/bpf.h> 51#include <net/if.h> 52#include <net/if_arp.h> 53#include <net/ethernet.h> 54#include <net/if_dl.h> 55#include <net/if_llc.h> 56#include <net/if_media.h> 57#include <net/if_types.h> 58#include <net/if_vlan_var.h> 59 60#include <netinet/in.h> 61#include <netinet/in_systm.h> 62#include <netinet/ip.h> 63#include <netinet/tcp.h> 64 65#include <dev/mii/mii.h> 66#include <dev/mii/miivar.h> 67 68#include <dev/pci/pcireg.h> 69#include <dev/pci/pcivar.h> 70 71#include <machine/bus.h> 72#include <machine/in_cksum.h> 73 74#include <dev/alc/if_alcreg.h> 75#include <dev/alc/if_alcvar.h> 76 77/* "device miibus" required. See GENERIC if you get errors here. */ 78#include "miibus_if.h" 79#undef ALC_USE_CUSTOM_CSUM 80 81#ifdef ALC_USE_CUSTOM_CSUM 82#define ALC_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 83#else 84#define ALC_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 85#endif 86 87MODULE_DEPEND(alc, pci, 1, 1, 1); 88MODULE_DEPEND(alc, ether, 1, 1, 1); 89MODULE_DEPEND(alc, miibus, 1, 1, 1); 90 91/* Tunables. */ 92static int msi_disable = 0; 93static int msix_disable = 0; 94TUNABLE_INT("hw.alc.msi_disable", &msi_disable); 95TUNABLE_INT("hw.alc.msix_disable", &msix_disable); 96 97/* 98 * Devices supported by this driver. 99 */ 100static struct alc_ident alc_ident_table[] = { 101 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8131, 9 * 1024, 102 "Atheros AR8131 PCIe Gigabit Ethernet" }, 103 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8132, 9 * 1024, 104 "Atheros AR8132 PCIe Fast Ethernet" }, 105 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151, 6 * 1024, 106 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" }, 107 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151_V2, 6 * 1024, 108 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" }, 109 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B, 6 * 1024, 110 "Atheros AR8152 v1.1 PCIe Fast Ethernet" }, 111 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B2, 6 * 1024, 112 "Atheros AR8152 v2.0 PCIe Fast Ethernet" }, 113 { 0, 0, 0, NULL} 114}; 115 116static void alc_aspm(struct alc_softc *, int); 117static int alc_attach(device_t); 118static int alc_check_boundary(struct alc_softc *); 119static int alc_detach(device_t); 120static void alc_disable_l0s_l1(struct alc_softc *); 121static int alc_dma_alloc(struct alc_softc *); 122static void alc_dma_free(struct alc_softc *); 123static void alc_dmamap_cb(void *, bus_dma_segment_t *, int, int); 124static int alc_encap(struct alc_softc *, struct mbuf **); 125static struct alc_ident * 126 alc_find_ident(device_t); 127#ifndef __NO_STRICT_ALIGNMENT 128static struct mbuf * 129 alc_fixup_rx(struct ifnet *, struct mbuf *); 130#endif 131static void alc_get_macaddr(struct alc_softc *); 132static void alc_init(void *); 133static void alc_init_cmb(struct alc_softc *); 134static void alc_init_locked(struct alc_softc *); 135static void alc_init_rr_ring(struct alc_softc *); 136static int alc_init_rx_ring(struct alc_softc *); 137static void alc_init_smb(struct alc_softc *); 138static void alc_init_tx_ring(struct alc_softc *); 139static void alc_int_task(void *, int); 140static int alc_intr(void *); 141static int alc_ioctl(struct ifnet *, u_long, caddr_t); 142static void alc_mac_config(struct alc_softc *); 143static int alc_miibus_readreg(device_t, int, int); 144static void alc_miibus_statchg(device_t); 145static int alc_miibus_writereg(device_t, int, int, int); 146static int alc_mediachange(struct ifnet *); 147static void alc_mediastatus(struct ifnet *, struct ifmediareq *); 148static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *); 149static void alc_phy_down(struct alc_softc *); 150static void alc_phy_reset(struct alc_softc *); 151static int alc_probe(device_t); 152static void alc_reset(struct alc_softc *); 153static int alc_resume(device_t); 154static void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 155static int alc_rxintr(struct alc_softc *, int); 156static void alc_rxfilter(struct alc_softc *); 157static void alc_rxvlan(struct alc_softc *); 158static void alc_setlinkspeed(struct alc_softc *); 159static void alc_setwol(struct alc_softc *); 160static int alc_shutdown(device_t); 161static void alc_start(struct ifnet *); 162static void alc_start_locked(struct ifnet *); 163static void alc_start_queue(struct alc_softc *); 164static void alc_stats_clear(struct alc_softc *); 165static void alc_stats_update(struct alc_softc *); 166static void alc_stop(struct alc_softc *); 167static void alc_stop_mac(struct alc_softc *); 168static void alc_stop_queue(struct alc_softc *); 169static int alc_suspend(device_t); 170static void alc_sysctl_node(struct alc_softc *); 171static void alc_tick(void *); 172static void alc_txeof(struct alc_softc *); 173static void alc_watchdog(struct alc_softc *); 174static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 175static int sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS); 176static int sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS); 177 178static device_method_t alc_methods[] = { 179 /* Device interface. */ 180 DEVMETHOD(device_probe, alc_probe), 181 DEVMETHOD(device_attach, alc_attach), 182 DEVMETHOD(device_detach, alc_detach), 183 DEVMETHOD(device_shutdown, alc_shutdown), 184 DEVMETHOD(device_suspend, alc_suspend), 185 DEVMETHOD(device_resume, alc_resume), 186 187 /* MII interface. */ 188 DEVMETHOD(miibus_readreg, alc_miibus_readreg), 189 DEVMETHOD(miibus_writereg, alc_miibus_writereg), 190 DEVMETHOD(miibus_statchg, alc_miibus_statchg), 191 192 { NULL, NULL } 193}; 194 195static driver_t alc_driver = { 196 "alc", 197 alc_methods, 198 sizeof(struct alc_softc) 199}; 200 201static devclass_t alc_devclass; 202 203DRIVER_MODULE(alc, pci, alc_driver, alc_devclass, 0, 0); 204DRIVER_MODULE(miibus, alc, miibus_driver, miibus_devclass, 0, 0); 205 206static struct resource_spec alc_res_spec_mem[] = { 207 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 208 { -1, 0, 0 } 209}; 210 211static struct resource_spec alc_irq_spec_legacy[] = { 212 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 213 { -1, 0, 0 } 214}; 215 216static struct resource_spec alc_irq_spec_msi[] = { 217 { SYS_RES_IRQ, 1, RF_ACTIVE }, 218 { -1, 0, 0 } 219}; 220 221static struct resource_spec alc_irq_spec_msix[] = { 222 { SYS_RES_IRQ, 1, RF_ACTIVE }, 223 { -1, 0, 0 } 224}; 225 226static uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0 }; 227 228static int 229alc_miibus_readreg(device_t dev, int phy, int reg) 230{ 231 struct alc_softc *sc; 232 uint32_t v; 233 int i; 234 235 sc = device_get_softc(dev); 236 237 /* 238 * For AR8132 fast ethernet controller, do not report 1000baseT 239 * capability to mii(4). Even though AR8132 uses the same 240 * model/revision number of F1 gigabit PHY, the PHY has no 241 * ability to establish 1000baseT link. 242 */ 243 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && 244 reg == MII_EXTSR) 245 return (0); 246 247 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 248 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 249 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 250 DELAY(5); 251 v = CSR_READ_4(sc, ALC_MDIO); 252 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 253 break; 254 } 255 256 if (i == 0) { 257 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 258 return (0); 259 } 260 261 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 262} 263 264static int 265alc_miibus_writereg(device_t dev, int phy, int reg, int val) 266{ 267 struct alc_softc *sc; 268 uint32_t v; 269 int i; 270 271 sc = device_get_softc(dev); 272 273 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 274 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 275 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 276 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 277 DELAY(5); 278 v = CSR_READ_4(sc, ALC_MDIO); 279 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 280 break; 281 } 282 283 if (i == 0) 284 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 285 286 return (0); 287} 288 289static void 290alc_miibus_statchg(device_t dev) 291{ 292 struct alc_softc *sc; 293 struct mii_data *mii; 294 struct ifnet *ifp; 295 uint32_t reg; 296 297 sc = device_get_softc(dev); 298 299 mii = device_get_softc(sc->alc_miibus); 300 ifp = sc->alc_ifp; 301 if (mii == NULL || ifp == NULL || 302 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 303 return; 304 305 sc->alc_flags &= ~ALC_FLAG_LINK; 306 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 307 (IFM_ACTIVE | IFM_AVALID)) { 308 switch (IFM_SUBTYPE(mii->mii_media_active)) { 309 case IFM_10_T: 310 case IFM_100_TX: 311 sc->alc_flags |= ALC_FLAG_LINK; 312 break; 313 case IFM_1000_T: 314 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 315 sc->alc_flags |= ALC_FLAG_LINK; 316 break; 317 default: 318 break; 319 } 320 } 321 alc_stop_queue(sc); 322 /* Stop Rx/Tx MACs. */ 323 alc_stop_mac(sc); 324 325 /* Program MACs with resolved speed/duplex/flow-control. */ 326 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 327 alc_start_queue(sc); 328 alc_mac_config(sc); 329 /* Re-enable Tx/Rx MACs. */ 330 reg = CSR_READ_4(sc, ALC_MAC_CFG); 331 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 332 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 333 alc_aspm(sc, IFM_SUBTYPE(mii->mii_media_active)); 334 } 335} 336 337static void 338alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 339{ 340 struct alc_softc *sc; 341 struct mii_data *mii; 342 343 sc = ifp->if_softc; 344 ALC_LOCK(sc); 345 if ((ifp->if_flags & IFF_UP) == 0) { 346 ALC_UNLOCK(sc); 347 return; 348 } 349 mii = device_get_softc(sc->alc_miibus); 350 351 mii_pollstat(mii); 352 ifmr->ifm_status = mii->mii_media_status; 353 ifmr->ifm_active = mii->mii_media_active; 354 ALC_UNLOCK(sc); 355} 356 357static int 358alc_mediachange(struct ifnet *ifp) 359{ 360 struct alc_softc *sc; 361 struct mii_data *mii; 362 struct mii_softc *miisc; 363 int error; 364 365 sc = ifp->if_softc; 366 ALC_LOCK(sc); 367 mii = device_get_softc(sc->alc_miibus); 368 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 369 PHY_RESET(miisc); 370 error = mii_mediachg(mii); 371 ALC_UNLOCK(sc); 372 373 return (error); 374} 375 376static struct alc_ident * 377alc_find_ident(device_t dev) 378{ 379 struct alc_ident *ident; 380 uint16_t vendor, devid; 381 382 vendor = pci_get_vendor(dev); 383 devid = pci_get_device(dev); 384 for (ident = alc_ident_table; ident->name != NULL; ident++) { 385 if (vendor == ident->vendorid && devid == ident->deviceid) 386 return (ident); 387 } 388 389 return (NULL); 390} 391 392static int 393alc_probe(device_t dev) 394{ 395 struct alc_ident *ident; 396 397 ident = alc_find_ident(dev); 398 if (ident != NULL) { 399 device_set_desc(dev, ident->name); 400 return (BUS_PROBE_DEFAULT); 401 } 402 403 return (ENXIO); 404} 405 406static void 407alc_get_macaddr(struct alc_softc *sc) 408{ 409 uint32_t ea[2], opt; 410 uint16_t val; 411 int eeprom, i; 412 413 eeprom = 0; 414 opt = CSR_READ_4(sc, ALC_OPT_CFG); 415 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 416 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 417 /* 418 * EEPROM found, let TWSI reload EEPROM configuration. 419 * This will set ethernet address of controller. 420 */ 421 eeprom++; 422 switch (sc->alc_ident->deviceid) { 423 case DEVICEID_ATHEROS_AR8131: 424 case DEVICEID_ATHEROS_AR8132: 425 if ((opt & OPT_CFG_CLK_ENB) == 0) { 426 opt |= OPT_CFG_CLK_ENB; 427 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 428 CSR_READ_4(sc, ALC_OPT_CFG); 429 DELAY(1000); 430 } 431 break; 432 case DEVICEID_ATHEROS_AR8151: 433 case DEVICEID_ATHEROS_AR8151_V2: 434 case DEVICEID_ATHEROS_AR8152_B: 435 case DEVICEID_ATHEROS_AR8152_B2: 436 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 437 ALC_MII_DBG_ADDR, 0x00); 438 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 439 ALC_MII_DBG_DATA); 440 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 441 ALC_MII_DBG_DATA, val & 0xFF7F); 442 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 443 ALC_MII_DBG_ADDR, 0x3B); 444 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 445 ALC_MII_DBG_DATA); 446 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 447 ALC_MII_DBG_DATA, val | 0x0008); 448 DELAY(20); 449 break; 450 } 451 452 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 453 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 454 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 455 CSR_READ_4(sc, ALC_WOL_CFG); 456 457 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 458 TWSI_CFG_SW_LD_START); 459 for (i = 100; i > 0; i--) { 460 DELAY(1000); 461 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 462 TWSI_CFG_SW_LD_START) == 0) 463 break; 464 } 465 if (i == 0) 466 device_printf(sc->alc_dev, 467 "reloading EEPROM timeout!\n"); 468 } else { 469 if (bootverbose) 470 device_printf(sc->alc_dev, "EEPROM not found!\n"); 471 } 472 if (eeprom != 0) { 473 switch (sc->alc_ident->deviceid) { 474 case DEVICEID_ATHEROS_AR8131: 475 case DEVICEID_ATHEROS_AR8132: 476 if ((opt & OPT_CFG_CLK_ENB) != 0) { 477 opt &= ~OPT_CFG_CLK_ENB; 478 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 479 CSR_READ_4(sc, ALC_OPT_CFG); 480 DELAY(1000); 481 } 482 break; 483 case DEVICEID_ATHEROS_AR8151: 484 case DEVICEID_ATHEROS_AR8151_V2: 485 case DEVICEID_ATHEROS_AR8152_B: 486 case DEVICEID_ATHEROS_AR8152_B2: 487 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 488 ALC_MII_DBG_ADDR, 0x00); 489 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 490 ALC_MII_DBG_DATA); 491 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 492 ALC_MII_DBG_DATA, val | 0x0080); 493 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 494 ALC_MII_DBG_ADDR, 0x3B); 495 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 496 ALC_MII_DBG_DATA); 497 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 498 ALC_MII_DBG_DATA, val & 0xFFF7); 499 DELAY(20); 500 break; 501 } 502 } 503 504 ea[0] = CSR_READ_4(sc, ALC_PAR0); 505 ea[1] = CSR_READ_4(sc, ALC_PAR1); 506 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 507 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 508 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 509 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 510 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 511 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 512} 513 514static void 515alc_disable_l0s_l1(struct alc_softc *sc) 516{ 517 uint32_t pmcfg; 518 519 /* Another magic from vendor. */ 520 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 521 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 522 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK | 523 PM_CFG_SERDES_PD_EX_L1); 524 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 525 PM_CFG_SERDES_L1_ENB; 526 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 527} 528 529static void 530alc_phy_reset(struct alc_softc *sc) 531{ 532 uint16_t data; 533 534 /* Reset magic from Linux. */ 535 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET); 536 CSR_READ_2(sc, ALC_GPHY_CFG); 537 DELAY(10 * 1000); 538 539 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 540 GPHY_CFG_SEL_ANA_RESET); 541 CSR_READ_2(sc, ALC_GPHY_CFG); 542 DELAY(10 * 1000); 543 544 /* DSP fixup, Vendor magic. */ 545 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 546 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 547 ALC_MII_DBG_ADDR, 0x000A); 548 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 549 ALC_MII_DBG_DATA); 550 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 551 ALC_MII_DBG_DATA, data & 0xDFFF); 552 } 553 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 554 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 555 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 556 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 557 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 558 ALC_MII_DBG_ADDR, 0x003B); 559 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 560 ALC_MII_DBG_DATA); 561 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 562 ALC_MII_DBG_DATA, data & 0xFFF7); 563 DELAY(20 * 1000); 564 } 565 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151) { 566 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 567 ALC_MII_DBG_ADDR, 0x0029); 568 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 569 ALC_MII_DBG_DATA, 0x929D); 570 } 571 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 572 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132 || 573 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 574 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 575 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 576 ALC_MII_DBG_ADDR, 0x0029); 577 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 578 ALC_MII_DBG_DATA, 0xB6DD); 579 } 580 581 /* Load DSP codes, vendor magic. */ 582 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 583 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 584 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 585 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 586 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 587 ALC_MII_DBG_DATA, data); 588 589 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 590 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 591 ANA_SERDES_EN_LCKDT; 592 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 593 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 594 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 595 ALC_MII_DBG_DATA, data); 596 597 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 598 ANA_LONG_CABLE_TH_100_MASK) | 599 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 600 ANA_SHORT_CABLE_TH_100_SHIFT) | 601 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 602 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 603 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 604 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 605 ALC_MII_DBG_DATA, data); 606 607 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 608 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 609 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 610 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 611 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 612 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 613 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 614 ALC_MII_DBG_DATA, data); 615 616 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 617 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 618 ANA_OEN_125M; 619 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 620 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 621 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 622 ALC_MII_DBG_DATA, data); 623 DELAY(1000); 624 625 /* Disable hibernation. */ 626 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 627 0x0029); 628 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 629 ALC_MII_DBG_DATA); 630 data &= ~0x8000; 631 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 632 data); 633 634 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 635 0x000B); 636 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 637 ALC_MII_DBG_DATA); 638 data &= ~0x8000; 639 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 640 data); 641} 642 643static void 644alc_phy_down(struct alc_softc *sc) 645{ 646 647 switch (sc->alc_ident->deviceid) { 648 case DEVICEID_ATHEROS_AR8151: 649 case DEVICEID_ATHEROS_AR8151_V2: 650 /* 651 * GPHY power down caused more problems on AR8151 v2.0. 652 * When driver is reloaded after GPHY power down, 653 * accesses to PHY/MAC registers hung the system. Only 654 * cold boot recovered from it. I'm not sure whether 655 * AR8151 v1.0 also requires this one though. I don't 656 * have AR8151 v1.0 controller in hand. 657 * The only option left is to isolate the PHY and 658 * initiates power down the PHY which in turn saves 659 * more power when driver is unloaded. 660 */ 661 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 662 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 663 break; 664 default: 665 /* Force PHY down. */ 666 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 667 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 668 GPHY_CFG_PWDOWN_HW); 669 DELAY(1000); 670 break; 671 } 672} 673 674static void 675alc_aspm(struct alc_softc *sc, int media) 676{ 677 uint32_t pmcfg; 678 uint16_t linkcfg; 679 680 ALC_LOCK_ASSERT(sc); 681 682 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 683 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 684 (ALC_FLAG_APS | ALC_FLAG_PCIE)) 685 linkcfg = CSR_READ_2(sc, sc->alc_expcap + 686 PCIER_LINK_CTL); 687 else 688 linkcfg = 0; 689 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 690 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 691 pmcfg |= PM_CFG_MAC_ASPM_CHK; 692 pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT); 693 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 694 695 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 696 /* Disable extended sync except AR8152 B v1.0 */ 697 linkcfg &= ~PCIEM_LINK_CTL_EXTENDED_SYNC; 698 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 699 sc->alc_rev == ATHEROS_AR8152_B_V10) 700 linkcfg |= PCIEM_LINK_CTL_EXTENDED_SYNC; 701 CSR_WRITE_2(sc, sc->alc_expcap + PCIER_LINK_CTL, 702 linkcfg); 703 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 704 PM_CFG_HOTRST); 705 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 706 PM_CFG_L1_ENTRY_TIMER_SHIFT); 707 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 708 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 709 PM_CFG_PM_REQ_TIMER_SHIFT); 710 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 711 } 712 713 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 714 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 715 pmcfg |= PM_CFG_ASPM_L0S_ENB; 716 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 717 pmcfg |= PM_CFG_ASPM_L1_ENB; 718 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 719 if (sc->alc_ident->deviceid == 720 DEVICEID_ATHEROS_AR8152_B) 721 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 722 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 723 PM_CFG_SERDES_PLL_L1_ENB | 724 PM_CFG_SERDES_BUDS_RX_L1_ENB); 725 pmcfg |= PM_CFG_CLK_SWH_L1; 726 if (media == IFM_100_TX || media == IFM_1000_T) { 727 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 728 switch (sc->alc_ident->deviceid) { 729 case DEVICEID_ATHEROS_AR8152_B: 730 pmcfg |= (7 << 731 PM_CFG_L1_ENTRY_TIMER_SHIFT); 732 break; 733 case DEVICEID_ATHEROS_AR8152_B2: 734 case DEVICEID_ATHEROS_AR8151_V2: 735 pmcfg |= (4 << 736 PM_CFG_L1_ENTRY_TIMER_SHIFT); 737 break; 738 default: 739 pmcfg |= (15 << 740 PM_CFG_L1_ENTRY_TIMER_SHIFT); 741 break; 742 } 743 } 744 } else { 745 pmcfg |= PM_CFG_SERDES_L1_ENB | 746 PM_CFG_SERDES_PLL_L1_ENB | 747 PM_CFG_SERDES_BUDS_RX_L1_ENB; 748 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 749 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 750 } 751 } else { 752 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 753 PM_CFG_SERDES_PLL_L1_ENB); 754 pmcfg |= PM_CFG_CLK_SWH_L1; 755 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 756 pmcfg |= PM_CFG_ASPM_L1_ENB; 757 } 758 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 759} 760 761static int 762alc_attach(device_t dev) 763{ 764 struct alc_softc *sc; 765 struct ifnet *ifp; 766 char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 767 uint16_t burst; 768 int base, error, i, msic, msixc, state; 769 uint32_t cap, ctl, val; 770 771 error = 0; 772 sc = device_get_softc(dev); 773 sc->alc_dev = dev; 774 775 mtx_init(&sc->alc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 776 MTX_DEF); 777 callout_init_mtx(&sc->alc_tick_ch, &sc->alc_mtx, 0); 778 TASK_INIT(&sc->alc_int_task, 0, alc_int_task, sc); 779 sc->alc_ident = alc_find_ident(dev); 780 781 /* Map the device. */ 782 pci_enable_busmaster(dev); 783 sc->alc_res_spec = alc_res_spec_mem; 784 sc->alc_irq_spec = alc_irq_spec_legacy; 785 error = bus_alloc_resources(dev, sc->alc_res_spec, sc->alc_res); 786 if (error != 0) { 787 device_printf(dev, "cannot allocate memory resources.\n"); 788 goto fail; 789 } 790 791 /* Set PHY address. */ 792 sc->alc_phyaddr = ALC_PHY_ADDR; 793 794 /* Initialize DMA parameters. */ 795 sc->alc_dma_rd_burst = 0; 796 sc->alc_dma_wr_burst = 0; 797 sc->alc_rcb = DMA_CFG_RCB_64; 798 if (pci_find_cap(dev, PCIY_EXPRESS, &base) == 0) { 799 sc->alc_flags |= ALC_FLAG_PCIE; 800 sc->alc_expcap = base; 801 burst = CSR_READ_2(sc, base + PCIER_DEVICE_CTL); 802 sc->alc_dma_rd_burst = 803 (burst & PCIEM_CTL_MAX_READ_REQUEST) >> 12; 804 sc->alc_dma_wr_burst = (burst & PCIEM_CTL_MAX_PAYLOAD) >> 5; 805 if (bootverbose) { 806 device_printf(dev, "Read request size : %u bytes.\n", 807 alc_dma_burst[sc->alc_dma_rd_burst]); 808 device_printf(dev, "TLP payload size : %u bytes.\n", 809 alc_dma_burst[sc->alc_dma_wr_burst]); 810 } 811 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) 812 sc->alc_dma_rd_burst = 3; 813 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) 814 sc->alc_dma_wr_burst = 3; 815 /* Clear data link and flow-control protocol error. */ 816 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 817 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 818 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 819 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 820 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 821 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 822 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 823 PCIE_PHYMISC_FORCE_RCV_DET); 824 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 825 pci_get_revid(dev) == ATHEROS_AR8152_B_V10) { 826 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 827 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 828 PCIE_PHYMISC2_SERDES_TH_MASK); 829 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 830 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 831 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 832 } 833 /* Disable ASPM L0S and L1. */ 834 cap = CSR_READ_2(sc, base + PCIER_LINK_CAP); 835 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { 836 ctl = CSR_READ_2(sc, base + PCIER_LINK_CTL); 837 if ((ctl & PCIEM_LINK_CTL_RCB) != 0) 838 sc->alc_rcb = DMA_CFG_RCB_128; 839 if (bootverbose) 840 device_printf(dev, "RCB %u bytes\n", 841 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 842 state = ctl & PCIEM_LINK_CTL_ASPMC; 843 if (state & PCIEM_LINK_CTL_ASPMC_L0S) 844 sc->alc_flags |= ALC_FLAG_L0S; 845 if (state & PCIEM_LINK_CTL_ASPMC_L1) 846 sc->alc_flags |= ALC_FLAG_L1S; 847 if (bootverbose) 848 device_printf(sc->alc_dev, "ASPM %s %s\n", 849 aspm_state[state], 850 state == 0 ? "disabled" : "enabled"); 851 alc_disable_l0s_l1(sc); 852 } else { 853 if (bootverbose) 854 device_printf(sc->alc_dev, 855 "no ASPM support\n"); 856 } 857 } 858 859 /* Reset PHY. */ 860 alc_phy_reset(sc); 861 862 /* Reset the ethernet controller. */ 863 alc_reset(sc); 864 865 /* 866 * One odd thing is AR8132 uses the same PHY hardware(F1 867 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 868 * the PHY supports 1000Mbps but that's not true. The PHY 869 * used in AR8132 can't establish gigabit link even if it 870 * shows the same PHY model/revision number of AR8131. 871 */ 872 switch (sc->alc_ident->deviceid) { 873 case DEVICEID_ATHEROS_AR8152_B: 874 case DEVICEID_ATHEROS_AR8152_B2: 875 sc->alc_flags |= ALC_FLAG_APS; 876 /* FALLTHROUGH */ 877 case DEVICEID_ATHEROS_AR8132: 878 sc->alc_flags |= ALC_FLAG_FASTETHER; 879 break; 880 case DEVICEID_ATHEROS_AR8151: 881 case DEVICEID_ATHEROS_AR8151_V2: 882 sc->alc_flags |= ALC_FLAG_APS; 883 /* FALLTHROUGH */ 884 default: 885 break; 886 } 887 sc->alc_flags |= ALC_FLAG_ASPM_MON | ALC_FLAG_JUMBO; 888 889 /* 890 * It seems that AR813x/AR815x has silicon bug for SMB. In 891 * addition, Atheros said that enabling SMB wouldn't improve 892 * performance. However I think it's bad to access lots of 893 * registers to extract MAC statistics. 894 */ 895 sc->alc_flags |= ALC_FLAG_SMB_BUG; 896 /* 897 * Don't use Tx CMB. It is known to have silicon bug. 898 */ 899 sc->alc_flags |= ALC_FLAG_CMB_BUG; 900 sc->alc_rev = pci_get_revid(dev); 901 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 902 MASTER_CHIP_REV_SHIFT; 903 if (bootverbose) { 904 device_printf(dev, "PCI device revision : 0x%04x\n", 905 sc->alc_rev); 906 device_printf(dev, "Chip id/revision : 0x%04x\n", 907 sc->alc_chip_rev); 908 } 909 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", 910 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 911 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 912 913 /* Allocate IRQ resources. */ 914 msixc = pci_msix_count(dev); 915 msic = pci_msi_count(dev); 916 if (bootverbose) { 917 device_printf(dev, "MSIX count : %d\n", msixc); 918 device_printf(dev, "MSI count : %d\n", msic); 919 } 920 /* Prefer MSIX over MSI. */ 921 if (msix_disable == 0 || msi_disable == 0) { 922 if (msix_disable == 0 && msixc == ALC_MSIX_MESSAGES && 923 pci_alloc_msix(dev, &msixc) == 0) { 924 if (msic == ALC_MSIX_MESSAGES) { 925 device_printf(dev, 926 "Using %d MSIX message(s).\n", msixc); 927 sc->alc_flags |= ALC_FLAG_MSIX; 928 sc->alc_irq_spec = alc_irq_spec_msix; 929 } else 930 pci_release_msi(dev); 931 } 932 if (msi_disable == 0 && (sc->alc_flags & ALC_FLAG_MSIX) == 0 && 933 msic == ALC_MSI_MESSAGES && 934 pci_alloc_msi(dev, &msic) == 0) { 935 if (msic == ALC_MSI_MESSAGES) { 936 device_printf(dev, 937 "Using %d MSI message(s).\n", msic); 938 sc->alc_flags |= ALC_FLAG_MSI; 939 sc->alc_irq_spec = alc_irq_spec_msi; 940 } else 941 pci_release_msi(dev); 942 } 943 } 944 945 error = bus_alloc_resources(dev, sc->alc_irq_spec, sc->alc_irq); 946 if (error != 0) { 947 device_printf(dev, "cannot allocate IRQ resources.\n"); 948 goto fail; 949 } 950 951 /* Create device sysctl node. */ 952 alc_sysctl_node(sc); 953 954 if ((error = alc_dma_alloc(sc) != 0)) 955 goto fail; 956 957 /* Load station address. */ 958 alc_get_macaddr(sc); 959 960 ifp = sc->alc_ifp = if_alloc(IFT_ETHER); 961 if (ifp == NULL) { 962 device_printf(dev, "cannot allocate ifnet structure.\n"); 963 error = ENXIO; 964 goto fail; 965 } 966 967 ifp->if_softc = sc; 968 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 969 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 970 ifp->if_ioctl = alc_ioctl; 971 ifp->if_start = alc_start; 972 ifp->if_init = alc_init; 973 ifp->if_snd.ifq_drv_maxlen = ALC_TX_RING_CNT - 1; 974 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 975 IFQ_SET_READY(&ifp->if_snd); 976 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4; 977 ifp->if_hwassist = ALC_CSUM_FEATURES | CSUM_TSO; 978 if (pci_find_cap(dev, PCIY_PMG, &base) == 0) { 979 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 980 sc->alc_flags |= ALC_FLAG_PM; 981 sc->alc_pmcap = base; 982 } 983 ifp->if_capenable = ifp->if_capabilities; 984 985 /* Set up MII bus. */ 986 error = mii_attach(dev, &sc->alc_miibus, ifp, alc_mediachange, 987 alc_mediastatus, BMSR_DEFCAPMASK, sc->alc_phyaddr, MII_OFFSET_ANY, 988 MIIF_DOPAUSE); 989 if (error != 0) { 990 device_printf(dev, "attaching PHYs failed\n"); 991 goto fail; 992 } 993 994 ether_ifattach(ifp, sc->alc_eaddr); 995 996 /* VLAN capability setup. */ 997 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 998 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 999 ifp->if_capenable = ifp->if_capabilities; 1000 /* 1001 * XXX 1002 * It seems enabling Tx checksum offloading makes more trouble. 1003 * Sometimes the controller does not receive any frames when 1004 * Tx checksum offloading is enabled. I'm not sure whether this 1005 * is a bug in Tx checksum offloading logic or I got broken 1006 * sample boards. To safety, don't enable Tx checksum offloading 1007 * by default but give chance to users to toggle it if they know 1008 * their controllers work without problems. 1009 */ 1010 ifp->if_capenable &= ~IFCAP_TXCSUM; 1011 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 1012 1013 /* Tell the upper layer(s) we support long frames. */ 1014 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1015 1016 /* Create local taskq. */ 1017 sc->alc_tq = taskqueue_create_fast("alc_taskq", M_WAITOK, 1018 taskqueue_thread_enqueue, &sc->alc_tq); 1019 if (sc->alc_tq == NULL) { 1020 device_printf(dev, "could not create taskqueue.\n"); 1021 ether_ifdetach(ifp); 1022 error = ENXIO; 1023 goto fail; 1024 } 1025 taskqueue_start_threads(&sc->alc_tq, 1, PI_NET, "%s taskq", 1026 device_get_nameunit(sc->alc_dev)); 1027 1028 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1029 msic = ALC_MSIX_MESSAGES; 1030 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1031 msic = ALC_MSI_MESSAGES; 1032 else 1033 msic = 1; 1034 for (i = 0; i < msic; i++) { 1035 error = bus_setup_intr(dev, sc->alc_irq[i], 1036 INTR_TYPE_NET | INTR_MPSAFE, alc_intr, NULL, sc, 1037 &sc->alc_intrhand[i]); 1038 if (error != 0) 1039 break; 1040 } 1041 if (error != 0) { 1042 device_printf(dev, "could not set up interrupt handler.\n"); 1043 taskqueue_free(sc->alc_tq); 1044 sc->alc_tq = NULL; 1045 ether_ifdetach(ifp); 1046 goto fail; 1047 } 1048 1049fail: 1050 if (error != 0) 1051 alc_detach(dev); 1052 1053 return (error); 1054} 1055 1056static int 1057alc_detach(device_t dev) 1058{ 1059 struct alc_softc *sc; 1060 struct ifnet *ifp; 1061 int i, msic; 1062 1063 sc = device_get_softc(dev); 1064 1065 ifp = sc->alc_ifp; 1066 if (device_is_attached(dev)) { 1067 ether_ifdetach(ifp); 1068 ALC_LOCK(sc); 1069 alc_stop(sc); 1070 ALC_UNLOCK(sc); 1071 callout_drain(&sc->alc_tick_ch); 1072 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1073 } 1074 1075 if (sc->alc_tq != NULL) { 1076 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1077 taskqueue_free(sc->alc_tq); 1078 sc->alc_tq = NULL; 1079 } 1080 1081 if (sc->alc_miibus != NULL) { 1082 device_delete_child(dev, sc->alc_miibus); 1083 sc->alc_miibus = NULL; 1084 } 1085 bus_generic_detach(dev); 1086 alc_dma_free(sc); 1087 1088 if (ifp != NULL) { 1089 if_free(ifp); 1090 sc->alc_ifp = NULL; 1091 } 1092 1093 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1094 msic = ALC_MSIX_MESSAGES; 1095 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1096 msic = ALC_MSI_MESSAGES; 1097 else 1098 msic = 1; 1099 for (i = 0; i < msic; i++) { 1100 if (sc->alc_intrhand[i] != NULL) { 1101 bus_teardown_intr(dev, sc->alc_irq[i], 1102 sc->alc_intrhand[i]); 1103 sc->alc_intrhand[i] = NULL; 1104 } 1105 } 1106 if (sc->alc_res[0] != NULL) 1107 alc_phy_down(sc); 1108 bus_release_resources(dev, sc->alc_irq_spec, sc->alc_irq); 1109 if ((sc->alc_flags & (ALC_FLAG_MSI | ALC_FLAG_MSIX)) != 0) 1110 pci_release_msi(dev); 1111 bus_release_resources(dev, sc->alc_res_spec, sc->alc_res); 1112 mtx_destroy(&sc->alc_mtx); 1113 1114 return (0); 1115} 1116 1117#define ALC_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 1118 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 1119#define ALC_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 1120 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 1121 1122static void 1123alc_sysctl_node(struct alc_softc *sc) 1124{ 1125 struct sysctl_ctx_list *ctx; 1126 struct sysctl_oid_list *child, *parent; 1127 struct sysctl_oid *tree; 1128 struct alc_hw_stats *stats; 1129 int error; 1130 1131 stats = &sc->alc_stats; 1132 ctx = device_get_sysctl_ctx(sc->alc_dev); 1133 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->alc_dev)); 1134 1135 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 1136 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_rx_mod, 0, 1137 sysctl_hw_alc_int_mod, "I", "alc Rx interrupt moderation"); 1138 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 1139 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_tx_mod, 0, 1140 sysctl_hw_alc_int_mod, "I", "alc Tx interrupt moderation"); 1141 /* Pull in device tunables. */ 1142 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1143 error = resource_int_value(device_get_name(sc->alc_dev), 1144 device_get_unit(sc->alc_dev), "int_rx_mod", &sc->alc_int_rx_mod); 1145 if (error == 0) { 1146 if (sc->alc_int_rx_mod < ALC_IM_TIMER_MIN || 1147 sc->alc_int_rx_mod > ALC_IM_TIMER_MAX) { 1148 device_printf(sc->alc_dev, "int_rx_mod value out of " 1149 "range; using default: %d\n", 1150 ALC_IM_RX_TIMER_DEFAULT); 1151 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1152 } 1153 } 1154 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1155 error = resource_int_value(device_get_name(sc->alc_dev), 1156 device_get_unit(sc->alc_dev), "int_tx_mod", &sc->alc_int_tx_mod); 1157 if (error == 0) { 1158 if (sc->alc_int_tx_mod < ALC_IM_TIMER_MIN || 1159 sc->alc_int_tx_mod > ALC_IM_TIMER_MAX) { 1160 device_printf(sc->alc_dev, "int_tx_mod value out of " 1161 "range; using default: %d\n", 1162 ALC_IM_TX_TIMER_DEFAULT); 1163 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1164 } 1165 } 1166 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 1167 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_process_limit, 0, 1168 sysctl_hw_alc_proc_limit, "I", 1169 "max number of Rx events to process"); 1170 /* Pull in device tunables. */ 1171 sc->alc_process_limit = ALC_PROC_DEFAULT; 1172 error = resource_int_value(device_get_name(sc->alc_dev), 1173 device_get_unit(sc->alc_dev), "process_limit", 1174 &sc->alc_process_limit); 1175 if (error == 0) { 1176 if (sc->alc_process_limit < ALC_PROC_MIN || 1177 sc->alc_process_limit > ALC_PROC_MAX) { 1178 device_printf(sc->alc_dev, 1179 "process_limit value out of range; " 1180 "using default: %d\n", ALC_PROC_DEFAULT); 1181 sc->alc_process_limit = ALC_PROC_DEFAULT; 1182 } 1183 } 1184 1185 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 1186 NULL, "ALC statistics"); 1187 parent = SYSCTL_CHILDREN(tree); 1188 1189 /* Rx statistics. */ 1190 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 1191 NULL, "Rx MAC statistics"); 1192 child = SYSCTL_CHILDREN(tree); 1193 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1194 &stats->rx_frames, "Good frames"); 1195 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1196 &stats->rx_bcast_frames, "Good broadcast frames"); 1197 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1198 &stats->rx_mcast_frames, "Good multicast frames"); 1199 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1200 &stats->rx_pause_frames, "Pause control frames"); 1201 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1202 &stats->rx_control_frames, "Control frames"); 1203 ALC_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 1204 &stats->rx_crcerrs, "CRC errors"); 1205 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1206 &stats->rx_lenerrs, "Frames with length mismatched"); 1207 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1208 &stats->rx_bytes, "Good octets"); 1209 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1210 &stats->rx_bcast_bytes, "Good broadcast octets"); 1211 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1212 &stats->rx_mcast_bytes, "Good multicast octets"); 1213 ALC_SYSCTL_STAT_ADD32(ctx, child, "runts", 1214 &stats->rx_runts, "Too short frames"); 1215 ALC_SYSCTL_STAT_ADD32(ctx, child, "fragments", 1216 &stats->rx_fragments, "Fragmented frames"); 1217 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1218 &stats->rx_pkts_64, "64 bytes frames"); 1219 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1220 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 1221 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1222 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 1223 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1224 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 1225 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1226 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 1227 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1228 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1229 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1230 &stats->rx_pkts_1519_max, "1519 to max frames"); 1231 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1232 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 1233 ALC_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 1234 &stats->rx_fifo_oflows, "FIFO overflows"); 1235 ALC_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 1236 &stats->rx_rrs_errs, "Return status write-back errors"); 1237 ALC_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 1238 &stats->rx_alignerrs, "Alignment errors"); 1239 ALC_SYSCTL_STAT_ADD32(ctx, child, "filtered", 1240 &stats->rx_pkts_filtered, 1241 "Frames dropped due to address filtering"); 1242 1243 /* Tx statistics. */ 1244 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 1245 NULL, "Tx MAC statistics"); 1246 child = SYSCTL_CHILDREN(tree); 1247 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1248 &stats->tx_frames, "Good frames"); 1249 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1250 &stats->tx_bcast_frames, "Good broadcast frames"); 1251 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1252 &stats->tx_mcast_frames, "Good multicast frames"); 1253 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1254 &stats->tx_pause_frames, "Pause control frames"); 1255 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1256 &stats->tx_control_frames, "Control frames"); 1257 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 1258 &stats->tx_excess_defer, "Frames with excessive derferrals"); 1259 ALC_SYSCTL_STAT_ADD32(ctx, child, "defers", 1260 &stats->tx_excess_defer, "Frames with derferrals"); 1261 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1262 &stats->tx_bytes, "Good octets"); 1263 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1264 &stats->tx_bcast_bytes, "Good broadcast octets"); 1265 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1266 &stats->tx_mcast_bytes, "Good multicast octets"); 1267 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1268 &stats->tx_pkts_64, "64 bytes frames"); 1269 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1270 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 1271 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1272 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 1273 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1274 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 1275 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1276 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 1277 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1278 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1279 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1280 &stats->tx_pkts_1519_max, "1519 to max frames"); 1281 ALC_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 1282 &stats->tx_single_colls, "Single collisions"); 1283 ALC_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 1284 &stats->tx_multi_colls, "Multiple collisions"); 1285 ALC_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 1286 &stats->tx_late_colls, "Late collisions"); 1287 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 1288 &stats->tx_excess_colls, "Excessive collisions"); 1289 ALC_SYSCTL_STAT_ADD32(ctx, child, "abort", 1290 &stats->tx_abort, "Aborted frames due to Excessive collisions"); 1291 ALC_SYSCTL_STAT_ADD32(ctx, child, "underruns", 1292 &stats->tx_underrun, "FIFO underruns"); 1293 ALC_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 1294 &stats->tx_desc_underrun, "Descriptor write-back errors"); 1295 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1296 &stats->tx_lenerrs, "Frames with length mismatched"); 1297 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1298 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 1299} 1300 1301#undef ALC_SYSCTL_STAT_ADD32 1302#undef ALC_SYSCTL_STAT_ADD64 1303 1304struct alc_dmamap_arg { 1305 bus_addr_t alc_busaddr; 1306}; 1307 1308static void 1309alc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1310{ 1311 struct alc_dmamap_arg *ctx; 1312 1313 if (error != 0) 1314 return; 1315 1316 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1317 1318 ctx = (struct alc_dmamap_arg *)arg; 1319 ctx->alc_busaddr = segs[0].ds_addr; 1320} 1321 1322/* 1323 * Normal and high Tx descriptors shares single Tx high address. 1324 * Four Rx descriptor/return rings and CMB shares the same Rx 1325 * high address. 1326 */ 1327static int 1328alc_check_boundary(struct alc_softc *sc) 1329{ 1330 bus_addr_t cmb_end, rx_ring_end, rr_ring_end, tx_ring_end; 1331 1332 rx_ring_end = sc->alc_rdata.alc_rx_ring_paddr + ALC_RX_RING_SZ; 1333 rr_ring_end = sc->alc_rdata.alc_rr_ring_paddr + ALC_RR_RING_SZ; 1334 cmb_end = sc->alc_rdata.alc_cmb_paddr + ALC_CMB_SZ; 1335 tx_ring_end = sc->alc_rdata.alc_tx_ring_paddr + ALC_TX_RING_SZ; 1336 1337 /* 4GB boundary crossing is not allowed. */ 1338 if ((ALC_ADDR_HI(rx_ring_end) != 1339 ALC_ADDR_HI(sc->alc_rdata.alc_rx_ring_paddr)) || 1340 (ALC_ADDR_HI(rr_ring_end) != 1341 ALC_ADDR_HI(sc->alc_rdata.alc_rr_ring_paddr)) || 1342 (ALC_ADDR_HI(cmb_end) != 1343 ALC_ADDR_HI(sc->alc_rdata.alc_cmb_paddr)) || 1344 (ALC_ADDR_HI(tx_ring_end) != 1345 ALC_ADDR_HI(sc->alc_rdata.alc_tx_ring_paddr))) 1346 return (EFBIG); 1347 /* 1348 * Make sure Rx return descriptor/Rx descriptor/CMB use 1349 * the same high address. 1350 */ 1351 if ((ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(rr_ring_end)) || 1352 (ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(cmb_end))) 1353 return (EFBIG); 1354 1355 return (0); 1356} 1357 1358static int 1359alc_dma_alloc(struct alc_softc *sc) 1360{ 1361 struct alc_txdesc *txd; 1362 struct alc_rxdesc *rxd; 1363 bus_addr_t lowaddr; 1364 struct alc_dmamap_arg ctx; 1365 int error, i; 1366 1367 lowaddr = BUS_SPACE_MAXADDR; 1368again: 1369 /* Create parent DMA tag. */ 1370 error = bus_dma_tag_create( 1371 bus_get_dma_tag(sc->alc_dev), /* parent */ 1372 1, 0, /* alignment, boundary */ 1373 lowaddr, /* lowaddr */ 1374 BUS_SPACE_MAXADDR, /* highaddr */ 1375 NULL, NULL, /* filter, filterarg */ 1376 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1377 0, /* nsegments */ 1378 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1379 0, /* flags */ 1380 NULL, NULL, /* lockfunc, lockarg */ 1381 &sc->alc_cdata.alc_parent_tag); 1382 if (error != 0) { 1383 device_printf(sc->alc_dev, 1384 "could not create parent DMA tag.\n"); 1385 goto fail; 1386 } 1387 1388 /* Create DMA tag for Tx descriptor ring. */ 1389 error = bus_dma_tag_create( 1390 sc->alc_cdata.alc_parent_tag, /* parent */ 1391 ALC_TX_RING_ALIGN, 0, /* alignment, boundary */ 1392 BUS_SPACE_MAXADDR, /* lowaddr */ 1393 BUS_SPACE_MAXADDR, /* highaddr */ 1394 NULL, NULL, /* filter, filterarg */ 1395 ALC_TX_RING_SZ, /* maxsize */ 1396 1, /* nsegments */ 1397 ALC_TX_RING_SZ, /* maxsegsize */ 1398 0, /* flags */ 1399 NULL, NULL, /* lockfunc, lockarg */ 1400 &sc->alc_cdata.alc_tx_ring_tag); 1401 if (error != 0) { 1402 device_printf(sc->alc_dev, 1403 "could not create Tx ring DMA tag.\n"); 1404 goto fail; 1405 } 1406 1407 /* Create DMA tag for Rx free descriptor ring. */ 1408 error = bus_dma_tag_create( 1409 sc->alc_cdata.alc_parent_tag, /* parent */ 1410 ALC_RX_RING_ALIGN, 0, /* alignment, boundary */ 1411 BUS_SPACE_MAXADDR, /* lowaddr */ 1412 BUS_SPACE_MAXADDR, /* highaddr */ 1413 NULL, NULL, /* filter, filterarg */ 1414 ALC_RX_RING_SZ, /* maxsize */ 1415 1, /* nsegments */ 1416 ALC_RX_RING_SZ, /* maxsegsize */ 1417 0, /* flags */ 1418 NULL, NULL, /* lockfunc, lockarg */ 1419 &sc->alc_cdata.alc_rx_ring_tag); 1420 if (error != 0) { 1421 device_printf(sc->alc_dev, 1422 "could not create Rx ring DMA tag.\n"); 1423 goto fail; 1424 } 1425 /* Create DMA tag for Rx return descriptor ring. */ 1426 error = bus_dma_tag_create( 1427 sc->alc_cdata.alc_parent_tag, /* parent */ 1428 ALC_RR_RING_ALIGN, 0, /* alignment, boundary */ 1429 BUS_SPACE_MAXADDR, /* lowaddr */ 1430 BUS_SPACE_MAXADDR, /* highaddr */ 1431 NULL, NULL, /* filter, filterarg */ 1432 ALC_RR_RING_SZ, /* maxsize */ 1433 1, /* nsegments */ 1434 ALC_RR_RING_SZ, /* maxsegsize */ 1435 0, /* flags */ 1436 NULL, NULL, /* lockfunc, lockarg */ 1437 &sc->alc_cdata.alc_rr_ring_tag); 1438 if (error != 0) { 1439 device_printf(sc->alc_dev, 1440 "could not create Rx return ring DMA tag.\n"); 1441 goto fail; 1442 } 1443 1444 /* Create DMA tag for coalescing message block. */ 1445 error = bus_dma_tag_create( 1446 sc->alc_cdata.alc_parent_tag, /* parent */ 1447 ALC_CMB_ALIGN, 0, /* alignment, boundary */ 1448 BUS_SPACE_MAXADDR, /* lowaddr */ 1449 BUS_SPACE_MAXADDR, /* highaddr */ 1450 NULL, NULL, /* filter, filterarg */ 1451 ALC_CMB_SZ, /* maxsize */ 1452 1, /* nsegments */ 1453 ALC_CMB_SZ, /* maxsegsize */ 1454 0, /* flags */ 1455 NULL, NULL, /* lockfunc, lockarg */ 1456 &sc->alc_cdata.alc_cmb_tag); 1457 if (error != 0) { 1458 device_printf(sc->alc_dev, 1459 "could not create CMB DMA tag.\n"); 1460 goto fail; 1461 } 1462 /* Create DMA tag for status message block. */ 1463 error = bus_dma_tag_create( 1464 sc->alc_cdata.alc_parent_tag, /* parent */ 1465 ALC_SMB_ALIGN, 0, /* alignment, boundary */ 1466 BUS_SPACE_MAXADDR, /* lowaddr */ 1467 BUS_SPACE_MAXADDR, /* highaddr */ 1468 NULL, NULL, /* filter, filterarg */ 1469 ALC_SMB_SZ, /* maxsize */ 1470 1, /* nsegments */ 1471 ALC_SMB_SZ, /* maxsegsize */ 1472 0, /* flags */ 1473 NULL, NULL, /* lockfunc, lockarg */ 1474 &sc->alc_cdata.alc_smb_tag); 1475 if (error != 0) { 1476 device_printf(sc->alc_dev, 1477 "could not create SMB DMA tag.\n"); 1478 goto fail; 1479 } 1480 1481 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1482 error = bus_dmamem_alloc(sc->alc_cdata.alc_tx_ring_tag, 1483 (void **)&sc->alc_rdata.alc_tx_ring, 1484 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1485 &sc->alc_cdata.alc_tx_ring_map); 1486 if (error != 0) { 1487 device_printf(sc->alc_dev, 1488 "could not allocate DMA'able memory for Tx ring.\n"); 1489 goto fail; 1490 } 1491 ctx.alc_busaddr = 0; 1492 error = bus_dmamap_load(sc->alc_cdata.alc_tx_ring_tag, 1493 sc->alc_cdata.alc_tx_ring_map, sc->alc_rdata.alc_tx_ring, 1494 ALC_TX_RING_SZ, alc_dmamap_cb, &ctx, 0); 1495 if (error != 0 || ctx.alc_busaddr == 0) { 1496 device_printf(sc->alc_dev, 1497 "could not load DMA'able memory for Tx ring.\n"); 1498 goto fail; 1499 } 1500 sc->alc_rdata.alc_tx_ring_paddr = ctx.alc_busaddr; 1501 1502 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 1503 error = bus_dmamem_alloc(sc->alc_cdata.alc_rx_ring_tag, 1504 (void **)&sc->alc_rdata.alc_rx_ring, 1505 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1506 &sc->alc_cdata.alc_rx_ring_map); 1507 if (error != 0) { 1508 device_printf(sc->alc_dev, 1509 "could not allocate DMA'able memory for Rx ring.\n"); 1510 goto fail; 1511 } 1512 ctx.alc_busaddr = 0; 1513 error = bus_dmamap_load(sc->alc_cdata.alc_rx_ring_tag, 1514 sc->alc_cdata.alc_rx_ring_map, sc->alc_rdata.alc_rx_ring, 1515 ALC_RX_RING_SZ, alc_dmamap_cb, &ctx, 0); 1516 if (error != 0 || ctx.alc_busaddr == 0) { 1517 device_printf(sc->alc_dev, 1518 "could not load DMA'able memory for Rx ring.\n"); 1519 goto fail; 1520 } 1521 sc->alc_rdata.alc_rx_ring_paddr = ctx.alc_busaddr; 1522 1523 /* Allocate DMA'able memory and load the DMA map for Rx return ring. */ 1524 error = bus_dmamem_alloc(sc->alc_cdata.alc_rr_ring_tag, 1525 (void **)&sc->alc_rdata.alc_rr_ring, 1526 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1527 &sc->alc_cdata.alc_rr_ring_map); 1528 if (error != 0) { 1529 device_printf(sc->alc_dev, 1530 "could not allocate DMA'able memory for Rx return ring.\n"); 1531 goto fail; 1532 } 1533 ctx.alc_busaddr = 0; 1534 error = bus_dmamap_load(sc->alc_cdata.alc_rr_ring_tag, 1535 sc->alc_cdata.alc_rr_ring_map, sc->alc_rdata.alc_rr_ring, 1536 ALC_RR_RING_SZ, alc_dmamap_cb, &ctx, 0); 1537 if (error != 0 || ctx.alc_busaddr == 0) { 1538 device_printf(sc->alc_dev, 1539 "could not load DMA'able memory for Tx ring.\n"); 1540 goto fail; 1541 } 1542 sc->alc_rdata.alc_rr_ring_paddr = ctx.alc_busaddr; 1543 1544 /* Allocate DMA'able memory and load the DMA map for CMB. */ 1545 error = bus_dmamem_alloc(sc->alc_cdata.alc_cmb_tag, 1546 (void **)&sc->alc_rdata.alc_cmb, 1547 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1548 &sc->alc_cdata.alc_cmb_map); 1549 if (error != 0) { 1550 device_printf(sc->alc_dev, 1551 "could not allocate DMA'able memory for CMB.\n"); 1552 goto fail; 1553 } 1554 ctx.alc_busaddr = 0; 1555 error = bus_dmamap_load(sc->alc_cdata.alc_cmb_tag, 1556 sc->alc_cdata.alc_cmb_map, sc->alc_rdata.alc_cmb, 1557 ALC_CMB_SZ, alc_dmamap_cb, &ctx, 0); 1558 if (error != 0 || ctx.alc_busaddr == 0) { 1559 device_printf(sc->alc_dev, 1560 "could not load DMA'able memory for CMB.\n"); 1561 goto fail; 1562 } 1563 sc->alc_rdata.alc_cmb_paddr = ctx.alc_busaddr; 1564 1565 /* Allocate DMA'able memory and load the DMA map for SMB. */ 1566 error = bus_dmamem_alloc(sc->alc_cdata.alc_smb_tag, 1567 (void **)&sc->alc_rdata.alc_smb, 1568 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1569 &sc->alc_cdata.alc_smb_map); 1570 if (error != 0) { 1571 device_printf(sc->alc_dev, 1572 "could not allocate DMA'able memory for SMB.\n"); 1573 goto fail; 1574 } 1575 ctx.alc_busaddr = 0; 1576 error = bus_dmamap_load(sc->alc_cdata.alc_smb_tag, 1577 sc->alc_cdata.alc_smb_map, sc->alc_rdata.alc_smb, 1578 ALC_SMB_SZ, alc_dmamap_cb, &ctx, 0); 1579 if (error != 0 || ctx.alc_busaddr == 0) { 1580 device_printf(sc->alc_dev, 1581 "could not load DMA'able memory for CMB.\n"); 1582 goto fail; 1583 } 1584 sc->alc_rdata.alc_smb_paddr = ctx.alc_busaddr; 1585 1586 /* Make sure we've not crossed 4GB boundary. */ 1587 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1588 (error = alc_check_boundary(sc)) != 0) { 1589 device_printf(sc->alc_dev, "4GB boundary crossed, " 1590 "switching to 32bit DMA addressing mode.\n"); 1591 alc_dma_free(sc); 1592 /* 1593 * Limit max allowable DMA address space to 32bit 1594 * and try again. 1595 */ 1596 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1597 goto again; 1598 } 1599 1600 /* 1601 * Create Tx buffer parent tag. 1602 * AR813x/AR815x allows 64bit DMA addressing of Tx/Rx buffers 1603 * so it needs separate parent DMA tag as parent DMA address 1604 * space could be restricted to be within 32bit address space 1605 * by 4GB boundary crossing. 1606 */ 1607 error = bus_dma_tag_create( 1608 bus_get_dma_tag(sc->alc_dev), /* parent */ 1609 1, 0, /* alignment, boundary */ 1610 BUS_SPACE_MAXADDR, /* lowaddr */ 1611 BUS_SPACE_MAXADDR, /* highaddr */ 1612 NULL, NULL, /* filter, filterarg */ 1613 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1614 0, /* nsegments */ 1615 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1616 0, /* flags */ 1617 NULL, NULL, /* lockfunc, lockarg */ 1618 &sc->alc_cdata.alc_buffer_tag); 1619 if (error != 0) { 1620 device_printf(sc->alc_dev, 1621 "could not create parent buffer DMA tag.\n"); 1622 goto fail; 1623 } 1624 1625 /* Create DMA tag for Tx buffers. */ 1626 error = bus_dma_tag_create( 1627 sc->alc_cdata.alc_buffer_tag, /* parent */ 1628 1, 0, /* alignment, boundary */ 1629 BUS_SPACE_MAXADDR, /* lowaddr */ 1630 BUS_SPACE_MAXADDR, /* highaddr */ 1631 NULL, NULL, /* filter, filterarg */ 1632 ALC_TSO_MAXSIZE, /* maxsize */ 1633 ALC_MAXTXSEGS, /* nsegments */ 1634 ALC_TSO_MAXSEGSIZE, /* maxsegsize */ 1635 0, /* flags */ 1636 NULL, NULL, /* lockfunc, lockarg */ 1637 &sc->alc_cdata.alc_tx_tag); 1638 if (error != 0) { 1639 device_printf(sc->alc_dev, "could not create Tx DMA tag.\n"); 1640 goto fail; 1641 } 1642 1643 /* Create DMA tag for Rx buffers. */ 1644 error = bus_dma_tag_create( 1645 sc->alc_cdata.alc_buffer_tag, /* parent */ 1646 ALC_RX_BUF_ALIGN, 0, /* alignment, boundary */ 1647 BUS_SPACE_MAXADDR, /* lowaddr */ 1648 BUS_SPACE_MAXADDR, /* highaddr */ 1649 NULL, NULL, /* filter, filterarg */ 1650 MCLBYTES, /* maxsize */ 1651 1, /* nsegments */ 1652 MCLBYTES, /* maxsegsize */ 1653 0, /* flags */ 1654 NULL, NULL, /* lockfunc, lockarg */ 1655 &sc->alc_cdata.alc_rx_tag); 1656 if (error != 0) { 1657 device_printf(sc->alc_dev, "could not create Rx DMA tag.\n"); 1658 goto fail; 1659 } 1660 /* Create DMA maps for Tx buffers. */ 1661 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1662 txd = &sc->alc_cdata.alc_txdesc[i]; 1663 txd->tx_m = NULL; 1664 txd->tx_dmamap = NULL; 1665 error = bus_dmamap_create(sc->alc_cdata.alc_tx_tag, 0, 1666 &txd->tx_dmamap); 1667 if (error != 0) { 1668 device_printf(sc->alc_dev, 1669 "could not create Tx dmamap.\n"); 1670 goto fail; 1671 } 1672 } 1673 /* Create DMA maps for Rx buffers. */ 1674 if ((error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 1675 &sc->alc_cdata.alc_rx_sparemap)) != 0) { 1676 device_printf(sc->alc_dev, 1677 "could not create spare Rx dmamap.\n"); 1678 goto fail; 1679 } 1680 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1681 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1682 rxd->rx_m = NULL; 1683 rxd->rx_dmamap = NULL; 1684 error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 1685 &rxd->rx_dmamap); 1686 if (error != 0) { 1687 device_printf(sc->alc_dev, 1688 "could not create Rx dmamap.\n"); 1689 goto fail; 1690 } 1691 } 1692 1693fail: 1694 return (error); 1695} 1696 1697static void 1698alc_dma_free(struct alc_softc *sc) 1699{ 1700 struct alc_txdesc *txd; 1701 struct alc_rxdesc *rxd; 1702 int i; 1703 1704 /* Tx buffers. */ 1705 if (sc->alc_cdata.alc_tx_tag != NULL) { 1706 for (i = 0; i < ALC_TX_RING_CNT; i++) { 1707 txd = &sc->alc_cdata.alc_txdesc[i]; 1708 if (txd->tx_dmamap != NULL) { 1709 bus_dmamap_destroy(sc->alc_cdata.alc_tx_tag, 1710 txd->tx_dmamap); 1711 txd->tx_dmamap = NULL; 1712 } 1713 } 1714 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_tag); 1715 sc->alc_cdata.alc_tx_tag = NULL; 1716 } 1717 /* Rx buffers */ 1718 if (sc->alc_cdata.alc_rx_tag != NULL) { 1719 for (i = 0; i < ALC_RX_RING_CNT; i++) { 1720 rxd = &sc->alc_cdata.alc_rxdesc[i]; 1721 if (rxd->rx_dmamap != NULL) { 1722 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 1723 rxd->rx_dmamap); 1724 rxd->rx_dmamap = NULL; 1725 } 1726 } 1727 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 1728 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 1729 sc->alc_cdata.alc_rx_sparemap); 1730 sc->alc_cdata.alc_rx_sparemap = NULL; 1731 } 1732 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_tag); 1733 sc->alc_cdata.alc_rx_tag = NULL; 1734 } 1735 /* Tx descriptor ring. */ 1736 if (sc->alc_cdata.alc_tx_ring_tag != NULL) { 1737 if (sc->alc_cdata.alc_tx_ring_map != NULL) 1738 bus_dmamap_unload(sc->alc_cdata.alc_tx_ring_tag, 1739 sc->alc_cdata.alc_tx_ring_map); 1740 if (sc->alc_cdata.alc_tx_ring_map != NULL && 1741 sc->alc_rdata.alc_tx_ring != NULL) 1742 bus_dmamem_free(sc->alc_cdata.alc_tx_ring_tag, 1743 sc->alc_rdata.alc_tx_ring, 1744 sc->alc_cdata.alc_tx_ring_map); 1745 sc->alc_rdata.alc_tx_ring = NULL; 1746 sc->alc_cdata.alc_tx_ring_map = NULL; 1747 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_ring_tag); 1748 sc->alc_cdata.alc_tx_ring_tag = NULL; 1749 } 1750 /* Rx ring. */ 1751 if (sc->alc_cdata.alc_rx_ring_tag != NULL) { 1752 if (sc->alc_cdata.alc_rx_ring_map != NULL) 1753 bus_dmamap_unload(sc->alc_cdata.alc_rx_ring_tag, 1754 sc->alc_cdata.alc_rx_ring_map); 1755 if (sc->alc_cdata.alc_rx_ring_map != NULL && 1756 sc->alc_rdata.alc_rx_ring != NULL) 1757 bus_dmamem_free(sc->alc_cdata.alc_rx_ring_tag, 1758 sc->alc_rdata.alc_rx_ring, 1759 sc->alc_cdata.alc_rx_ring_map); 1760 sc->alc_rdata.alc_rx_ring = NULL; 1761 sc->alc_cdata.alc_rx_ring_map = NULL; 1762 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_ring_tag); 1763 sc->alc_cdata.alc_rx_ring_tag = NULL; 1764 } 1765 /* Rx return ring. */ 1766 if (sc->alc_cdata.alc_rr_ring_tag != NULL) { 1767 if (sc->alc_cdata.alc_rr_ring_map != NULL) 1768 bus_dmamap_unload(sc->alc_cdata.alc_rr_ring_tag, 1769 sc->alc_cdata.alc_rr_ring_map); 1770 if (sc->alc_cdata.alc_rr_ring_map != NULL && 1771 sc->alc_rdata.alc_rr_ring != NULL) 1772 bus_dmamem_free(sc->alc_cdata.alc_rr_ring_tag, 1773 sc->alc_rdata.alc_rr_ring, 1774 sc->alc_cdata.alc_rr_ring_map); 1775 sc->alc_rdata.alc_rr_ring = NULL; 1776 sc->alc_cdata.alc_rr_ring_map = NULL; 1777 bus_dma_tag_destroy(sc->alc_cdata.alc_rr_ring_tag); 1778 sc->alc_cdata.alc_rr_ring_tag = NULL; 1779 } 1780 /* CMB block */ 1781 if (sc->alc_cdata.alc_cmb_tag != NULL) { 1782 if (sc->alc_cdata.alc_cmb_map != NULL) 1783 bus_dmamap_unload(sc->alc_cdata.alc_cmb_tag, 1784 sc->alc_cdata.alc_cmb_map); 1785 if (sc->alc_cdata.alc_cmb_map != NULL && 1786 sc->alc_rdata.alc_cmb != NULL) 1787 bus_dmamem_free(sc->alc_cdata.alc_cmb_tag, 1788 sc->alc_rdata.alc_cmb, 1789 sc->alc_cdata.alc_cmb_map); 1790 sc->alc_rdata.alc_cmb = NULL; 1791 sc->alc_cdata.alc_cmb_map = NULL; 1792 bus_dma_tag_destroy(sc->alc_cdata.alc_cmb_tag); 1793 sc->alc_cdata.alc_cmb_tag = NULL; 1794 } 1795 /* SMB block */ 1796 if (sc->alc_cdata.alc_smb_tag != NULL) { 1797 if (sc->alc_cdata.alc_smb_map != NULL) 1798 bus_dmamap_unload(sc->alc_cdata.alc_smb_tag, 1799 sc->alc_cdata.alc_smb_map); 1800 if (sc->alc_cdata.alc_smb_map != NULL && 1801 sc->alc_rdata.alc_smb != NULL) 1802 bus_dmamem_free(sc->alc_cdata.alc_smb_tag, 1803 sc->alc_rdata.alc_smb, 1804 sc->alc_cdata.alc_smb_map); 1805 sc->alc_rdata.alc_smb = NULL; 1806 sc->alc_cdata.alc_smb_map = NULL; 1807 bus_dma_tag_destroy(sc->alc_cdata.alc_smb_tag); 1808 sc->alc_cdata.alc_smb_tag = NULL; 1809 } 1810 if (sc->alc_cdata.alc_buffer_tag != NULL) { 1811 bus_dma_tag_destroy(sc->alc_cdata.alc_buffer_tag); 1812 sc->alc_cdata.alc_buffer_tag = NULL; 1813 } 1814 if (sc->alc_cdata.alc_parent_tag != NULL) { 1815 bus_dma_tag_destroy(sc->alc_cdata.alc_parent_tag); 1816 sc->alc_cdata.alc_parent_tag = NULL; 1817 } 1818} 1819 1820static int 1821alc_shutdown(device_t dev) 1822{ 1823 1824 return (alc_suspend(dev)); 1825} 1826 1827/* 1828 * Note, this driver resets the link speed to 10/100Mbps by 1829 * restarting auto-negotiation in suspend/shutdown phase but we 1830 * don't know whether that auto-negotiation would succeed or not 1831 * as driver has no control after powering off/suspend operation. 1832 * If the renegotiation fail WOL may not work. Running at 1Gbps 1833 * will draw more power than 375mA at 3.3V which is specified in 1834 * PCI specification and that would result in complete 1835 * shutdowning power to ethernet controller. 1836 * 1837 * TODO 1838 * Save current negotiated media speed/duplex/flow-control to 1839 * softc and restore the same link again after resuming. PHY 1840 * handling such as power down/resetting to 100Mbps may be better 1841 * handled in suspend method in phy driver. 1842 */ 1843static void 1844alc_setlinkspeed(struct alc_softc *sc) 1845{ 1846 struct mii_data *mii; 1847 int aneg, i; 1848 1849 mii = device_get_softc(sc->alc_miibus); 1850 mii_pollstat(mii); 1851 aneg = 0; 1852 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1853 (IFM_ACTIVE | IFM_AVALID)) { 1854 switch IFM_SUBTYPE(mii->mii_media_active) { 1855 case IFM_10_T: 1856 case IFM_100_TX: 1857 return; 1858 case IFM_1000_T: 1859 aneg++; 1860 break; 1861 default: 1862 break; 1863 } 1864 } 1865 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, MII_100T2CR, 0); 1866 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 1867 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1868 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 1869 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1870 DELAY(1000); 1871 if (aneg != 0) { 1872 /* 1873 * Poll link state until alc(4) get a 10/100Mbps link. 1874 */ 1875 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1876 mii_pollstat(mii); 1877 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 1878 == (IFM_ACTIVE | IFM_AVALID)) { 1879 switch (IFM_SUBTYPE( 1880 mii->mii_media_active)) { 1881 case IFM_10_T: 1882 case IFM_100_TX: 1883 alc_mac_config(sc); 1884 return; 1885 default: 1886 break; 1887 } 1888 } 1889 ALC_UNLOCK(sc); 1890 pause("alclnk", hz); 1891 ALC_LOCK(sc); 1892 } 1893 if (i == MII_ANEGTICKS_GIGE) 1894 device_printf(sc->alc_dev, 1895 "establishing a link failed, WOL may not work!"); 1896 } 1897 /* 1898 * No link, force MAC to have 100Mbps, full-duplex link. 1899 * This is the last resort and may/may not work. 1900 */ 1901 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1902 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1903 alc_mac_config(sc); 1904} 1905 1906static void 1907alc_setwol(struct alc_softc *sc) 1908{ 1909 struct ifnet *ifp; 1910 uint32_t reg, pmcs; 1911 uint16_t pmstat; 1912 1913 ALC_LOCK_ASSERT(sc); 1914 1915 alc_disable_l0s_l1(sc); 1916 ifp = sc->alc_ifp; 1917 if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 1918 /* Disable WOL. */ 1919 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 1920 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 1921 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1922 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 1923 /* Force PHY power down. */ 1924 alc_phy_down(sc); 1925 CSR_WRITE_4(sc, ALC_MASTER_CFG, 1926 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 1927 return; 1928 } 1929 1930 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1931 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 1932 alc_setlinkspeed(sc); 1933 CSR_WRITE_4(sc, ALC_MASTER_CFG, 1934 CSR_READ_4(sc, ALC_MASTER_CFG) & ~MASTER_CLK_SEL_DIS); 1935 } 1936 1937 pmcs = 0; 1938 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1939 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1940 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 1941 reg = CSR_READ_4(sc, ALC_MAC_CFG); 1942 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 1943 MAC_CFG_BCAST); 1944 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 1945 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1946 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1947 reg |= MAC_CFG_RX_ENB; 1948 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 1949 1950 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 1951 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1952 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 1953 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1954 /* WOL disabled, PHY power down. */ 1955 alc_phy_down(sc); 1956 CSR_WRITE_4(sc, ALC_MASTER_CFG, 1957 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 1958 } 1959 /* Request PME. */ 1960 pmstat = pci_read_config(sc->alc_dev, 1961 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 1962 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1963 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1964 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1965 pci_write_config(sc->alc_dev, 1966 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 1967} 1968 1969static int 1970alc_suspend(device_t dev) 1971{ 1972 struct alc_softc *sc; 1973 1974 sc = device_get_softc(dev); 1975 1976 ALC_LOCK(sc); 1977 alc_stop(sc); 1978 alc_setwol(sc); 1979 ALC_UNLOCK(sc); 1980 1981 return (0); 1982} 1983 1984static int 1985alc_resume(device_t dev) 1986{ 1987 struct alc_softc *sc; 1988 struct ifnet *ifp; 1989 uint16_t pmstat; 1990 1991 sc = device_get_softc(dev); 1992 1993 ALC_LOCK(sc); 1994 if ((sc->alc_flags & ALC_FLAG_PM) != 0) { 1995 /* Disable PME and clear PME status. */ 1996 pmstat = pci_read_config(sc->alc_dev, 1997 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 1998 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 1999 pmstat &= ~PCIM_PSTAT_PMEENABLE; 2000 pci_write_config(sc->alc_dev, 2001 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2002 } 2003 } 2004 /* Reset PHY. */ 2005 alc_phy_reset(sc); 2006 ifp = sc->alc_ifp; 2007 if ((ifp->if_flags & IFF_UP) != 0) { 2008 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2009 alc_init_locked(sc); 2010 } 2011 ALC_UNLOCK(sc); 2012 2013 return (0); 2014} 2015 2016static int 2017alc_encap(struct alc_softc *sc, struct mbuf **m_head) 2018{ 2019 struct alc_txdesc *txd, *txd_last; 2020 struct tx_desc *desc; 2021 struct mbuf *m; 2022 struct ip *ip; 2023 struct tcphdr *tcp; 2024 bus_dma_segment_t txsegs[ALC_MAXTXSEGS]; 2025 bus_dmamap_t map; 2026 uint32_t cflags, hdrlen, ip_off, poff, vtag; 2027 int error, idx, nsegs, prod; 2028 2029 ALC_LOCK_ASSERT(sc); 2030 2031 M_ASSERTPKTHDR((*m_head)); 2032 2033 m = *m_head; 2034 ip = NULL; 2035 tcp = NULL; 2036 ip_off = poff = 0; 2037 if ((m->m_pkthdr.csum_flags & (ALC_CSUM_FEATURES | CSUM_TSO)) != 0) { 2038 /* 2039 * AR813x/AR815x requires offset of TCP/UDP header in its 2040 * Tx descriptor to perform Tx checksum offloading. TSO 2041 * also requires TCP header offset and modification of 2042 * IP/TCP header. This kind of operation takes many CPU 2043 * cycles on FreeBSD so fast host CPU is required to get 2044 * smooth TSO performance. 2045 */ 2046 struct ether_header *eh; 2047 2048 if (M_WRITABLE(m) == 0) { 2049 /* Get a writable copy. */ 2050 m = m_dup(*m_head, M_NOWAIT); 2051 /* Release original mbufs. */ 2052 m_freem(*m_head); 2053 if (m == NULL) { 2054 *m_head = NULL; 2055 return (ENOBUFS); 2056 } 2057 *m_head = m; 2058 } 2059 2060 ip_off = sizeof(struct ether_header); 2061 m = m_pullup(m, ip_off); 2062 if (m == NULL) { 2063 *m_head = NULL; 2064 return (ENOBUFS); 2065 } 2066 eh = mtod(m, struct ether_header *); 2067 /* 2068 * Check if hardware VLAN insertion is off. 2069 * Additional check for LLC/SNAP frame? 2070 */ 2071 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2072 ip_off = sizeof(struct ether_vlan_header); 2073 m = m_pullup(m, ip_off); 2074 if (m == NULL) { 2075 *m_head = NULL; 2076 return (ENOBUFS); 2077 } 2078 } 2079 m = m_pullup(m, ip_off + sizeof(struct ip)); 2080 if (m == NULL) { 2081 *m_head = NULL; 2082 return (ENOBUFS); 2083 } 2084 ip = (struct ip *)(mtod(m, char *) + ip_off); 2085 poff = ip_off + (ip->ip_hl << 2); 2086 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2087 m = m_pullup(m, poff + sizeof(struct tcphdr)); 2088 if (m == NULL) { 2089 *m_head = NULL; 2090 return (ENOBUFS); 2091 } 2092 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2093 m = m_pullup(m, poff + (tcp->th_off << 2)); 2094 if (m == NULL) { 2095 *m_head = NULL; 2096 return (ENOBUFS); 2097 } 2098 /* 2099 * Due to strict adherence of Microsoft NDIS 2100 * Large Send specification, hardware expects 2101 * a pseudo TCP checksum inserted by upper 2102 * stack. Unfortunately the pseudo TCP 2103 * checksum that NDIS refers to does not include 2104 * TCP payload length so driver should recompute 2105 * the pseudo checksum here. Hopefully this 2106 * wouldn't be much burden on modern CPUs. 2107 * 2108 * Reset IP checksum and recompute TCP pseudo 2109 * checksum as NDIS specification said. 2110 */ 2111 ip = (struct ip *)(mtod(m, char *) + ip_off); 2112 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2113 ip->ip_sum = 0; 2114 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 2115 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2116 } 2117 *m_head = m; 2118 } 2119 2120 prod = sc->alc_cdata.alc_tx_prod; 2121 txd = &sc->alc_cdata.alc_txdesc[prod]; 2122 txd_last = txd; 2123 map = txd->tx_dmamap; 2124 2125 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2126 *m_head, txsegs, &nsegs, 0); 2127 if (error == EFBIG) { 2128 m = m_collapse(*m_head, M_NOWAIT, ALC_MAXTXSEGS); 2129 if (m == NULL) { 2130 m_freem(*m_head); 2131 *m_head = NULL; 2132 return (ENOMEM); 2133 } 2134 *m_head = m; 2135 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2136 *m_head, txsegs, &nsegs, 0); 2137 if (error != 0) { 2138 m_freem(*m_head); 2139 *m_head = NULL; 2140 return (error); 2141 } 2142 } else if (error != 0) 2143 return (error); 2144 if (nsegs == 0) { 2145 m_freem(*m_head); 2146 *m_head = NULL; 2147 return (EIO); 2148 } 2149 2150 /* Check descriptor overrun. */ 2151 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) { 2152 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, map); 2153 return (ENOBUFS); 2154 } 2155 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, map, BUS_DMASYNC_PREWRITE); 2156 2157 m = *m_head; 2158 cflags = TD_ETHERNET; 2159 vtag = 0; 2160 desc = NULL; 2161 idx = 0; 2162 /* Configure VLAN hardware tag insertion. */ 2163 if ((m->m_flags & M_VLANTAG) != 0) { 2164 vtag = htons(m->m_pkthdr.ether_vtag); 2165 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 2166 cflags |= TD_INS_VLAN_TAG; 2167 } 2168 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2169 /* Request TSO and set MSS. */ 2170 cflags |= TD_TSO | TD_TSO_DESCV1; 2171 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << TD_MSS_SHIFT) & 2172 TD_MSS_MASK; 2173 /* Set TCP header offset. */ 2174 cflags |= (poff << TD_TCPHDR_OFFSET_SHIFT) & 2175 TD_TCPHDR_OFFSET_MASK; 2176 /* 2177 * AR813x/AR815x requires the first buffer should 2178 * only hold IP/TCP header data. Payload should 2179 * be handled in other descriptors. 2180 */ 2181 hdrlen = poff + (tcp->th_off << 2); 2182 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2183 desc->len = htole32(TX_BYTES(hdrlen | vtag)); 2184 desc->flags = htole32(cflags); 2185 desc->addr = htole64(txsegs[0].ds_addr); 2186 sc->alc_cdata.alc_tx_cnt++; 2187 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2188 if (m->m_len - hdrlen > 0) { 2189 /* Handle remaining payload of the first fragment. */ 2190 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2191 desc->len = htole32(TX_BYTES((m->m_len - hdrlen) | 2192 vtag)); 2193 desc->flags = htole32(cflags); 2194 desc->addr = htole64(txsegs[0].ds_addr + hdrlen); 2195 sc->alc_cdata.alc_tx_cnt++; 2196 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2197 } 2198 /* Handle remaining fragments. */ 2199 idx = 1; 2200 } else if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 2201 /* Configure Tx checksum offload. */ 2202#ifdef ALC_USE_CUSTOM_CSUM 2203 cflags |= TD_CUSTOM_CSUM; 2204 /* Set checksum start offset. */ 2205 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 2206 TD_PLOAD_OFFSET_MASK; 2207 /* Set checksum insertion position of TCP/UDP. */ 2208 cflags |= (((poff + m->m_pkthdr.csum_data) >> 1) << 2209 TD_CUSTOM_CSUM_OFFSET_SHIFT) & TD_CUSTOM_CSUM_OFFSET_MASK; 2210#else 2211 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 2212 cflags |= TD_IPCSUM; 2213 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2214 cflags |= TD_TCPCSUM; 2215 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2216 cflags |= TD_UDPCSUM; 2217 /* Set TCP/UDP header offset. */ 2218 cflags |= (poff << TD_L4HDR_OFFSET_SHIFT) & 2219 TD_L4HDR_OFFSET_MASK; 2220#endif 2221 } 2222 for (; idx < nsegs; idx++) { 2223 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2224 desc->len = htole32(TX_BYTES(txsegs[idx].ds_len) | vtag); 2225 desc->flags = htole32(cflags); 2226 desc->addr = htole64(txsegs[idx].ds_addr); 2227 sc->alc_cdata.alc_tx_cnt++; 2228 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2229 } 2230 /* Update producer index. */ 2231 sc->alc_cdata.alc_tx_prod = prod; 2232 2233 /* Finally set EOP on the last descriptor. */ 2234 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 2235 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2236 desc->flags |= htole32(TD_EOP); 2237 2238 /* Swap dmamap of the first and the last. */ 2239 txd = &sc->alc_cdata.alc_txdesc[prod]; 2240 map = txd_last->tx_dmamap; 2241 txd_last->tx_dmamap = txd->tx_dmamap; 2242 txd->tx_dmamap = map; 2243 txd->tx_m = m; 2244 2245 return (0); 2246} 2247 2248static void 2249alc_start(struct ifnet *ifp) 2250{ 2251 struct alc_softc *sc; 2252 2253 sc = ifp->if_softc; 2254 ALC_LOCK(sc); 2255 alc_start_locked(ifp); 2256 ALC_UNLOCK(sc); 2257} 2258 2259static void 2260alc_start_locked(struct ifnet *ifp) 2261{ 2262 struct alc_softc *sc; 2263 struct mbuf *m_head; 2264 int enq; 2265 2266 sc = ifp->if_softc; 2267 2268 ALC_LOCK_ASSERT(sc); 2269 2270 /* Reclaim transmitted frames. */ 2271 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 2272 alc_txeof(sc); 2273 2274 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2275 IFF_DRV_RUNNING || (sc->alc_flags & ALC_FLAG_LINK) == 0) 2276 return; 2277 2278 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 2279 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2280 if (m_head == NULL) 2281 break; 2282 /* 2283 * Pack the data into the transmit ring. If we 2284 * don't have room, set the OACTIVE flag and wait 2285 * for the NIC to drain the ring. 2286 */ 2287 if (alc_encap(sc, &m_head)) { 2288 if (m_head == NULL) 2289 break; 2290 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2291 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2292 break; 2293 } 2294 2295 enq++; 2296 /* 2297 * If there's a BPF listener, bounce a copy of this frame 2298 * to him. 2299 */ 2300 ETHER_BPF_MTAP(ifp, m_head); 2301 } 2302 2303 if (enq > 0) { 2304 /* Sync descriptors. */ 2305 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 2306 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 2307 /* Kick. Assume we're using normal Tx priority queue. */ 2308 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 2309 (sc->alc_cdata.alc_tx_prod << 2310 MBOX_TD_PROD_LO_IDX_SHIFT) & 2311 MBOX_TD_PROD_LO_IDX_MASK); 2312 /* Set a timeout in case the chip goes out to lunch. */ 2313 sc->alc_watchdog_timer = ALC_TX_TIMEOUT; 2314 } 2315} 2316 2317static void 2318alc_watchdog(struct alc_softc *sc) 2319{ 2320 struct ifnet *ifp; 2321 2322 ALC_LOCK_ASSERT(sc); 2323 2324 if (sc->alc_watchdog_timer == 0 || --sc->alc_watchdog_timer) 2325 return; 2326 2327 ifp = sc->alc_ifp; 2328 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 2329 if_printf(sc->alc_ifp, "watchdog timeout (lost link)\n"); 2330 ifp->if_oerrors++; 2331 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2332 alc_init_locked(sc); 2333 return; 2334 } 2335 if_printf(sc->alc_ifp, "watchdog timeout -- resetting\n"); 2336 ifp->if_oerrors++; 2337 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2338 alc_init_locked(sc); 2339 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2340 alc_start_locked(ifp); 2341} 2342 2343static int 2344alc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2345{ 2346 struct alc_softc *sc; 2347 struct ifreq *ifr; 2348 struct mii_data *mii; 2349 int error, mask; 2350 2351 sc = ifp->if_softc; 2352 ifr = (struct ifreq *)data; 2353 error = 0; 2354 switch (cmd) { 2355 case SIOCSIFMTU: 2356 if (ifr->ifr_mtu < ETHERMIN || 2357 ifr->ifr_mtu > (sc->alc_ident->max_framelen - 2358 sizeof(struct ether_vlan_header) - ETHER_CRC_LEN) || 2359 ((sc->alc_flags & ALC_FLAG_JUMBO) == 0 && 2360 ifr->ifr_mtu > ETHERMTU)) 2361 error = EINVAL; 2362 else if (ifp->if_mtu != ifr->ifr_mtu) { 2363 ALC_LOCK(sc); 2364 ifp->if_mtu = ifr->ifr_mtu; 2365 /* AR813x/AR815x has 13 bits MSS field. */ 2366 if (ifp->if_mtu > ALC_TSO_MTU && 2367 (ifp->if_capenable & IFCAP_TSO4) != 0) { 2368 ifp->if_capenable &= ~IFCAP_TSO4; 2369 ifp->if_hwassist &= ~CSUM_TSO; 2370 VLAN_CAPABILITIES(ifp); 2371 } 2372 ALC_UNLOCK(sc); 2373 } 2374 break; 2375 case SIOCSIFFLAGS: 2376 ALC_LOCK(sc); 2377 if ((ifp->if_flags & IFF_UP) != 0) { 2378 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2379 ((ifp->if_flags ^ sc->alc_if_flags) & 2380 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2381 alc_rxfilter(sc); 2382 else 2383 alc_init_locked(sc); 2384 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2385 alc_stop(sc); 2386 sc->alc_if_flags = ifp->if_flags; 2387 ALC_UNLOCK(sc); 2388 break; 2389 case SIOCADDMULTI: 2390 case SIOCDELMULTI: 2391 ALC_LOCK(sc); 2392 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2393 alc_rxfilter(sc); 2394 ALC_UNLOCK(sc); 2395 break; 2396 case SIOCSIFMEDIA: 2397 case SIOCGIFMEDIA: 2398 mii = device_get_softc(sc->alc_miibus); 2399 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2400 break; 2401 case SIOCSIFCAP: 2402 ALC_LOCK(sc); 2403 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2404 if ((mask & IFCAP_TXCSUM) != 0 && 2405 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 2406 ifp->if_capenable ^= IFCAP_TXCSUM; 2407 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2408 ifp->if_hwassist |= ALC_CSUM_FEATURES; 2409 else 2410 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 2411 } 2412 if ((mask & IFCAP_TSO4) != 0 && 2413 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 2414 ifp->if_capenable ^= IFCAP_TSO4; 2415 if ((ifp->if_capenable & IFCAP_TSO4) != 0) { 2416 /* AR813x/AR815x has 13 bits MSS field. */ 2417 if (ifp->if_mtu > ALC_TSO_MTU) { 2418 ifp->if_capenable &= ~IFCAP_TSO4; 2419 ifp->if_hwassist &= ~CSUM_TSO; 2420 } else 2421 ifp->if_hwassist |= CSUM_TSO; 2422 } else 2423 ifp->if_hwassist &= ~CSUM_TSO; 2424 } 2425 if ((mask & IFCAP_WOL_MCAST) != 0 && 2426 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 2427 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2428 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2429 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 2430 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2431 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2432 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2433 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2434 alc_rxvlan(sc); 2435 } 2436 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2437 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 2438 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2439 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2440 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 2441 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 2442 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 2443 ifp->if_capenable &= 2444 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 2445 ALC_UNLOCK(sc); 2446 VLAN_CAPABILITIES(ifp); 2447 break; 2448 default: 2449 error = ether_ioctl(ifp, cmd, data); 2450 break; 2451 } 2452 2453 return (error); 2454} 2455 2456static void 2457alc_mac_config(struct alc_softc *sc) 2458{ 2459 struct mii_data *mii; 2460 uint32_t reg; 2461 2462 ALC_LOCK_ASSERT(sc); 2463 2464 mii = device_get_softc(sc->alc_miibus); 2465 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2466 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2467 MAC_CFG_SPEED_MASK); 2468 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 2469 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 2470 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 2471 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 2472 /* Reprogram MAC with resolved speed/duplex. */ 2473 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2474 case IFM_10_T: 2475 case IFM_100_TX: 2476 reg |= MAC_CFG_SPEED_10_100; 2477 break; 2478 case IFM_1000_T: 2479 reg |= MAC_CFG_SPEED_1000; 2480 break; 2481 } 2482 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2483 reg |= MAC_CFG_FULL_DUPLEX; 2484 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2485 reg |= MAC_CFG_TX_FC; 2486 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2487 reg |= MAC_CFG_RX_FC; 2488 } 2489 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2490} 2491 2492static void 2493alc_stats_clear(struct alc_softc *sc) 2494{ 2495 struct smb sb, *smb; 2496 uint32_t *reg; 2497 int i; 2498 2499 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2500 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2501 sc->alc_cdata.alc_smb_map, 2502 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2503 smb = sc->alc_rdata.alc_smb; 2504 /* Update done, clear. */ 2505 smb->updated = 0; 2506 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2507 sc->alc_cdata.alc_smb_map, 2508 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2509 } else { 2510 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2511 reg++) { 2512 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2513 i += sizeof(uint32_t); 2514 } 2515 /* Read Tx statistics. */ 2516 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2517 reg++) { 2518 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2519 i += sizeof(uint32_t); 2520 } 2521 } 2522} 2523 2524static void 2525alc_stats_update(struct alc_softc *sc) 2526{ 2527 struct alc_hw_stats *stat; 2528 struct smb sb, *smb; 2529 struct ifnet *ifp; 2530 uint32_t *reg; 2531 int i; 2532 2533 ALC_LOCK_ASSERT(sc); 2534 2535 ifp = sc->alc_ifp; 2536 stat = &sc->alc_stats; 2537 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2538 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2539 sc->alc_cdata.alc_smb_map, 2540 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2541 smb = sc->alc_rdata.alc_smb; 2542 if (smb->updated == 0) 2543 return; 2544 } else { 2545 smb = &sb; 2546 /* Read Rx statistics. */ 2547 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 2548 reg++) { 2549 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 2550 i += sizeof(uint32_t); 2551 } 2552 /* Read Tx statistics. */ 2553 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 2554 reg++) { 2555 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 2556 i += sizeof(uint32_t); 2557 } 2558 } 2559 2560 /* Rx stats. */ 2561 stat->rx_frames += smb->rx_frames; 2562 stat->rx_bcast_frames += smb->rx_bcast_frames; 2563 stat->rx_mcast_frames += smb->rx_mcast_frames; 2564 stat->rx_pause_frames += smb->rx_pause_frames; 2565 stat->rx_control_frames += smb->rx_control_frames; 2566 stat->rx_crcerrs += smb->rx_crcerrs; 2567 stat->rx_lenerrs += smb->rx_lenerrs; 2568 stat->rx_bytes += smb->rx_bytes; 2569 stat->rx_runts += smb->rx_runts; 2570 stat->rx_fragments += smb->rx_fragments; 2571 stat->rx_pkts_64 += smb->rx_pkts_64; 2572 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2573 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2574 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2575 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2576 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2577 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2578 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2579 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2580 stat->rx_rrs_errs += smb->rx_rrs_errs; 2581 stat->rx_alignerrs += smb->rx_alignerrs; 2582 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2583 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2584 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2585 2586 /* Tx stats. */ 2587 stat->tx_frames += smb->tx_frames; 2588 stat->tx_bcast_frames += smb->tx_bcast_frames; 2589 stat->tx_mcast_frames += smb->tx_mcast_frames; 2590 stat->tx_pause_frames += smb->tx_pause_frames; 2591 stat->tx_excess_defer += smb->tx_excess_defer; 2592 stat->tx_control_frames += smb->tx_control_frames; 2593 stat->tx_deferred += smb->tx_deferred; 2594 stat->tx_bytes += smb->tx_bytes; 2595 stat->tx_pkts_64 += smb->tx_pkts_64; 2596 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2597 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2598 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2599 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2600 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2601 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2602 stat->tx_single_colls += smb->tx_single_colls; 2603 stat->tx_multi_colls += smb->tx_multi_colls; 2604 stat->tx_late_colls += smb->tx_late_colls; 2605 stat->tx_excess_colls += smb->tx_excess_colls; 2606 stat->tx_abort += smb->tx_abort; 2607 stat->tx_underrun += smb->tx_underrun; 2608 stat->tx_desc_underrun += smb->tx_desc_underrun; 2609 stat->tx_lenerrs += smb->tx_lenerrs; 2610 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2611 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2612 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2613 2614 /* Update counters in ifnet. */ 2615 ifp->if_opackets += smb->tx_frames; 2616 2617 ifp->if_collisions += smb->tx_single_colls + 2618 smb->tx_multi_colls * 2 + smb->tx_late_colls + 2619 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 2620 2621 /* 2622 * XXX 2623 * tx_pkts_truncated counter looks suspicious. It constantly 2624 * increments with no sign of Tx errors. This may indicate 2625 * the counter name is not correct one so I've removed the 2626 * counter in output errors. 2627 */ 2628 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 2629 smb->tx_underrun; 2630 2631 ifp->if_ipackets += smb->rx_frames; 2632 2633 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2634 smb->rx_runts + smb->rx_pkts_truncated + 2635 smb->rx_fifo_oflows + smb->rx_rrs_errs + 2636 smb->rx_alignerrs; 2637 2638 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 2639 /* Update done, clear. */ 2640 smb->updated = 0; 2641 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 2642 sc->alc_cdata.alc_smb_map, 2643 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2644 } 2645} 2646 2647static int 2648alc_intr(void *arg) 2649{ 2650 struct alc_softc *sc; 2651 uint32_t status; 2652 2653 sc = (struct alc_softc *)arg; 2654 2655 status = CSR_READ_4(sc, ALC_INTR_STATUS); 2656 if ((status & ALC_INTRS) == 0) 2657 return (FILTER_STRAY); 2658 /* Disable interrupts. */ 2659 CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT); 2660 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 2661 2662 return (FILTER_HANDLED); 2663} 2664 2665static void 2666alc_int_task(void *arg, int pending) 2667{ 2668 struct alc_softc *sc; 2669 struct ifnet *ifp; 2670 uint32_t status; 2671 int more; 2672 2673 sc = (struct alc_softc *)arg; 2674 ifp = sc->alc_ifp; 2675 2676 status = CSR_READ_4(sc, ALC_INTR_STATUS); 2677 ALC_LOCK(sc); 2678 if (sc->alc_morework != 0) { 2679 sc->alc_morework = 0; 2680 status |= INTR_RX_PKT; 2681 } 2682 if ((status & ALC_INTRS) == 0) 2683 goto done; 2684 2685 /* Acknowledge interrupts but still disable interrupts. */ 2686 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 2687 2688 more = 0; 2689 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2690 if ((status & INTR_RX_PKT) != 0) { 2691 more = alc_rxintr(sc, sc->alc_process_limit); 2692 if (more == EAGAIN) 2693 sc->alc_morework = 1; 2694 else if (more == EIO) { 2695 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2696 alc_init_locked(sc); 2697 ALC_UNLOCK(sc); 2698 return; 2699 } 2700 } 2701 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 2702 INTR_TXQ_TO_RST)) != 0) { 2703 if ((status & INTR_DMA_RD_TO_RST) != 0) 2704 device_printf(sc->alc_dev, 2705 "DMA read error! -- resetting\n"); 2706 if ((status & INTR_DMA_WR_TO_RST) != 0) 2707 device_printf(sc->alc_dev, 2708 "DMA write error! -- resetting\n"); 2709 if ((status & INTR_TXQ_TO_RST) != 0) 2710 device_printf(sc->alc_dev, 2711 "TxQ reset! -- resetting\n"); 2712 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2713 alc_init_locked(sc); 2714 ALC_UNLOCK(sc); 2715 return; 2716 } 2717 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2718 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2719 alc_start_locked(ifp); 2720 } 2721 2722 if (more == EAGAIN || 2723 (CSR_READ_4(sc, ALC_INTR_STATUS) & ALC_INTRS) != 0) { 2724 ALC_UNLOCK(sc); 2725 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 2726 return; 2727 } 2728 2729done: 2730 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2731 /* Re-enable interrupts if we're running. */ 2732 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 2733 } 2734 ALC_UNLOCK(sc); 2735} 2736 2737static void 2738alc_txeof(struct alc_softc *sc) 2739{ 2740 struct ifnet *ifp; 2741 struct alc_txdesc *txd; 2742 uint32_t cons, prod; 2743 int prog; 2744 2745 ALC_LOCK_ASSERT(sc); 2746 2747 ifp = sc->alc_ifp; 2748 2749 if (sc->alc_cdata.alc_tx_cnt == 0) 2750 return; 2751 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 2752 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_POSTWRITE); 2753 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 2754 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 2755 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_POSTREAD); 2756 prod = sc->alc_rdata.alc_cmb->cons; 2757 } else 2758 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 2759 /* Assume we're using normal Tx priority queue. */ 2760 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 2761 MBOX_TD_CONS_LO_IDX_SHIFT; 2762 cons = sc->alc_cdata.alc_tx_cons; 2763 /* 2764 * Go through our Tx list and free mbufs for those 2765 * frames which have been transmitted. 2766 */ 2767 for (prog = 0; cons != prod; prog++, 2768 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 2769 if (sc->alc_cdata.alc_tx_cnt <= 0) 2770 break; 2771 prog++; 2772 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2773 sc->alc_cdata.alc_tx_cnt--; 2774 txd = &sc->alc_cdata.alc_txdesc[cons]; 2775 if (txd->tx_m != NULL) { 2776 /* Reclaim transmitted mbufs. */ 2777 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 2778 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2779 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 2780 txd->tx_dmamap); 2781 m_freem(txd->tx_m); 2782 txd->tx_m = NULL; 2783 } 2784 } 2785 2786 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 2787 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 2788 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_PREREAD); 2789 sc->alc_cdata.alc_tx_cons = cons; 2790 /* 2791 * Unarm watchdog timer only when there is no pending 2792 * frames in Tx queue. 2793 */ 2794 if (sc->alc_cdata.alc_tx_cnt == 0) 2795 sc->alc_watchdog_timer = 0; 2796} 2797 2798static int 2799alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd) 2800{ 2801 struct mbuf *m; 2802 bus_dma_segment_t segs[1]; 2803 bus_dmamap_t map; 2804 int nsegs; 2805 2806 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 2807 if (m == NULL) 2808 return (ENOBUFS); 2809 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 2810#ifndef __NO_STRICT_ALIGNMENT 2811 m_adj(m, sizeof(uint64_t)); 2812#endif 2813 2814 if (bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_rx_tag, 2815 sc->alc_cdata.alc_rx_sparemap, m, segs, &nsegs, 0) != 0) { 2816 m_freem(m); 2817 return (ENOBUFS); 2818 } 2819 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2820 2821 if (rxd->rx_m != NULL) { 2822 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 2823 BUS_DMASYNC_POSTREAD); 2824 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap); 2825 } 2826 map = rxd->rx_dmamap; 2827 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 2828 sc->alc_cdata.alc_rx_sparemap = map; 2829 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 2830 BUS_DMASYNC_PREREAD); 2831 rxd->rx_m = m; 2832 rxd->rx_desc->addr = htole64(segs[0].ds_addr); 2833 return (0); 2834} 2835 2836static int 2837alc_rxintr(struct alc_softc *sc, int count) 2838{ 2839 struct ifnet *ifp; 2840 struct rx_rdesc *rrd; 2841 uint32_t nsegs, status; 2842 int rr_cons, prog; 2843 2844 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 2845 sc->alc_cdata.alc_rr_ring_map, 2846 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2847 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 2848 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_POSTWRITE); 2849 rr_cons = sc->alc_cdata.alc_rr_cons; 2850 ifp = sc->alc_ifp; 2851 for (prog = 0; (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0;) { 2852 if (count-- <= 0) 2853 break; 2854 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 2855 status = le32toh(rrd->status); 2856 if ((status & RRD_VALID) == 0) 2857 break; 2858 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo)); 2859 if (nsegs == 0) { 2860 /* This should not happen! */ 2861 device_printf(sc->alc_dev, 2862 "unexpected segment count -- resetting\n"); 2863 return (EIO); 2864 } 2865 alc_rxeof(sc, rrd); 2866 /* Clear Rx return status. */ 2867 rrd->status = 0; 2868 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 2869 sc->alc_cdata.alc_rx_cons += nsegs; 2870 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 2871 prog += nsegs; 2872 } 2873 2874 if (prog > 0) { 2875 /* Update the consumer index. */ 2876 sc->alc_cdata.alc_rr_cons = rr_cons; 2877 /* Sync Rx return descriptors. */ 2878 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 2879 sc->alc_cdata.alc_rr_ring_map, 2880 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2881 /* 2882 * Sync updated Rx descriptors such that controller see 2883 * modified buffer addresses. 2884 */ 2885 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 2886 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 2887 /* 2888 * Let controller know availability of new Rx buffers. 2889 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 2890 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 2891 * only when Rx buffer pre-fetching is required. In 2892 * addition we already set ALC_RX_RD_FREE_THRESH to 2893 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 2894 * it still seems that pre-fetching needs more 2895 * experimentation. 2896 */ 2897 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 2898 sc->alc_cdata.alc_rx_cons); 2899 } 2900 2901 return (count > 0 ? 0 : EAGAIN); 2902} 2903 2904#ifndef __NO_STRICT_ALIGNMENT 2905static struct mbuf * 2906alc_fixup_rx(struct ifnet *ifp, struct mbuf *m) 2907{ 2908 struct mbuf *n; 2909 int i; 2910 uint16_t *src, *dst; 2911 2912 src = mtod(m, uint16_t *); 2913 dst = src - 3; 2914 2915 if (m->m_next == NULL) { 2916 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2917 *dst++ = *src++; 2918 m->m_data -= 6; 2919 return (m); 2920 } 2921 /* 2922 * Append a new mbuf to received mbuf chain and copy ethernet 2923 * header from the mbuf chain. This can save lots of CPU 2924 * cycles for jumbo frame. 2925 */ 2926 MGETHDR(n, M_NOWAIT, MT_DATA); 2927 if (n == NULL) { 2928 ifp->if_iqdrops++; 2929 m_freem(m); 2930 return (NULL); 2931 } 2932 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 2933 m->m_data += ETHER_HDR_LEN; 2934 m->m_len -= ETHER_HDR_LEN; 2935 n->m_len = ETHER_HDR_LEN; 2936 M_MOVE_PKTHDR(n, m); 2937 n->m_next = m; 2938 return (n); 2939} 2940#endif 2941 2942/* Receive a frame. */ 2943static void 2944alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 2945{ 2946 struct alc_rxdesc *rxd; 2947 struct ifnet *ifp; 2948 struct mbuf *mp, *m; 2949 uint32_t rdinfo, status, vtag; 2950 int count, nsegs, rx_cons; 2951 2952 ifp = sc->alc_ifp; 2953 status = le32toh(rrd->status); 2954 rdinfo = le32toh(rrd->rdinfo); 2955 rx_cons = RRD_RD_IDX(rdinfo); 2956 nsegs = RRD_RD_CNT(rdinfo); 2957 2958 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 2959 if ((status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) != 0) { 2960 /* 2961 * We want to pass the following frames to upper 2962 * layer regardless of error status of Rx return 2963 * ring. 2964 * 2965 * o IP/TCP/UDP checksum is bad. 2966 * o frame length and protocol specific length 2967 * does not match. 2968 * 2969 * Force network stack compute checksum for 2970 * errored frames. 2971 */ 2972 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK; 2973 if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN | 2974 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0) 2975 return; 2976 } 2977 2978 for (count = 0; count < nsegs; count++, 2979 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 2980 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 2981 mp = rxd->rx_m; 2982 /* Add a new receive buffer to the ring. */ 2983 if (alc_newbuf(sc, rxd) != 0) { 2984 ifp->if_iqdrops++; 2985 /* Reuse Rx buffers. */ 2986 if (sc->alc_cdata.alc_rxhead != NULL) 2987 m_freem(sc->alc_cdata.alc_rxhead); 2988 break; 2989 } 2990 2991 /* 2992 * Assume we've received a full sized frame. 2993 * Actual size is fixed when we encounter the end of 2994 * multi-segmented frame. 2995 */ 2996 mp->m_len = sc->alc_buf_size; 2997 2998 /* Chain received mbufs. */ 2999 if (sc->alc_cdata.alc_rxhead == NULL) { 3000 sc->alc_cdata.alc_rxhead = mp; 3001 sc->alc_cdata.alc_rxtail = mp; 3002 } else { 3003 mp->m_flags &= ~M_PKTHDR; 3004 sc->alc_cdata.alc_rxprev_tail = 3005 sc->alc_cdata.alc_rxtail; 3006 sc->alc_cdata.alc_rxtail->m_next = mp; 3007 sc->alc_cdata.alc_rxtail = mp; 3008 } 3009 3010 if (count == nsegs - 1) { 3011 /* Last desc. for this frame. */ 3012 m = sc->alc_cdata.alc_rxhead; 3013 m->m_flags |= M_PKTHDR; 3014 /* 3015 * It seems that L1C/L2C controller has no way 3016 * to tell hardware to strip CRC bytes. 3017 */ 3018 m->m_pkthdr.len = 3019 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 3020 if (nsegs > 1) { 3021 /* Set last mbuf size. */ 3022 mp->m_len = sc->alc_cdata.alc_rxlen - 3023 (nsegs - 1) * sc->alc_buf_size; 3024 /* Remove the CRC bytes in chained mbufs. */ 3025 if (mp->m_len <= ETHER_CRC_LEN) { 3026 sc->alc_cdata.alc_rxtail = 3027 sc->alc_cdata.alc_rxprev_tail; 3028 sc->alc_cdata.alc_rxtail->m_len -= 3029 (ETHER_CRC_LEN - mp->m_len); 3030 sc->alc_cdata.alc_rxtail->m_next = NULL; 3031 m_freem(mp); 3032 } else { 3033 mp->m_len -= ETHER_CRC_LEN; 3034 } 3035 } else 3036 m->m_len = m->m_pkthdr.len; 3037 m->m_pkthdr.rcvif = ifp; 3038 /* 3039 * Due to hardware bugs, Rx checksum offloading 3040 * was intentionally disabled. 3041 */ 3042 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 3043 (status & RRD_VLAN_TAG) != 0) { 3044 vtag = RRD_VLAN(le32toh(rrd->vtag)); 3045 m->m_pkthdr.ether_vtag = ntohs(vtag); 3046 m->m_flags |= M_VLANTAG; 3047 } 3048#ifndef __NO_STRICT_ALIGNMENT 3049 m = alc_fixup_rx(ifp, m); 3050 if (m != NULL) 3051#endif 3052 { 3053 /* Pass it on. */ 3054 ALC_UNLOCK(sc); 3055 (*ifp->if_input)(ifp, m); 3056 ALC_LOCK(sc); 3057 } 3058 } 3059 } 3060 /* Reset mbuf chains. */ 3061 ALC_RXCHAIN_RESET(sc); 3062} 3063 3064static void 3065alc_tick(void *arg) 3066{ 3067 struct alc_softc *sc; 3068 struct mii_data *mii; 3069 3070 sc = (struct alc_softc *)arg; 3071 3072 ALC_LOCK_ASSERT(sc); 3073 3074 mii = device_get_softc(sc->alc_miibus); 3075 mii_tick(mii); 3076 alc_stats_update(sc); 3077 /* 3078 * alc(4) does not rely on Tx completion interrupts to reclaim 3079 * transferred buffers. Instead Tx completion interrupts are 3080 * used to hint for scheduling Tx task. So it's necessary to 3081 * release transmitted buffers by kicking Tx completion 3082 * handler. This limits the maximum reclamation delay to a hz. 3083 */ 3084 alc_txeof(sc); 3085 alc_watchdog(sc); 3086 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 3087} 3088 3089static void 3090alc_reset(struct alc_softc *sc) 3091{ 3092 uint32_t reg; 3093 int i; 3094 3095 reg = CSR_READ_4(sc, ALC_MASTER_CFG) & 0xFFFF; 3096 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 3097 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3098 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3099 DELAY(10); 3100 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 3101 break; 3102 } 3103 if (i == 0) 3104 device_printf(sc->alc_dev, "master reset timeout!\n"); 3105 3106 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3107 if ((reg = CSR_READ_4(sc, ALC_IDLE_STATUS)) == 0) 3108 break; 3109 DELAY(10); 3110 } 3111 3112 if (i == 0) 3113 device_printf(sc->alc_dev, "reset timeout(0x%08x)!\n", reg); 3114} 3115 3116static void 3117alc_init(void *xsc) 3118{ 3119 struct alc_softc *sc; 3120 3121 sc = (struct alc_softc *)xsc; 3122 ALC_LOCK(sc); 3123 alc_init_locked(sc); 3124 ALC_UNLOCK(sc); 3125} 3126 3127static void 3128alc_init_locked(struct alc_softc *sc) 3129{ 3130 struct ifnet *ifp; 3131 struct mii_data *mii; 3132 uint8_t eaddr[ETHER_ADDR_LEN]; 3133 bus_addr_t paddr; 3134 uint32_t reg, rxf_hi, rxf_lo; 3135 3136 ALC_LOCK_ASSERT(sc); 3137 3138 ifp = sc->alc_ifp; 3139 mii = device_get_softc(sc->alc_miibus); 3140 3141 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3142 return; 3143 /* 3144 * Cancel any pending I/O. 3145 */ 3146 alc_stop(sc); 3147 /* 3148 * Reset the chip to a known state. 3149 */ 3150 alc_reset(sc); 3151 3152 /* Initialize Rx descriptors. */ 3153 if (alc_init_rx_ring(sc) != 0) { 3154 device_printf(sc->alc_dev, "no memory for Rx buffers.\n"); 3155 alc_stop(sc); 3156 return; 3157 } 3158 alc_init_rr_ring(sc); 3159 alc_init_tx_ring(sc); 3160 alc_init_cmb(sc); 3161 alc_init_smb(sc); 3162 3163 /* Enable all clocks. */ 3164 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0); 3165 3166 /* Reprogram the station address. */ 3167 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 3168 CSR_WRITE_4(sc, ALC_PAR0, 3169 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 3170 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 3171 /* 3172 * Clear WOL status and disable all WOL feature as WOL 3173 * would interfere Rx operation under normal environments. 3174 */ 3175 CSR_READ_4(sc, ALC_WOL_CFG); 3176 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 3177 /* Set Tx descriptor base addresses. */ 3178 paddr = sc->alc_rdata.alc_tx_ring_paddr; 3179 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3180 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3181 /* We don't use high priority ring. */ 3182 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 3183 /* Set Tx descriptor counter. */ 3184 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 3185 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 3186 /* Set Rx descriptor base addresses. */ 3187 paddr = sc->alc_rdata.alc_rx_ring_paddr; 3188 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3189 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3190 /* We use one Rx ring. */ 3191 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 3192 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 3193 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 3194 /* Set Rx descriptor counter. */ 3195 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 3196 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 3197 3198 /* 3199 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 3200 * if it do not fit the buffer size. Rx return descriptor holds 3201 * a counter that indicates how many fragments were made by the 3202 * hardware. The buffer size should be multiple of 8 bytes. 3203 * Since hardware has limit on the size of buffer size, always 3204 * use the maximum value. 3205 * For strict-alignment architectures make sure to reduce buffer 3206 * size by 8 bytes to make room for alignment fixup. 3207 */ 3208#ifndef __NO_STRICT_ALIGNMENT 3209 sc->alc_buf_size = RX_BUF_SIZE_MAX - sizeof(uint64_t); 3210#else 3211 sc->alc_buf_size = RX_BUF_SIZE_MAX; 3212#endif 3213 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 3214 3215 paddr = sc->alc_rdata.alc_rr_ring_paddr; 3216 /* Set Rx return descriptor base addresses. */ 3217 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3218 /* We use one Rx return ring. */ 3219 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 3220 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 3221 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 3222 /* Set Rx return descriptor counter. */ 3223 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 3224 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 3225 paddr = sc->alc_rdata.alc_cmb_paddr; 3226 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 3227 paddr = sc->alc_rdata.alc_smb_paddr; 3228 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3229 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 3230 3231 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 3232 /* Reconfigure SRAM - Vendor magic. */ 3233 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 3234 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 3235 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 3236 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 3237 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 3238 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 3239 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 3240 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 3241 } 3242 3243 /* Tell hardware that we're ready to load DMA blocks. */ 3244 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 3245 3246 /* Configure interrupt moderation timer. */ 3247 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 3248 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 3249 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 3250 /* 3251 * We don't want to automatic interrupt clear as task queue 3252 * for the interrupt should know interrupt status. 3253 */ 3254 reg = MASTER_SA_TIMER_ENB; 3255 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 3256 reg |= MASTER_IM_RX_TIMER_ENB; 3257 if (ALC_USECS(sc->alc_int_tx_mod) != 0) 3258 reg |= MASTER_IM_TX_TIMER_ENB; 3259 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3260 /* 3261 * Disable interrupt re-trigger timer. We don't want automatic 3262 * re-triggering of un-ACKed interrupts. 3263 */ 3264 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 3265 /* Configure CMB. */ 3266 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 3267 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 3268 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 3269 } else 3270 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 3271 /* 3272 * Hardware can be configured to issue SMB interrupt based 3273 * on programmed interval. Since there is a callout that is 3274 * invoked for every hz in driver we use that instead of 3275 * relying on periodic SMB interrupt. 3276 */ 3277 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 3278 /* Clear MAC statistics. */ 3279 alc_stats_clear(sc); 3280 3281 /* 3282 * Always use maximum frame size that controller can support. 3283 * Otherwise received frames that has larger frame length 3284 * than alc(4) MTU would be silently dropped in hardware. This 3285 * would make path-MTU discovery hard as sender wouldn't get 3286 * any responses from receiver. alc(4) supports 3287 * multi-fragmented frames on Rx path so it has no issue on 3288 * assembling fragmented frames. Using maximum frame size also 3289 * removes the need to reinitialize hardware when interface 3290 * MTU configuration was changed. 3291 * 3292 * Be conservative in what you do, be liberal in what you 3293 * accept from others - RFC 793. 3294 */ 3295 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen); 3296 3297 /* Disable header split(?) */ 3298 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 3299 3300 /* Configure IPG/IFG parameters. */ 3301 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 3302 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 3303 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 3304 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 3305 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 3306 /* Set parameters for half-duplex media. */ 3307 CSR_WRITE_4(sc, ALC_HDPX_CFG, 3308 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 3309 HDPX_CFG_LCOL_MASK) | 3310 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 3311 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 3312 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 3313 HDPX_CFG_ABEBT_MASK) | 3314 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 3315 HDPX_CFG_JAMIPG_MASK)); 3316 /* 3317 * Set TSO/checksum offload threshold. For frames that is 3318 * larger than this threshold, hardware wouldn't do 3319 * TSO/checksum offloading. 3320 */ 3321 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, 3322 (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 3323 TSO_OFFLOAD_THRESH_MASK); 3324 /* Configure TxQ. */ 3325 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 3326 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 3327 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 3328 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 3329 reg >>= 1; 3330 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 3331 TXQ_CFG_TD_BURST_MASK; 3332 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 3333 3334 /* Configure Rx free descriptor pre-fetching. */ 3335 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 3336 ((RX_RD_FREE_THRESH_HI_DEFAULT << RX_RD_FREE_THRESH_HI_SHIFT) & 3337 RX_RD_FREE_THRESH_HI_MASK) | 3338 ((RX_RD_FREE_THRESH_LO_DEFAULT << RX_RD_FREE_THRESH_LO_SHIFT) & 3339 RX_RD_FREE_THRESH_LO_MASK)); 3340 3341 /* 3342 * Configure flow control parameters. 3343 * XON : 80% of Rx FIFO 3344 * XOFF : 30% of Rx FIFO 3345 */ 3346 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 3347 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132) { 3348 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 3349 rxf_hi = (reg * 8) / 10; 3350 rxf_lo = (reg * 3) / 10; 3351 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 3352 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 3353 RX_FIFO_PAUSE_THRESH_LO_MASK) | 3354 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 3355 RX_FIFO_PAUSE_THRESH_HI_MASK)); 3356 } 3357 3358 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 3359 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2) 3360 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 3361 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | 3362 SERDES_PHY_CLK_SLOWDOWN); 3363 3364 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 3365 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 3366 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 3367 3368 /* Configure RxQ. */ 3369 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 3370 RXQ_CFG_RD_BURST_MASK; 3371 reg |= RXQ_CFG_RSS_MODE_DIS; 3372 if ((sc->alc_flags & ALC_FLAG_ASPM_MON) != 0) 3373 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_1M; 3374 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3375 3376 /* Configure DMA parameters. */ 3377 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 3378 reg |= sc->alc_rcb; 3379 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 3380 reg |= DMA_CFG_CMB_ENB; 3381 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 3382 reg |= DMA_CFG_SMB_ENB; 3383 else 3384 reg |= DMA_CFG_SMB_DIS; 3385 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 3386 DMA_CFG_RD_BURST_SHIFT; 3387 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 3388 DMA_CFG_WR_BURST_SHIFT; 3389 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 3390 DMA_CFG_RD_DELAY_CNT_MASK; 3391 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 3392 DMA_CFG_WR_DELAY_CNT_MASK; 3393 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3394 3395 /* 3396 * Configure Tx/Rx MACs. 3397 * - Auto-padding for short frames. 3398 * - Enable CRC generation. 3399 * Actual reconfiguration of MAC for resolved speed/duplex 3400 * is followed after detection of link establishment. 3401 * AR813x/AR815x always does checksum computation regardless 3402 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 3403 * have bug in protocol field in Rx return structure so 3404 * these controllers can't handle fragmented frames. Disable 3405 * Rx checksum offloading until there is a newer controller 3406 * that has sane implementation. 3407 */ 3408 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 3409 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 3410 MAC_CFG_PREAMBLE_MASK); 3411 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 3412 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 3413 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 3414 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 3415 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 3416 reg |= MAC_CFG_SPEED_10_100; 3417 else 3418 reg |= MAC_CFG_SPEED_1000; 3419 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3420 3421 /* Set up the receive filter. */ 3422 alc_rxfilter(sc); 3423 alc_rxvlan(sc); 3424 3425 /* Acknowledge all pending interrupts and clear it. */ 3426 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 3427 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3428 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 3429 3430 sc->alc_flags &= ~ALC_FLAG_LINK; 3431 /* Switch to the current media. */ 3432 mii_mediachg(mii); 3433 3434 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 3435 3436 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3437 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3438} 3439 3440static void 3441alc_stop(struct alc_softc *sc) 3442{ 3443 struct ifnet *ifp; 3444 struct alc_txdesc *txd; 3445 struct alc_rxdesc *rxd; 3446 uint32_t reg; 3447 int i; 3448 3449 ALC_LOCK_ASSERT(sc); 3450 /* 3451 * Mark the interface down and cancel the watchdog timer. 3452 */ 3453 ifp = sc->alc_ifp; 3454 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3455 sc->alc_flags &= ~ALC_FLAG_LINK; 3456 callout_stop(&sc->alc_tick_ch); 3457 sc->alc_watchdog_timer = 0; 3458 alc_stats_update(sc); 3459 /* Disable interrupts. */ 3460 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 3461 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3462 alc_stop_queue(sc); 3463 /* Disable DMA. */ 3464 reg = CSR_READ_4(sc, ALC_DMA_CFG); 3465 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 3466 reg |= DMA_CFG_SMB_DIS; 3467 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 3468 DELAY(1000); 3469 /* Stop Rx/Tx MACs. */ 3470 alc_stop_mac(sc); 3471 /* Disable interrupts which might be touched in taskq handler. */ 3472 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 3473 3474 /* Reclaim Rx buffers that have been processed. */ 3475 if (sc->alc_cdata.alc_rxhead != NULL) 3476 m_freem(sc->alc_cdata.alc_rxhead); 3477 ALC_RXCHAIN_RESET(sc); 3478 /* 3479 * Free Tx/Rx mbufs still in the queues. 3480 */ 3481 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3482 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3483 if (rxd->rx_m != NULL) { 3484 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, 3485 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3486 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, 3487 rxd->rx_dmamap); 3488 m_freem(rxd->rx_m); 3489 rxd->rx_m = NULL; 3490 } 3491 } 3492 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3493 txd = &sc->alc_cdata.alc_txdesc[i]; 3494 if (txd->tx_m != NULL) { 3495 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 3496 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3497 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 3498 txd->tx_dmamap); 3499 m_freem(txd->tx_m); 3500 txd->tx_m = NULL; 3501 } 3502 } 3503} 3504 3505static void 3506alc_stop_mac(struct alc_softc *sc) 3507{ 3508 uint32_t reg; 3509 int i; 3510 3511 ALC_LOCK_ASSERT(sc); 3512 3513 /* Disable Rx/Tx MAC. */ 3514 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3515 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 3516 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 3517 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3518 } 3519 for (i = ALC_TIMEOUT; i > 0; i--) { 3520 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3521 if (reg == 0) 3522 break; 3523 DELAY(10); 3524 } 3525 if (i == 0) 3526 device_printf(sc->alc_dev, 3527 "could not disable Rx/Tx MAC(0x%08x)!\n", reg); 3528} 3529 3530static void 3531alc_start_queue(struct alc_softc *sc) 3532{ 3533 uint32_t qcfg[] = { 3534 0, 3535 RXQ_CFG_QUEUE0_ENB, 3536 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 3537 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 3538 RXQ_CFG_ENB 3539 }; 3540 uint32_t cfg; 3541 3542 ALC_LOCK_ASSERT(sc); 3543 3544 /* Enable RxQ. */ 3545 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 3546 cfg &= ~RXQ_CFG_ENB; 3547 cfg |= qcfg[1]; 3548 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 3549 /* Enable TxQ. */ 3550 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 3551 cfg |= TXQ_CFG_ENB; 3552 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 3553} 3554 3555static void 3556alc_stop_queue(struct alc_softc *sc) 3557{ 3558 uint32_t reg; 3559 int i; 3560 3561 ALC_LOCK_ASSERT(sc); 3562 3563 /* Disable RxQ. */ 3564 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 3565 if ((reg & RXQ_CFG_ENB) != 0) { 3566 reg &= ~RXQ_CFG_ENB; 3567 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 3568 } 3569 /* Disable TxQ. */ 3570 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 3571 if ((reg & TXQ_CFG_ENB) != 0) { 3572 reg &= ~TXQ_CFG_ENB; 3573 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 3574 } 3575 for (i = ALC_TIMEOUT; i > 0; i--) { 3576 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3577 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 3578 break; 3579 DELAY(10); 3580 } 3581 if (i == 0) 3582 device_printf(sc->alc_dev, 3583 "could not disable RxQ/TxQ (0x%08x)!\n", reg); 3584} 3585 3586static void 3587alc_init_tx_ring(struct alc_softc *sc) 3588{ 3589 struct alc_ring_data *rd; 3590 struct alc_txdesc *txd; 3591 int i; 3592 3593 ALC_LOCK_ASSERT(sc); 3594 3595 sc->alc_cdata.alc_tx_prod = 0; 3596 sc->alc_cdata.alc_tx_cons = 0; 3597 sc->alc_cdata.alc_tx_cnt = 0; 3598 3599 rd = &sc->alc_rdata; 3600 bzero(rd->alc_tx_ring, ALC_TX_RING_SZ); 3601 for (i = 0; i < ALC_TX_RING_CNT; i++) { 3602 txd = &sc->alc_cdata.alc_txdesc[i]; 3603 txd->tx_m = NULL; 3604 } 3605 3606 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 3607 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 3608} 3609 3610static int 3611alc_init_rx_ring(struct alc_softc *sc) 3612{ 3613 struct alc_ring_data *rd; 3614 struct alc_rxdesc *rxd; 3615 int i; 3616 3617 ALC_LOCK_ASSERT(sc); 3618 3619 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 3620 sc->alc_morework = 0; 3621 rd = &sc->alc_rdata; 3622 bzero(rd->alc_rx_ring, ALC_RX_RING_SZ); 3623 for (i = 0; i < ALC_RX_RING_CNT; i++) { 3624 rxd = &sc->alc_cdata.alc_rxdesc[i]; 3625 rxd->rx_m = NULL; 3626 rxd->rx_desc = &rd->alc_rx_ring[i]; 3627 if (alc_newbuf(sc, rxd) != 0) 3628 return (ENOBUFS); 3629 } 3630 3631 /* 3632 * Since controller does not update Rx descriptors, driver 3633 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 3634 * is enough to ensure coherence. 3635 */ 3636 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3637 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 3638 /* Let controller know availability of new Rx buffers. */ 3639 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 3640 3641 return (0); 3642} 3643 3644static void 3645alc_init_rr_ring(struct alc_softc *sc) 3646{ 3647 struct alc_ring_data *rd; 3648 3649 ALC_LOCK_ASSERT(sc); 3650 3651 sc->alc_cdata.alc_rr_cons = 0; 3652 ALC_RXCHAIN_RESET(sc); 3653 3654 rd = &sc->alc_rdata; 3655 bzero(rd->alc_rr_ring, ALC_RR_RING_SZ); 3656 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3657 sc->alc_cdata.alc_rr_ring_map, 3658 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3659} 3660 3661static void 3662alc_init_cmb(struct alc_softc *sc) 3663{ 3664 struct alc_ring_data *rd; 3665 3666 ALC_LOCK_ASSERT(sc); 3667 3668 rd = &sc->alc_rdata; 3669 bzero(rd->alc_cmb, ALC_CMB_SZ); 3670 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, sc->alc_cdata.alc_cmb_map, 3671 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3672} 3673 3674static void 3675alc_init_smb(struct alc_softc *sc) 3676{ 3677 struct alc_ring_data *rd; 3678 3679 ALC_LOCK_ASSERT(sc); 3680 3681 rd = &sc->alc_rdata; 3682 bzero(rd->alc_smb, ALC_SMB_SZ); 3683 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, sc->alc_cdata.alc_smb_map, 3684 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3685} 3686 3687static void 3688alc_rxvlan(struct alc_softc *sc) 3689{ 3690 struct ifnet *ifp; 3691 uint32_t reg; 3692 3693 ALC_LOCK_ASSERT(sc); 3694 3695 ifp = sc->alc_ifp; 3696 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3697 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3698 reg |= MAC_CFG_VLAN_TAG_STRIP; 3699 else 3700 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3701 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3702} 3703 3704static void 3705alc_rxfilter(struct alc_softc *sc) 3706{ 3707 struct ifnet *ifp; 3708 struct ifmultiaddr *ifma; 3709 uint32_t crc; 3710 uint32_t mchash[2]; 3711 uint32_t rxcfg; 3712 3713 ALC_LOCK_ASSERT(sc); 3714 3715 ifp = sc->alc_ifp; 3716 3717 bzero(mchash, sizeof(mchash)); 3718 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 3719 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3720 if ((ifp->if_flags & IFF_BROADCAST) != 0) 3721 rxcfg |= MAC_CFG_BCAST; 3722 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3723 if ((ifp->if_flags & IFF_PROMISC) != 0) 3724 rxcfg |= MAC_CFG_PROMISC; 3725 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3726 rxcfg |= MAC_CFG_ALLMULTI; 3727 mchash[0] = 0xFFFFFFFF; 3728 mchash[1] = 0xFFFFFFFF; 3729 goto chipit; 3730 } 3731 3732 if_maddr_rlock(ifp); 3733 TAILQ_FOREACH(ifma, &sc->alc_ifp->if_multiaddrs, ifma_link) { 3734 if (ifma->ifma_addr->sa_family != AF_LINK) 3735 continue; 3736 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 3737 ifma->ifma_addr), ETHER_ADDR_LEN); 3738 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3739 } 3740 if_maddr_runlock(ifp); 3741 3742chipit: 3743 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 3744 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 3745 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 3746} 3747 3748static int 3749sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3750{ 3751 int error, value; 3752 3753 if (arg1 == NULL) 3754 return (EINVAL); 3755 value = *(int *)arg1; 3756 error = sysctl_handle_int(oidp, &value, 0, req); 3757 if (error || req->newptr == NULL) 3758 return (error); 3759 if (value < low || value > high) 3760 return (EINVAL); 3761 *(int *)arg1 = value; 3762 3763 return (0); 3764} 3765 3766static int 3767sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS) 3768{ 3769 return (sysctl_int_range(oidp, arg1, arg2, req, 3770 ALC_PROC_MIN, ALC_PROC_MAX)); 3771} 3772 3773static int 3774sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS) 3775{ 3776 3777 return (sysctl_int_range(oidp, arg1, arg2, req, 3778 ALC_IM_TIMER_MIN, ALC_IM_TIMER_MAX)); 3779} 3780