cvmx-usbnx-defs.h revision 215976
1963Sats/***********************license start*************** 24435Sgibbs * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights 38876Srgrimes * reserved. 4963Sats * 54435Sgibbs * 64435Sgibbs * Redistribution and use in source and binary forms, with or without 74435Sgibbs * modification, are permitted provided that the following conditions are 84435Sgibbs * met: 913765Smpp * 108876Srgrimes * * Redistributions of source code must retain the above copyright 114435Sgibbs * notice, this list of conditions and the following disclaimer. 124435Sgibbs * 134435Sgibbs * * Redistributions in binary form must reproduce the above 144435Sgibbs * copyright notice, this list of conditions and the following 154435Sgibbs * disclaimer in the documentation and/or other materials provided 164435Sgibbs * with the distribution. 174435Sgibbs 184435Sgibbs * * Neither the name of Cavium Networks nor the names of 194435Sgibbs * its contributors may be used to endorse or promote products 204435Sgibbs * derived from this software without specific prior written 218876Srgrimes * permission. 2250477Speter 237510Sjkh * This Software, including technical data, may be subject to U.S. export control 244435Sgibbs * laws, including the U.S. Export Administration Act and its associated 254435Sgibbs * regulations, and may be subject to export or import regulations in other 2651673Smdodd * countries. 2751673Smdodd 2816374Snate * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 2951673Smdodd * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS OR 3051673Smdodd * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 3116374Snate * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 3216374Snate * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 334435Sgibbs * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 344435Sgibbs * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 354435Sgibbs * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 364435Sgibbs * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 374435Sgibbs * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38117700Smarkm ***********************license end**************************************/ 3930398Sitojun 404435Sgibbs 414435Sgibbs/** 424435Sgibbs * cvmx-usbnx-defs.h 434435Sgibbs * 444435Sgibbs * Configuration and status register (CSR) type definitions for 4514259Sgibbs * Octeon usbnx. 464435Sgibbs * 474435Sgibbs * This file is auto generated. Do not edit. 484435Sgibbs * 494435Sgibbs * <hr>$Revision$<hr> 504435Sgibbs * 514435Sgibbs */ 524435Sgibbs#ifndef __CVMX_USBNX_TYPEDEFS_H__ 534435Sgibbs#define __CVMX_USBNX_TYPEDEFS_H__ 544435Sgibbs 554435Sgibbs#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 564435Sgibbsstatic inline uint64_t CVMX_USBNX_BIST_STATUS(unsigned long block_id) 574435Sgibbs{ 584435Sgibbs if (!( 594435Sgibbs (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 604435Sgibbs (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 614435Sgibbs (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 62121492Simp (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 63121588Simp (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 644435Sgibbs cvmx_warn("CVMX_USBNX_BIST_STATUS(%lu) is invalid on this chip\n", block_id); 65963Sats return CVMX_ADD_IO_SEG(0x00011800680007F8ull) + ((block_id) & 1) * 0x10000000ull; 664435Sgibbs} 67963Sats#else 6813765Smpp#define CVMX_USBNX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800680007F8ull) + ((block_id) & 1) * 0x10000000ull) 69963Sats#endif 70963Sats#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 71963Satsstatic inline uint64_t CVMX_USBNX_CLK_CTL(unsigned long block_id) 72963Sats{ 73963Sats if (!( 74963Sats (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 75963Sats (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 76963Sats (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 77117700Smarkm (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 78117700Smarkm (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 79117700Smarkm cvmx_warn("CVMX_USBNX_CLK_CTL(%lu) is invalid on this chip\n", block_id); 80963Sats return CVMX_ADD_IO_SEG(0x0001180068000010ull) + ((block_id) & 1) * 0x10000000ull; 81963Sats} 82117700Smarkm#else 83117700Smarkm#define CVMX_USBNX_CLK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180068000010ull) + ((block_id) & 1) * 0x10000000ull) 844435Sgibbs#endif 8554201Smdodd#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 8654201Smdoddstatic inline uint64_t CVMX_USBNX_CTL_STATUS(unsigned long block_id) 8754201Smdodd{ 8854201Smdodd if (!( 8954201Smdodd (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 9054201Smdodd (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 9154201Smdodd (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 92117700Smarkm (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 93117700Smarkm (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 9454201Smdodd cvmx_warn("CVMX_USBNX_CTL_STATUS(%lu) is invalid on this chip\n", block_id); 9554201Smdodd return CVMX_ADD_IO_SEG(0x00016F0000000800ull) + ((block_id) & 1) * 0x100000000000ull; 9654201Smdodd} 97117700Smarkm#else 98117700Smarkm#define CVMX_USBNX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000800ull) + ((block_id) & 1) * 0x100000000000ull) 99117700Smarkm#endif 100117700Smarkm#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 101117700Smarkmstatic inline uint64_t CVMX_USBNX_DMA0_INB_CHN0(unsigned long block_id) 102117700Smarkm{ 103117700Smarkm if (!( 10454201Smdodd (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 105117700Smarkm (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 106117700Smarkm (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 107117700Smarkm (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 108117700Smarkm (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 109117700Smarkm cvmx_warn("CVMX_USBNX_DMA0_INB_CHN0(%lu) is invalid on this chip\n", block_id); 110963Sats return CVMX_ADD_IO_SEG(0x00016F0000000818ull) + ((block_id) & 1) * 0x100000000000ull; 11154201Smdodd} 11254201Smdodd#else 113963Sats#define CVMX_USBNX_DMA0_INB_CHN0(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000818ull) + ((block_id) & 1) * 0x100000000000ull) 114963Sats#endif 115963Sats#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 116963Satsstatic inline uint64_t CVMX_USBNX_DMA0_INB_CHN1(unsigned long block_id) 117963Sats{ 118963Sats if (!( 119963Sats (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 120963Sats (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 121963Sats (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 1224435Sgibbs (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1234435Sgibbs (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 1244435Sgibbs cvmx_warn("CVMX_USBNX_DMA0_INB_CHN1(%lu) is invalid on this chip\n", block_id); 1254435Sgibbs return CVMX_ADD_IO_SEG(0x00016F0000000820ull) + ((block_id) & 1) * 0x100000000000ull; 1264435Sgibbs} 1274435Sgibbs#else 128963Sats#define CVMX_USBNX_DMA0_INB_CHN1(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000820ull) + ((block_id) & 1) * 0x100000000000ull) 129963Sats#endif 130963Sats#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1314435Sgibbsstatic inline uint64_t CVMX_USBNX_DMA0_INB_CHN2(unsigned long block_id) 132963Sats{ 133963Sats if (!( 134963Sats (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 135963Sats (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 136963Sats (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 137121492Simp (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 138963Sats (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 139963Sats cvmx_warn("CVMX_USBNX_DMA0_INB_CHN2(%lu) is invalid on this chip\n", block_id); 140963Sats return CVMX_ADD_IO_SEG(0x00016F0000000828ull) + ((block_id) & 1) * 0x100000000000ull; 141963Sats} 142963Sats#else 143963Sats#define CVMX_USBNX_DMA0_INB_CHN2(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000828ull) + ((block_id) & 1) * 0x100000000000ull) 1444435Sgibbs#endif 145963Sats#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 146963Satsstatic inline uint64_t CVMX_USBNX_DMA0_INB_CHN3(unsigned long block_id) 1474435Sgibbs{ 148963Sats if (!( 1494435Sgibbs (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 1504435Sgibbs (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 151963Sats (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 152963Sats (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 153963Sats (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 154963Sats cvmx_warn("CVMX_USBNX_DMA0_INB_CHN3(%lu) is invalid on this chip\n", block_id); 155963Sats return CVMX_ADD_IO_SEG(0x00016F0000000830ull) + ((block_id) & 1) * 0x100000000000ull; 156963Sats} 157963Sats#else 1584435Sgibbs#define CVMX_USBNX_DMA0_INB_CHN3(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000830ull) + ((block_id) & 1) * 0x100000000000ull) 159121902Simp#endif 160963Sats#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 161963Satsstatic inline uint64_t CVMX_USBNX_DMA0_INB_CHN4(unsigned long block_id) 162963Sats{ 163963Sats if (!( 164963Sats (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 165963Sats (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 166963Sats (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 1674435Sgibbs (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 168963Sats (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 169963Sats cvmx_warn("CVMX_USBNX_DMA0_INB_CHN4(%lu) is invalid on this chip\n", block_id); 1704435Sgibbs return CVMX_ADD_IO_SEG(0x00016F0000000838ull) + ((block_id) & 1) * 0x100000000000ull; 171963Sats} 172963Sats#else 17349070Shosokawa#define CVMX_USBNX_DMA0_INB_CHN4(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000838ull) + ((block_id) & 1) * 0x100000000000ull) 174963Sats#endif 175963Sats#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 176963Satsstatic inline uint64_t CVMX_USBNX_DMA0_INB_CHN5(unsigned long block_id) 177963Sats{ 1784435Sgibbs if (!( 179963Sats (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 180963Sats (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 181963Sats (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 182963Sats (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 183963Sats (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 184963Sats cvmx_warn("CVMX_USBNX_DMA0_INB_CHN5(%lu) is invalid on this chip\n", block_id); 185963Sats return CVMX_ADD_IO_SEG(0x00016F0000000840ull) + ((block_id) & 1) * 0x100000000000ull; 186963Sats} 187963Sats#else 188963Sats#define CVMX_USBNX_DMA0_INB_CHN5(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000840ull) + ((block_id) & 1) * 0x100000000000ull) 1894435Sgibbs#endif 190963Sats#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 191963Satsstatic inline uint64_t CVMX_USBNX_DMA0_INB_CHN6(unsigned long block_id) 192963Sats{ 193963Sats if (!( 194963Sats (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 195963Sats (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 196963Sats (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 197963Sats (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 198963Sats (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 199963Sats cvmx_warn("CVMX_USBNX_DMA0_INB_CHN6(%lu) is invalid on this chip\n", block_id); 2004435Sgibbs return CVMX_ADD_IO_SEG(0x00016F0000000848ull) + ((block_id) & 1) * 0x100000000000ull; 201963Sats} 202963Sats#else 203963Sats#define CVMX_USBNX_DMA0_INB_CHN6(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000848ull) + ((block_id) & 1) * 0x100000000000ull) 204963Sats#endif 205963Sats#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 206963Satsstatic inline uint64_t CVMX_USBNX_DMA0_INB_CHN7(unsigned long block_id) 207963Sats{ 208963Sats if (!( 209963Sats (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 210963Sats (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 211963Sats (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 212963Sats (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 213963Sats (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 214963Sats cvmx_warn("CVMX_USBNX_DMA0_INB_CHN7(%lu) is invalid on this chip\n", block_id); 215963Sats return CVMX_ADD_IO_SEG(0x00016F0000000850ull) + ((block_id) & 1) * 0x100000000000ull; 216963Sats} 217963Sats#else 218963Sats#define CVMX_USBNX_DMA0_INB_CHN7(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000850ull) + ((block_id) & 1) * 0x100000000000ull) 219117700Smarkm#endif 22055834Smdodd#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 22155834Smdoddstatic inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN0(unsigned long block_id) 22255834Smdodd{ 22355834Smdodd if (!( 22455834Smdodd (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 225117700Smarkm (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 22655834Smdodd (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 22755834Smdodd (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 228963Sats (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 229963Sats cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN0(%lu) is invalid on this chip\n", block_id); 230963Sats return CVMX_ADD_IO_SEG(0x00016F0000000858ull) + ((block_id) & 1) * 0x100000000000ull; 231963Sats} 232963Sats#else 233963Sats#define CVMX_USBNX_DMA0_OUTB_CHN0(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000858ull) + ((block_id) & 1) * 0x100000000000ull) 234963Sats#endif 235963Sats#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 2364435Sgibbsstatic inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN1(unsigned long block_id) 2374435Sgibbs{ 238963Sats if (!( 2394435Sgibbs (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 2404435Sgibbs (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 2414435Sgibbs (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 2424435Sgibbs (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 2434435Sgibbs (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 2444435Sgibbs cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN1(%lu) is invalid on this chip\n", block_id); 2454435Sgibbs return CVMX_ADD_IO_SEG(0x00016F0000000860ull) + ((block_id) & 1) * 0x100000000000ull; 2464435Sgibbs} 247963Sats#else 248963Sats#define CVMX_USBNX_DMA0_OUTB_CHN1(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000860ull) + ((block_id) & 1) * 0x100000000000ull) 249963Sats#endif 250963Sats#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 251963Satsstatic inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN2(unsigned long block_id) 252963Sats{ 253963Sats if (!( 254121492Simp (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 255121492Simp (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 256121492Simp (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 257121492Simp (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 258121492Simp (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 259121492Simp cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN2(%lu) is invalid on this chip\n", block_id); 260121492Simp return CVMX_ADD_IO_SEG(0x00016F0000000868ull) + ((block_id) & 1) * 0x100000000000ull; 261121492Simp} 262121492Simp#else 263121492Simp#define CVMX_USBNX_DMA0_OUTB_CHN2(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000868ull) + ((block_id) & 1) * 0x100000000000ull) 264121492Simp#endif 265121492Simp#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 266121492Simpstatic inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN3(unsigned long block_id) 267963Sats{ 268963Sats if (!( 269963Sats (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 270121492Simp (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 271121492Simp (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 272121492Simp (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 273121492Simp (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 274963Sats cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN3(%lu) is invalid on this chip\n", block_id); 275963Sats return CVMX_ADD_IO_SEG(0x00016F0000000870ull) + ((block_id) & 1) * 0x100000000000ull; 276963Sats} 277963Sats#else 278963Sats#define CVMX_USBNX_DMA0_OUTB_CHN3(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000870ull) + ((block_id) & 1) * 0x100000000000ull) 279963Sats#endif 280963Sats#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 281963Satsstatic inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN4(unsigned long block_id) 282963Sats{ 283963Sats if (!( 284963Sats (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 285963Sats (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 286963Sats (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 287963Sats (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 288963Sats (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 289963Sats cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN4(%lu) is invalid on this chip\n", block_id); 290963Sats return CVMX_ADD_IO_SEG(0x00016F0000000878ull) + ((block_id) & 1) * 0x100000000000ull; 291963Sats} 292963Sats#else 293963Sats#define CVMX_USBNX_DMA0_OUTB_CHN4(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000878ull) + ((block_id) & 1) * 0x100000000000ull) 294963Sats#endif 295963Sats#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 296963Satsstatic inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN5(unsigned long block_id) 297963Sats{ 298963Sats if (!( 299963Sats (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 300963Sats (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 301963Sats (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 302963Sats (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 303963Sats (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 304963Sats cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN5(%lu) is invalid on this chip\n", block_id); 305963Sats return CVMX_ADD_IO_SEG(0x00016F0000000880ull) + ((block_id) & 1) * 0x100000000000ull; 306963Sats} 307117700Smarkm#else 3084435Sgibbs#define CVMX_USBNX_DMA0_OUTB_CHN5(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000880ull) + ((block_id) & 1) * 0x100000000000ull) 3094435Sgibbs#endif 310963Sats#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 311963Satsstatic inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN6(unsigned long block_id) 312121515Simp{ 313121492Simp if (!( 3147510Sjkh (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 3157510Sjkh (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 3167510Sjkh (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 3177510Sjkh (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 3187510Sjkh (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 3197510Sjkh cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN6(%lu) is invalid on this chip\n", block_id); 3207510Sjkh return CVMX_ADD_IO_SEG(0x00016F0000000888ull) + ((block_id) & 1) * 0x100000000000ull; 3217510Sjkh} 3227510Sjkh#else 3237510Sjkh#define CVMX_USBNX_DMA0_OUTB_CHN6(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000888ull) + ((block_id) & 1) * 0x100000000000ull) 3247510Sjkh#endif 3257510Sjkh#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 3267510Sjkhstatic inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN7(unsigned long block_id) 3277510Sjkh{ 328121492Simp if (!( 329121492Simp (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 330121492Simp (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 3317510Sjkh (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 332963Sats (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 3338876Srgrimes (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 3344435Sgibbs cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN7(%lu) is invalid on this chip\n", block_id); 335963Sats return CVMX_ADD_IO_SEG(0x00016F0000000890ull) + ((block_id) & 1) * 0x100000000000ull; 336963Sats} 337963Sats#else 338963Sats#define CVMX_USBNX_DMA0_OUTB_CHN7(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000890ull) + ((block_id) & 1) * 0x100000000000ull) 339963Sats#endif 340963Sats#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 341963Satsstatic inline uint64_t CVMX_USBNX_DMA_TEST(unsigned long block_id) 342963Sats{ 343963Sats if (!( 344963Sats (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 345963Sats (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 346963Sats (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 347963Sats (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 348963Sats (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 3494435Sgibbs cvmx_warn("CVMX_USBNX_DMA_TEST(%lu) is invalid on this chip\n", block_id); 3504435Sgibbs return CVMX_ADD_IO_SEG(0x00016F0000000808ull) + ((block_id) & 1) * 0x100000000000ull; 3514435Sgibbs} 3524435Sgibbs#else 3534435Sgibbs#define CVMX_USBNX_DMA_TEST(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000808ull) + ((block_id) & 1) * 0x100000000000ull) 3544435Sgibbs#endif 3554435Sgibbs#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 3564435Sgibbsstatic inline uint64_t CVMX_USBNX_INT_ENB(unsigned long block_id) 357963Sats{ 358963Sats if (!( 3598876Srgrimes (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 3604435Sgibbs (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 361963Sats (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 362963Sats (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 363963Sats (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 364963Sats cvmx_warn("CVMX_USBNX_INT_ENB(%lu) is invalid on this chip\n", block_id); 365963Sats return CVMX_ADD_IO_SEG(0x0001180068000008ull) + ((block_id) & 1) * 0x10000000ull; 366963Sats} 367963Sats#else 368963Sats#define CVMX_USBNX_INT_ENB(block_id) (CVMX_ADD_IO_SEG(0x0001180068000008ull) + ((block_id) & 1) * 0x10000000ull) 369963Sats#endif 370963Sats#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 371963Satsstatic inline uint64_t CVMX_USBNX_INT_SUM(unsigned long block_id) 372963Sats{ 373963Sats if (!( 374963Sats (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 375963Sats (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 376963Sats (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 3774435Sgibbs (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 378963Sats (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 379963Sats cvmx_warn("CVMX_USBNX_INT_SUM(%lu) is invalid on this chip\n", block_id); 380963Sats return CVMX_ADD_IO_SEG(0x0001180068000000ull) + ((block_id) & 1) * 0x10000000ull; 381963Sats} 382963Sats#else 383963Sats#define CVMX_USBNX_INT_SUM(block_id) (CVMX_ADD_IO_SEG(0x0001180068000000ull) + ((block_id) & 1) * 0x10000000ull) 3848876Srgrimes#endif 3854435Sgibbs#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 3864435Sgibbsstatic inline uint64_t CVMX_USBNX_USBP_CTL_STATUS(unsigned long block_id) 3874435Sgibbs{ 3884435Sgibbs if (!( 3894435Sgibbs (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 3904435Sgibbs (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 3914435Sgibbs (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 3924435Sgibbs (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 3934435Sgibbs (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 3944435Sgibbs cvmx_warn("CVMX_USBNX_USBP_CTL_STATUS(%lu) is invalid on this chip\n", block_id); 395121492Simp return CVMX_ADD_IO_SEG(0x0001180068000018ull) + ((block_id) & 1) * 0x10000000ull; 3968876Srgrimes} 3974435Sgibbs#else 3984435Sgibbs#define CVMX_USBNX_USBP_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x0001180068000018ull) + ((block_id) & 1) * 0x10000000ull) 3994435Sgibbs#endif 400121492Simp 401121492Simp/** 402121492Simp * cvmx_usbn#_bist_status 403121492Simp * 4044435Sgibbs * USBN_BIST_STATUS = USBN's Control and Status 4054435Sgibbs * 406963Sats * Contain general control bits and status information for the USBN. 407963Sats */ 408117700Smarkmunion cvmx_usbnx_bist_status 409117700Smarkm{ 410117700Smarkm uint64_t u64; 4114435Sgibbs struct cvmx_usbnx_bist_status_s 4124435Sgibbs { 413963Sats#if __BYTE_ORDER == __BIG_ENDIAN 414963Sats uint64_t reserved_7_63 : 57; 415963Sats uint64_t u2nc_bis : 1; /**< Bist status U2N CTL FIFO Memory. */ 4164435Sgibbs uint64_t u2nf_bis : 1; /**< Bist status U2N FIFO Memory. */ 417963Sats uint64_t e2hc_bis : 1; /**< Bist status E2H CTL FIFO Memory. */ 418 uint64_t n2uf_bis : 1; /**< Bist status N2U FIFO Memory. */ 419 uint64_t usbc_bis : 1; /**< Bist status USBC FIFO Memory. */ 420 uint64_t nif_bis : 1; /**< Bist status for Inbound Memory. */ 421 uint64_t nof_bis : 1; /**< Bist status for Outbound Memory. */ 422#else 423 uint64_t nof_bis : 1; 424 uint64_t nif_bis : 1; 425 uint64_t usbc_bis : 1; 426 uint64_t n2uf_bis : 1; 427 uint64_t e2hc_bis : 1; 428 uint64_t u2nf_bis : 1; 429 uint64_t u2nc_bis : 1; 430 uint64_t reserved_7_63 : 57; 431#endif 432 } s; 433 struct cvmx_usbnx_bist_status_cn30xx 434 { 435#if __BYTE_ORDER == __BIG_ENDIAN 436 uint64_t reserved_3_63 : 61; 437 uint64_t usbc_bis : 1; /**< Bist status USBC FIFO Memory. */ 438 uint64_t nif_bis : 1; /**< Bist status for Inbound Memory. */ 439 uint64_t nof_bis : 1; /**< Bist status for Outbound Memory. */ 440#else 441 uint64_t nof_bis : 1; 442 uint64_t nif_bis : 1; 443 uint64_t usbc_bis : 1; 444 uint64_t reserved_3_63 : 61; 445#endif 446 } cn30xx; 447 struct cvmx_usbnx_bist_status_cn30xx cn31xx; 448 struct cvmx_usbnx_bist_status_s cn50xx; 449 struct cvmx_usbnx_bist_status_s cn52xx; 450 struct cvmx_usbnx_bist_status_s cn52xxp1; 451 struct cvmx_usbnx_bist_status_s cn56xx; 452 struct cvmx_usbnx_bist_status_s cn56xxp1; 453}; 454typedef union cvmx_usbnx_bist_status cvmx_usbnx_bist_status_t; 455 456/** 457 * cvmx_usbn#_clk_ctl 458 * 459 * USBN_CLK_CTL = USBN's Clock Control 460 * 461 * This register is used to control the frequency of the hclk and the hreset and phy_rst signals. 462 */ 463union cvmx_usbnx_clk_ctl 464{ 465 uint64_t u64; 466 struct cvmx_usbnx_clk_ctl_s 467 { 468#if __BYTE_ORDER == __BIG_ENDIAN 469 uint64_t reserved_20_63 : 44; 470 uint64_t divide2 : 2; /**< The 'hclk' used by the USB subsystem is derived 471 from the eclk. 472 Also see the field DIVIDE. DIVIDE2<1> must currently 473 be zero because it is not implemented, so the maximum 474 ratio of eclk/hclk is currently 16. 475 The actual divide number for hclk is: 476 (DIVIDE2 + 1) * (DIVIDE + 1) */ 477 uint64_t hclk_rst : 1; /**< When this field is '0' the HCLK-DIVIDER used to 478 generate the hclk in the USB Subsystem is held 479 in reset. This bit must be set to '0' before 480 changing the value os DIVIDE in this register. 481 The reset to the HCLK_DIVIDERis also asserted 482 when core reset is asserted. */ 483 uint64_t p_x_on : 1; /**< Force USB-PHY on during suspend. 484 '1' USB-PHY XO block is powered-down during 485 suspend. 486 '0' USB-PHY XO block is powered-up during 487 suspend. 488 The value of this field must be set while POR is 489 active. */ 490 uint64_t reserved_14_15 : 2; 491 uint64_t p_com_on : 1; /**< '0' Force USB-PHY XO Bias, Bandgap and PLL to 492 remain powered in Suspend Mode. 493 '1' The USB-PHY XO Bias, Bandgap and PLL are 494 powered down in suspend mode. 495 The value of this field must be set while POR is 496 active. */ 497 uint64_t p_c_sel : 2; /**< Phy clock speed select. 498 Selects the reference clock / crystal frequency. 499 '11': Reserved 500 '10': 48 MHz (reserved when a crystal is used) 501 '01': 24 MHz (reserved when a crystal is used) 502 '00': 12 MHz 503 The value of this field must be set while POR is 504 active. 505 NOTE: if a crystal is used as a reference clock, 506 this field must be set to 12 MHz. */ 507 uint64_t cdiv_byp : 1; /**< Used to enable the bypass input to the USB_CLK_DIV. */ 508 uint64_t sd_mode : 2; /**< Scaledown mode for the USBC. Control timing events 509 in the USBC, for normal operation this must be '0'. */ 510 uint64_t s_bist : 1; /**< Starts bist on the hclk memories, during the '0' 511 to '1' transition. */ 512 uint64_t por : 1; /**< Power On Reset for the PHY. 513 Resets all the PHYS registers and state machines. */ 514 uint64_t enable : 1; /**< When '1' allows the generation of the hclk. When 515 '0' the hclk will not be generated. SEE DIVIDE 516 field of this register. */ 517 uint64_t prst : 1; /**< When this field is '0' the reset associated with 518 the phy_clk functionality in the USB Subsystem is 519 help in reset. This bit should not be set to '1' 520 until the time it takes 6 clocks (hclk or phy_clk, 521 whichever is slower) has passed. Under normal 522 operation once this bit is set to '1' it should not 523 be set to '0'. */ 524 uint64_t hrst : 1; /**< When this field is '0' the reset associated with 525 the hclk functioanlity in the USB Subsystem is 526 held in reset.This bit should not be set to '1' 527 until 12ms after phy_clk is stable. Under normal 528 operation, once this bit is set to '1' it should 529 not be set to '0'. */ 530 uint64_t divide : 3; /**< The frequency of 'hclk' used by the USB subsystem 531 is the eclk frequency divided by the value of 532 (DIVIDE2 + 1) * (DIVIDE + 1), also see the field 533 DIVIDE2 of this register. 534 The hclk frequency should be less than 125Mhz. 535 After writing a value to this field the SW should 536 read the field for the value written. 537 The ENABLE field of this register should not be set 538 until AFTER this field is set and then read. */ 539#else 540 uint64_t divide : 3; 541 uint64_t hrst : 1; 542 uint64_t prst : 1; 543 uint64_t enable : 1; 544 uint64_t por : 1; 545 uint64_t s_bist : 1; 546 uint64_t sd_mode : 2; 547 uint64_t cdiv_byp : 1; 548 uint64_t p_c_sel : 2; 549 uint64_t p_com_on : 1; 550 uint64_t reserved_14_15 : 2; 551 uint64_t p_x_on : 1; 552 uint64_t hclk_rst : 1; 553 uint64_t divide2 : 2; 554 uint64_t reserved_20_63 : 44; 555#endif 556 } s; 557 struct cvmx_usbnx_clk_ctl_cn30xx 558 { 559#if __BYTE_ORDER == __BIG_ENDIAN 560 uint64_t reserved_18_63 : 46; 561 uint64_t hclk_rst : 1; /**< When this field is '0' the HCLK-DIVIDER used to 562 generate the hclk in the USB Subsystem is held 563 in reset. This bit must be set to '0' before 564 changing the value os DIVIDE in this register. 565 The reset to the HCLK_DIVIDERis also asserted 566 when core reset is asserted. */ 567 uint64_t p_x_on : 1; /**< Force USB-PHY on during suspend. 568 '1' USB-PHY XO block is powered-down during 569 suspend. 570 '0' USB-PHY XO block is powered-up during 571 suspend. 572 The value of this field must be set while POR is 573 active. */ 574 uint64_t p_rclk : 1; /**< Phy refrence clock enable. 575 '1' The PHY PLL uses the XO block output as a 576 reference. 577 '0' Reserved. */ 578 uint64_t p_xenbn : 1; /**< Phy external clock enable. 579 '1' The XO block uses the clock from a crystal. 580 '0' The XO block uses an external clock supplied 581 on the XO pin. USB_XI should be tied to 582 ground for this usage. */ 583 uint64_t p_com_on : 1; /**< '0' Force USB-PHY XO Bias, Bandgap and PLL to 584 remain powered in Suspend Mode. 585 '1' The USB-PHY XO Bias, Bandgap and PLL are 586 powered down in suspend mode. 587 The value of this field must be set while POR is 588 active. */ 589 uint64_t p_c_sel : 2; /**< Phy clock speed select. 590 Selects the reference clock / crystal frequency. 591 '11': Reserved 592 '10': 48 MHz 593 '01': 24 MHz 594 '00': 12 MHz 595 The value of this field must be set while POR is 596 active. */ 597 uint64_t cdiv_byp : 1; /**< Used to enable the bypass input to the USB_CLK_DIV. */ 598 uint64_t sd_mode : 2; /**< Scaledown mode for the USBC. Control timing events 599 in the USBC, for normal operation this must be '0'. */ 600 uint64_t s_bist : 1; /**< Starts bist on the hclk memories, during the '0' 601 to '1' transition. */ 602 uint64_t por : 1; /**< Power On Reset for the PHY. 603 Resets all the PHYS registers and state machines. */ 604 uint64_t enable : 1; /**< When '1' allows the generation of the hclk. When 605 '0' the hclk will not be generated. */ 606 uint64_t prst : 1; /**< When this field is '0' the reset associated with 607 the phy_clk functionality in the USB Subsystem is 608 help in reset. This bit should not be set to '1' 609 until the time it takes 6 clocks (hclk or phy_clk, 610 whichever is slower) has passed. Under normal 611 operation once this bit is set to '1' it should not 612 be set to '0'. */ 613 uint64_t hrst : 1; /**< When this field is '0' the reset associated with 614 the hclk functioanlity in the USB Subsystem is 615 held in reset.This bit should not be set to '1' 616 until 12ms after phy_clk is stable. Under normal 617 operation, once this bit is set to '1' it should 618 not be set to '0'. */ 619 uint64_t divide : 3; /**< The 'hclk' used by the USB subsystem is derived 620 from the eclk. The eclk will be divided by the 621 value of this field +1 to determine the hclk 622 frequency. (Also see HRST of this register). 623 The hclk frequency must be less than 125 MHz. */ 624#else 625 uint64_t divide : 3; 626 uint64_t hrst : 1; 627 uint64_t prst : 1; 628 uint64_t enable : 1; 629 uint64_t por : 1; 630 uint64_t s_bist : 1; 631 uint64_t sd_mode : 2; 632 uint64_t cdiv_byp : 1; 633 uint64_t p_c_sel : 2; 634 uint64_t p_com_on : 1; 635 uint64_t p_xenbn : 1; 636 uint64_t p_rclk : 1; 637 uint64_t p_x_on : 1; 638 uint64_t hclk_rst : 1; 639 uint64_t reserved_18_63 : 46; 640#endif 641 } cn30xx; 642 struct cvmx_usbnx_clk_ctl_cn30xx cn31xx; 643 struct cvmx_usbnx_clk_ctl_cn50xx 644 { 645#if __BYTE_ORDER == __BIG_ENDIAN 646 uint64_t reserved_20_63 : 44; 647 uint64_t divide2 : 2; /**< The 'hclk' used by the USB subsystem is derived 648 from the eclk. 649 Also see the field DIVIDE. DIVIDE2<1> must currently 650 be zero because it is not implemented, so the maximum 651 ratio of eclk/hclk is currently 16. 652 The actual divide number for hclk is: 653 (DIVIDE2 + 1) * (DIVIDE + 1) */ 654 uint64_t hclk_rst : 1; /**< When this field is '0' the HCLK-DIVIDER used to 655 generate the hclk in the USB Subsystem is held 656 in reset. This bit must be set to '0' before 657 changing the value os DIVIDE in this register. 658 The reset to the HCLK_DIVIDERis also asserted 659 when core reset is asserted. */ 660 uint64_t reserved_16_16 : 1; 661 uint64_t p_rtype : 2; /**< PHY reference clock type 662 '0' The USB-PHY uses a 12MHz crystal as a clock 663 source at the USB_XO and USB_XI pins 664 '1' Reserved 665 '2' The USB_PHY uses 12/24/48MHz 2.5V board clock 666 at the USB_XO pin. USB_XI should be tied to 667 ground in this case. 668 '3' Reserved 669 (bit 14 was P_XENBN on 3xxx) 670 (bit 15 was P_RCLK on 3xxx) */ 671 uint64_t p_com_on : 1; /**< '0' Force USB-PHY XO Bias, Bandgap and PLL to 672 remain powered in Suspend Mode. 673 '1' The USB-PHY XO Bias, Bandgap and PLL are 674 powered down in suspend mode. 675 The value of this field must be set while POR is 676 active. */ 677 uint64_t p_c_sel : 2; /**< Phy clock speed select. 678 Selects the reference clock / crystal frequency. 679 '11': Reserved 680 '10': 48 MHz (reserved when a crystal is used) 681 '01': 24 MHz (reserved when a crystal is used) 682 '00': 12 MHz 683 The value of this field must be set while POR is 684 active. 685 NOTE: if a crystal is used as a reference clock, 686 this field must be set to 12 MHz. */ 687 uint64_t cdiv_byp : 1; /**< Used to enable the bypass input to the USB_CLK_DIV. */ 688 uint64_t sd_mode : 2; /**< Scaledown mode for the USBC. Control timing events 689 in the USBC, for normal operation this must be '0'. */ 690 uint64_t s_bist : 1; /**< Starts bist on the hclk memories, during the '0' 691 to '1' transition. */ 692 uint64_t por : 1; /**< Power On Reset for the PHY. 693 Resets all the PHYS registers and state machines. */ 694 uint64_t enable : 1; /**< When '1' allows the generation of the hclk. When 695 '0' the hclk will not be generated. SEE DIVIDE 696 field of this register. */ 697 uint64_t prst : 1; /**< When this field is '0' the reset associated with 698 the phy_clk functionality in the USB Subsystem is 699 help in reset. This bit should not be set to '1' 700 until the time it takes 6 clocks (hclk or phy_clk, 701 whichever is slower) has passed. Under normal 702 operation once this bit is set to '1' it should not 703 be set to '0'. */ 704 uint64_t hrst : 1; /**< When this field is '0' the reset associated with 705 the hclk functioanlity in the USB Subsystem is 706 held in reset.This bit should not be set to '1' 707 until 12ms after phy_clk is stable. Under normal 708 operation, once this bit is set to '1' it should 709 not be set to '0'. */ 710 uint64_t divide : 3; /**< The frequency of 'hclk' used by the USB subsystem 711 is the eclk frequency divided by the value of 712 (DIVIDE2 + 1) * (DIVIDE + 1), also see the field 713 DIVIDE2 of this register. 714 The hclk frequency should be less than 125Mhz. 715 After writing a value to this field the SW should 716 read the field for the value written. 717 The ENABLE field of this register should not be set 718 until AFTER this field is set and then read. */ 719#else 720 uint64_t divide : 3; 721 uint64_t hrst : 1; 722 uint64_t prst : 1; 723 uint64_t enable : 1; 724 uint64_t por : 1; 725 uint64_t s_bist : 1; 726 uint64_t sd_mode : 2; 727 uint64_t cdiv_byp : 1; 728 uint64_t p_c_sel : 2; 729 uint64_t p_com_on : 1; 730 uint64_t p_rtype : 2; 731 uint64_t reserved_16_16 : 1; 732 uint64_t hclk_rst : 1; 733 uint64_t divide2 : 2; 734 uint64_t reserved_20_63 : 44; 735#endif 736 } cn50xx; 737 struct cvmx_usbnx_clk_ctl_cn50xx cn52xx; 738 struct cvmx_usbnx_clk_ctl_cn50xx cn52xxp1; 739 struct cvmx_usbnx_clk_ctl_cn50xx cn56xx; 740 struct cvmx_usbnx_clk_ctl_cn50xx cn56xxp1; 741}; 742typedef union cvmx_usbnx_clk_ctl cvmx_usbnx_clk_ctl_t; 743 744/** 745 * cvmx_usbn#_ctl_status 746 * 747 * USBN_CTL_STATUS = USBN's Control And Status Register 748 * 749 * Contains general control and status information for the USBN block. 750 */ 751union cvmx_usbnx_ctl_status 752{ 753 uint64_t u64; 754 struct cvmx_usbnx_ctl_status_s 755 { 756#if __BYTE_ORDER == __BIG_ENDIAN 757 uint64_t reserved_6_63 : 58; 758 uint64_t dma_0pag : 1; /**< When '1' sets the DMA engine will set the zero-Page 759 bit in the L2C store operation to the IOB. */ 760 uint64_t dma_stt : 1; /**< When '1' sets the DMA engine to use STT operations. */ 761 uint64_t dma_test : 1; /**< When '1' sets the DMA engine into Test-Mode. 762 For normal operation this bit should be '0'. */ 763 uint64_t inv_a2 : 1; /**< When '1' causes the address[2] driven on the AHB 764 for USB-CORE FIFO access to be inverted. Also data 765 writen to and read from the AHB will have it byte 766 order swapped. If the orginal order was A-B-C-D the 767 new byte order will be D-C-B-A. */ 768 uint64_t l2c_emod : 2; /**< Endian format for data from/to the L2C. 769 IN: A-B-C-D-E-F-G-H 770 OUT0: A-B-C-D-E-F-G-H 771 OUT1: H-G-F-E-D-C-B-A 772 OUT2: D-C-B-A-H-G-F-E 773 OUT3: E-F-G-H-A-B-C-D */ 774#else 775 uint64_t l2c_emod : 2; 776 uint64_t inv_a2 : 1; 777 uint64_t dma_test : 1; 778 uint64_t dma_stt : 1; 779 uint64_t dma_0pag : 1; 780 uint64_t reserved_6_63 : 58; 781#endif 782 } s; 783 struct cvmx_usbnx_ctl_status_s cn30xx; 784 struct cvmx_usbnx_ctl_status_s cn31xx; 785 struct cvmx_usbnx_ctl_status_s cn50xx; 786 struct cvmx_usbnx_ctl_status_s cn52xx; 787 struct cvmx_usbnx_ctl_status_s cn52xxp1; 788 struct cvmx_usbnx_ctl_status_s cn56xx; 789 struct cvmx_usbnx_ctl_status_s cn56xxp1; 790}; 791typedef union cvmx_usbnx_ctl_status cvmx_usbnx_ctl_status_t; 792 793/** 794 * cvmx_usbn#_dma0_inb_chn0 795 * 796 * USBN_DMA0_INB_CHN0 = USBN's Inbound DMA for USB0 Channel0 797 * 798 * Contains the starting address for use when USB0 writes to L2C via Channel0. 799 * Writing of this register sets the base address. 800 */ 801union cvmx_usbnx_dma0_inb_chn0 802{ 803 uint64_t u64; 804 struct cvmx_usbnx_dma0_inb_chn0_s 805 { 806#if __BYTE_ORDER == __BIG_ENDIAN 807 uint64_t reserved_36_63 : 28; 808 uint64_t addr : 36; /**< Base address for DMA Write to L2C. */ 809#else 810 uint64_t addr : 36; 811 uint64_t reserved_36_63 : 28; 812#endif 813 } s; 814 struct cvmx_usbnx_dma0_inb_chn0_s cn30xx; 815 struct cvmx_usbnx_dma0_inb_chn0_s cn31xx; 816 struct cvmx_usbnx_dma0_inb_chn0_s cn50xx; 817 struct cvmx_usbnx_dma0_inb_chn0_s cn52xx; 818 struct cvmx_usbnx_dma0_inb_chn0_s cn52xxp1; 819 struct cvmx_usbnx_dma0_inb_chn0_s cn56xx; 820 struct cvmx_usbnx_dma0_inb_chn0_s cn56xxp1; 821}; 822typedef union cvmx_usbnx_dma0_inb_chn0 cvmx_usbnx_dma0_inb_chn0_t; 823 824/** 825 * cvmx_usbn#_dma0_inb_chn1 826 * 827 * USBN_DMA0_INB_CHN1 = USBN's Inbound DMA for USB0 Channel1 828 * 829 * Contains the starting address for use when USB0 writes to L2C via Channel1. 830 * Writing of this register sets the base address. 831 */ 832union cvmx_usbnx_dma0_inb_chn1 833{ 834 uint64_t u64; 835 struct cvmx_usbnx_dma0_inb_chn1_s 836 { 837#if __BYTE_ORDER == __BIG_ENDIAN 838 uint64_t reserved_36_63 : 28; 839 uint64_t addr : 36; /**< Base address for DMA Write to L2C. */ 840#else 841 uint64_t addr : 36; 842 uint64_t reserved_36_63 : 28; 843#endif 844 } s; 845 struct cvmx_usbnx_dma0_inb_chn1_s cn30xx; 846 struct cvmx_usbnx_dma0_inb_chn1_s cn31xx; 847 struct cvmx_usbnx_dma0_inb_chn1_s cn50xx; 848 struct cvmx_usbnx_dma0_inb_chn1_s cn52xx; 849 struct cvmx_usbnx_dma0_inb_chn1_s cn52xxp1; 850 struct cvmx_usbnx_dma0_inb_chn1_s cn56xx; 851 struct cvmx_usbnx_dma0_inb_chn1_s cn56xxp1; 852}; 853typedef union cvmx_usbnx_dma0_inb_chn1 cvmx_usbnx_dma0_inb_chn1_t; 854 855/** 856 * cvmx_usbn#_dma0_inb_chn2 857 * 858 * USBN_DMA0_INB_CHN2 = USBN's Inbound DMA for USB0 Channel2 859 * 860 * Contains the starting address for use when USB0 writes to L2C via Channel2. 861 * Writing of this register sets the base address. 862 */ 863union cvmx_usbnx_dma0_inb_chn2 864{ 865 uint64_t u64; 866 struct cvmx_usbnx_dma0_inb_chn2_s 867 { 868#if __BYTE_ORDER == __BIG_ENDIAN 869 uint64_t reserved_36_63 : 28; 870 uint64_t addr : 36; /**< Base address for DMA Write to L2C. */ 871#else 872 uint64_t addr : 36; 873 uint64_t reserved_36_63 : 28; 874#endif 875 } s; 876 struct cvmx_usbnx_dma0_inb_chn2_s cn30xx; 877 struct cvmx_usbnx_dma0_inb_chn2_s cn31xx; 878 struct cvmx_usbnx_dma0_inb_chn2_s cn50xx; 879 struct cvmx_usbnx_dma0_inb_chn2_s cn52xx; 880 struct cvmx_usbnx_dma0_inb_chn2_s cn52xxp1; 881 struct cvmx_usbnx_dma0_inb_chn2_s cn56xx; 882 struct cvmx_usbnx_dma0_inb_chn2_s cn56xxp1; 883}; 884typedef union cvmx_usbnx_dma0_inb_chn2 cvmx_usbnx_dma0_inb_chn2_t; 885 886/** 887 * cvmx_usbn#_dma0_inb_chn3 888 * 889 * USBN_DMA0_INB_CHN3 = USBN's Inbound DMA for USB0 Channel3 890 * 891 * Contains the starting address for use when USB0 writes to L2C via Channel3. 892 * Writing of this register sets the base address. 893 */ 894union cvmx_usbnx_dma0_inb_chn3 895{ 896 uint64_t u64; 897 struct cvmx_usbnx_dma0_inb_chn3_s 898 { 899#if __BYTE_ORDER == __BIG_ENDIAN 900 uint64_t reserved_36_63 : 28; 901 uint64_t addr : 36; /**< Base address for DMA Write to L2C. */ 902#else 903 uint64_t addr : 36; 904 uint64_t reserved_36_63 : 28; 905#endif 906 } s; 907 struct cvmx_usbnx_dma0_inb_chn3_s cn30xx; 908 struct cvmx_usbnx_dma0_inb_chn3_s cn31xx; 909 struct cvmx_usbnx_dma0_inb_chn3_s cn50xx; 910 struct cvmx_usbnx_dma0_inb_chn3_s cn52xx; 911 struct cvmx_usbnx_dma0_inb_chn3_s cn52xxp1; 912 struct cvmx_usbnx_dma0_inb_chn3_s cn56xx; 913 struct cvmx_usbnx_dma0_inb_chn3_s cn56xxp1; 914}; 915typedef union cvmx_usbnx_dma0_inb_chn3 cvmx_usbnx_dma0_inb_chn3_t; 916 917/** 918 * cvmx_usbn#_dma0_inb_chn4 919 * 920 * USBN_DMA0_INB_CHN4 = USBN's Inbound DMA for USB0 Channel4 921 * 922 * Contains the starting address for use when USB0 writes to L2C via Channel4. 923 * Writing of this register sets the base address. 924 */ 925union cvmx_usbnx_dma0_inb_chn4 926{ 927 uint64_t u64; 928 struct cvmx_usbnx_dma0_inb_chn4_s 929 { 930#if __BYTE_ORDER == __BIG_ENDIAN 931 uint64_t reserved_36_63 : 28; 932 uint64_t addr : 36; /**< Base address for DMA Write to L2C. */ 933#else 934 uint64_t addr : 36; 935 uint64_t reserved_36_63 : 28; 936#endif 937 } s; 938 struct cvmx_usbnx_dma0_inb_chn4_s cn30xx; 939 struct cvmx_usbnx_dma0_inb_chn4_s cn31xx; 940 struct cvmx_usbnx_dma0_inb_chn4_s cn50xx; 941 struct cvmx_usbnx_dma0_inb_chn4_s cn52xx; 942 struct cvmx_usbnx_dma0_inb_chn4_s cn52xxp1; 943 struct cvmx_usbnx_dma0_inb_chn4_s cn56xx; 944 struct cvmx_usbnx_dma0_inb_chn4_s cn56xxp1; 945}; 946typedef union cvmx_usbnx_dma0_inb_chn4 cvmx_usbnx_dma0_inb_chn4_t; 947 948/** 949 * cvmx_usbn#_dma0_inb_chn5 950 * 951 * USBN_DMA0_INB_CHN5 = USBN's Inbound DMA for USB0 Channel5 952 * 953 * Contains the starting address for use when USB0 writes to L2C via Channel5. 954 * Writing of this register sets the base address. 955 */ 956union cvmx_usbnx_dma0_inb_chn5 957{ 958 uint64_t u64; 959 struct cvmx_usbnx_dma0_inb_chn5_s 960 { 961#if __BYTE_ORDER == __BIG_ENDIAN 962 uint64_t reserved_36_63 : 28; 963 uint64_t addr : 36; /**< Base address for DMA Write to L2C. */ 964#else 965 uint64_t addr : 36; 966 uint64_t reserved_36_63 : 28; 967#endif 968 } s; 969 struct cvmx_usbnx_dma0_inb_chn5_s cn30xx; 970 struct cvmx_usbnx_dma0_inb_chn5_s cn31xx; 971 struct cvmx_usbnx_dma0_inb_chn5_s cn50xx; 972 struct cvmx_usbnx_dma0_inb_chn5_s cn52xx; 973 struct cvmx_usbnx_dma0_inb_chn5_s cn52xxp1; 974 struct cvmx_usbnx_dma0_inb_chn5_s cn56xx; 975 struct cvmx_usbnx_dma0_inb_chn5_s cn56xxp1; 976}; 977typedef union cvmx_usbnx_dma0_inb_chn5 cvmx_usbnx_dma0_inb_chn5_t; 978 979/** 980 * cvmx_usbn#_dma0_inb_chn6 981 * 982 * USBN_DMA0_INB_CHN6 = USBN's Inbound DMA for USB0 Channel6 983 * 984 * Contains the starting address for use when USB0 writes to L2C via Channel6. 985 * Writing of this register sets the base address. 986 */ 987union cvmx_usbnx_dma0_inb_chn6 988{ 989 uint64_t u64; 990 struct cvmx_usbnx_dma0_inb_chn6_s 991 { 992#if __BYTE_ORDER == __BIG_ENDIAN 993 uint64_t reserved_36_63 : 28; 994 uint64_t addr : 36; /**< Base address for DMA Write to L2C. */ 995#else 996 uint64_t addr : 36; 997 uint64_t reserved_36_63 : 28; 998#endif 999 } s; 1000 struct cvmx_usbnx_dma0_inb_chn6_s cn30xx; 1001 struct cvmx_usbnx_dma0_inb_chn6_s cn31xx; 1002 struct cvmx_usbnx_dma0_inb_chn6_s cn50xx; 1003 struct cvmx_usbnx_dma0_inb_chn6_s cn52xx; 1004 struct cvmx_usbnx_dma0_inb_chn6_s cn52xxp1; 1005 struct cvmx_usbnx_dma0_inb_chn6_s cn56xx; 1006 struct cvmx_usbnx_dma0_inb_chn6_s cn56xxp1; 1007}; 1008typedef union cvmx_usbnx_dma0_inb_chn6 cvmx_usbnx_dma0_inb_chn6_t; 1009 1010/** 1011 * cvmx_usbn#_dma0_inb_chn7 1012 * 1013 * USBN_DMA0_INB_CHN7 = USBN's Inbound DMA for USB0 Channel7 1014 * 1015 * Contains the starting address for use when USB0 writes to L2C via Channel7. 1016 * Writing of this register sets the base address. 1017 */ 1018union cvmx_usbnx_dma0_inb_chn7 1019{ 1020 uint64_t u64; 1021 struct cvmx_usbnx_dma0_inb_chn7_s 1022 { 1023#if __BYTE_ORDER == __BIG_ENDIAN 1024 uint64_t reserved_36_63 : 28; 1025 uint64_t addr : 36; /**< Base address for DMA Write to L2C. */ 1026#else 1027 uint64_t addr : 36; 1028 uint64_t reserved_36_63 : 28; 1029#endif 1030 } s; 1031 struct cvmx_usbnx_dma0_inb_chn7_s cn30xx; 1032 struct cvmx_usbnx_dma0_inb_chn7_s cn31xx; 1033 struct cvmx_usbnx_dma0_inb_chn7_s cn50xx; 1034 struct cvmx_usbnx_dma0_inb_chn7_s cn52xx; 1035 struct cvmx_usbnx_dma0_inb_chn7_s cn52xxp1; 1036 struct cvmx_usbnx_dma0_inb_chn7_s cn56xx; 1037 struct cvmx_usbnx_dma0_inb_chn7_s cn56xxp1; 1038}; 1039typedef union cvmx_usbnx_dma0_inb_chn7 cvmx_usbnx_dma0_inb_chn7_t; 1040 1041/** 1042 * cvmx_usbn#_dma0_outb_chn0 1043 * 1044 * USBN_DMA0_OUTB_CHN0 = USBN's Outbound DMA for USB0 Channel0 1045 * 1046 * Contains the starting address for use when USB0 reads from L2C via Channel0. 1047 * Writing of this register sets the base address. 1048 */ 1049union cvmx_usbnx_dma0_outb_chn0 1050{ 1051 uint64_t u64; 1052 struct cvmx_usbnx_dma0_outb_chn0_s 1053 { 1054#if __BYTE_ORDER == __BIG_ENDIAN 1055 uint64_t reserved_36_63 : 28; 1056 uint64_t addr : 36; /**< Base address for DMA Read from L2C. */ 1057#else 1058 uint64_t addr : 36; 1059 uint64_t reserved_36_63 : 28; 1060#endif 1061 } s; 1062 struct cvmx_usbnx_dma0_outb_chn0_s cn30xx; 1063 struct cvmx_usbnx_dma0_outb_chn0_s cn31xx; 1064 struct cvmx_usbnx_dma0_outb_chn0_s cn50xx; 1065 struct cvmx_usbnx_dma0_outb_chn0_s cn52xx; 1066 struct cvmx_usbnx_dma0_outb_chn0_s cn52xxp1; 1067 struct cvmx_usbnx_dma0_outb_chn0_s cn56xx; 1068 struct cvmx_usbnx_dma0_outb_chn0_s cn56xxp1; 1069}; 1070typedef union cvmx_usbnx_dma0_outb_chn0 cvmx_usbnx_dma0_outb_chn0_t; 1071 1072/** 1073 * cvmx_usbn#_dma0_outb_chn1 1074 * 1075 * USBN_DMA0_OUTB_CHN1 = USBN's Outbound DMA for USB0 Channel1 1076 * 1077 * Contains the starting address for use when USB0 reads from L2C via Channel1. 1078 * Writing of this register sets the base address. 1079 */ 1080union cvmx_usbnx_dma0_outb_chn1 1081{ 1082 uint64_t u64; 1083 struct cvmx_usbnx_dma0_outb_chn1_s 1084 { 1085#if __BYTE_ORDER == __BIG_ENDIAN 1086 uint64_t reserved_36_63 : 28; 1087 uint64_t addr : 36; /**< Base address for DMA Read from L2C. */ 1088#else 1089 uint64_t addr : 36; 1090 uint64_t reserved_36_63 : 28; 1091#endif 1092 } s; 1093 struct cvmx_usbnx_dma0_outb_chn1_s cn30xx; 1094 struct cvmx_usbnx_dma0_outb_chn1_s cn31xx; 1095 struct cvmx_usbnx_dma0_outb_chn1_s cn50xx; 1096 struct cvmx_usbnx_dma0_outb_chn1_s cn52xx; 1097 struct cvmx_usbnx_dma0_outb_chn1_s cn52xxp1; 1098 struct cvmx_usbnx_dma0_outb_chn1_s cn56xx; 1099 struct cvmx_usbnx_dma0_outb_chn1_s cn56xxp1; 1100}; 1101typedef union cvmx_usbnx_dma0_outb_chn1 cvmx_usbnx_dma0_outb_chn1_t; 1102 1103/** 1104 * cvmx_usbn#_dma0_outb_chn2 1105 * 1106 * USBN_DMA0_OUTB_CHN2 = USBN's Outbound DMA for USB0 Channel2 1107 * 1108 * Contains the starting address for use when USB0 reads from L2C via Channel2. 1109 * Writing of this register sets the base address. 1110 */ 1111union cvmx_usbnx_dma0_outb_chn2 1112{ 1113 uint64_t u64; 1114 struct cvmx_usbnx_dma0_outb_chn2_s 1115 { 1116#if __BYTE_ORDER == __BIG_ENDIAN 1117 uint64_t reserved_36_63 : 28; 1118 uint64_t addr : 36; /**< Base address for DMA Read from L2C. */ 1119#else 1120 uint64_t addr : 36; 1121 uint64_t reserved_36_63 : 28; 1122#endif 1123 } s; 1124 struct cvmx_usbnx_dma0_outb_chn2_s cn30xx; 1125 struct cvmx_usbnx_dma0_outb_chn2_s cn31xx; 1126 struct cvmx_usbnx_dma0_outb_chn2_s cn50xx; 1127 struct cvmx_usbnx_dma0_outb_chn2_s cn52xx; 1128 struct cvmx_usbnx_dma0_outb_chn2_s cn52xxp1; 1129 struct cvmx_usbnx_dma0_outb_chn2_s cn56xx; 1130 struct cvmx_usbnx_dma0_outb_chn2_s cn56xxp1; 1131}; 1132typedef union cvmx_usbnx_dma0_outb_chn2 cvmx_usbnx_dma0_outb_chn2_t; 1133 1134/** 1135 * cvmx_usbn#_dma0_outb_chn3 1136 * 1137 * USBN_DMA0_OUTB_CHN3 = USBN's Outbound DMA for USB0 Channel3 1138 * 1139 * Contains the starting address for use when USB0 reads from L2C via Channel3. 1140 * Writing of this register sets the base address. 1141 */ 1142union cvmx_usbnx_dma0_outb_chn3 1143{ 1144 uint64_t u64; 1145 struct cvmx_usbnx_dma0_outb_chn3_s 1146 { 1147#if __BYTE_ORDER == __BIG_ENDIAN 1148 uint64_t reserved_36_63 : 28; 1149 uint64_t addr : 36; /**< Base address for DMA Read from L2C. */ 1150#else 1151 uint64_t addr : 36; 1152 uint64_t reserved_36_63 : 28; 1153#endif 1154 } s; 1155 struct cvmx_usbnx_dma0_outb_chn3_s cn30xx; 1156 struct cvmx_usbnx_dma0_outb_chn3_s cn31xx; 1157 struct cvmx_usbnx_dma0_outb_chn3_s cn50xx; 1158 struct cvmx_usbnx_dma0_outb_chn3_s cn52xx; 1159 struct cvmx_usbnx_dma0_outb_chn3_s cn52xxp1; 1160 struct cvmx_usbnx_dma0_outb_chn3_s cn56xx; 1161 struct cvmx_usbnx_dma0_outb_chn3_s cn56xxp1; 1162}; 1163typedef union cvmx_usbnx_dma0_outb_chn3 cvmx_usbnx_dma0_outb_chn3_t; 1164 1165/** 1166 * cvmx_usbn#_dma0_outb_chn4 1167 * 1168 * USBN_DMA0_OUTB_CHN4 = USBN's Outbound DMA for USB0 Channel4 1169 * 1170 * Contains the starting address for use when USB0 reads from L2C via Channel4. 1171 * Writing of this register sets the base address. 1172 */ 1173union cvmx_usbnx_dma0_outb_chn4 1174{ 1175 uint64_t u64; 1176 struct cvmx_usbnx_dma0_outb_chn4_s 1177 { 1178#if __BYTE_ORDER == __BIG_ENDIAN 1179 uint64_t reserved_36_63 : 28; 1180 uint64_t addr : 36; /**< Base address for DMA Read from L2C. */ 1181#else 1182 uint64_t addr : 36; 1183 uint64_t reserved_36_63 : 28; 1184#endif 1185 } s; 1186 struct cvmx_usbnx_dma0_outb_chn4_s cn30xx; 1187 struct cvmx_usbnx_dma0_outb_chn4_s cn31xx; 1188 struct cvmx_usbnx_dma0_outb_chn4_s cn50xx; 1189 struct cvmx_usbnx_dma0_outb_chn4_s cn52xx; 1190 struct cvmx_usbnx_dma0_outb_chn4_s cn52xxp1; 1191 struct cvmx_usbnx_dma0_outb_chn4_s cn56xx; 1192 struct cvmx_usbnx_dma0_outb_chn4_s cn56xxp1; 1193}; 1194typedef union cvmx_usbnx_dma0_outb_chn4 cvmx_usbnx_dma0_outb_chn4_t; 1195 1196/** 1197 * cvmx_usbn#_dma0_outb_chn5 1198 * 1199 * USBN_DMA0_OUTB_CHN5 = USBN's Outbound DMA for USB0 Channel5 1200 * 1201 * Contains the starting address for use when USB0 reads from L2C via Channel5. 1202 * Writing of this register sets the base address. 1203 */ 1204union cvmx_usbnx_dma0_outb_chn5 1205{ 1206 uint64_t u64; 1207 struct cvmx_usbnx_dma0_outb_chn5_s 1208 { 1209#if __BYTE_ORDER == __BIG_ENDIAN 1210 uint64_t reserved_36_63 : 28; 1211 uint64_t addr : 36; /**< Base address for DMA Read from L2C. */ 1212#else 1213 uint64_t addr : 36; 1214 uint64_t reserved_36_63 : 28; 1215#endif 1216 } s; 1217 struct cvmx_usbnx_dma0_outb_chn5_s cn30xx; 1218 struct cvmx_usbnx_dma0_outb_chn5_s cn31xx; 1219 struct cvmx_usbnx_dma0_outb_chn5_s cn50xx; 1220 struct cvmx_usbnx_dma0_outb_chn5_s cn52xx; 1221 struct cvmx_usbnx_dma0_outb_chn5_s cn52xxp1; 1222 struct cvmx_usbnx_dma0_outb_chn5_s cn56xx; 1223 struct cvmx_usbnx_dma0_outb_chn5_s cn56xxp1; 1224}; 1225typedef union cvmx_usbnx_dma0_outb_chn5 cvmx_usbnx_dma0_outb_chn5_t; 1226 1227/** 1228 * cvmx_usbn#_dma0_outb_chn6 1229 * 1230 * USBN_DMA0_OUTB_CHN6 = USBN's Outbound DMA for USB0 Channel6 1231 * 1232 * Contains the starting address for use when USB0 reads from L2C via Channel6. 1233 * Writing of this register sets the base address. 1234 */ 1235union cvmx_usbnx_dma0_outb_chn6 1236{ 1237 uint64_t u64; 1238 struct cvmx_usbnx_dma0_outb_chn6_s 1239 { 1240#if __BYTE_ORDER == __BIG_ENDIAN 1241 uint64_t reserved_36_63 : 28; 1242 uint64_t addr : 36; /**< Base address for DMA Read from L2C. */ 1243#else 1244 uint64_t addr : 36; 1245 uint64_t reserved_36_63 : 28; 1246#endif 1247 } s; 1248 struct cvmx_usbnx_dma0_outb_chn6_s cn30xx; 1249 struct cvmx_usbnx_dma0_outb_chn6_s cn31xx; 1250 struct cvmx_usbnx_dma0_outb_chn6_s cn50xx; 1251 struct cvmx_usbnx_dma0_outb_chn6_s cn52xx; 1252 struct cvmx_usbnx_dma0_outb_chn6_s cn52xxp1; 1253 struct cvmx_usbnx_dma0_outb_chn6_s cn56xx; 1254 struct cvmx_usbnx_dma0_outb_chn6_s cn56xxp1; 1255}; 1256typedef union cvmx_usbnx_dma0_outb_chn6 cvmx_usbnx_dma0_outb_chn6_t; 1257 1258/** 1259 * cvmx_usbn#_dma0_outb_chn7 1260 * 1261 * USBN_DMA0_OUTB_CHN7 = USBN's Outbound DMA for USB0 Channel7 1262 * 1263 * Contains the starting address for use when USB0 reads from L2C via Channel7. 1264 * Writing of this register sets the base address. 1265 */ 1266union cvmx_usbnx_dma0_outb_chn7 1267{ 1268 uint64_t u64; 1269 struct cvmx_usbnx_dma0_outb_chn7_s 1270 { 1271#if __BYTE_ORDER == __BIG_ENDIAN 1272 uint64_t reserved_36_63 : 28; 1273 uint64_t addr : 36; /**< Base address for DMA Read from L2C. */ 1274#else 1275 uint64_t addr : 36; 1276 uint64_t reserved_36_63 : 28; 1277#endif 1278 } s; 1279 struct cvmx_usbnx_dma0_outb_chn7_s cn30xx; 1280 struct cvmx_usbnx_dma0_outb_chn7_s cn31xx; 1281 struct cvmx_usbnx_dma0_outb_chn7_s cn50xx; 1282 struct cvmx_usbnx_dma0_outb_chn7_s cn52xx; 1283 struct cvmx_usbnx_dma0_outb_chn7_s cn52xxp1; 1284 struct cvmx_usbnx_dma0_outb_chn7_s cn56xx; 1285 struct cvmx_usbnx_dma0_outb_chn7_s cn56xxp1; 1286}; 1287typedef union cvmx_usbnx_dma0_outb_chn7 cvmx_usbnx_dma0_outb_chn7_t; 1288 1289/** 1290 * cvmx_usbn#_dma_test 1291 * 1292 * USBN_DMA_TEST = USBN's DMA TestRegister 1293 * 1294 * This register can cause the external DMA engine to the USB-Core to make transfers from/to L2C/USB-FIFOs 1295 */ 1296union cvmx_usbnx_dma_test 1297{ 1298 uint64_t u64; 1299 struct cvmx_usbnx_dma_test_s 1300 { 1301#if __BYTE_ORDER == __BIG_ENDIAN 1302 uint64_t reserved_40_63 : 24; 1303 uint64_t done : 1; /**< This field is set when a DMA completes. Writing a 1304 '1' to this field clears this bit. */ 1305 uint64_t req : 1; /**< DMA Request. Writing a 1 to this register 1306 will cause a DMA request as specified in the other 1307 fields of this register to take place. This field 1308 will always read as '0'. */ 1309 uint64_t f_addr : 18; /**< The address to read from in the Data-Fifo. */ 1310 uint64_t count : 11; /**< DMA Request Count. */ 1311 uint64_t channel : 5; /**< DMA Channel/Enpoint. */ 1312 uint64_t burst : 4; /**< DMA Burst Size. */ 1313#else 1314 uint64_t burst : 4; 1315 uint64_t channel : 5; 1316 uint64_t count : 11; 1317 uint64_t f_addr : 18; 1318 uint64_t req : 1; 1319 uint64_t done : 1; 1320 uint64_t reserved_40_63 : 24; 1321#endif 1322 } s; 1323 struct cvmx_usbnx_dma_test_s cn30xx; 1324 struct cvmx_usbnx_dma_test_s cn31xx; 1325 struct cvmx_usbnx_dma_test_s cn50xx; 1326 struct cvmx_usbnx_dma_test_s cn52xx; 1327 struct cvmx_usbnx_dma_test_s cn52xxp1; 1328 struct cvmx_usbnx_dma_test_s cn56xx; 1329 struct cvmx_usbnx_dma_test_s cn56xxp1; 1330}; 1331typedef union cvmx_usbnx_dma_test cvmx_usbnx_dma_test_t; 1332 1333/** 1334 * cvmx_usbn#_int_enb 1335 * 1336 * USBN_INT_ENB = USBN's Interrupt Enable 1337 * 1338 * The USBN's interrupt enable register. 1339 */ 1340union cvmx_usbnx_int_enb 1341{ 1342 uint64_t u64; 1343 struct cvmx_usbnx_int_enb_s 1344 { 1345#if __BYTE_ORDER == __BIG_ENDIAN 1346 uint64_t reserved_38_63 : 26; 1347 uint64_t nd4o_dpf : 1; /**< When set (1) and bit 37 of the USBN_INT_SUM 1348 register is asserted the USBN will assert an 1349 interrupt. */ 1350 uint64_t nd4o_dpe : 1; /**< When set (1) and bit 36 of the USBN_INT_SUM 1351 register is asserted the USBN will assert an 1352 interrupt. */ 1353 uint64_t nd4o_rpf : 1; /**< When set (1) and bit 35 of the USBN_INT_SUM 1354 register is asserted the USBN will assert an 1355 interrupt. */ 1356 uint64_t nd4o_rpe : 1; /**< When set (1) and bit 34 of the USBN_INT_SUM 1357 register is asserted the USBN will assert an 1358 interrupt. */ 1359 uint64_t ltl_f_pf : 1; /**< When set (1) and bit 33 of the USBN_INT_SUM 1360 register is asserted the USBN will assert an 1361 interrupt. */ 1362 uint64_t ltl_f_pe : 1; /**< When set (1) and bit 32 of the USBN_INT_SUM 1363 register is asserted the USBN will assert an 1364 interrupt. */ 1365 uint64_t u2n_c_pe : 1; /**< When set (1) and bit 31 of the USBN_INT_SUM 1366 register is asserted the USBN will assert an 1367 interrupt. */ 1368 uint64_t u2n_c_pf : 1; /**< When set (1) and bit 30 of the USBN_INT_SUM 1369 register is asserted the USBN will assert an 1370 interrupt. */ 1371 uint64_t u2n_d_pf : 1; /**< When set (1) and bit 29 of the USBN_INT_SUM 1372 register is asserted the USBN will assert an 1373 interrupt. */ 1374 uint64_t u2n_d_pe : 1; /**< When set (1) and bit 28 of the USBN_INT_SUM 1375 register is asserted the USBN will assert an 1376 interrupt. */ 1377 uint64_t n2u_pe : 1; /**< When set (1) and bit 27 of the USBN_INT_SUM 1378 register is asserted the USBN will assert an 1379 interrupt. */ 1380 uint64_t n2u_pf : 1; /**< When set (1) and bit 26 of the USBN_INT_SUM 1381 register is asserted the USBN will assert an 1382 interrupt. */ 1383 uint64_t uod_pf : 1; /**< When set (1) and bit 25 of the USBN_INT_SUM 1384 register is asserted the USBN will assert an 1385 interrupt. */ 1386 uint64_t uod_pe : 1; /**< When set (1) and bit 24 of the USBN_INT_SUM 1387 register is asserted the USBN will assert an 1388 interrupt. */ 1389 uint64_t rq_q3_e : 1; /**< When set (1) and bit 23 of the USBN_INT_SUM 1390 register is asserted the USBN will assert an 1391 interrupt. */ 1392 uint64_t rq_q3_f : 1; /**< When set (1) and bit 22 of the USBN_INT_SUM 1393 register is asserted the USBN will assert an 1394 interrupt. */ 1395 uint64_t rq_q2_e : 1; /**< When set (1) and bit 21 of the USBN_INT_SUM 1396 register is asserted the USBN will assert an 1397 interrupt. */ 1398 uint64_t rq_q2_f : 1; /**< When set (1) and bit 20 of the USBN_INT_SUM 1399 register is asserted the USBN will assert an 1400 interrupt. */ 1401 uint64_t rg_fi_f : 1; /**< When set (1) and bit 19 of the USBN_INT_SUM 1402 register is asserted the USBN will assert an 1403 interrupt. */ 1404 uint64_t rg_fi_e : 1; /**< When set (1) and bit 18 of the USBN_INT_SUM 1405 register is asserted the USBN will assert an 1406 interrupt. */ 1407 uint64_t l2_fi_f : 1; /**< When set (1) and bit 17 of the USBN_INT_SUM 1408 register is asserted the USBN will assert an 1409 interrupt. */ 1410 uint64_t l2_fi_e : 1; /**< When set (1) and bit 16 of the USBN_INT_SUM 1411 register is asserted the USBN will assert an 1412 interrupt. */ 1413 uint64_t l2c_a_f : 1; /**< When set (1) and bit 15 of the USBN_INT_SUM 1414 register is asserted the USBN will assert an 1415 interrupt. */ 1416 uint64_t l2c_s_e : 1; /**< When set (1) and bit 14 of the USBN_INT_SUM 1417 register is asserted the USBN will assert an 1418 interrupt. */ 1419 uint64_t dcred_f : 1; /**< When set (1) and bit 13 of the USBN_INT_SUM 1420 register is asserted the USBN will assert an 1421 interrupt. */ 1422 uint64_t dcred_e : 1; /**< When set (1) and bit 12 of the USBN_INT_SUM 1423 register is asserted the USBN will assert an 1424 interrupt. */ 1425 uint64_t lt_pu_f : 1; /**< When set (1) and bit 11 of the USBN_INT_SUM 1426 register is asserted the USBN will assert an 1427 interrupt. */ 1428 uint64_t lt_po_e : 1; /**< When set (1) and bit 10 of the USBN_INT_SUM 1429 register is asserted the USBN will assert an 1430 interrupt. */ 1431 uint64_t nt_pu_f : 1; /**< When set (1) and bit 9 of the USBN_INT_SUM 1432 register is asserted the USBN will assert an 1433 interrupt. */ 1434 uint64_t nt_po_e : 1; /**< When set (1) and bit 8 of the USBN_INT_SUM 1435 register is asserted the USBN will assert an 1436 interrupt. */ 1437 uint64_t pt_pu_f : 1; /**< When set (1) and bit 7 of the USBN_INT_SUM 1438 register is asserted the USBN will assert an 1439 interrupt. */ 1440 uint64_t pt_po_e : 1; /**< When set (1) and bit 6 of the USBN_INT_SUM 1441 register is asserted the USBN will assert an 1442 interrupt. */ 1443 uint64_t lr_pu_f : 1; /**< When set (1) and bit 5 of the USBN_INT_SUM 1444 register is asserted the USBN will assert an 1445 interrupt. */ 1446 uint64_t lr_po_e : 1; /**< When set (1) and bit 4 of the USBN_INT_SUM 1447 register is asserted the USBN will assert an 1448 interrupt. */ 1449 uint64_t nr_pu_f : 1; /**< When set (1) and bit 3 of the USBN_INT_SUM 1450 register is asserted the USBN will assert an 1451 interrupt. */ 1452 uint64_t nr_po_e : 1; /**< When set (1) and bit 2 of the USBN_INT_SUM 1453 register is asserted the USBN will assert an 1454 interrupt. */ 1455 uint64_t pr_pu_f : 1; /**< When set (1) and bit 1 of the USBN_INT_SUM 1456 register is asserted the USBN will assert an 1457 interrupt. */ 1458 uint64_t pr_po_e : 1; /**< When set (1) and bit 0 of the USBN_INT_SUM 1459 register is asserted the USBN will assert an 1460 interrupt. */ 1461#else 1462 uint64_t pr_po_e : 1; 1463 uint64_t pr_pu_f : 1; 1464 uint64_t nr_po_e : 1; 1465 uint64_t nr_pu_f : 1; 1466 uint64_t lr_po_e : 1; 1467 uint64_t lr_pu_f : 1; 1468 uint64_t pt_po_e : 1; 1469 uint64_t pt_pu_f : 1; 1470 uint64_t nt_po_e : 1; 1471 uint64_t nt_pu_f : 1; 1472 uint64_t lt_po_e : 1; 1473 uint64_t lt_pu_f : 1; 1474 uint64_t dcred_e : 1; 1475 uint64_t dcred_f : 1; 1476 uint64_t l2c_s_e : 1; 1477 uint64_t l2c_a_f : 1; 1478 uint64_t l2_fi_e : 1; 1479 uint64_t l2_fi_f : 1; 1480 uint64_t rg_fi_e : 1; 1481 uint64_t rg_fi_f : 1; 1482 uint64_t rq_q2_f : 1; 1483 uint64_t rq_q2_e : 1; 1484 uint64_t rq_q3_f : 1; 1485 uint64_t rq_q3_e : 1; 1486 uint64_t uod_pe : 1; 1487 uint64_t uod_pf : 1; 1488 uint64_t n2u_pf : 1; 1489 uint64_t n2u_pe : 1; 1490 uint64_t u2n_d_pe : 1; 1491 uint64_t u2n_d_pf : 1; 1492 uint64_t u2n_c_pf : 1; 1493 uint64_t u2n_c_pe : 1; 1494 uint64_t ltl_f_pe : 1; 1495 uint64_t ltl_f_pf : 1; 1496 uint64_t nd4o_rpe : 1; 1497 uint64_t nd4o_rpf : 1; 1498 uint64_t nd4o_dpe : 1; 1499 uint64_t nd4o_dpf : 1; 1500 uint64_t reserved_38_63 : 26; 1501#endif 1502 } s; 1503 struct cvmx_usbnx_int_enb_s cn30xx; 1504 struct cvmx_usbnx_int_enb_s cn31xx; 1505 struct cvmx_usbnx_int_enb_cn50xx 1506 { 1507#if __BYTE_ORDER == __BIG_ENDIAN 1508 uint64_t reserved_38_63 : 26; 1509 uint64_t nd4o_dpf : 1; /**< When set (1) and bit 37 of the USBN_INT_SUM 1510 register is asserted the USBN will assert an 1511 interrupt. */ 1512 uint64_t nd4o_dpe : 1; /**< When set (1) and bit 36 of the USBN_INT_SUM 1513 register is asserted the USBN will assert an 1514 interrupt. */ 1515 uint64_t nd4o_rpf : 1; /**< When set (1) and bit 35 of the USBN_INT_SUM 1516 register is asserted the USBN will assert an 1517 interrupt. */ 1518 uint64_t nd4o_rpe : 1; /**< When set (1) and bit 34 of the USBN_INT_SUM 1519 register is asserted the USBN will assert an 1520 interrupt. */ 1521 uint64_t ltl_f_pf : 1; /**< When set (1) and bit 33 of the USBN_INT_SUM 1522 register is asserted the USBN will assert an 1523 interrupt. */ 1524 uint64_t ltl_f_pe : 1; /**< When set (1) and bit 32 of the USBN_INT_SUM 1525 register is asserted the USBN will assert an 1526 interrupt. */ 1527 uint64_t reserved_26_31 : 6; 1528 uint64_t uod_pf : 1; /**< When set (1) and bit 25 of the USBN_INT_SUM 1529 register is asserted the USBN will assert an 1530 interrupt. */ 1531 uint64_t uod_pe : 1; /**< When set (1) and bit 24 of the USBN_INT_SUM 1532 register is asserted the USBN will assert an 1533 interrupt. */ 1534 uint64_t rq_q3_e : 1; /**< When set (1) and bit 23 of the USBN_INT_SUM 1535 register is asserted the USBN will assert an 1536 interrupt. */ 1537 uint64_t rq_q3_f : 1; /**< When set (1) and bit 22 of the USBN_INT_SUM 1538 register is asserted the USBN will assert an 1539 interrupt. */ 1540 uint64_t rq_q2_e : 1; /**< When set (1) and bit 21 of the USBN_INT_SUM 1541 register is asserted the USBN will assert an 1542 interrupt. */ 1543 uint64_t rq_q2_f : 1; /**< When set (1) and bit 20 of the USBN_INT_SUM 1544 register is asserted the USBN will assert an 1545 interrupt. */ 1546 uint64_t rg_fi_f : 1; /**< When set (1) and bit 19 of the USBN_INT_SUM 1547 register is asserted the USBN will assert an 1548 interrupt. */ 1549 uint64_t rg_fi_e : 1; /**< When set (1) and bit 18 of the USBN_INT_SUM 1550 register is asserted the USBN will assert an 1551 interrupt. */ 1552 uint64_t l2_fi_f : 1; /**< When set (1) and bit 17 of the USBN_INT_SUM 1553 register is asserted the USBN will assert an 1554 interrupt. */ 1555 uint64_t l2_fi_e : 1; /**< When set (1) and bit 16 of the USBN_INT_SUM 1556 register is asserted the USBN will assert an 1557 interrupt. */ 1558 uint64_t l2c_a_f : 1; /**< When set (1) and bit 15 of the USBN_INT_SUM 1559 register is asserted the USBN will assert an 1560 interrupt. */ 1561 uint64_t l2c_s_e : 1; /**< When set (1) and bit 14 of the USBN_INT_SUM 1562 register is asserted the USBN will assert an 1563 interrupt. */ 1564 uint64_t dcred_f : 1; /**< When set (1) and bit 13 of the USBN_INT_SUM 1565 register is asserted the USBN will assert an 1566 interrupt. */ 1567 uint64_t dcred_e : 1; /**< When set (1) and bit 12 of the USBN_INT_SUM 1568 register is asserted the USBN will assert an 1569 interrupt. */ 1570 uint64_t lt_pu_f : 1; /**< When set (1) and bit 11 of the USBN_INT_SUM 1571 register is asserted the USBN will assert an 1572 interrupt. */ 1573 uint64_t lt_po_e : 1; /**< When set (1) and bit 10 of the USBN_INT_SUM 1574 register is asserted the USBN will assert an 1575 interrupt. */ 1576 uint64_t nt_pu_f : 1; /**< When set (1) and bit 9 of the USBN_INT_SUM 1577 register is asserted the USBN will assert an 1578 interrupt. */ 1579 uint64_t nt_po_e : 1; /**< When set (1) and bit 8 of the USBN_INT_SUM 1580 register is asserted the USBN will assert an 1581 interrupt. */ 1582 uint64_t pt_pu_f : 1; /**< When set (1) and bit 7 of the USBN_INT_SUM 1583 register is asserted the USBN will assert an 1584 interrupt. */ 1585 uint64_t pt_po_e : 1; /**< When set (1) and bit 6 of the USBN_INT_SUM 1586 register is asserted the USBN will assert an 1587 interrupt. */ 1588 uint64_t lr_pu_f : 1; /**< When set (1) and bit 5 of the USBN_INT_SUM 1589 register is asserted the USBN will assert an 1590 interrupt. */ 1591 uint64_t lr_po_e : 1; /**< When set (1) and bit 4 of the USBN_INT_SUM 1592 register is asserted the USBN will assert an 1593 interrupt. */ 1594 uint64_t nr_pu_f : 1; /**< When set (1) and bit 3 of the USBN_INT_SUM 1595 register is asserted the USBN will assert an 1596 interrupt. */ 1597 uint64_t nr_po_e : 1; /**< When set (1) and bit 2 of the USBN_INT_SUM 1598 register is asserted the USBN will assert an 1599 interrupt. */ 1600 uint64_t pr_pu_f : 1; /**< When set (1) and bit 1 of the USBN_INT_SUM 1601 register is asserted the USBN will assert an 1602 interrupt. */ 1603 uint64_t pr_po_e : 1; /**< When set (1) and bit 0 of the USBN_INT_SUM 1604 register is asserted the USBN will assert an 1605 interrupt. */ 1606#else 1607 uint64_t pr_po_e : 1; 1608 uint64_t pr_pu_f : 1; 1609 uint64_t nr_po_e : 1; 1610 uint64_t nr_pu_f : 1; 1611 uint64_t lr_po_e : 1; 1612 uint64_t lr_pu_f : 1; 1613 uint64_t pt_po_e : 1; 1614 uint64_t pt_pu_f : 1; 1615 uint64_t nt_po_e : 1; 1616 uint64_t nt_pu_f : 1; 1617 uint64_t lt_po_e : 1; 1618 uint64_t lt_pu_f : 1; 1619 uint64_t dcred_e : 1; 1620 uint64_t dcred_f : 1; 1621 uint64_t l2c_s_e : 1; 1622 uint64_t l2c_a_f : 1; 1623 uint64_t l2_fi_e : 1; 1624 uint64_t l2_fi_f : 1; 1625 uint64_t rg_fi_e : 1; 1626 uint64_t rg_fi_f : 1; 1627 uint64_t rq_q2_f : 1; 1628 uint64_t rq_q2_e : 1; 1629 uint64_t rq_q3_f : 1; 1630 uint64_t rq_q3_e : 1; 1631 uint64_t uod_pe : 1; 1632 uint64_t uod_pf : 1; 1633 uint64_t reserved_26_31 : 6; 1634 uint64_t ltl_f_pe : 1; 1635 uint64_t ltl_f_pf : 1; 1636 uint64_t nd4o_rpe : 1; 1637 uint64_t nd4o_rpf : 1; 1638 uint64_t nd4o_dpe : 1; 1639 uint64_t nd4o_dpf : 1; 1640 uint64_t reserved_38_63 : 26; 1641#endif 1642 } cn50xx; 1643 struct cvmx_usbnx_int_enb_cn50xx cn52xx; 1644 struct cvmx_usbnx_int_enb_cn50xx cn52xxp1; 1645 struct cvmx_usbnx_int_enb_cn50xx cn56xx; 1646 struct cvmx_usbnx_int_enb_cn50xx cn56xxp1; 1647}; 1648typedef union cvmx_usbnx_int_enb cvmx_usbnx_int_enb_t; 1649 1650/** 1651 * cvmx_usbn#_int_sum 1652 * 1653 * USBN_INT_SUM = USBN's Interrupt Summary Register 1654 * 1655 * Contains the diffrent interrupt summary bits of the USBN. 1656 */ 1657union cvmx_usbnx_int_sum 1658{ 1659 uint64_t u64; 1660 struct cvmx_usbnx_int_sum_s 1661 { 1662#if __BYTE_ORDER == __BIG_ENDIAN 1663 uint64_t reserved_38_63 : 26; 1664 uint64_t nd4o_dpf : 1; /**< NCB DMA Out Data Fifo Push Full. */ 1665 uint64_t nd4o_dpe : 1; /**< NCB DMA Out Data Fifo Pop Empty. */ 1666 uint64_t nd4o_rpf : 1; /**< NCB DMA Out Request Fifo Push Full. */ 1667 uint64_t nd4o_rpe : 1; /**< NCB DMA Out Request Fifo Pop Empty. */ 1668 uint64_t ltl_f_pf : 1; /**< L2C Transfer Length Fifo Push Full. */ 1669 uint64_t ltl_f_pe : 1; /**< L2C Transfer Length Fifo Pop Empty. */ 1670 uint64_t u2n_c_pe : 1; /**< U2N Control Fifo Pop Empty. */ 1671 uint64_t u2n_c_pf : 1; /**< U2N Control Fifo Push Full. */ 1672 uint64_t u2n_d_pf : 1; /**< U2N Data Fifo Push Full. */ 1673 uint64_t u2n_d_pe : 1; /**< U2N Data Fifo Pop Empty. */ 1674 uint64_t n2u_pe : 1; /**< N2U Fifo Pop Empty. */ 1675 uint64_t n2u_pf : 1; /**< N2U Fifo Push Full. */ 1676 uint64_t uod_pf : 1; /**< UOD Fifo Push Full. */ 1677 uint64_t uod_pe : 1; /**< UOD Fifo Pop Empty. */ 1678 uint64_t rq_q3_e : 1; /**< Request Queue-3 Fifo Pushed When Full. */ 1679 uint64_t rq_q3_f : 1; /**< Request Queue-3 Fifo Pushed When Full. */ 1680 uint64_t rq_q2_e : 1; /**< Request Queue-2 Fifo Pushed When Full. */ 1681 uint64_t rq_q2_f : 1; /**< Request Queue-2 Fifo Pushed When Full. */ 1682 uint64_t rg_fi_f : 1; /**< Register Request Fifo Pushed When Full. */ 1683 uint64_t rg_fi_e : 1; /**< Register Request Fifo Pushed When Full. */ 1684 uint64_t lt_fi_f : 1; /**< L2C Request Fifo Pushed When Full. */ 1685 uint64_t lt_fi_e : 1; /**< L2C Request Fifo Pushed When Full. */ 1686 uint64_t l2c_a_f : 1; /**< L2C Credit Count Added When Full. */ 1687 uint64_t l2c_s_e : 1; /**< L2C Credit Count Subtracted When Empty. */ 1688 uint64_t dcred_f : 1; /**< Data CreditFifo Pushed When Full. */ 1689 uint64_t dcred_e : 1; /**< Data Credit Fifo Pushed When Full. */ 1690 uint64_t lt_pu_f : 1; /**< L2C Trasaction Fifo Pushed When Full. */ 1691 uint64_t lt_po_e : 1; /**< L2C Trasaction Fifo Popped When Full. */ 1692 uint64_t nt_pu_f : 1; /**< NPI Trasaction Fifo Pushed When Full. */ 1693 uint64_t nt_po_e : 1; /**< NPI Trasaction Fifo Popped When Full. */ 1694 uint64_t pt_pu_f : 1; /**< PP Trasaction Fifo Pushed When Full. */ 1695 uint64_t pt_po_e : 1; /**< PP Trasaction Fifo Popped When Full. */ 1696 uint64_t lr_pu_f : 1; /**< L2C Request Fifo Pushed When Full. */ 1697 uint64_t lr_po_e : 1; /**< L2C Request Fifo Popped When Empty. */ 1698 uint64_t nr_pu_f : 1; /**< NPI Request Fifo Pushed When Full. */ 1699 uint64_t nr_po_e : 1; /**< NPI Request Fifo Popped When Empty. */ 1700 uint64_t pr_pu_f : 1; /**< PP Request Fifo Pushed When Full. */ 1701 uint64_t pr_po_e : 1; /**< PP Request Fifo Popped When Empty. */ 1702#else 1703 uint64_t pr_po_e : 1; 1704 uint64_t pr_pu_f : 1; 1705 uint64_t nr_po_e : 1; 1706 uint64_t nr_pu_f : 1; 1707 uint64_t lr_po_e : 1; 1708 uint64_t lr_pu_f : 1; 1709 uint64_t pt_po_e : 1; 1710 uint64_t pt_pu_f : 1; 1711 uint64_t nt_po_e : 1; 1712 uint64_t nt_pu_f : 1; 1713 uint64_t lt_po_e : 1; 1714 uint64_t lt_pu_f : 1; 1715 uint64_t dcred_e : 1; 1716 uint64_t dcred_f : 1; 1717 uint64_t l2c_s_e : 1; 1718 uint64_t l2c_a_f : 1; 1719 uint64_t lt_fi_e : 1; 1720 uint64_t lt_fi_f : 1; 1721 uint64_t rg_fi_e : 1; 1722 uint64_t rg_fi_f : 1; 1723 uint64_t rq_q2_f : 1; 1724 uint64_t rq_q2_e : 1; 1725 uint64_t rq_q3_f : 1; 1726 uint64_t rq_q3_e : 1; 1727 uint64_t uod_pe : 1; 1728 uint64_t uod_pf : 1; 1729 uint64_t n2u_pf : 1; 1730 uint64_t n2u_pe : 1; 1731 uint64_t u2n_d_pe : 1; 1732 uint64_t u2n_d_pf : 1; 1733 uint64_t u2n_c_pf : 1; 1734 uint64_t u2n_c_pe : 1; 1735 uint64_t ltl_f_pe : 1; 1736 uint64_t ltl_f_pf : 1; 1737 uint64_t nd4o_rpe : 1; 1738 uint64_t nd4o_rpf : 1; 1739 uint64_t nd4o_dpe : 1; 1740 uint64_t nd4o_dpf : 1; 1741 uint64_t reserved_38_63 : 26; 1742#endif 1743 } s; 1744 struct cvmx_usbnx_int_sum_s cn30xx; 1745 struct cvmx_usbnx_int_sum_s cn31xx; 1746 struct cvmx_usbnx_int_sum_cn50xx 1747 { 1748#if __BYTE_ORDER == __BIG_ENDIAN 1749 uint64_t reserved_38_63 : 26; 1750 uint64_t nd4o_dpf : 1; /**< NCB DMA Out Data Fifo Push Full. */ 1751 uint64_t nd4o_dpe : 1; /**< NCB DMA Out Data Fifo Pop Empty. */ 1752 uint64_t nd4o_rpf : 1; /**< NCB DMA Out Request Fifo Push Full. */ 1753 uint64_t nd4o_rpe : 1; /**< NCB DMA Out Request Fifo Pop Empty. */ 1754 uint64_t ltl_f_pf : 1; /**< L2C Transfer Length Fifo Push Full. */ 1755 uint64_t ltl_f_pe : 1; /**< L2C Transfer Length Fifo Pop Empty. */ 1756 uint64_t reserved_26_31 : 6; 1757 uint64_t uod_pf : 1; /**< UOD Fifo Push Full. */ 1758 uint64_t uod_pe : 1; /**< UOD Fifo Pop Empty. */ 1759 uint64_t rq_q3_e : 1; /**< Request Queue-3 Fifo Pushed When Full. */ 1760 uint64_t rq_q3_f : 1; /**< Request Queue-3 Fifo Pushed When Full. */ 1761 uint64_t rq_q2_e : 1; /**< Request Queue-2 Fifo Pushed When Full. */ 1762 uint64_t rq_q2_f : 1; /**< Request Queue-2 Fifo Pushed When Full. */ 1763 uint64_t rg_fi_f : 1; /**< Register Request Fifo Pushed When Full. */ 1764 uint64_t rg_fi_e : 1; /**< Register Request Fifo Pushed When Full. */ 1765 uint64_t lt_fi_f : 1; /**< L2C Request Fifo Pushed When Full. */ 1766 uint64_t lt_fi_e : 1; /**< L2C Request Fifo Pushed When Full. */ 1767 uint64_t l2c_a_f : 1; /**< L2C Credit Count Added When Full. */ 1768 uint64_t l2c_s_e : 1; /**< L2C Credit Count Subtracted When Empty. */ 1769 uint64_t dcred_f : 1; /**< Data CreditFifo Pushed When Full. */ 1770 uint64_t dcred_e : 1; /**< Data Credit Fifo Pushed When Full. */ 1771 uint64_t lt_pu_f : 1; /**< L2C Trasaction Fifo Pushed When Full. */ 1772 uint64_t lt_po_e : 1; /**< L2C Trasaction Fifo Popped When Full. */ 1773 uint64_t nt_pu_f : 1; /**< NPI Trasaction Fifo Pushed When Full. */ 1774 uint64_t nt_po_e : 1; /**< NPI Trasaction Fifo Popped When Full. */ 1775 uint64_t pt_pu_f : 1; /**< PP Trasaction Fifo Pushed When Full. */ 1776 uint64_t pt_po_e : 1; /**< PP Trasaction Fifo Popped When Full. */ 1777 uint64_t lr_pu_f : 1; /**< L2C Request Fifo Pushed When Full. */ 1778 uint64_t lr_po_e : 1; /**< L2C Request Fifo Popped When Empty. */ 1779 uint64_t nr_pu_f : 1; /**< NPI Request Fifo Pushed When Full. */ 1780 uint64_t nr_po_e : 1; /**< NPI Request Fifo Popped When Empty. */ 1781 uint64_t pr_pu_f : 1; /**< PP Request Fifo Pushed When Full. */ 1782 uint64_t pr_po_e : 1; /**< PP Request Fifo Popped When Empty. */ 1783#else 1784 uint64_t pr_po_e : 1; 1785 uint64_t pr_pu_f : 1; 1786 uint64_t nr_po_e : 1; 1787 uint64_t nr_pu_f : 1; 1788 uint64_t lr_po_e : 1; 1789 uint64_t lr_pu_f : 1; 1790 uint64_t pt_po_e : 1; 1791 uint64_t pt_pu_f : 1; 1792 uint64_t nt_po_e : 1; 1793 uint64_t nt_pu_f : 1; 1794 uint64_t lt_po_e : 1; 1795 uint64_t lt_pu_f : 1; 1796 uint64_t dcred_e : 1; 1797 uint64_t dcred_f : 1; 1798 uint64_t l2c_s_e : 1; 1799 uint64_t l2c_a_f : 1; 1800 uint64_t lt_fi_e : 1; 1801 uint64_t lt_fi_f : 1; 1802 uint64_t rg_fi_e : 1; 1803 uint64_t rg_fi_f : 1; 1804 uint64_t rq_q2_f : 1; 1805 uint64_t rq_q2_e : 1; 1806 uint64_t rq_q3_f : 1; 1807 uint64_t rq_q3_e : 1; 1808 uint64_t uod_pe : 1; 1809 uint64_t uod_pf : 1; 1810 uint64_t reserved_26_31 : 6; 1811 uint64_t ltl_f_pe : 1; 1812 uint64_t ltl_f_pf : 1; 1813 uint64_t nd4o_rpe : 1; 1814 uint64_t nd4o_rpf : 1; 1815 uint64_t nd4o_dpe : 1; 1816 uint64_t nd4o_dpf : 1; 1817 uint64_t reserved_38_63 : 26; 1818#endif 1819 } cn50xx; 1820 struct cvmx_usbnx_int_sum_cn50xx cn52xx; 1821 struct cvmx_usbnx_int_sum_cn50xx cn52xxp1; 1822 struct cvmx_usbnx_int_sum_cn50xx cn56xx; 1823 struct cvmx_usbnx_int_sum_cn50xx cn56xxp1; 1824}; 1825typedef union cvmx_usbnx_int_sum cvmx_usbnx_int_sum_t; 1826 1827/** 1828 * cvmx_usbn#_usbp_ctl_status 1829 * 1830 * USBN_USBP_CTL_STATUS = USBP Control And Status Register 1831 * 1832 * Contains general control and status information for the USBN block. 1833 */ 1834union cvmx_usbnx_usbp_ctl_status 1835{ 1836 uint64_t u64; 1837 struct cvmx_usbnx_usbp_ctl_status_s 1838 { 1839#if __BYTE_ORDER == __BIG_ENDIAN 1840 uint64_t txrisetune : 1; /**< HS Transmitter Rise/Fall Time Adjustment */ 1841 uint64_t txvreftune : 4; /**< HS DC Voltage Level Adjustment */ 1842 uint64_t txfslstune : 4; /**< FS/LS Source Impedence Adjustment */ 1843 uint64_t txhsxvtune : 2; /**< Transmitter High-Speed Crossover Adjustment */ 1844 uint64_t sqrxtune : 3; /**< Squelch Threshold Adjustment */ 1845 uint64_t compdistune : 3; /**< Disconnect Threshold Adjustment */ 1846 uint64_t otgtune : 3; /**< VBUS Valid Threshold Adjustment */ 1847 uint64_t otgdisable : 1; /**< OTG Block Disable */ 1848 uint64_t portreset : 1; /**< Per_Port Reset */ 1849 uint64_t drvvbus : 1; /**< Drive VBUS */ 1850 uint64_t lsbist : 1; /**< Low-Speed BIST Enable. */ 1851 uint64_t fsbist : 1; /**< Full-Speed BIST Enable. */ 1852 uint64_t hsbist : 1; /**< High-Speed BIST Enable. */ 1853 uint64_t bist_done : 1; /**< PHY Bist Done. 1854 Asserted at the end of the PHY BIST sequence. */ 1855 uint64_t bist_err : 1; /**< PHY Bist Error. 1856 Indicates an internal error was detected during 1857 the BIST sequence. */ 1858 uint64_t tdata_out : 4; /**< PHY Test Data Out. 1859 Presents either internaly generated signals or 1860 test register contents, based upon the value of 1861 test_data_out_sel. */ 1862 uint64_t siddq : 1; /**< Drives the USBP (USB-PHY) SIDDQ input. 1863 Normally should be set to zero. 1864 When customers have no intent to use USB PHY 1865 interface, they should: 1866 - still provide 3.3V to USB_VDD33, and 1867 - tie USB_REXT to 3.3V supply, and 1868 - set USBN*_USBP_CTL_STATUS[SIDDQ]=1 */ 1869 uint64_t txpreemphasistune : 1; /**< HS Transmitter Pre-Emphasis Enable */ 1870 uint64_t dma_bmode : 1; /**< When set to 1 the L2C DMA address will be updated 1871 with byte-counts between packets. When set to 0 1872 the L2C DMA address is incremented to the next 1873 4-byte aligned address after adding byte-count. */ 1874 uint64_t usbc_end : 1; /**< Bigendian input to the USB Core. This should be 1875 set to '0' for operation. */ 1876 uint64_t usbp_bist : 1; /**< PHY, This is cleared '0' to run BIST on the USBP. */ 1877 uint64_t tclk : 1; /**< PHY Test Clock, used to load TDATA_IN to the USBP. */ 1878 uint64_t dp_pulld : 1; /**< PHY DP_PULLDOWN input to the USB-PHY. 1879 This signal enables the pull-down resistance on 1880 the D+ line. '1' pull down-resistance is connected 1881 to D+/ '0' pull down resistance is not connected 1882 to D+. When an A/B device is acting as a host 1883 (downstream-facing port), dp_pulldown and 1884 dm_pulldown are enabled. This must not toggle 1885 during normal opeartion. */ 1886 uint64_t dm_pulld : 1; /**< PHY DM_PULLDOWN input to the USB-PHY. 1887 This signal enables the pull-down resistance on 1888 the D- line. '1' pull down-resistance is connected 1889 to D-. '0' pull down resistance is not connected 1890 to D-. When an A/B device is acting as a host 1891 (downstream-facing port), dp_pulldown and 1892 dm_pulldown are enabled. This must not toggle 1893 during normal opeartion. */ 1894 uint64_t hst_mode : 1; /**< When '0' the USB is acting as HOST, when '1' 1895 USB is acting as device. This field needs to be 1896 set while the USB is in reset. */ 1897 uint64_t tuning : 4; /**< Transmitter Tuning for High-Speed Operation. 1898 Tunes the current supply and rise/fall output 1899 times for high-speed operation. 1900 [20:19] == 11: Current supply increased 1901 approximately 9% 1902 [20:19] == 10: Current supply increased 1903 approximately 4.5% 1904 [20:19] == 01: Design default. 1905 [20:19] == 00: Current supply decreased 1906 approximately 4.5% 1907 [22:21] == 11: Rise and fall times are increased. 1908 [22:21] == 10: Design default. 1909 [22:21] == 01: Rise and fall times are decreased. 1910 [22:21] == 00: Rise and fall times are decreased 1911 further as compared to the 01 setting. */ 1912 uint64_t tx_bs_enh : 1; /**< Transmit Bit Stuffing on [15:8]. 1913 Enables or disables bit stuffing on data[15:8] 1914 when bit-stuffing is enabled. */ 1915 uint64_t tx_bs_en : 1; /**< Transmit Bit Stuffing on [7:0]. 1916 Enables or disables bit stuffing on data[7:0] 1917 when bit-stuffing is enabled. */ 1918 uint64_t loop_enb : 1; /**< PHY Loopback Test Enable. 1919 '1': During data transmission the receive is 1920 enabled. 1921 '0': During data transmission the receive is 1922 disabled. 1923 Must be '0' for normal operation. */ 1924 uint64_t vtest_enb : 1; /**< Analog Test Pin Enable. 1925 '1' The PHY's analog_test pin is enabled for the 1926 input and output of applicable analog test signals. 1927 '0' THe analog_test pin is disabled. */ 1928 uint64_t bist_enb : 1; /**< Built-In Self Test Enable. 1929 Used to activate BIST in the PHY. */ 1930 uint64_t tdata_sel : 1; /**< Test Data Out Select. 1931 '1' test_data_out[3:0] (PHY) register contents 1932 are output. '0' internaly generated signals are 1933 output. */ 1934 uint64_t taddr_in : 4; /**< Mode Address for Test Interface. 1935 Specifies the register address for writing to or 1936 reading from the PHY test interface register. */ 1937 uint64_t tdata_in : 8; /**< Internal Testing Register Input Data and Select 1938 This is a test bus. Data is present on [3:0], 1939 and its corresponding select (enable) is present 1940 on bits [7:4]. */ 1941 uint64_t ate_reset : 1; /**< Reset input from automatic test equipment. 1942 This is a test signal. When the USB Core is 1943 powered up (not in Susned Mode), an automatic 1944 tester can use this to disable phy_clock and 1945 free_clk, then re-eanable them with an aligned 1946 phase. 1947 '1': The phy_clk and free_clk outputs are 1948 disabled. "0": The phy_clock and free_clk outputs 1949 are available within a specific period after the 1950 de-assertion. */ 1951#else 1952 uint64_t ate_reset : 1; 1953 uint64_t tdata_in : 8; 1954 uint64_t taddr_in : 4; 1955 uint64_t tdata_sel : 1; 1956 uint64_t bist_enb : 1; 1957 uint64_t vtest_enb : 1; 1958 uint64_t loop_enb : 1; 1959 uint64_t tx_bs_en : 1; 1960 uint64_t tx_bs_enh : 1; 1961 uint64_t tuning : 4; 1962 uint64_t hst_mode : 1; 1963 uint64_t dm_pulld : 1; 1964 uint64_t dp_pulld : 1; 1965 uint64_t tclk : 1; 1966 uint64_t usbp_bist : 1; 1967 uint64_t usbc_end : 1; 1968 uint64_t dma_bmode : 1; 1969 uint64_t txpreemphasistune : 1; 1970 uint64_t siddq : 1; 1971 uint64_t tdata_out : 4; 1972 uint64_t bist_err : 1; 1973 uint64_t bist_done : 1; 1974 uint64_t hsbist : 1; 1975 uint64_t fsbist : 1; 1976 uint64_t lsbist : 1; 1977 uint64_t drvvbus : 1; 1978 uint64_t portreset : 1; 1979 uint64_t otgdisable : 1; 1980 uint64_t otgtune : 3; 1981 uint64_t compdistune : 3; 1982 uint64_t sqrxtune : 3; 1983 uint64_t txhsxvtune : 2; 1984 uint64_t txfslstune : 4; 1985 uint64_t txvreftune : 4; 1986 uint64_t txrisetune : 1; 1987#endif 1988 } s; 1989 struct cvmx_usbnx_usbp_ctl_status_cn30xx 1990 { 1991#if __BYTE_ORDER == __BIG_ENDIAN 1992 uint64_t reserved_38_63 : 26; 1993 uint64_t bist_done : 1; /**< PHY Bist Done. 1994 Asserted at the end of the PHY BIST sequence. */ 1995 uint64_t bist_err : 1; /**< PHY Bist Error. 1996 Indicates an internal error was detected during 1997 the BIST sequence. */ 1998 uint64_t tdata_out : 4; /**< PHY Test Data Out. 1999 Presents either internaly generated signals or 2000 test register contents, based upon the value of 2001 test_data_out_sel. */ 2002 uint64_t reserved_30_31 : 2; 2003 uint64_t dma_bmode : 1; /**< When set to 1 the L2C DMA address will be updated 2004 with byte-counts between packets. When set to 0 2005 the L2C DMA address is incremented to the next 2006 4-byte aligned address after adding byte-count. */ 2007 uint64_t usbc_end : 1; /**< Bigendian input to the USB Core. This should be 2008 set to '0' for operation. */ 2009 uint64_t usbp_bist : 1; /**< PHY, This is cleared '0' to run BIST on the USBP. */ 2010 uint64_t tclk : 1; /**< PHY Test Clock, used to load TDATA_IN to the USBP. */ 2011 uint64_t dp_pulld : 1; /**< PHY DP_PULLDOWN input to the USB-PHY. 2012 This signal enables the pull-down resistance on 2013 the D+ line. '1' pull down-resistance is connected 2014 to D+/ '0' pull down resistance is not connected 2015 to D+. When an A/B device is acting as a host 2016 (downstream-facing port), dp_pulldown and 2017 dm_pulldown are enabled. This must not toggle 2018 during normal opeartion. */ 2019 uint64_t dm_pulld : 1; /**< PHY DM_PULLDOWN input to the USB-PHY. 2020 This signal enables the pull-down resistance on 2021 the D- line. '1' pull down-resistance is connected 2022 to D-. '0' pull down resistance is not connected 2023 to D-. When an A/B device is acting as a host 2024 (downstream-facing port), dp_pulldown and 2025 dm_pulldown are enabled. This must not toggle 2026 during normal opeartion. */ 2027 uint64_t hst_mode : 1; /**< When '0' the USB is acting as HOST, when '1' 2028 USB is acting as device. This field needs to be 2029 set while the USB is in reset. */ 2030 uint64_t tuning : 4; /**< Transmitter Tuning for High-Speed Operation. 2031 Tunes the current supply and rise/fall output 2032 times for high-speed operation. 2033 [20:19] == 11: Current supply increased 2034 approximately 9% 2035 [20:19] == 10: Current supply increased 2036 approximately 4.5% 2037 [20:19] == 01: Design default. 2038 [20:19] == 00: Current supply decreased 2039 approximately 4.5% 2040 [22:21] == 11: Rise and fall times are increased. 2041 [22:21] == 10: Design default. 2042 [22:21] == 01: Rise and fall times are decreased. 2043 [22:21] == 00: Rise and fall times are decreased 2044 further as compared to the 01 setting. */ 2045 uint64_t tx_bs_enh : 1; /**< Transmit Bit Stuffing on [15:8]. 2046 Enables or disables bit stuffing on data[15:8] 2047 when bit-stuffing is enabled. */ 2048 uint64_t tx_bs_en : 1; /**< Transmit Bit Stuffing on [7:0]. 2049 Enables or disables bit stuffing on data[7:0] 2050 when bit-stuffing is enabled. */ 2051 uint64_t loop_enb : 1; /**< PHY Loopback Test Enable. 2052 '1': During data transmission the receive is 2053 enabled. 2054 '0': During data transmission the receive is 2055 disabled. 2056 Must be '0' for normal operation. */ 2057 uint64_t vtest_enb : 1; /**< Analog Test Pin Enable. 2058 '1' The PHY's analog_test pin is enabled for the 2059 input and output of applicable analog test signals. 2060 '0' THe analog_test pin is disabled. */ 2061 uint64_t bist_enb : 1; /**< Built-In Self Test Enable. 2062 Used to activate BIST in the PHY. */ 2063 uint64_t tdata_sel : 1; /**< Test Data Out Select. 2064 '1' test_data_out[3:0] (PHY) register contents 2065 are output. '0' internaly generated signals are 2066 output. */ 2067 uint64_t taddr_in : 4; /**< Mode Address for Test Interface. 2068 Specifies the register address for writing to or 2069 reading from the PHY test interface register. */ 2070 uint64_t tdata_in : 8; /**< Internal Testing Register Input Data and Select 2071 This is a test bus. Data is present on [3:0], 2072 and its corresponding select (enable) is present 2073 on bits [7:4]. */ 2074 uint64_t ate_reset : 1; /**< Reset input from automatic test equipment. 2075 This is a test signal. When the USB Core is 2076 powered up (not in Susned Mode), an automatic 2077 tester can use this to disable phy_clock and 2078 free_clk, then re-eanable them with an aligned 2079 phase. 2080 '1': The phy_clk and free_clk outputs are 2081 disabled. "0": The phy_clock and free_clk outputs 2082 are available within a specific period after the 2083 de-assertion. */ 2084#else 2085 uint64_t ate_reset : 1; 2086 uint64_t tdata_in : 8; 2087 uint64_t taddr_in : 4; 2088 uint64_t tdata_sel : 1; 2089 uint64_t bist_enb : 1; 2090 uint64_t vtest_enb : 1; 2091 uint64_t loop_enb : 1; 2092 uint64_t tx_bs_en : 1; 2093 uint64_t tx_bs_enh : 1; 2094 uint64_t tuning : 4; 2095 uint64_t hst_mode : 1; 2096 uint64_t dm_pulld : 1; 2097 uint64_t dp_pulld : 1; 2098 uint64_t tclk : 1; 2099 uint64_t usbp_bist : 1; 2100 uint64_t usbc_end : 1; 2101 uint64_t dma_bmode : 1; 2102 uint64_t reserved_30_31 : 2; 2103 uint64_t tdata_out : 4; 2104 uint64_t bist_err : 1; 2105 uint64_t bist_done : 1; 2106 uint64_t reserved_38_63 : 26; 2107#endif 2108 } cn30xx; 2109 struct cvmx_usbnx_usbp_ctl_status_cn30xx cn31xx; 2110 struct cvmx_usbnx_usbp_ctl_status_cn50xx 2111 { 2112#if __BYTE_ORDER == __BIG_ENDIAN 2113 uint64_t txrisetune : 1; /**< HS Transmitter Rise/Fall Time Adjustment */ 2114 uint64_t txvreftune : 4; /**< HS DC Voltage Level Adjustment */ 2115 uint64_t txfslstune : 4; /**< FS/LS Source Impedence Adjustment */ 2116 uint64_t txhsxvtune : 2; /**< Transmitter High-Speed Crossover Adjustment */ 2117 uint64_t sqrxtune : 3; /**< Squelch Threshold Adjustment */ 2118 uint64_t compdistune : 3; /**< Disconnect Threshold Adjustment */ 2119 uint64_t otgtune : 3; /**< VBUS Valid Threshold Adjustment */ 2120 uint64_t otgdisable : 1; /**< OTG Block Disable */ 2121 uint64_t portreset : 1; /**< Per_Port Reset */ 2122 uint64_t drvvbus : 1; /**< Drive VBUS */ 2123 uint64_t lsbist : 1; /**< Low-Speed BIST Enable. */ 2124 uint64_t fsbist : 1; /**< Full-Speed BIST Enable. */ 2125 uint64_t hsbist : 1; /**< High-Speed BIST Enable. */ 2126 uint64_t bist_done : 1; /**< PHY Bist Done. 2127 Asserted at the end of the PHY BIST sequence. */ 2128 uint64_t bist_err : 1; /**< PHY Bist Error. 2129 Indicates an internal error was detected during 2130 the BIST sequence. */ 2131 uint64_t tdata_out : 4; /**< PHY Test Data Out. 2132 Presents either internaly generated signals or 2133 test register contents, based upon the value of 2134 test_data_out_sel. */ 2135 uint64_t reserved_31_31 : 1; 2136 uint64_t txpreemphasistune : 1; /**< HS Transmitter Pre-Emphasis Enable */ 2137 uint64_t dma_bmode : 1; /**< When set to 1 the L2C DMA address will be updated 2138 with byte-counts between packets. When set to 0 2139 the L2C DMA address is incremented to the next 2140 4-byte aligned address after adding byte-count. */ 2141 uint64_t usbc_end : 1; /**< Bigendian input to the USB Core. This should be 2142 set to '0' for operation. */ 2143 uint64_t usbp_bist : 1; /**< PHY, This is cleared '0' to run BIST on the USBP. */ 2144 uint64_t tclk : 1; /**< PHY Test Clock, used to load TDATA_IN to the USBP. */ 2145 uint64_t dp_pulld : 1; /**< PHY DP_PULLDOWN input to the USB-PHY. 2146 This signal enables the pull-down resistance on 2147 the D+ line. '1' pull down-resistance is connected 2148 to D+/ '0' pull down resistance is not connected 2149 to D+. When an A/B device is acting as a host 2150 (downstream-facing port), dp_pulldown and 2151 dm_pulldown are enabled. This must not toggle 2152 during normal opeartion. */ 2153 uint64_t dm_pulld : 1; /**< PHY DM_PULLDOWN input to the USB-PHY. 2154 This signal enables the pull-down resistance on 2155 the D- line. '1' pull down-resistance is connected 2156 to D-. '0' pull down resistance is not connected 2157 to D-. When an A/B device is acting as a host 2158 (downstream-facing port), dp_pulldown and 2159 dm_pulldown are enabled. This must not toggle 2160 during normal opeartion. */ 2161 uint64_t hst_mode : 1; /**< When '0' the USB is acting as HOST, when '1' 2162 USB is acting as device. This field needs to be 2163 set while the USB is in reset. */ 2164 uint64_t reserved_19_22 : 4; 2165 uint64_t tx_bs_enh : 1; /**< Transmit Bit Stuffing on [15:8]. 2166 Enables or disables bit stuffing on data[15:8] 2167 when bit-stuffing is enabled. */ 2168 uint64_t tx_bs_en : 1; /**< Transmit Bit Stuffing on [7:0]. 2169 Enables or disables bit stuffing on data[7:0] 2170 when bit-stuffing is enabled. */ 2171 uint64_t loop_enb : 1; /**< PHY Loopback Test Enable. 2172 '1': During data transmission the receive is 2173 enabled. 2174 '0': During data transmission the receive is 2175 disabled. 2176 Must be '0' for normal operation. */ 2177 uint64_t vtest_enb : 1; /**< Analog Test Pin Enable. 2178 '1' The PHY's analog_test pin is enabled for the 2179 input and output of applicable analog test signals. 2180 '0' THe analog_test pin is disabled. */ 2181 uint64_t bist_enb : 1; /**< Built-In Self Test Enable. 2182 Used to activate BIST in the PHY. */ 2183 uint64_t tdata_sel : 1; /**< Test Data Out Select. 2184 '1' test_data_out[3:0] (PHY) register contents 2185 are output. '0' internaly generated signals are 2186 output. */ 2187 uint64_t taddr_in : 4; /**< Mode Address for Test Interface. 2188 Specifies the register address for writing to or 2189 reading from the PHY test interface register. */ 2190 uint64_t tdata_in : 8; /**< Internal Testing Register Input Data and Select 2191 This is a test bus. Data is present on [3:0], 2192 and its corresponding select (enable) is present 2193 on bits [7:4]. */ 2194 uint64_t ate_reset : 1; /**< Reset input from automatic test equipment. 2195 This is a test signal. When the USB Core is 2196 powered up (not in Susned Mode), an automatic 2197 tester can use this to disable phy_clock and 2198 free_clk, then re-eanable them with an aligned 2199 phase. 2200 '1': The phy_clk and free_clk outputs are 2201 disabled. "0": The phy_clock and free_clk outputs 2202 are available within a specific period after the 2203 de-assertion. */ 2204#else 2205 uint64_t ate_reset : 1; 2206 uint64_t tdata_in : 8; 2207 uint64_t taddr_in : 4; 2208 uint64_t tdata_sel : 1; 2209 uint64_t bist_enb : 1; 2210 uint64_t vtest_enb : 1; 2211 uint64_t loop_enb : 1; 2212 uint64_t tx_bs_en : 1; 2213 uint64_t tx_bs_enh : 1; 2214 uint64_t reserved_19_22 : 4; 2215 uint64_t hst_mode : 1; 2216 uint64_t dm_pulld : 1; 2217 uint64_t dp_pulld : 1; 2218 uint64_t tclk : 1; 2219 uint64_t usbp_bist : 1; 2220 uint64_t usbc_end : 1; 2221 uint64_t dma_bmode : 1; 2222 uint64_t txpreemphasistune : 1; 2223 uint64_t reserved_31_31 : 1; 2224 uint64_t tdata_out : 4; 2225 uint64_t bist_err : 1; 2226 uint64_t bist_done : 1; 2227 uint64_t hsbist : 1; 2228 uint64_t fsbist : 1; 2229 uint64_t lsbist : 1; 2230 uint64_t drvvbus : 1; 2231 uint64_t portreset : 1; 2232 uint64_t otgdisable : 1; 2233 uint64_t otgtune : 3; 2234 uint64_t compdistune : 3; 2235 uint64_t sqrxtune : 3; 2236 uint64_t txhsxvtune : 2; 2237 uint64_t txfslstune : 4; 2238 uint64_t txvreftune : 4; 2239 uint64_t txrisetune : 1; 2240#endif 2241 } cn50xx; 2242 struct cvmx_usbnx_usbp_ctl_status_cn52xx 2243 { 2244#if __BYTE_ORDER == __BIG_ENDIAN 2245 uint64_t txrisetune : 1; /**< HS Transmitter Rise/Fall Time Adjustment */ 2246 uint64_t txvreftune : 4; /**< HS DC Voltage Level Adjustment */ 2247 uint64_t txfslstune : 4; /**< FS/LS Source Impedence Adjustment */ 2248 uint64_t txhsxvtune : 2; /**< Transmitter High-Speed Crossover Adjustment */ 2249 uint64_t sqrxtune : 3; /**< Squelch Threshold Adjustment */ 2250 uint64_t compdistune : 3; /**< Disconnect Threshold Adjustment */ 2251 uint64_t otgtune : 3; /**< VBUS Valid Threshold Adjustment */ 2252 uint64_t otgdisable : 1; /**< OTG Block Disable */ 2253 uint64_t portreset : 1; /**< Per_Port Reset */ 2254 uint64_t drvvbus : 1; /**< Drive VBUS */ 2255 uint64_t lsbist : 1; /**< Low-Speed BIST Enable. */ 2256 uint64_t fsbist : 1; /**< Full-Speed BIST Enable. */ 2257 uint64_t hsbist : 1; /**< High-Speed BIST Enable. */ 2258 uint64_t bist_done : 1; /**< PHY Bist Done. 2259 Asserted at the end of the PHY BIST sequence. */ 2260 uint64_t bist_err : 1; /**< PHY Bist Error. 2261 Indicates an internal error was detected during 2262 the BIST sequence. */ 2263 uint64_t tdata_out : 4; /**< PHY Test Data Out. 2264 Presents either internaly generated signals or 2265 test register contents, based upon the value of 2266 test_data_out_sel. */ 2267 uint64_t siddq : 1; /**< Drives the USBP (USB-PHY) SIDDQ input. 2268 Normally should be set to zero. 2269 When customers have no intent to use USB PHY 2270 interface, they should: 2271 - still provide 3.3V to USB_VDD33, and 2272 - tie USB_REXT to 3.3V supply, and 2273 - set USBN*_USBP_CTL_STATUS[SIDDQ]=1 */ 2274 uint64_t txpreemphasistune : 1; /**< HS Transmitter Pre-Emphasis Enable */ 2275 uint64_t dma_bmode : 1; /**< When set to 1 the L2C DMA address will be updated 2276 with byte-counts between packets. When set to 0 2277 the L2C DMA address is incremented to the next 2278 4-byte aligned address after adding byte-count. */ 2279 uint64_t usbc_end : 1; /**< Bigendian input to the USB Core. This should be 2280 set to '0' for operation. */ 2281 uint64_t usbp_bist : 1; /**< PHY, This is cleared '0' to run BIST on the USBP. */ 2282 uint64_t tclk : 1; /**< PHY Test Clock, used to load TDATA_IN to the USBP. */ 2283 uint64_t dp_pulld : 1; /**< PHY DP_PULLDOWN input to the USB-PHY. 2284 This signal enables the pull-down resistance on 2285 the D+ line. '1' pull down-resistance is connected 2286 to D+/ '0' pull down resistance is not connected 2287 to D+. When an A/B device is acting as a host 2288 (downstream-facing port), dp_pulldown and 2289 dm_pulldown are enabled. This must not toggle 2290 during normal opeartion. */ 2291 uint64_t dm_pulld : 1; /**< PHY DM_PULLDOWN input to the USB-PHY. 2292 This signal enables the pull-down resistance on 2293 the D- line. '1' pull down-resistance is connected 2294 to D-. '0' pull down resistance is not connected 2295 to D-. When an A/B device is acting as a host 2296 (downstream-facing port), dp_pulldown and 2297 dm_pulldown are enabled. This must not toggle 2298 during normal opeartion. */ 2299 uint64_t hst_mode : 1; /**< When '0' the USB is acting as HOST, when '1' 2300 USB is acting as device. This field needs to be 2301 set while the USB is in reset. */ 2302 uint64_t reserved_19_22 : 4; 2303 uint64_t tx_bs_enh : 1; /**< Transmit Bit Stuffing on [15:8]. 2304 Enables or disables bit stuffing on data[15:8] 2305 when bit-stuffing is enabled. */ 2306 uint64_t tx_bs_en : 1; /**< Transmit Bit Stuffing on [7:0]. 2307 Enables or disables bit stuffing on data[7:0] 2308 when bit-stuffing is enabled. */ 2309 uint64_t loop_enb : 1; /**< PHY Loopback Test Enable. 2310 '1': During data transmission the receive is 2311 enabled. 2312 '0': During data transmission the receive is 2313 disabled. 2314 Must be '0' for normal operation. */ 2315 uint64_t vtest_enb : 1; /**< Analog Test Pin Enable. 2316 '1' The PHY's analog_test pin is enabled for the 2317 input and output of applicable analog test signals. 2318 '0' THe analog_test pin is disabled. */ 2319 uint64_t bist_enb : 1; /**< Built-In Self Test Enable. 2320 Used to activate BIST in the PHY. */ 2321 uint64_t tdata_sel : 1; /**< Test Data Out Select. 2322 '1' test_data_out[3:0] (PHY) register contents 2323 are output. '0' internaly generated signals are 2324 output. */ 2325 uint64_t taddr_in : 4; /**< Mode Address for Test Interface. 2326 Specifies the register address for writing to or 2327 reading from the PHY test interface register. */ 2328 uint64_t tdata_in : 8; /**< Internal Testing Register Input Data and Select 2329 This is a test bus. Data is present on [3:0], 2330 and its corresponding select (enable) is present 2331 on bits [7:4]. */ 2332 uint64_t ate_reset : 1; /**< Reset input from automatic test equipment. 2333 This is a test signal. When the USB Core is 2334 powered up (not in Susned Mode), an automatic 2335 tester can use this to disable phy_clock and 2336 free_clk, then re-eanable them with an aligned 2337 phase. 2338 '1': The phy_clk and free_clk outputs are 2339 disabled. "0": The phy_clock and free_clk outputs 2340 are available within a specific period after the 2341 de-assertion. */ 2342#else 2343 uint64_t ate_reset : 1; 2344 uint64_t tdata_in : 8; 2345 uint64_t taddr_in : 4; 2346 uint64_t tdata_sel : 1; 2347 uint64_t bist_enb : 1; 2348 uint64_t vtest_enb : 1; 2349 uint64_t loop_enb : 1; 2350 uint64_t tx_bs_en : 1; 2351 uint64_t tx_bs_enh : 1; 2352 uint64_t reserved_19_22 : 4; 2353 uint64_t hst_mode : 1; 2354 uint64_t dm_pulld : 1; 2355 uint64_t dp_pulld : 1; 2356 uint64_t tclk : 1; 2357 uint64_t usbp_bist : 1; 2358 uint64_t usbc_end : 1; 2359 uint64_t dma_bmode : 1; 2360 uint64_t txpreemphasistune : 1; 2361 uint64_t siddq : 1; 2362 uint64_t tdata_out : 4; 2363 uint64_t bist_err : 1; 2364 uint64_t bist_done : 1; 2365 uint64_t hsbist : 1; 2366 uint64_t fsbist : 1; 2367 uint64_t lsbist : 1; 2368 uint64_t drvvbus : 1; 2369 uint64_t portreset : 1; 2370 uint64_t otgdisable : 1; 2371 uint64_t otgtune : 3; 2372 uint64_t compdistune : 3; 2373 uint64_t sqrxtune : 3; 2374 uint64_t txhsxvtune : 2; 2375 uint64_t txfslstune : 4; 2376 uint64_t txvreftune : 4; 2377 uint64_t txrisetune : 1; 2378#endif 2379 } cn52xx; 2380 struct cvmx_usbnx_usbp_ctl_status_cn50xx cn52xxp1; 2381 struct cvmx_usbnx_usbp_ctl_status_cn52xx cn56xx; 2382 struct cvmx_usbnx_usbp_ctl_status_cn50xx cn56xxp1; 2383}; 2384typedef union cvmx_usbnx_usbp_ctl_status cvmx_usbnx_usbp_ctl_status_t; 2385 2386#endif 2387