1/***********************license start*************** 2 * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Inc. nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * cvmx-usbnx-defs.h 43 * 44 * Configuration and status register (CSR) type definitions for 45 * Octeon usbnx. 46 * 47 * This file is auto generated. Do not edit. 48 * 49 * <hr>$Revision$<hr> 50 * 51 */ 52#ifndef __CVMX_USBNX_DEFS_H__ 53#define __CVMX_USBNX_DEFS_H__ 54 55#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56static inline uint64_t CVMX_USBNX_BIST_STATUS(unsigned long block_id) 57{ 58 if (!( 59 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 60 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 61 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 62 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 63 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 64 cvmx_warn("CVMX_USBNX_BIST_STATUS(%lu) is invalid on this chip\n", block_id); 65 return CVMX_ADD_IO_SEG(0x00011800680007F8ull) + ((block_id) & 1) * 0x10000000ull; 66} 67#else 68#define CVMX_USBNX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800680007F8ull) + ((block_id) & 1) * 0x10000000ull) 69#endif 70#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 71static inline uint64_t CVMX_USBNX_CLK_CTL(unsigned long block_id) 72{ 73 if (!( 74 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 75 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 76 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 77 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 78 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 79 cvmx_warn("CVMX_USBNX_CLK_CTL(%lu) is invalid on this chip\n", block_id); 80 return CVMX_ADD_IO_SEG(0x0001180068000010ull) + ((block_id) & 1) * 0x10000000ull; 81} 82#else 83#define CVMX_USBNX_CLK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180068000010ull) + ((block_id) & 1) * 0x10000000ull) 84#endif 85#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 86static inline uint64_t CVMX_USBNX_CTL_STATUS(unsigned long block_id) 87{ 88 if (!( 89 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 90 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 91 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 92 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 93 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 94 cvmx_warn("CVMX_USBNX_CTL_STATUS(%lu) is invalid on this chip\n", block_id); 95 return CVMX_ADD_IO_SEG(0x00016F0000000800ull) + ((block_id) & 1) * 0x100000000000ull; 96} 97#else 98#define CVMX_USBNX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000800ull) + ((block_id) & 1) * 0x100000000000ull) 99#endif 100#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 101static inline uint64_t CVMX_USBNX_DMA0_INB_CHN0(unsigned long block_id) 102{ 103 if (!( 104 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 105 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 106 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 107 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 108 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 109 cvmx_warn("CVMX_USBNX_DMA0_INB_CHN0(%lu) is invalid on this chip\n", block_id); 110 return CVMX_ADD_IO_SEG(0x00016F0000000818ull) + ((block_id) & 1) * 0x100000000000ull; 111} 112#else 113#define CVMX_USBNX_DMA0_INB_CHN0(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000818ull) + ((block_id) & 1) * 0x100000000000ull) 114#endif 115#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 116static inline uint64_t CVMX_USBNX_DMA0_INB_CHN1(unsigned long block_id) 117{ 118 if (!( 119 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 120 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 121 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 122 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 123 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 124 cvmx_warn("CVMX_USBNX_DMA0_INB_CHN1(%lu) is invalid on this chip\n", block_id); 125 return CVMX_ADD_IO_SEG(0x00016F0000000820ull) + ((block_id) & 1) * 0x100000000000ull; 126} 127#else 128#define CVMX_USBNX_DMA0_INB_CHN1(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000820ull) + ((block_id) & 1) * 0x100000000000ull) 129#endif 130#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 131static inline uint64_t CVMX_USBNX_DMA0_INB_CHN2(unsigned long block_id) 132{ 133 if (!( 134 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 135 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 136 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 137 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 138 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 139 cvmx_warn("CVMX_USBNX_DMA0_INB_CHN2(%lu) is invalid on this chip\n", block_id); 140 return CVMX_ADD_IO_SEG(0x00016F0000000828ull) + ((block_id) & 1) * 0x100000000000ull; 141} 142#else 143#define CVMX_USBNX_DMA0_INB_CHN2(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000828ull) + ((block_id) & 1) * 0x100000000000ull) 144#endif 145#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 146static inline uint64_t CVMX_USBNX_DMA0_INB_CHN3(unsigned long block_id) 147{ 148 if (!( 149 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 150 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 151 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 152 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 153 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 154 cvmx_warn("CVMX_USBNX_DMA0_INB_CHN3(%lu) is invalid on this chip\n", block_id); 155 return CVMX_ADD_IO_SEG(0x00016F0000000830ull) + ((block_id) & 1) * 0x100000000000ull; 156} 157#else 158#define CVMX_USBNX_DMA0_INB_CHN3(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000830ull) + ((block_id) & 1) * 0x100000000000ull) 159#endif 160#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 161static inline uint64_t CVMX_USBNX_DMA0_INB_CHN4(unsigned long block_id) 162{ 163 if (!( 164 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 165 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 166 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 167 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 168 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 169 cvmx_warn("CVMX_USBNX_DMA0_INB_CHN4(%lu) is invalid on this chip\n", block_id); 170 return CVMX_ADD_IO_SEG(0x00016F0000000838ull) + ((block_id) & 1) * 0x100000000000ull; 171} 172#else 173#define CVMX_USBNX_DMA0_INB_CHN4(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000838ull) + ((block_id) & 1) * 0x100000000000ull) 174#endif 175#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 176static inline uint64_t CVMX_USBNX_DMA0_INB_CHN5(unsigned long block_id) 177{ 178 if (!( 179 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 180 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 181 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 182 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 183 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 184 cvmx_warn("CVMX_USBNX_DMA0_INB_CHN5(%lu) is invalid on this chip\n", block_id); 185 return CVMX_ADD_IO_SEG(0x00016F0000000840ull) + ((block_id) & 1) * 0x100000000000ull; 186} 187#else 188#define CVMX_USBNX_DMA0_INB_CHN5(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000840ull) + ((block_id) & 1) * 0x100000000000ull) 189#endif 190#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 191static inline uint64_t CVMX_USBNX_DMA0_INB_CHN6(unsigned long block_id) 192{ 193 if (!( 194 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 195 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 196 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 197 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 198 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 199 cvmx_warn("CVMX_USBNX_DMA0_INB_CHN6(%lu) is invalid on this chip\n", block_id); 200 return CVMX_ADD_IO_SEG(0x00016F0000000848ull) + ((block_id) & 1) * 0x100000000000ull; 201} 202#else 203#define CVMX_USBNX_DMA0_INB_CHN6(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000848ull) + ((block_id) & 1) * 0x100000000000ull) 204#endif 205#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 206static inline uint64_t CVMX_USBNX_DMA0_INB_CHN7(unsigned long block_id) 207{ 208 if (!( 209 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 210 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 211 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 212 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 213 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 214 cvmx_warn("CVMX_USBNX_DMA0_INB_CHN7(%lu) is invalid on this chip\n", block_id); 215 return CVMX_ADD_IO_SEG(0x00016F0000000850ull) + ((block_id) & 1) * 0x100000000000ull; 216} 217#else 218#define CVMX_USBNX_DMA0_INB_CHN7(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000850ull) + ((block_id) & 1) * 0x100000000000ull) 219#endif 220#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 221static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN0(unsigned long block_id) 222{ 223 if (!( 224 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 225 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 226 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 227 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 228 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 229 cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN0(%lu) is invalid on this chip\n", block_id); 230 return CVMX_ADD_IO_SEG(0x00016F0000000858ull) + ((block_id) & 1) * 0x100000000000ull; 231} 232#else 233#define CVMX_USBNX_DMA0_OUTB_CHN0(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000858ull) + ((block_id) & 1) * 0x100000000000ull) 234#endif 235#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 236static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN1(unsigned long block_id) 237{ 238 if (!( 239 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 240 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 241 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 242 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 243 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 244 cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN1(%lu) is invalid on this chip\n", block_id); 245 return CVMX_ADD_IO_SEG(0x00016F0000000860ull) + ((block_id) & 1) * 0x100000000000ull; 246} 247#else 248#define CVMX_USBNX_DMA0_OUTB_CHN1(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000860ull) + ((block_id) & 1) * 0x100000000000ull) 249#endif 250#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 251static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN2(unsigned long block_id) 252{ 253 if (!( 254 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 255 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 256 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 257 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 258 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 259 cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN2(%lu) is invalid on this chip\n", block_id); 260 return CVMX_ADD_IO_SEG(0x00016F0000000868ull) + ((block_id) & 1) * 0x100000000000ull; 261} 262#else 263#define CVMX_USBNX_DMA0_OUTB_CHN2(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000868ull) + ((block_id) & 1) * 0x100000000000ull) 264#endif 265#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 266static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN3(unsigned long block_id) 267{ 268 if (!( 269 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 270 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 271 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 272 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 273 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 274 cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN3(%lu) is invalid on this chip\n", block_id); 275 return CVMX_ADD_IO_SEG(0x00016F0000000870ull) + ((block_id) & 1) * 0x100000000000ull; 276} 277#else 278#define CVMX_USBNX_DMA0_OUTB_CHN3(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000870ull) + ((block_id) & 1) * 0x100000000000ull) 279#endif 280#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 281static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN4(unsigned long block_id) 282{ 283 if (!( 284 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 285 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 286 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 287 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 288 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 289 cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN4(%lu) is invalid on this chip\n", block_id); 290 return CVMX_ADD_IO_SEG(0x00016F0000000878ull) + ((block_id) & 1) * 0x100000000000ull; 291} 292#else 293#define CVMX_USBNX_DMA0_OUTB_CHN4(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000878ull) + ((block_id) & 1) * 0x100000000000ull) 294#endif 295#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 296static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN5(unsigned long block_id) 297{ 298 if (!( 299 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 300 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 301 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 302 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 303 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 304 cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN5(%lu) is invalid on this chip\n", block_id); 305 return CVMX_ADD_IO_SEG(0x00016F0000000880ull) + ((block_id) & 1) * 0x100000000000ull; 306} 307#else 308#define CVMX_USBNX_DMA0_OUTB_CHN5(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000880ull) + ((block_id) & 1) * 0x100000000000ull) 309#endif 310#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 311static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN6(unsigned long block_id) 312{ 313 if (!( 314 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 315 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 316 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 317 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 318 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 319 cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN6(%lu) is invalid on this chip\n", block_id); 320 return CVMX_ADD_IO_SEG(0x00016F0000000888ull) + ((block_id) & 1) * 0x100000000000ull; 321} 322#else 323#define CVMX_USBNX_DMA0_OUTB_CHN6(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000888ull) + ((block_id) & 1) * 0x100000000000ull) 324#endif 325#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 326static inline uint64_t CVMX_USBNX_DMA0_OUTB_CHN7(unsigned long block_id) 327{ 328 if (!( 329 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 330 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 331 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 332 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 333 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 334 cvmx_warn("CVMX_USBNX_DMA0_OUTB_CHN7(%lu) is invalid on this chip\n", block_id); 335 return CVMX_ADD_IO_SEG(0x00016F0000000890ull) + ((block_id) & 1) * 0x100000000000ull; 336} 337#else 338#define CVMX_USBNX_DMA0_OUTB_CHN7(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000890ull) + ((block_id) & 1) * 0x100000000000ull) 339#endif 340#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 341static inline uint64_t CVMX_USBNX_DMA_TEST(unsigned long block_id) 342{ 343 if (!( 344 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 345 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 346 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 347 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 348 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 349 cvmx_warn("CVMX_USBNX_DMA_TEST(%lu) is invalid on this chip\n", block_id); 350 return CVMX_ADD_IO_SEG(0x00016F0000000808ull) + ((block_id) & 1) * 0x100000000000ull; 351} 352#else 353#define CVMX_USBNX_DMA_TEST(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000808ull) + ((block_id) & 1) * 0x100000000000ull) 354#endif 355#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 356static inline uint64_t CVMX_USBNX_INT_ENB(unsigned long block_id) 357{ 358 if (!( 359 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 360 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 361 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 362 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 363 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 364 cvmx_warn("CVMX_USBNX_INT_ENB(%lu) is invalid on this chip\n", block_id); 365 return CVMX_ADD_IO_SEG(0x0001180068000008ull) + ((block_id) & 1) * 0x10000000ull; 366} 367#else 368#define CVMX_USBNX_INT_ENB(block_id) (CVMX_ADD_IO_SEG(0x0001180068000008ull) + ((block_id) & 1) * 0x10000000ull) 369#endif 370#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 371static inline uint64_t CVMX_USBNX_INT_SUM(unsigned long block_id) 372{ 373 if (!( 374 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 375 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 376 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 377 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 378 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 379 cvmx_warn("CVMX_USBNX_INT_SUM(%lu) is invalid on this chip\n", block_id); 380 return CVMX_ADD_IO_SEG(0x0001180068000000ull) + ((block_id) & 1) * 0x10000000ull; 381} 382#else 383#define CVMX_USBNX_INT_SUM(block_id) (CVMX_ADD_IO_SEG(0x0001180068000000ull) + ((block_id) & 1) * 0x10000000ull) 384#endif 385#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 386static inline uint64_t CVMX_USBNX_USBP_CTL_STATUS(unsigned long block_id) 387{ 388 if (!( 389 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((block_id == 0))) || 390 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((block_id == 0))) || 391 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((block_id == 0))) || 392 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 393 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id == 0))))) 394 cvmx_warn("CVMX_USBNX_USBP_CTL_STATUS(%lu) is invalid on this chip\n", block_id); 395 return CVMX_ADD_IO_SEG(0x0001180068000018ull) + ((block_id) & 1) * 0x10000000ull; 396} 397#else 398#define CVMX_USBNX_USBP_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x0001180068000018ull) + ((block_id) & 1) * 0x10000000ull) 399#endif 400 401/** 402 * cvmx_usbn#_bist_status 403 * 404 * USBN_BIST_STATUS = USBN's Control and Status 405 * 406 * Contain general control bits and status information for the USBN. 407 */ 408union cvmx_usbnx_bist_status { 409 uint64_t u64; 410 struct cvmx_usbnx_bist_status_s { 411#ifdef __BIG_ENDIAN_BITFIELD 412 uint64_t reserved_7_63 : 57; 413 uint64_t u2nc_bis : 1; /**< Bist status U2N CTL FIFO Memory. */ 414 uint64_t u2nf_bis : 1; /**< Bist status U2N FIFO Memory. */ 415 uint64_t e2hc_bis : 1; /**< Bist status E2H CTL FIFO Memory. */ 416 uint64_t n2uf_bis : 1; /**< Bist status N2U FIFO Memory. */ 417 uint64_t usbc_bis : 1; /**< Bist status USBC FIFO Memory. */ 418 uint64_t nif_bis : 1; /**< Bist status for Inbound Memory. */ 419 uint64_t nof_bis : 1; /**< Bist status for Outbound Memory. */ 420#else 421 uint64_t nof_bis : 1; 422 uint64_t nif_bis : 1; 423 uint64_t usbc_bis : 1; 424 uint64_t n2uf_bis : 1; 425 uint64_t e2hc_bis : 1; 426 uint64_t u2nf_bis : 1; 427 uint64_t u2nc_bis : 1; 428 uint64_t reserved_7_63 : 57; 429#endif 430 } s; 431 struct cvmx_usbnx_bist_status_cn30xx { 432#ifdef __BIG_ENDIAN_BITFIELD 433 uint64_t reserved_3_63 : 61; 434 uint64_t usbc_bis : 1; /**< Bist status USBC FIFO Memory. */ 435 uint64_t nif_bis : 1; /**< Bist status for Inbound Memory. */ 436 uint64_t nof_bis : 1; /**< Bist status for Outbound Memory. */ 437#else 438 uint64_t nof_bis : 1; 439 uint64_t nif_bis : 1; 440 uint64_t usbc_bis : 1; 441 uint64_t reserved_3_63 : 61; 442#endif 443 } cn30xx; 444 struct cvmx_usbnx_bist_status_cn30xx cn31xx; 445 struct cvmx_usbnx_bist_status_s cn50xx; 446 struct cvmx_usbnx_bist_status_s cn52xx; 447 struct cvmx_usbnx_bist_status_s cn52xxp1; 448 struct cvmx_usbnx_bist_status_s cn56xx; 449 struct cvmx_usbnx_bist_status_s cn56xxp1; 450}; 451typedef union cvmx_usbnx_bist_status cvmx_usbnx_bist_status_t; 452 453/** 454 * cvmx_usbn#_clk_ctl 455 * 456 * USBN_CLK_CTL = USBN's Clock Control 457 * 458 * This register is used to control the frequency of the hclk and the hreset and phy_rst signals. 459 */ 460union cvmx_usbnx_clk_ctl { 461 uint64_t u64; 462 struct cvmx_usbnx_clk_ctl_s { 463#ifdef __BIG_ENDIAN_BITFIELD 464 uint64_t reserved_20_63 : 44; 465 uint64_t divide2 : 2; /**< The 'hclk' used by the USB subsystem is derived 466 from the eclk. 467 Also see the field DIVIDE. DIVIDE2<1> must currently 468 be zero because it is not implemented, so the maximum 469 ratio of eclk/hclk is currently 16. 470 The actual divide number for hclk is: 471 (DIVIDE2 + 1) * (DIVIDE + 1) */ 472 uint64_t hclk_rst : 1; /**< When this field is '0' the HCLK-DIVIDER used to 473 generate the hclk in the USB Subsystem is held 474 in reset. This bit must be set to '0' before 475 changing the value os DIVIDE in this register. 476 The reset to the HCLK_DIVIDERis also asserted 477 when core reset is asserted. */ 478 uint64_t p_x_on : 1; /**< Force USB-PHY on during suspend. 479 '1' USB-PHY XO block is powered-down during 480 suspend. 481 '0' USB-PHY XO block is powered-up during 482 suspend. 483 The value of this field must be set while POR is 484 active. */ 485 uint64_t reserved_14_15 : 2; 486 uint64_t p_com_on : 1; /**< '0' Force USB-PHY XO Bias, Bandgap and PLL to 487 remain powered in Suspend Mode. 488 '1' The USB-PHY XO Bias, Bandgap and PLL are 489 powered down in suspend mode. 490 The value of this field must be set while POR is 491 active. */ 492 uint64_t p_c_sel : 2; /**< Phy clock speed select. 493 Selects the reference clock / crystal frequency. 494 '11': Reserved 495 '10': 48 MHz (reserved when a crystal is used) 496 '01': 24 MHz (reserved when a crystal is used) 497 '00': 12 MHz 498 The value of this field must be set while POR is 499 active. 500 NOTE: if a crystal is used as a reference clock, 501 this field must be set to 12 MHz. */ 502 uint64_t cdiv_byp : 1; /**< Used to enable the bypass input to the USB_CLK_DIV. */ 503 uint64_t sd_mode : 2; /**< Scaledown mode for the USBC. Control timing events 504 in the USBC, for normal operation this must be '0'. */ 505 uint64_t s_bist : 1; /**< Starts bist on the hclk memories, during the '0' 506 to '1' transition. */ 507 uint64_t por : 1; /**< Power On Reset for the PHY. 508 Resets all the PHYS registers and state machines. */ 509 uint64_t enable : 1; /**< When '1' allows the generation of the hclk. When 510 '0' the hclk will not be generated. SEE DIVIDE 511 field of this register. */ 512 uint64_t prst : 1; /**< When this field is '0' the reset associated with 513 the phy_clk functionality in the USB Subsystem is 514 help in reset. This bit should not be set to '1' 515 until the time it takes 6 clocks (hclk or phy_clk, 516 whichever is slower) has passed. Under normal 517 operation once this bit is set to '1' it should not 518 be set to '0'. */ 519 uint64_t hrst : 1; /**< When this field is '0' the reset associated with 520 the hclk functioanlity in the USB Subsystem is 521 held in reset.This bit should not be set to '1' 522 until 12ms after phy_clk is stable. Under normal 523 operation, once this bit is set to '1' it should 524 not be set to '0'. */ 525 uint64_t divide : 3; /**< The frequency of 'hclk' used by the USB subsystem 526 is the eclk frequency divided by the value of 527 (DIVIDE2 + 1) * (DIVIDE + 1), also see the field 528 DIVIDE2 of this register. 529 The hclk frequency should be less than 125Mhz. 530 After writing a value to this field the SW should 531 read the field for the value written. 532 The ENABLE field of this register should not be set 533 until AFTER this field is set and then read. */ 534#else 535 uint64_t divide : 3; 536 uint64_t hrst : 1; 537 uint64_t prst : 1; 538 uint64_t enable : 1; 539 uint64_t por : 1; 540 uint64_t s_bist : 1; 541 uint64_t sd_mode : 2; 542 uint64_t cdiv_byp : 1; 543 uint64_t p_c_sel : 2; 544 uint64_t p_com_on : 1; 545 uint64_t reserved_14_15 : 2; 546 uint64_t p_x_on : 1; 547 uint64_t hclk_rst : 1; 548 uint64_t divide2 : 2; 549 uint64_t reserved_20_63 : 44; 550#endif 551 } s; 552 struct cvmx_usbnx_clk_ctl_cn30xx { 553#ifdef __BIG_ENDIAN_BITFIELD 554 uint64_t reserved_18_63 : 46; 555 uint64_t hclk_rst : 1; /**< When this field is '0' the HCLK-DIVIDER used to 556 generate the hclk in the USB Subsystem is held 557 in reset. This bit must be set to '0' before 558 changing the value os DIVIDE in this register. 559 The reset to the HCLK_DIVIDERis also asserted 560 when core reset is asserted. */ 561 uint64_t p_x_on : 1; /**< Force USB-PHY on during suspend. 562 '1' USB-PHY XO block is powered-down during 563 suspend. 564 '0' USB-PHY XO block is powered-up during 565 suspend. 566 The value of this field must be set while POR is 567 active. */ 568 uint64_t p_rclk : 1; /**< Phy refrence clock enable. 569 '1' The PHY PLL uses the XO block output as a 570 reference. 571 '0' Reserved. */ 572 uint64_t p_xenbn : 1; /**< Phy external clock enable. 573 '1' The XO block uses the clock from a crystal. 574 '0' The XO block uses an external clock supplied 575 on the XO pin. USB_XI should be tied to 576 ground for this usage. */ 577 uint64_t p_com_on : 1; /**< '0' Force USB-PHY XO Bias, Bandgap and PLL to 578 remain powered in Suspend Mode. 579 '1' The USB-PHY XO Bias, Bandgap and PLL are 580 powered down in suspend mode. 581 The value of this field must be set while POR is 582 active. */ 583 uint64_t p_c_sel : 2; /**< Phy clock speed select. 584 Selects the reference clock / crystal frequency. 585 '11': Reserved 586 '10': 48 MHz 587 '01': 24 MHz 588 '00': 12 MHz 589 The value of this field must be set while POR is 590 active. */ 591 uint64_t cdiv_byp : 1; /**< Used to enable the bypass input to the USB_CLK_DIV. */ 592 uint64_t sd_mode : 2; /**< Scaledown mode for the USBC. Control timing events 593 in the USBC, for normal operation this must be '0'. */ 594 uint64_t s_bist : 1; /**< Starts bist on the hclk memories, during the '0' 595 to '1' transition. */ 596 uint64_t por : 1; /**< Power On Reset for the PHY. 597 Resets all the PHYS registers and state machines. */ 598 uint64_t enable : 1; /**< When '1' allows the generation of the hclk. When 599 '0' the hclk will not be generated. */ 600 uint64_t prst : 1; /**< When this field is '0' the reset associated with 601 the phy_clk functionality in the USB Subsystem is 602 help in reset. This bit should not be set to '1' 603 until the time it takes 6 clocks (hclk or phy_clk, 604 whichever is slower) has passed. Under normal 605 operation once this bit is set to '1' it should not 606 be set to '0'. */ 607 uint64_t hrst : 1; /**< When this field is '0' the reset associated with 608 the hclk functioanlity in the USB Subsystem is 609 held in reset.This bit should not be set to '1' 610 until 12ms after phy_clk is stable. Under normal 611 operation, once this bit is set to '1' it should 612 not be set to '0'. */ 613 uint64_t divide : 3; /**< The 'hclk' used by the USB subsystem is derived 614 from the eclk. The eclk will be divided by the 615 value of this field +1 to determine the hclk 616 frequency. (Also see HRST of this register). 617 The hclk frequency must be less than 125 MHz. */ 618#else 619 uint64_t divide : 3; 620 uint64_t hrst : 1; 621 uint64_t prst : 1; 622 uint64_t enable : 1; 623 uint64_t por : 1; 624 uint64_t s_bist : 1; 625 uint64_t sd_mode : 2; 626 uint64_t cdiv_byp : 1; 627 uint64_t p_c_sel : 2; 628 uint64_t p_com_on : 1; 629 uint64_t p_xenbn : 1; 630 uint64_t p_rclk : 1; 631 uint64_t p_x_on : 1; 632 uint64_t hclk_rst : 1; 633 uint64_t reserved_18_63 : 46; 634#endif 635 } cn30xx; 636 struct cvmx_usbnx_clk_ctl_cn30xx cn31xx; 637 struct cvmx_usbnx_clk_ctl_cn50xx { 638#ifdef __BIG_ENDIAN_BITFIELD 639 uint64_t reserved_20_63 : 44; 640 uint64_t divide2 : 2; /**< The 'hclk' used by the USB subsystem is derived 641 from the eclk. 642 Also see the field DIVIDE. DIVIDE2<1> must currently 643 be zero because it is not implemented, so the maximum 644 ratio of eclk/hclk is currently 16. 645 The actual divide number for hclk is: 646 (DIVIDE2 + 1) * (DIVIDE + 1) */ 647 uint64_t hclk_rst : 1; /**< When this field is '0' the HCLK-DIVIDER used to 648 generate the hclk in the USB Subsystem is held 649 in reset. This bit must be set to '0' before 650 changing the value os DIVIDE in this register. 651 The reset to the HCLK_DIVIDERis also asserted 652 when core reset is asserted. */ 653 uint64_t reserved_16_16 : 1; 654 uint64_t p_rtype : 2; /**< PHY reference clock type 655 '0' The USB-PHY uses a 12MHz crystal as a clock 656 source at the USB_XO and USB_XI pins 657 '1' Reserved 658 '2' The USB_PHY uses 12/24/48MHz 2.5V board clock 659 at the USB_XO pin. USB_XI should be tied to 660 ground in this case. 661 '3' Reserved 662 (bit 14 was P_XENBN on 3xxx) 663 (bit 15 was P_RCLK on 3xxx) */ 664 uint64_t p_com_on : 1; /**< '0' Force USB-PHY XO Bias, Bandgap and PLL to 665 remain powered in Suspend Mode. 666 '1' The USB-PHY XO Bias, Bandgap and PLL are 667 powered down in suspend mode. 668 The value of this field must be set while POR is 669 active. */ 670 uint64_t p_c_sel : 2; /**< Phy clock speed select. 671 Selects the reference clock / crystal frequency. 672 '11': Reserved 673 '10': 48 MHz (reserved when a crystal is used) 674 '01': 24 MHz (reserved when a crystal is used) 675 '00': 12 MHz 676 The value of this field must be set while POR is 677 active. 678 NOTE: if a crystal is used as a reference clock, 679 this field must be set to 12 MHz. */ 680 uint64_t cdiv_byp : 1; /**< Used to enable the bypass input to the USB_CLK_DIV. */ 681 uint64_t sd_mode : 2; /**< Scaledown mode for the USBC. Control timing events 682 in the USBC, for normal operation this must be '0'. */ 683 uint64_t s_bist : 1; /**< Starts bist on the hclk memories, during the '0' 684 to '1' transition. */ 685 uint64_t por : 1; /**< Power On Reset for the PHY. 686 Resets all the PHYS registers and state machines. */ 687 uint64_t enable : 1; /**< When '1' allows the generation of the hclk. When 688 '0' the hclk will not be generated. SEE DIVIDE 689 field of this register. */ 690 uint64_t prst : 1; /**< When this field is '0' the reset associated with 691 the phy_clk functionality in the USB Subsystem is 692 help in reset. This bit should not be set to '1' 693 until the time it takes 6 clocks (hclk or phy_clk, 694 whichever is slower) has passed. Under normal 695 operation once this bit is set to '1' it should not 696 be set to '0'. */ 697 uint64_t hrst : 1; /**< When this field is '0' the reset associated with 698 the hclk functioanlity in the USB Subsystem is 699 held in reset.This bit should not be set to '1' 700 until 12ms after phy_clk is stable. Under normal 701 operation, once this bit is set to '1' it should 702 not be set to '0'. */ 703 uint64_t divide : 3; /**< The frequency of 'hclk' used by the USB subsystem 704 is the eclk frequency divided by the value of 705 (DIVIDE2 + 1) * (DIVIDE + 1), also see the field 706 DIVIDE2 of this register. 707 The hclk frequency should be less than 125Mhz. 708 After writing a value to this field the SW should 709 read the field for the value written. 710 The ENABLE field of this register should not be set 711 until AFTER this field is set and then read. */ 712#else 713 uint64_t divide : 3; 714 uint64_t hrst : 1; 715 uint64_t prst : 1; 716 uint64_t enable : 1; 717 uint64_t por : 1; 718 uint64_t s_bist : 1; 719 uint64_t sd_mode : 2; 720 uint64_t cdiv_byp : 1; 721 uint64_t p_c_sel : 2; 722 uint64_t p_com_on : 1; 723 uint64_t p_rtype : 2; 724 uint64_t reserved_16_16 : 1; 725 uint64_t hclk_rst : 1; 726 uint64_t divide2 : 2; 727 uint64_t reserved_20_63 : 44; 728#endif 729 } cn50xx; 730 struct cvmx_usbnx_clk_ctl_cn50xx cn52xx; 731 struct cvmx_usbnx_clk_ctl_cn50xx cn52xxp1; 732 struct cvmx_usbnx_clk_ctl_cn50xx cn56xx; 733 struct cvmx_usbnx_clk_ctl_cn50xx cn56xxp1; 734}; 735typedef union cvmx_usbnx_clk_ctl cvmx_usbnx_clk_ctl_t; 736 737/** 738 * cvmx_usbn#_ctl_status 739 * 740 * USBN_CTL_STATUS = USBN's Control And Status Register 741 * 742 * Contains general control and status information for the USBN block. 743 */ 744union cvmx_usbnx_ctl_status { 745 uint64_t u64; 746 struct cvmx_usbnx_ctl_status_s { 747#ifdef __BIG_ENDIAN_BITFIELD 748 uint64_t reserved_6_63 : 58; 749 uint64_t dma_0pag : 1; /**< When '1' sets the DMA engine will set the zero-Page 750 bit in the L2C store operation to the IOB. */ 751 uint64_t dma_stt : 1; /**< When '1' sets the DMA engine to use STT operations. */ 752 uint64_t dma_test : 1; /**< When '1' sets the DMA engine into Test-Mode. 753 For normal operation this bit should be '0'. */ 754 uint64_t inv_a2 : 1; /**< When '1' causes the address[2] driven on the AHB 755 for USB-CORE FIFO access to be inverted. Also data 756 writen to and read from the AHB will have it byte 757 order swapped. If the orginal order was A-B-C-D the 758 new byte order will be D-C-B-A. */ 759 uint64_t l2c_emod : 2; /**< Endian format for data from/to the L2C. 760 IN: A-B-C-D-E-F-G-H 761 OUT0: A-B-C-D-E-F-G-H 762 OUT1: H-G-F-E-D-C-B-A 763 OUT2: D-C-B-A-H-G-F-E 764 OUT3: E-F-G-H-A-B-C-D */ 765#else 766 uint64_t l2c_emod : 2; 767 uint64_t inv_a2 : 1; 768 uint64_t dma_test : 1; 769 uint64_t dma_stt : 1; 770 uint64_t dma_0pag : 1; 771 uint64_t reserved_6_63 : 58; 772#endif 773 } s; 774 struct cvmx_usbnx_ctl_status_s cn30xx; 775 struct cvmx_usbnx_ctl_status_s cn31xx; 776 struct cvmx_usbnx_ctl_status_s cn50xx; 777 struct cvmx_usbnx_ctl_status_s cn52xx; 778 struct cvmx_usbnx_ctl_status_s cn52xxp1; 779 struct cvmx_usbnx_ctl_status_s cn56xx; 780 struct cvmx_usbnx_ctl_status_s cn56xxp1; 781}; 782typedef union cvmx_usbnx_ctl_status cvmx_usbnx_ctl_status_t; 783 784/** 785 * cvmx_usbn#_dma0_inb_chn0 786 * 787 * USBN_DMA0_INB_CHN0 = USBN's Inbound DMA for USB0 Channel0 788 * 789 * Contains the starting address for use when USB0 writes to L2C via Channel0. 790 * Writing of this register sets the base address. 791 */ 792union cvmx_usbnx_dma0_inb_chn0 { 793 uint64_t u64; 794 struct cvmx_usbnx_dma0_inb_chn0_s { 795#ifdef __BIG_ENDIAN_BITFIELD 796 uint64_t reserved_36_63 : 28; 797 uint64_t addr : 36; /**< Base address for DMA Write to L2C. */ 798#else 799 uint64_t addr : 36; 800 uint64_t reserved_36_63 : 28; 801#endif 802 } s; 803 struct cvmx_usbnx_dma0_inb_chn0_s cn30xx; 804 struct cvmx_usbnx_dma0_inb_chn0_s cn31xx; 805 struct cvmx_usbnx_dma0_inb_chn0_s cn50xx; 806 struct cvmx_usbnx_dma0_inb_chn0_s cn52xx; 807 struct cvmx_usbnx_dma0_inb_chn0_s cn52xxp1; 808 struct cvmx_usbnx_dma0_inb_chn0_s cn56xx; 809 struct cvmx_usbnx_dma0_inb_chn0_s cn56xxp1; 810}; 811typedef union cvmx_usbnx_dma0_inb_chn0 cvmx_usbnx_dma0_inb_chn0_t; 812 813/** 814 * cvmx_usbn#_dma0_inb_chn1 815 * 816 * USBN_DMA0_INB_CHN1 = USBN's Inbound DMA for USB0 Channel1 817 * 818 * Contains the starting address for use when USB0 writes to L2C via Channel1. 819 * Writing of this register sets the base address. 820 */ 821union cvmx_usbnx_dma0_inb_chn1 { 822 uint64_t u64; 823 struct cvmx_usbnx_dma0_inb_chn1_s { 824#ifdef __BIG_ENDIAN_BITFIELD 825 uint64_t reserved_36_63 : 28; 826 uint64_t addr : 36; /**< Base address for DMA Write to L2C. */ 827#else 828 uint64_t addr : 36; 829 uint64_t reserved_36_63 : 28; 830#endif 831 } s; 832 struct cvmx_usbnx_dma0_inb_chn1_s cn30xx; 833 struct cvmx_usbnx_dma0_inb_chn1_s cn31xx; 834 struct cvmx_usbnx_dma0_inb_chn1_s cn50xx; 835 struct cvmx_usbnx_dma0_inb_chn1_s cn52xx; 836 struct cvmx_usbnx_dma0_inb_chn1_s cn52xxp1; 837 struct cvmx_usbnx_dma0_inb_chn1_s cn56xx; 838 struct cvmx_usbnx_dma0_inb_chn1_s cn56xxp1; 839}; 840typedef union cvmx_usbnx_dma0_inb_chn1 cvmx_usbnx_dma0_inb_chn1_t; 841 842/** 843 * cvmx_usbn#_dma0_inb_chn2 844 * 845 * USBN_DMA0_INB_CHN2 = USBN's Inbound DMA for USB0 Channel2 846 * 847 * Contains the starting address for use when USB0 writes to L2C via Channel2. 848 * Writing of this register sets the base address. 849 */ 850union cvmx_usbnx_dma0_inb_chn2 { 851 uint64_t u64; 852 struct cvmx_usbnx_dma0_inb_chn2_s { 853#ifdef __BIG_ENDIAN_BITFIELD 854 uint64_t reserved_36_63 : 28; 855 uint64_t addr : 36; /**< Base address for DMA Write to L2C. */ 856#else 857 uint64_t addr : 36; 858 uint64_t reserved_36_63 : 28; 859#endif 860 } s; 861 struct cvmx_usbnx_dma0_inb_chn2_s cn30xx; 862 struct cvmx_usbnx_dma0_inb_chn2_s cn31xx; 863 struct cvmx_usbnx_dma0_inb_chn2_s cn50xx; 864 struct cvmx_usbnx_dma0_inb_chn2_s cn52xx; 865 struct cvmx_usbnx_dma0_inb_chn2_s cn52xxp1; 866 struct cvmx_usbnx_dma0_inb_chn2_s cn56xx; 867 struct cvmx_usbnx_dma0_inb_chn2_s cn56xxp1; 868}; 869typedef union cvmx_usbnx_dma0_inb_chn2 cvmx_usbnx_dma0_inb_chn2_t; 870 871/** 872 * cvmx_usbn#_dma0_inb_chn3 873 * 874 * USBN_DMA0_INB_CHN3 = USBN's Inbound DMA for USB0 Channel3 875 * 876 * Contains the starting address for use when USB0 writes to L2C via Channel3. 877 * Writing of this register sets the base address. 878 */ 879union cvmx_usbnx_dma0_inb_chn3 { 880 uint64_t u64; 881 struct cvmx_usbnx_dma0_inb_chn3_s { 882#ifdef __BIG_ENDIAN_BITFIELD 883 uint64_t reserved_36_63 : 28; 884 uint64_t addr : 36; /**< Base address for DMA Write to L2C. */ 885#else 886 uint64_t addr : 36; 887 uint64_t reserved_36_63 : 28; 888#endif 889 } s; 890 struct cvmx_usbnx_dma0_inb_chn3_s cn30xx; 891 struct cvmx_usbnx_dma0_inb_chn3_s cn31xx; 892 struct cvmx_usbnx_dma0_inb_chn3_s cn50xx; 893 struct cvmx_usbnx_dma0_inb_chn3_s cn52xx; 894 struct cvmx_usbnx_dma0_inb_chn3_s cn52xxp1; 895 struct cvmx_usbnx_dma0_inb_chn3_s cn56xx; 896 struct cvmx_usbnx_dma0_inb_chn3_s cn56xxp1; 897}; 898typedef union cvmx_usbnx_dma0_inb_chn3 cvmx_usbnx_dma0_inb_chn3_t; 899 900/** 901 * cvmx_usbn#_dma0_inb_chn4 902 * 903 * USBN_DMA0_INB_CHN4 = USBN's Inbound DMA for USB0 Channel4 904 * 905 * Contains the starting address for use when USB0 writes to L2C via Channel4. 906 * Writing of this register sets the base address. 907 */ 908union cvmx_usbnx_dma0_inb_chn4 { 909 uint64_t u64; 910 struct cvmx_usbnx_dma0_inb_chn4_s { 911#ifdef __BIG_ENDIAN_BITFIELD 912 uint64_t reserved_36_63 : 28; 913 uint64_t addr : 36; /**< Base address for DMA Write to L2C. */ 914#else 915 uint64_t addr : 36; 916 uint64_t reserved_36_63 : 28; 917#endif 918 } s; 919 struct cvmx_usbnx_dma0_inb_chn4_s cn30xx; 920 struct cvmx_usbnx_dma0_inb_chn4_s cn31xx; 921 struct cvmx_usbnx_dma0_inb_chn4_s cn50xx; 922 struct cvmx_usbnx_dma0_inb_chn4_s cn52xx; 923 struct cvmx_usbnx_dma0_inb_chn4_s cn52xxp1; 924 struct cvmx_usbnx_dma0_inb_chn4_s cn56xx; 925 struct cvmx_usbnx_dma0_inb_chn4_s cn56xxp1; 926}; 927typedef union cvmx_usbnx_dma0_inb_chn4 cvmx_usbnx_dma0_inb_chn4_t; 928 929/** 930 * cvmx_usbn#_dma0_inb_chn5 931 * 932 * USBN_DMA0_INB_CHN5 = USBN's Inbound DMA for USB0 Channel5 933 * 934 * Contains the starting address for use when USB0 writes to L2C via Channel5. 935 * Writing of this register sets the base address. 936 */ 937union cvmx_usbnx_dma0_inb_chn5 { 938 uint64_t u64; 939 struct cvmx_usbnx_dma0_inb_chn5_s { 940#ifdef __BIG_ENDIAN_BITFIELD 941 uint64_t reserved_36_63 : 28; 942 uint64_t addr : 36; /**< Base address for DMA Write to L2C. */ 943#else 944 uint64_t addr : 36; 945 uint64_t reserved_36_63 : 28; 946#endif 947 } s; 948 struct cvmx_usbnx_dma0_inb_chn5_s cn30xx; 949 struct cvmx_usbnx_dma0_inb_chn5_s cn31xx; 950 struct cvmx_usbnx_dma0_inb_chn5_s cn50xx; 951 struct cvmx_usbnx_dma0_inb_chn5_s cn52xx; 952 struct cvmx_usbnx_dma0_inb_chn5_s cn52xxp1; 953 struct cvmx_usbnx_dma0_inb_chn5_s cn56xx; 954 struct cvmx_usbnx_dma0_inb_chn5_s cn56xxp1; 955}; 956typedef union cvmx_usbnx_dma0_inb_chn5 cvmx_usbnx_dma0_inb_chn5_t; 957 958/** 959 * cvmx_usbn#_dma0_inb_chn6 960 * 961 * USBN_DMA0_INB_CHN6 = USBN's Inbound DMA for USB0 Channel6 962 * 963 * Contains the starting address for use when USB0 writes to L2C via Channel6. 964 * Writing of this register sets the base address. 965 */ 966union cvmx_usbnx_dma0_inb_chn6 { 967 uint64_t u64; 968 struct cvmx_usbnx_dma0_inb_chn6_s { 969#ifdef __BIG_ENDIAN_BITFIELD 970 uint64_t reserved_36_63 : 28; 971 uint64_t addr : 36; /**< Base address for DMA Write to L2C. */ 972#else 973 uint64_t addr : 36; 974 uint64_t reserved_36_63 : 28; 975#endif 976 } s; 977 struct cvmx_usbnx_dma0_inb_chn6_s cn30xx; 978 struct cvmx_usbnx_dma0_inb_chn6_s cn31xx; 979 struct cvmx_usbnx_dma0_inb_chn6_s cn50xx; 980 struct cvmx_usbnx_dma0_inb_chn6_s cn52xx; 981 struct cvmx_usbnx_dma0_inb_chn6_s cn52xxp1; 982 struct cvmx_usbnx_dma0_inb_chn6_s cn56xx; 983 struct cvmx_usbnx_dma0_inb_chn6_s cn56xxp1; 984}; 985typedef union cvmx_usbnx_dma0_inb_chn6 cvmx_usbnx_dma0_inb_chn6_t; 986 987/** 988 * cvmx_usbn#_dma0_inb_chn7 989 * 990 * USBN_DMA0_INB_CHN7 = USBN's Inbound DMA for USB0 Channel7 991 * 992 * Contains the starting address for use when USB0 writes to L2C via Channel7. 993 * Writing of this register sets the base address. 994 */ 995union cvmx_usbnx_dma0_inb_chn7 { 996 uint64_t u64; 997 struct cvmx_usbnx_dma0_inb_chn7_s { 998#ifdef __BIG_ENDIAN_BITFIELD 999 uint64_t reserved_36_63 : 28; 1000 uint64_t addr : 36; /**< Base address for DMA Write to L2C. */ 1001#else 1002 uint64_t addr : 36; 1003 uint64_t reserved_36_63 : 28; 1004#endif 1005 } s; 1006 struct cvmx_usbnx_dma0_inb_chn7_s cn30xx; 1007 struct cvmx_usbnx_dma0_inb_chn7_s cn31xx; 1008 struct cvmx_usbnx_dma0_inb_chn7_s cn50xx; 1009 struct cvmx_usbnx_dma0_inb_chn7_s cn52xx; 1010 struct cvmx_usbnx_dma0_inb_chn7_s cn52xxp1; 1011 struct cvmx_usbnx_dma0_inb_chn7_s cn56xx; 1012 struct cvmx_usbnx_dma0_inb_chn7_s cn56xxp1; 1013}; 1014typedef union cvmx_usbnx_dma0_inb_chn7 cvmx_usbnx_dma0_inb_chn7_t; 1015 1016/** 1017 * cvmx_usbn#_dma0_outb_chn0 1018 * 1019 * USBN_DMA0_OUTB_CHN0 = USBN's Outbound DMA for USB0 Channel0 1020 * 1021 * Contains the starting address for use when USB0 reads from L2C via Channel0. 1022 * Writing of this register sets the base address. 1023 */ 1024union cvmx_usbnx_dma0_outb_chn0 { 1025 uint64_t u64; 1026 struct cvmx_usbnx_dma0_outb_chn0_s { 1027#ifdef __BIG_ENDIAN_BITFIELD 1028 uint64_t reserved_36_63 : 28; 1029 uint64_t addr : 36; /**< Base address for DMA Read from L2C. */ 1030#else 1031 uint64_t addr : 36; 1032 uint64_t reserved_36_63 : 28; 1033#endif 1034 } s; 1035 struct cvmx_usbnx_dma0_outb_chn0_s cn30xx; 1036 struct cvmx_usbnx_dma0_outb_chn0_s cn31xx; 1037 struct cvmx_usbnx_dma0_outb_chn0_s cn50xx; 1038 struct cvmx_usbnx_dma0_outb_chn0_s cn52xx; 1039 struct cvmx_usbnx_dma0_outb_chn0_s cn52xxp1; 1040 struct cvmx_usbnx_dma0_outb_chn0_s cn56xx; 1041 struct cvmx_usbnx_dma0_outb_chn0_s cn56xxp1; 1042}; 1043typedef union cvmx_usbnx_dma0_outb_chn0 cvmx_usbnx_dma0_outb_chn0_t; 1044 1045/** 1046 * cvmx_usbn#_dma0_outb_chn1 1047 * 1048 * USBN_DMA0_OUTB_CHN1 = USBN's Outbound DMA for USB0 Channel1 1049 * 1050 * Contains the starting address for use when USB0 reads from L2C via Channel1. 1051 * Writing of this register sets the base address. 1052 */ 1053union cvmx_usbnx_dma0_outb_chn1 { 1054 uint64_t u64; 1055 struct cvmx_usbnx_dma0_outb_chn1_s { 1056#ifdef __BIG_ENDIAN_BITFIELD 1057 uint64_t reserved_36_63 : 28; 1058 uint64_t addr : 36; /**< Base address for DMA Read from L2C. */ 1059#else 1060 uint64_t addr : 36; 1061 uint64_t reserved_36_63 : 28; 1062#endif 1063 } s; 1064 struct cvmx_usbnx_dma0_outb_chn1_s cn30xx; 1065 struct cvmx_usbnx_dma0_outb_chn1_s cn31xx; 1066 struct cvmx_usbnx_dma0_outb_chn1_s cn50xx; 1067 struct cvmx_usbnx_dma0_outb_chn1_s cn52xx; 1068 struct cvmx_usbnx_dma0_outb_chn1_s cn52xxp1; 1069 struct cvmx_usbnx_dma0_outb_chn1_s cn56xx; 1070 struct cvmx_usbnx_dma0_outb_chn1_s cn56xxp1; 1071}; 1072typedef union cvmx_usbnx_dma0_outb_chn1 cvmx_usbnx_dma0_outb_chn1_t; 1073 1074/** 1075 * cvmx_usbn#_dma0_outb_chn2 1076 * 1077 * USBN_DMA0_OUTB_CHN2 = USBN's Outbound DMA for USB0 Channel2 1078 * 1079 * Contains the starting address for use when USB0 reads from L2C via Channel2. 1080 * Writing of this register sets the base address. 1081 */ 1082union cvmx_usbnx_dma0_outb_chn2 { 1083 uint64_t u64; 1084 struct cvmx_usbnx_dma0_outb_chn2_s { 1085#ifdef __BIG_ENDIAN_BITFIELD 1086 uint64_t reserved_36_63 : 28; 1087 uint64_t addr : 36; /**< Base address for DMA Read from L2C. */ 1088#else 1089 uint64_t addr : 36; 1090 uint64_t reserved_36_63 : 28; 1091#endif 1092 } s; 1093 struct cvmx_usbnx_dma0_outb_chn2_s cn30xx; 1094 struct cvmx_usbnx_dma0_outb_chn2_s cn31xx; 1095 struct cvmx_usbnx_dma0_outb_chn2_s cn50xx; 1096 struct cvmx_usbnx_dma0_outb_chn2_s cn52xx; 1097 struct cvmx_usbnx_dma0_outb_chn2_s cn52xxp1; 1098 struct cvmx_usbnx_dma0_outb_chn2_s cn56xx; 1099 struct cvmx_usbnx_dma0_outb_chn2_s cn56xxp1; 1100}; 1101typedef union cvmx_usbnx_dma0_outb_chn2 cvmx_usbnx_dma0_outb_chn2_t; 1102 1103/** 1104 * cvmx_usbn#_dma0_outb_chn3 1105 * 1106 * USBN_DMA0_OUTB_CHN3 = USBN's Outbound DMA for USB0 Channel3 1107 * 1108 * Contains the starting address for use when USB0 reads from L2C via Channel3. 1109 * Writing of this register sets the base address. 1110 */ 1111union cvmx_usbnx_dma0_outb_chn3 { 1112 uint64_t u64; 1113 struct cvmx_usbnx_dma0_outb_chn3_s { 1114#ifdef __BIG_ENDIAN_BITFIELD 1115 uint64_t reserved_36_63 : 28; 1116 uint64_t addr : 36; /**< Base address for DMA Read from L2C. */ 1117#else 1118 uint64_t addr : 36; 1119 uint64_t reserved_36_63 : 28; 1120#endif 1121 } s; 1122 struct cvmx_usbnx_dma0_outb_chn3_s cn30xx; 1123 struct cvmx_usbnx_dma0_outb_chn3_s cn31xx; 1124 struct cvmx_usbnx_dma0_outb_chn3_s cn50xx; 1125 struct cvmx_usbnx_dma0_outb_chn3_s cn52xx; 1126 struct cvmx_usbnx_dma0_outb_chn3_s cn52xxp1; 1127 struct cvmx_usbnx_dma0_outb_chn3_s cn56xx; 1128 struct cvmx_usbnx_dma0_outb_chn3_s cn56xxp1; 1129}; 1130typedef union cvmx_usbnx_dma0_outb_chn3 cvmx_usbnx_dma0_outb_chn3_t; 1131 1132/** 1133 * cvmx_usbn#_dma0_outb_chn4 1134 * 1135 * USBN_DMA0_OUTB_CHN4 = USBN's Outbound DMA for USB0 Channel4 1136 * 1137 * Contains the starting address for use when USB0 reads from L2C via Channel4. 1138 * Writing of this register sets the base address. 1139 */ 1140union cvmx_usbnx_dma0_outb_chn4 { 1141 uint64_t u64; 1142 struct cvmx_usbnx_dma0_outb_chn4_s { 1143#ifdef __BIG_ENDIAN_BITFIELD 1144 uint64_t reserved_36_63 : 28; 1145 uint64_t addr : 36; /**< Base address for DMA Read from L2C. */ 1146#else 1147 uint64_t addr : 36; 1148 uint64_t reserved_36_63 : 28; 1149#endif 1150 } s; 1151 struct cvmx_usbnx_dma0_outb_chn4_s cn30xx; 1152 struct cvmx_usbnx_dma0_outb_chn4_s cn31xx; 1153 struct cvmx_usbnx_dma0_outb_chn4_s cn50xx; 1154 struct cvmx_usbnx_dma0_outb_chn4_s cn52xx; 1155 struct cvmx_usbnx_dma0_outb_chn4_s cn52xxp1; 1156 struct cvmx_usbnx_dma0_outb_chn4_s cn56xx; 1157 struct cvmx_usbnx_dma0_outb_chn4_s cn56xxp1; 1158}; 1159typedef union cvmx_usbnx_dma0_outb_chn4 cvmx_usbnx_dma0_outb_chn4_t; 1160 1161/** 1162 * cvmx_usbn#_dma0_outb_chn5 1163 * 1164 * USBN_DMA0_OUTB_CHN5 = USBN's Outbound DMA for USB0 Channel5 1165 * 1166 * Contains the starting address for use when USB0 reads from L2C via Channel5. 1167 * Writing of this register sets the base address. 1168 */ 1169union cvmx_usbnx_dma0_outb_chn5 { 1170 uint64_t u64; 1171 struct cvmx_usbnx_dma0_outb_chn5_s { 1172#ifdef __BIG_ENDIAN_BITFIELD 1173 uint64_t reserved_36_63 : 28; 1174 uint64_t addr : 36; /**< Base address for DMA Read from L2C. */ 1175#else 1176 uint64_t addr : 36; 1177 uint64_t reserved_36_63 : 28; 1178#endif 1179 } s; 1180 struct cvmx_usbnx_dma0_outb_chn5_s cn30xx; 1181 struct cvmx_usbnx_dma0_outb_chn5_s cn31xx; 1182 struct cvmx_usbnx_dma0_outb_chn5_s cn50xx; 1183 struct cvmx_usbnx_dma0_outb_chn5_s cn52xx; 1184 struct cvmx_usbnx_dma0_outb_chn5_s cn52xxp1; 1185 struct cvmx_usbnx_dma0_outb_chn5_s cn56xx; 1186 struct cvmx_usbnx_dma0_outb_chn5_s cn56xxp1; 1187}; 1188typedef union cvmx_usbnx_dma0_outb_chn5 cvmx_usbnx_dma0_outb_chn5_t; 1189 1190/** 1191 * cvmx_usbn#_dma0_outb_chn6 1192 * 1193 * USBN_DMA0_OUTB_CHN6 = USBN's Outbound DMA for USB0 Channel6 1194 * 1195 * Contains the starting address for use when USB0 reads from L2C via Channel6. 1196 * Writing of this register sets the base address. 1197 */ 1198union cvmx_usbnx_dma0_outb_chn6 { 1199 uint64_t u64; 1200 struct cvmx_usbnx_dma0_outb_chn6_s { 1201#ifdef __BIG_ENDIAN_BITFIELD 1202 uint64_t reserved_36_63 : 28; 1203 uint64_t addr : 36; /**< Base address for DMA Read from L2C. */ 1204#else 1205 uint64_t addr : 36; 1206 uint64_t reserved_36_63 : 28; 1207#endif 1208 } s; 1209 struct cvmx_usbnx_dma0_outb_chn6_s cn30xx; 1210 struct cvmx_usbnx_dma0_outb_chn6_s cn31xx; 1211 struct cvmx_usbnx_dma0_outb_chn6_s cn50xx; 1212 struct cvmx_usbnx_dma0_outb_chn6_s cn52xx; 1213 struct cvmx_usbnx_dma0_outb_chn6_s cn52xxp1; 1214 struct cvmx_usbnx_dma0_outb_chn6_s cn56xx; 1215 struct cvmx_usbnx_dma0_outb_chn6_s cn56xxp1; 1216}; 1217typedef union cvmx_usbnx_dma0_outb_chn6 cvmx_usbnx_dma0_outb_chn6_t; 1218 1219/** 1220 * cvmx_usbn#_dma0_outb_chn7 1221 * 1222 * USBN_DMA0_OUTB_CHN7 = USBN's Outbound DMA for USB0 Channel7 1223 * 1224 * Contains the starting address for use when USB0 reads from L2C via Channel7. 1225 * Writing of this register sets the base address. 1226 */ 1227union cvmx_usbnx_dma0_outb_chn7 { 1228 uint64_t u64; 1229 struct cvmx_usbnx_dma0_outb_chn7_s { 1230#ifdef __BIG_ENDIAN_BITFIELD 1231 uint64_t reserved_36_63 : 28; 1232 uint64_t addr : 36; /**< Base address for DMA Read from L2C. */ 1233#else 1234 uint64_t addr : 36; 1235 uint64_t reserved_36_63 : 28; 1236#endif 1237 } s; 1238 struct cvmx_usbnx_dma0_outb_chn7_s cn30xx; 1239 struct cvmx_usbnx_dma0_outb_chn7_s cn31xx; 1240 struct cvmx_usbnx_dma0_outb_chn7_s cn50xx; 1241 struct cvmx_usbnx_dma0_outb_chn7_s cn52xx; 1242 struct cvmx_usbnx_dma0_outb_chn7_s cn52xxp1; 1243 struct cvmx_usbnx_dma0_outb_chn7_s cn56xx; 1244 struct cvmx_usbnx_dma0_outb_chn7_s cn56xxp1; 1245}; 1246typedef union cvmx_usbnx_dma0_outb_chn7 cvmx_usbnx_dma0_outb_chn7_t; 1247 1248/** 1249 * cvmx_usbn#_dma_test 1250 * 1251 * USBN_DMA_TEST = USBN's DMA TestRegister 1252 * 1253 * This register can cause the external DMA engine to the USB-Core to make transfers from/to L2C/USB-FIFOs 1254 */ 1255union cvmx_usbnx_dma_test { 1256 uint64_t u64; 1257 struct cvmx_usbnx_dma_test_s { 1258#ifdef __BIG_ENDIAN_BITFIELD 1259 uint64_t reserved_40_63 : 24; 1260 uint64_t done : 1; /**< This field is set when a DMA completes. Writing a 1261 '1' to this field clears this bit. */ 1262 uint64_t req : 1; /**< DMA Request. Writing a 1 to this register 1263 will cause a DMA request as specified in the other 1264 fields of this register to take place. This field 1265 will always read as '0'. */ 1266 uint64_t f_addr : 18; /**< The address to read from in the Data-Fifo. */ 1267 uint64_t count : 11; /**< DMA Request Count. */ 1268 uint64_t channel : 5; /**< DMA Channel/Enpoint. */ 1269 uint64_t burst : 4; /**< DMA Burst Size. */ 1270#else 1271 uint64_t burst : 4; 1272 uint64_t channel : 5; 1273 uint64_t count : 11; 1274 uint64_t f_addr : 18; 1275 uint64_t req : 1; 1276 uint64_t done : 1; 1277 uint64_t reserved_40_63 : 24; 1278#endif 1279 } s; 1280 struct cvmx_usbnx_dma_test_s cn30xx; 1281 struct cvmx_usbnx_dma_test_s cn31xx; 1282 struct cvmx_usbnx_dma_test_s cn50xx; 1283 struct cvmx_usbnx_dma_test_s cn52xx; 1284 struct cvmx_usbnx_dma_test_s cn52xxp1; 1285 struct cvmx_usbnx_dma_test_s cn56xx; 1286 struct cvmx_usbnx_dma_test_s cn56xxp1; 1287}; 1288typedef union cvmx_usbnx_dma_test cvmx_usbnx_dma_test_t; 1289 1290/** 1291 * cvmx_usbn#_int_enb 1292 * 1293 * USBN_INT_ENB = USBN's Interrupt Enable 1294 * 1295 * The USBN's interrupt enable register. 1296 */ 1297union cvmx_usbnx_int_enb { 1298 uint64_t u64; 1299 struct cvmx_usbnx_int_enb_s { 1300#ifdef __BIG_ENDIAN_BITFIELD 1301 uint64_t reserved_38_63 : 26; 1302 uint64_t nd4o_dpf : 1; /**< When set (1) and bit 37 of the USBN_INT_SUM 1303 register is asserted the USBN will assert an 1304 interrupt. */ 1305 uint64_t nd4o_dpe : 1; /**< When set (1) and bit 36 of the USBN_INT_SUM 1306 register is asserted the USBN will assert an 1307 interrupt. */ 1308 uint64_t nd4o_rpf : 1; /**< When set (1) and bit 35 of the USBN_INT_SUM 1309 register is asserted the USBN will assert an 1310 interrupt. */ 1311 uint64_t nd4o_rpe : 1; /**< When set (1) and bit 34 of the USBN_INT_SUM 1312 register is asserted the USBN will assert an 1313 interrupt. */ 1314 uint64_t ltl_f_pf : 1; /**< When set (1) and bit 33 of the USBN_INT_SUM 1315 register is asserted the USBN will assert an 1316 interrupt. */ 1317 uint64_t ltl_f_pe : 1; /**< When set (1) and bit 32 of the USBN_INT_SUM 1318 register is asserted the USBN will assert an 1319 interrupt. */ 1320 uint64_t u2n_c_pe : 1; /**< When set (1) and bit 31 of the USBN_INT_SUM 1321 register is asserted the USBN will assert an 1322 interrupt. */ 1323 uint64_t u2n_c_pf : 1; /**< When set (1) and bit 30 of the USBN_INT_SUM 1324 register is asserted the USBN will assert an 1325 interrupt. */ 1326 uint64_t u2n_d_pf : 1; /**< When set (1) and bit 29 of the USBN_INT_SUM 1327 register is asserted the USBN will assert an 1328 interrupt. */ 1329 uint64_t u2n_d_pe : 1; /**< When set (1) and bit 28 of the USBN_INT_SUM 1330 register is asserted the USBN will assert an 1331 interrupt. */ 1332 uint64_t n2u_pe : 1; /**< When set (1) and bit 27 of the USBN_INT_SUM 1333 register is asserted the USBN will assert an 1334 interrupt. */ 1335 uint64_t n2u_pf : 1; /**< When set (1) and bit 26 of the USBN_INT_SUM 1336 register is asserted the USBN will assert an 1337 interrupt. */ 1338 uint64_t uod_pf : 1; /**< When set (1) and bit 25 of the USBN_INT_SUM 1339 register is asserted the USBN will assert an 1340 interrupt. */ 1341 uint64_t uod_pe : 1; /**< When set (1) and bit 24 of the USBN_INT_SUM 1342 register is asserted the USBN will assert an 1343 interrupt. */ 1344 uint64_t rq_q3_e : 1; /**< When set (1) and bit 23 of the USBN_INT_SUM 1345 register is asserted the USBN will assert an 1346 interrupt. */ 1347 uint64_t rq_q3_f : 1; /**< When set (1) and bit 22 of the USBN_INT_SUM 1348 register is asserted the USBN will assert an 1349 interrupt. */ 1350 uint64_t rq_q2_e : 1; /**< When set (1) and bit 21 of the USBN_INT_SUM 1351 register is asserted the USBN will assert an 1352 interrupt. */ 1353 uint64_t rq_q2_f : 1; /**< When set (1) and bit 20 of the USBN_INT_SUM 1354 register is asserted the USBN will assert an 1355 interrupt. */ 1356 uint64_t rg_fi_f : 1; /**< When set (1) and bit 19 of the USBN_INT_SUM 1357 register is asserted the USBN will assert an 1358 interrupt. */ 1359 uint64_t rg_fi_e : 1; /**< When set (1) and bit 18 of the USBN_INT_SUM 1360 register is asserted the USBN will assert an 1361 interrupt. */ 1362 uint64_t l2_fi_f : 1; /**< When set (1) and bit 17 of the USBN_INT_SUM 1363 register is asserted the USBN will assert an 1364 interrupt. */ 1365 uint64_t l2_fi_e : 1; /**< When set (1) and bit 16 of the USBN_INT_SUM 1366 register is asserted the USBN will assert an 1367 interrupt. */ 1368 uint64_t l2c_a_f : 1; /**< When set (1) and bit 15 of the USBN_INT_SUM 1369 register is asserted the USBN will assert an 1370 interrupt. */ 1371 uint64_t l2c_s_e : 1; /**< When set (1) and bit 14 of the USBN_INT_SUM 1372 register is asserted the USBN will assert an 1373 interrupt. */ 1374 uint64_t dcred_f : 1; /**< When set (1) and bit 13 of the USBN_INT_SUM 1375 register is asserted the USBN will assert an 1376 interrupt. */ 1377 uint64_t dcred_e : 1; /**< When set (1) and bit 12 of the USBN_INT_SUM 1378 register is asserted the USBN will assert an 1379 interrupt. */ 1380 uint64_t lt_pu_f : 1; /**< When set (1) and bit 11 of the USBN_INT_SUM 1381 register is asserted the USBN will assert an 1382 interrupt. */ 1383 uint64_t lt_po_e : 1; /**< When set (1) and bit 10 of the USBN_INT_SUM 1384 register is asserted the USBN will assert an 1385 interrupt. */ 1386 uint64_t nt_pu_f : 1; /**< When set (1) and bit 9 of the USBN_INT_SUM 1387 register is asserted the USBN will assert an 1388 interrupt. */ 1389 uint64_t nt_po_e : 1; /**< When set (1) and bit 8 of the USBN_INT_SUM 1390 register is asserted the USBN will assert an 1391 interrupt. */ 1392 uint64_t pt_pu_f : 1; /**< When set (1) and bit 7 of the USBN_INT_SUM 1393 register is asserted the USBN will assert an 1394 interrupt. */ 1395 uint64_t pt_po_e : 1; /**< When set (1) and bit 6 of the USBN_INT_SUM 1396 register is asserted the USBN will assert an 1397 interrupt. */ 1398 uint64_t lr_pu_f : 1; /**< When set (1) and bit 5 of the USBN_INT_SUM 1399 register is asserted the USBN will assert an 1400 interrupt. */ 1401 uint64_t lr_po_e : 1; /**< When set (1) and bit 4 of the USBN_INT_SUM 1402 register is asserted the USBN will assert an 1403 interrupt. */ 1404 uint64_t nr_pu_f : 1; /**< When set (1) and bit 3 of the USBN_INT_SUM 1405 register is asserted the USBN will assert an 1406 interrupt. */ 1407 uint64_t nr_po_e : 1; /**< When set (1) and bit 2 of the USBN_INT_SUM 1408 register is asserted the USBN will assert an 1409 interrupt. */ 1410 uint64_t pr_pu_f : 1; /**< When set (1) and bit 1 of the USBN_INT_SUM 1411 register is asserted the USBN will assert an 1412 interrupt. */ 1413 uint64_t pr_po_e : 1; /**< When set (1) and bit 0 of the USBN_INT_SUM 1414 register is asserted the USBN will assert an 1415 interrupt. */ 1416#else 1417 uint64_t pr_po_e : 1; 1418 uint64_t pr_pu_f : 1; 1419 uint64_t nr_po_e : 1; 1420 uint64_t nr_pu_f : 1; 1421 uint64_t lr_po_e : 1; 1422 uint64_t lr_pu_f : 1; 1423 uint64_t pt_po_e : 1; 1424 uint64_t pt_pu_f : 1; 1425 uint64_t nt_po_e : 1; 1426 uint64_t nt_pu_f : 1; 1427 uint64_t lt_po_e : 1; 1428 uint64_t lt_pu_f : 1; 1429 uint64_t dcred_e : 1; 1430 uint64_t dcred_f : 1; 1431 uint64_t l2c_s_e : 1; 1432 uint64_t l2c_a_f : 1; 1433 uint64_t l2_fi_e : 1; 1434 uint64_t l2_fi_f : 1; 1435 uint64_t rg_fi_e : 1; 1436 uint64_t rg_fi_f : 1; 1437 uint64_t rq_q2_f : 1; 1438 uint64_t rq_q2_e : 1; 1439 uint64_t rq_q3_f : 1; 1440 uint64_t rq_q3_e : 1; 1441 uint64_t uod_pe : 1; 1442 uint64_t uod_pf : 1; 1443 uint64_t n2u_pf : 1; 1444 uint64_t n2u_pe : 1; 1445 uint64_t u2n_d_pe : 1; 1446 uint64_t u2n_d_pf : 1; 1447 uint64_t u2n_c_pf : 1; 1448 uint64_t u2n_c_pe : 1; 1449 uint64_t ltl_f_pe : 1; 1450 uint64_t ltl_f_pf : 1; 1451 uint64_t nd4o_rpe : 1; 1452 uint64_t nd4o_rpf : 1; 1453 uint64_t nd4o_dpe : 1; 1454 uint64_t nd4o_dpf : 1; 1455 uint64_t reserved_38_63 : 26; 1456#endif 1457 } s; 1458 struct cvmx_usbnx_int_enb_s cn30xx; 1459 struct cvmx_usbnx_int_enb_s cn31xx; 1460 struct cvmx_usbnx_int_enb_cn50xx { 1461#ifdef __BIG_ENDIAN_BITFIELD 1462 uint64_t reserved_38_63 : 26; 1463 uint64_t nd4o_dpf : 1; /**< When set (1) and bit 37 of the USBN_INT_SUM 1464 register is asserted the USBN will assert an 1465 interrupt. */ 1466 uint64_t nd4o_dpe : 1; /**< When set (1) and bit 36 of the USBN_INT_SUM 1467 register is asserted the USBN will assert an 1468 interrupt. */ 1469 uint64_t nd4o_rpf : 1; /**< When set (1) and bit 35 of the USBN_INT_SUM 1470 register is asserted the USBN will assert an 1471 interrupt. */ 1472 uint64_t nd4o_rpe : 1; /**< When set (1) and bit 34 of the USBN_INT_SUM 1473 register is asserted the USBN will assert an 1474 interrupt. */ 1475 uint64_t ltl_f_pf : 1; /**< When set (1) and bit 33 of the USBN_INT_SUM 1476 register is asserted the USBN will assert an 1477 interrupt. */ 1478 uint64_t ltl_f_pe : 1; /**< When set (1) and bit 32 of the USBN_INT_SUM 1479 register is asserted the USBN will assert an 1480 interrupt. */ 1481 uint64_t reserved_26_31 : 6; 1482 uint64_t uod_pf : 1; /**< When set (1) and bit 25 of the USBN_INT_SUM 1483 register is asserted the USBN will assert an 1484 interrupt. */ 1485 uint64_t uod_pe : 1; /**< When set (1) and bit 24 of the USBN_INT_SUM 1486 register is asserted the USBN will assert an 1487 interrupt. */ 1488 uint64_t rq_q3_e : 1; /**< When set (1) and bit 23 of the USBN_INT_SUM 1489 register is asserted the USBN will assert an 1490 interrupt. */ 1491 uint64_t rq_q3_f : 1; /**< When set (1) and bit 22 of the USBN_INT_SUM 1492 register is asserted the USBN will assert an 1493 interrupt. */ 1494 uint64_t rq_q2_e : 1; /**< When set (1) and bit 21 of the USBN_INT_SUM 1495 register is asserted the USBN will assert an 1496 interrupt. */ 1497 uint64_t rq_q2_f : 1; /**< When set (1) and bit 20 of the USBN_INT_SUM 1498 register is asserted the USBN will assert an 1499 interrupt. */ 1500 uint64_t rg_fi_f : 1; /**< When set (1) and bit 19 of the USBN_INT_SUM 1501 register is asserted the USBN will assert an 1502 interrupt. */ 1503 uint64_t rg_fi_e : 1; /**< When set (1) and bit 18 of the USBN_INT_SUM 1504 register is asserted the USBN will assert an 1505 interrupt. */ 1506 uint64_t l2_fi_f : 1; /**< When set (1) and bit 17 of the USBN_INT_SUM 1507 register is asserted the USBN will assert an 1508 interrupt. */ 1509 uint64_t l2_fi_e : 1; /**< When set (1) and bit 16 of the USBN_INT_SUM 1510 register is asserted the USBN will assert an 1511 interrupt. */ 1512 uint64_t l2c_a_f : 1; /**< When set (1) and bit 15 of the USBN_INT_SUM 1513 register is asserted the USBN will assert an 1514 interrupt. */ 1515 uint64_t l2c_s_e : 1; /**< When set (1) and bit 14 of the USBN_INT_SUM 1516 register is asserted the USBN will assert an 1517 interrupt. */ 1518 uint64_t dcred_f : 1; /**< When set (1) and bit 13 of the USBN_INT_SUM 1519 register is asserted the USBN will assert an 1520 interrupt. */ 1521 uint64_t dcred_e : 1; /**< When set (1) and bit 12 of the USBN_INT_SUM 1522 register is asserted the USBN will assert an 1523 interrupt. */ 1524 uint64_t lt_pu_f : 1; /**< When set (1) and bit 11 of the USBN_INT_SUM 1525 register is asserted the USBN will assert an 1526 interrupt. */ 1527 uint64_t lt_po_e : 1; /**< When set (1) and bit 10 of the USBN_INT_SUM 1528 register is asserted the USBN will assert an 1529 interrupt. */ 1530 uint64_t nt_pu_f : 1; /**< When set (1) and bit 9 of the USBN_INT_SUM 1531 register is asserted the USBN will assert an 1532 interrupt. */ 1533 uint64_t nt_po_e : 1; /**< When set (1) and bit 8 of the USBN_INT_SUM 1534 register is asserted the USBN will assert an 1535 interrupt. */ 1536 uint64_t pt_pu_f : 1; /**< When set (1) and bit 7 of the USBN_INT_SUM 1537 register is asserted the USBN will assert an 1538 interrupt. */ 1539 uint64_t pt_po_e : 1; /**< When set (1) and bit 6 of the USBN_INT_SUM 1540 register is asserted the USBN will assert an 1541 interrupt. */ 1542 uint64_t lr_pu_f : 1; /**< When set (1) and bit 5 of the USBN_INT_SUM 1543 register is asserted the USBN will assert an 1544 interrupt. */ 1545 uint64_t lr_po_e : 1; /**< When set (1) and bit 4 of the USBN_INT_SUM 1546 register is asserted the USBN will assert an 1547 interrupt. */ 1548 uint64_t nr_pu_f : 1; /**< When set (1) and bit 3 of the USBN_INT_SUM 1549 register is asserted the USBN will assert an 1550 interrupt. */ 1551 uint64_t nr_po_e : 1; /**< When set (1) and bit 2 of the USBN_INT_SUM 1552 register is asserted the USBN will assert an 1553 interrupt. */ 1554 uint64_t pr_pu_f : 1; /**< When set (1) and bit 1 of the USBN_INT_SUM 1555 register is asserted the USBN will assert an 1556 interrupt. */ 1557 uint64_t pr_po_e : 1; /**< When set (1) and bit 0 of the USBN_INT_SUM 1558 register is asserted the USBN will assert an 1559 interrupt. */ 1560#else 1561 uint64_t pr_po_e : 1; 1562 uint64_t pr_pu_f : 1; 1563 uint64_t nr_po_e : 1; 1564 uint64_t nr_pu_f : 1; 1565 uint64_t lr_po_e : 1; 1566 uint64_t lr_pu_f : 1; 1567 uint64_t pt_po_e : 1; 1568 uint64_t pt_pu_f : 1; 1569 uint64_t nt_po_e : 1; 1570 uint64_t nt_pu_f : 1; 1571 uint64_t lt_po_e : 1; 1572 uint64_t lt_pu_f : 1; 1573 uint64_t dcred_e : 1; 1574 uint64_t dcred_f : 1; 1575 uint64_t l2c_s_e : 1; 1576 uint64_t l2c_a_f : 1; 1577 uint64_t l2_fi_e : 1; 1578 uint64_t l2_fi_f : 1; 1579 uint64_t rg_fi_e : 1; 1580 uint64_t rg_fi_f : 1; 1581 uint64_t rq_q2_f : 1; 1582 uint64_t rq_q2_e : 1; 1583 uint64_t rq_q3_f : 1; 1584 uint64_t rq_q3_e : 1; 1585 uint64_t uod_pe : 1; 1586 uint64_t uod_pf : 1; 1587 uint64_t reserved_26_31 : 6; 1588 uint64_t ltl_f_pe : 1; 1589 uint64_t ltl_f_pf : 1; 1590 uint64_t nd4o_rpe : 1; 1591 uint64_t nd4o_rpf : 1; 1592 uint64_t nd4o_dpe : 1; 1593 uint64_t nd4o_dpf : 1; 1594 uint64_t reserved_38_63 : 26; 1595#endif 1596 } cn50xx; 1597 struct cvmx_usbnx_int_enb_cn50xx cn52xx; 1598 struct cvmx_usbnx_int_enb_cn50xx cn52xxp1; 1599 struct cvmx_usbnx_int_enb_cn50xx cn56xx; 1600 struct cvmx_usbnx_int_enb_cn50xx cn56xxp1; 1601}; 1602typedef union cvmx_usbnx_int_enb cvmx_usbnx_int_enb_t; 1603 1604/** 1605 * cvmx_usbn#_int_sum 1606 * 1607 * USBN_INT_SUM = USBN's Interrupt Summary Register 1608 * 1609 * Contains the diffrent interrupt summary bits of the USBN. 1610 */ 1611union cvmx_usbnx_int_sum { 1612 uint64_t u64; 1613 struct cvmx_usbnx_int_sum_s { 1614#ifdef __BIG_ENDIAN_BITFIELD 1615 uint64_t reserved_38_63 : 26; 1616 uint64_t nd4o_dpf : 1; /**< NCB DMA Out Data Fifo Push Full. */ 1617 uint64_t nd4o_dpe : 1; /**< NCB DMA Out Data Fifo Pop Empty. */ 1618 uint64_t nd4o_rpf : 1; /**< NCB DMA Out Request Fifo Push Full. */ 1619 uint64_t nd4o_rpe : 1; /**< NCB DMA Out Request Fifo Pop Empty. */ 1620 uint64_t ltl_f_pf : 1; /**< L2C Transfer Length Fifo Push Full. */ 1621 uint64_t ltl_f_pe : 1; /**< L2C Transfer Length Fifo Pop Empty. */ 1622 uint64_t u2n_c_pe : 1; /**< U2N Control Fifo Pop Empty. */ 1623 uint64_t u2n_c_pf : 1; /**< U2N Control Fifo Push Full. */ 1624 uint64_t u2n_d_pf : 1; /**< U2N Data Fifo Push Full. */ 1625 uint64_t u2n_d_pe : 1; /**< U2N Data Fifo Pop Empty. */ 1626 uint64_t n2u_pe : 1; /**< N2U Fifo Pop Empty. */ 1627 uint64_t n2u_pf : 1; /**< N2U Fifo Push Full. */ 1628 uint64_t uod_pf : 1; /**< UOD Fifo Push Full. */ 1629 uint64_t uod_pe : 1; /**< UOD Fifo Pop Empty. */ 1630 uint64_t rq_q3_e : 1; /**< Request Queue-3 Fifo Pushed When Full. */ 1631 uint64_t rq_q3_f : 1; /**< Request Queue-3 Fifo Pushed When Full. */ 1632 uint64_t rq_q2_e : 1; /**< Request Queue-2 Fifo Pushed When Full. */ 1633 uint64_t rq_q2_f : 1; /**< Request Queue-2 Fifo Pushed When Full. */ 1634 uint64_t rg_fi_f : 1; /**< Register Request Fifo Pushed When Full. */ 1635 uint64_t rg_fi_e : 1; /**< Register Request Fifo Pushed When Full. */ 1636 uint64_t lt_fi_f : 1; /**< L2C Request Fifo Pushed When Full. */ 1637 uint64_t lt_fi_e : 1; /**< L2C Request Fifo Pushed When Full. */ 1638 uint64_t l2c_a_f : 1; /**< L2C Credit Count Added When Full. */ 1639 uint64_t l2c_s_e : 1; /**< L2C Credit Count Subtracted When Empty. */ 1640 uint64_t dcred_f : 1; /**< Data CreditFifo Pushed When Full. */ 1641 uint64_t dcred_e : 1; /**< Data Credit Fifo Pushed When Full. */ 1642 uint64_t lt_pu_f : 1; /**< L2C Trasaction Fifo Pushed When Full. */ 1643 uint64_t lt_po_e : 1; /**< L2C Trasaction Fifo Popped When Full. */ 1644 uint64_t nt_pu_f : 1; /**< NPI Trasaction Fifo Pushed When Full. */ 1645 uint64_t nt_po_e : 1; /**< NPI Trasaction Fifo Popped When Full. */ 1646 uint64_t pt_pu_f : 1; /**< PP Trasaction Fifo Pushed When Full. */ 1647 uint64_t pt_po_e : 1; /**< PP Trasaction Fifo Popped When Full. */ 1648 uint64_t lr_pu_f : 1; /**< L2C Request Fifo Pushed When Full. */ 1649 uint64_t lr_po_e : 1; /**< L2C Request Fifo Popped When Empty. */ 1650 uint64_t nr_pu_f : 1; /**< NPI Request Fifo Pushed When Full. */ 1651 uint64_t nr_po_e : 1; /**< NPI Request Fifo Popped When Empty. */ 1652 uint64_t pr_pu_f : 1; /**< PP Request Fifo Pushed When Full. */ 1653 uint64_t pr_po_e : 1; /**< PP Request Fifo Popped When Empty. */ 1654#else 1655 uint64_t pr_po_e : 1; 1656 uint64_t pr_pu_f : 1; 1657 uint64_t nr_po_e : 1; 1658 uint64_t nr_pu_f : 1; 1659 uint64_t lr_po_e : 1; 1660 uint64_t lr_pu_f : 1; 1661 uint64_t pt_po_e : 1; 1662 uint64_t pt_pu_f : 1; 1663 uint64_t nt_po_e : 1; 1664 uint64_t nt_pu_f : 1; 1665 uint64_t lt_po_e : 1; 1666 uint64_t lt_pu_f : 1; 1667 uint64_t dcred_e : 1; 1668 uint64_t dcred_f : 1; 1669 uint64_t l2c_s_e : 1; 1670 uint64_t l2c_a_f : 1; 1671 uint64_t lt_fi_e : 1; 1672 uint64_t lt_fi_f : 1; 1673 uint64_t rg_fi_e : 1; 1674 uint64_t rg_fi_f : 1; 1675 uint64_t rq_q2_f : 1; 1676 uint64_t rq_q2_e : 1; 1677 uint64_t rq_q3_f : 1; 1678 uint64_t rq_q3_e : 1; 1679 uint64_t uod_pe : 1; 1680 uint64_t uod_pf : 1; 1681 uint64_t n2u_pf : 1; 1682 uint64_t n2u_pe : 1; 1683 uint64_t u2n_d_pe : 1; 1684 uint64_t u2n_d_pf : 1; 1685 uint64_t u2n_c_pf : 1; 1686 uint64_t u2n_c_pe : 1; 1687 uint64_t ltl_f_pe : 1; 1688 uint64_t ltl_f_pf : 1; 1689 uint64_t nd4o_rpe : 1; 1690 uint64_t nd4o_rpf : 1; 1691 uint64_t nd4o_dpe : 1; 1692 uint64_t nd4o_dpf : 1; 1693 uint64_t reserved_38_63 : 26; 1694#endif 1695 } s; 1696 struct cvmx_usbnx_int_sum_s cn30xx; 1697 struct cvmx_usbnx_int_sum_s cn31xx; 1698 struct cvmx_usbnx_int_sum_cn50xx { 1699#ifdef __BIG_ENDIAN_BITFIELD 1700 uint64_t reserved_38_63 : 26; 1701 uint64_t nd4o_dpf : 1; /**< NCB DMA Out Data Fifo Push Full. */ 1702 uint64_t nd4o_dpe : 1; /**< NCB DMA Out Data Fifo Pop Empty. */ 1703 uint64_t nd4o_rpf : 1; /**< NCB DMA Out Request Fifo Push Full. */ 1704 uint64_t nd4o_rpe : 1; /**< NCB DMA Out Request Fifo Pop Empty. */ 1705 uint64_t ltl_f_pf : 1; /**< L2C Transfer Length Fifo Push Full. */ 1706 uint64_t ltl_f_pe : 1; /**< L2C Transfer Length Fifo Pop Empty. */ 1707 uint64_t reserved_26_31 : 6; 1708 uint64_t uod_pf : 1; /**< UOD Fifo Push Full. */ 1709 uint64_t uod_pe : 1; /**< UOD Fifo Pop Empty. */ 1710 uint64_t rq_q3_e : 1; /**< Request Queue-3 Fifo Pushed When Full. */ 1711 uint64_t rq_q3_f : 1; /**< Request Queue-3 Fifo Pushed When Full. */ 1712 uint64_t rq_q2_e : 1; /**< Request Queue-2 Fifo Pushed When Full. */ 1713 uint64_t rq_q2_f : 1; /**< Request Queue-2 Fifo Pushed When Full. */ 1714 uint64_t rg_fi_f : 1; /**< Register Request Fifo Pushed When Full. */ 1715 uint64_t rg_fi_e : 1; /**< Register Request Fifo Pushed When Full. */ 1716 uint64_t lt_fi_f : 1; /**< L2C Request Fifo Pushed When Full. */ 1717 uint64_t lt_fi_e : 1; /**< L2C Request Fifo Pushed When Full. */ 1718 uint64_t l2c_a_f : 1; /**< L2C Credit Count Added When Full. */ 1719 uint64_t l2c_s_e : 1; /**< L2C Credit Count Subtracted When Empty. */ 1720 uint64_t dcred_f : 1; /**< Data CreditFifo Pushed When Full. */ 1721 uint64_t dcred_e : 1; /**< Data Credit Fifo Pushed When Full. */ 1722 uint64_t lt_pu_f : 1; /**< L2C Trasaction Fifo Pushed When Full. */ 1723 uint64_t lt_po_e : 1; /**< L2C Trasaction Fifo Popped When Full. */ 1724 uint64_t nt_pu_f : 1; /**< NPI Trasaction Fifo Pushed When Full. */ 1725 uint64_t nt_po_e : 1; /**< NPI Trasaction Fifo Popped When Full. */ 1726 uint64_t pt_pu_f : 1; /**< PP Trasaction Fifo Pushed When Full. */ 1727 uint64_t pt_po_e : 1; /**< PP Trasaction Fifo Popped When Full. */ 1728 uint64_t lr_pu_f : 1; /**< L2C Request Fifo Pushed When Full. */ 1729 uint64_t lr_po_e : 1; /**< L2C Request Fifo Popped When Empty. */ 1730 uint64_t nr_pu_f : 1; /**< NPI Request Fifo Pushed When Full. */ 1731 uint64_t nr_po_e : 1; /**< NPI Request Fifo Popped When Empty. */ 1732 uint64_t pr_pu_f : 1; /**< PP Request Fifo Pushed When Full. */ 1733 uint64_t pr_po_e : 1; /**< PP Request Fifo Popped When Empty. */ 1734#else 1735 uint64_t pr_po_e : 1; 1736 uint64_t pr_pu_f : 1; 1737 uint64_t nr_po_e : 1; 1738 uint64_t nr_pu_f : 1; 1739 uint64_t lr_po_e : 1; 1740 uint64_t lr_pu_f : 1; 1741 uint64_t pt_po_e : 1; 1742 uint64_t pt_pu_f : 1; 1743 uint64_t nt_po_e : 1; 1744 uint64_t nt_pu_f : 1; 1745 uint64_t lt_po_e : 1; 1746 uint64_t lt_pu_f : 1; 1747 uint64_t dcred_e : 1; 1748 uint64_t dcred_f : 1; 1749 uint64_t l2c_s_e : 1; 1750 uint64_t l2c_a_f : 1; 1751 uint64_t lt_fi_e : 1; 1752 uint64_t lt_fi_f : 1; 1753 uint64_t rg_fi_e : 1; 1754 uint64_t rg_fi_f : 1; 1755 uint64_t rq_q2_f : 1; 1756 uint64_t rq_q2_e : 1; 1757 uint64_t rq_q3_f : 1; 1758 uint64_t rq_q3_e : 1; 1759 uint64_t uod_pe : 1; 1760 uint64_t uod_pf : 1; 1761 uint64_t reserved_26_31 : 6; 1762 uint64_t ltl_f_pe : 1; 1763 uint64_t ltl_f_pf : 1; 1764 uint64_t nd4o_rpe : 1; 1765 uint64_t nd4o_rpf : 1; 1766 uint64_t nd4o_dpe : 1; 1767 uint64_t nd4o_dpf : 1; 1768 uint64_t reserved_38_63 : 26; 1769#endif 1770 } cn50xx; 1771 struct cvmx_usbnx_int_sum_cn50xx cn52xx; 1772 struct cvmx_usbnx_int_sum_cn50xx cn52xxp1; 1773 struct cvmx_usbnx_int_sum_cn50xx cn56xx; 1774 struct cvmx_usbnx_int_sum_cn50xx cn56xxp1; 1775}; 1776typedef union cvmx_usbnx_int_sum cvmx_usbnx_int_sum_t; 1777 1778/** 1779 * cvmx_usbn#_usbp_ctl_status 1780 * 1781 * USBN_USBP_CTL_STATUS = USBP Control And Status Register 1782 * 1783 * Contains general control and status information for the USBN block. 1784 */ 1785union cvmx_usbnx_usbp_ctl_status { 1786 uint64_t u64; 1787 struct cvmx_usbnx_usbp_ctl_status_s { 1788#ifdef __BIG_ENDIAN_BITFIELD 1789 uint64_t txrisetune : 1; /**< HS Transmitter Rise/Fall Time Adjustment */ 1790 uint64_t txvreftune : 4; /**< HS DC Voltage Level Adjustment */ 1791 uint64_t txfslstune : 4; /**< FS/LS Source Impedence Adjustment */ 1792 uint64_t txhsxvtune : 2; /**< Transmitter High-Speed Crossover Adjustment */ 1793 uint64_t sqrxtune : 3; /**< Squelch Threshold Adjustment */ 1794 uint64_t compdistune : 3; /**< Disconnect Threshold Adjustment */ 1795 uint64_t otgtune : 3; /**< VBUS Valid Threshold Adjustment */ 1796 uint64_t otgdisable : 1; /**< OTG Block Disable */ 1797 uint64_t portreset : 1; /**< Per_Port Reset */ 1798 uint64_t drvvbus : 1; /**< Drive VBUS */ 1799 uint64_t lsbist : 1; /**< Low-Speed BIST Enable. */ 1800 uint64_t fsbist : 1; /**< Full-Speed BIST Enable. */ 1801 uint64_t hsbist : 1; /**< High-Speed BIST Enable. */ 1802 uint64_t bist_done : 1; /**< PHY Bist Done. 1803 Asserted at the end of the PHY BIST sequence. */ 1804 uint64_t bist_err : 1; /**< PHY Bist Error. 1805 Indicates an internal error was detected during 1806 the BIST sequence. */ 1807 uint64_t tdata_out : 4; /**< PHY Test Data Out. 1808 Presents either internaly generated signals or 1809 test register contents, based upon the value of 1810 test_data_out_sel. */ 1811 uint64_t siddq : 1; /**< Drives the USBP (USB-PHY) SIDDQ input. 1812 Normally should be set to zero. 1813 When customers have no intent to use USB PHY 1814 interface, they should: 1815 - still provide 3.3V to USB_VDD33, and 1816 - tie USB_REXT to 3.3V supply, and 1817 - set USBN*_USBP_CTL_STATUS[SIDDQ]=1 */ 1818 uint64_t txpreemphasistune : 1; /**< HS Transmitter Pre-Emphasis Enable */ 1819 uint64_t dma_bmode : 1; /**< When set to 1 the L2C DMA address will be updated 1820 with byte-counts between packets. When set to 0 1821 the L2C DMA address is incremented to the next 1822 4-byte aligned address after adding byte-count. */ 1823 uint64_t usbc_end : 1; /**< Bigendian input to the USB Core. This should be 1824 set to '0' for operation. */ 1825 uint64_t usbp_bist : 1; /**< PHY, This is cleared '0' to run BIST on the USBP. */ 1826 uint64_t tclk : 1; /**< PHY Test Clock, used to load TDATA_IN to the USBP. */ 1827 uint64_t dp_pulld : 1; /**< PHY DP_PULLDOWN input to the USB-PHY. 1828 This signal enables the pull-down resistance on 1829 the D+ line. '1' pull down-resistance is connected 1830 to D+/ '0' pull down resistance is not connected 1831 to D+. When an A/B device is acting as a host 1832 (downstream-facing port), dp_pulldown and 1833 dm_pulldown are enabled. This must not toggle 1834 during normal opeartion. */ 1835 uint64_t dm_pulld : 1; /**< PHY DM_PULLDOWN input to the USB-PHY. 1836 This signal enables the pull-down resistance on 1837 the D- line. '1' pull down-resistance is connected 1838 to D-. '0' pull down resistance is not connected 1839 to D-. When an A/B device is acting as a host 1840 (downstream-facing port), dp_pulldown and 1841 dm_pulldown are enabled. This must not toggle 1842 during normal opeartion. */ 1843 uint64_t hst_mode : 1; /**< When '0' the USB is acting as HOST, when '1' 1844 USB is acting as device. This field needs to be 1845 set while the USB is in reset. */ 1846 uint64_t tuning : 4; /**< Transmitter Tuning for High-Speed Operation. 1847 Tunes the current supply and rise/fall output 1848 times for high-speed operation. 1849 [20:19] == 11: Current supply increased 1850 approximately 9% 1851 [20:19] == 10: Current supply increased 1852 approximately 4.5% 1853 [20:19] == 01: Design default. 1854 [20:19] == 00: Current supply decreased 1855 approximately 4.5% 1856 [22:21] == 11: Rise and fall times are increased. 1857 [22:21] == 10: Design default. 1858 [22:21] == 01: Rise and fall times are decreased. 1859 [22:21] == 00: Rise and fall times are decreased 1860 further as compared to the 01 setting. */ 1861 uint64_t tx_bs_enh : 1; /**< Transmit Bit Stuffing on [15:8]. 1862 Enables or disables bit stuffing on data[15:8] 1863 when bit-stuffing is enabled. */ 1864 uint64_t tx_bs_en : 1; /**< Transmit Bit Stuffing on [7:0]. 1865 Enables or disables bit stuffing on data[7:0] 1866 when bit-stuffing is enabled. */ 1867 uint64_t loop_enb : 1; /**< PHY Loopback Test Enable. 1868 '1': During data transmission the receive is 1869 enabled. 1870 '0': During data transmission the receive is 1871 disabled. 1872 Must be '0' for normal operation. */ 1873 uint64_t vtest_enb : 1; /**< Analog Test Pin Enable. 1874 '1' The PHY's analog_test pin is enabled for the 1875 input and output of applicable analog test signals. 1876 '0' THe analog_test pin is disabled. */ 1877 uint64_t bist_enb : 1; /**< Built-In Self Test Enable. 1878 Used to activate BIST in the PHY. */ 1879 uint64_t tdata_sel : 1; /**< Test Data Out Select. 1880 '1' test_data_out[3:0] (PHY) register contents 1881 are output. '0' internaly generated signals are 1882 output. */ 1883 uint64_t taddr_in : 4; /**< Mode Address for Test Interface. 1884 Specifies the register address for writing to or 1885 reading from the PHY test interface register. */ 1886 uint64_t tdata_in : 8; /**< Internal Testing Register Input Data and Select 1887 This is a test bus. Data is present on [3:0], 1888 and its corresponding select (enable) is present 1889 on bits [7:4]. */ 1890 uint64_t ate_reset : 1; /**< Reset input from automatic test equipment. 1891 This is a test signal. When the USB Core is 1892 powered up (not in Susned Mode), an automatic 1893 tester can use this to disable phy_clock and 1894 free_clk, then re-eanable them with an aligned 1895 phase. 1896 '1': The phy_clk and free_clk outputs are 1897 disabled. "0": The phy_clock and free_clk outputs 1898 are available within a specific period after the 1899 de-assertion. */ 1900#else 1901 uint64_t ate_reset : 1; 1902 uint64_t tdata_in : 8; 1903 uint64_t taddr_in : 4; 1904 uint64_t tdata_sel : 1; 1905 uint64_t bist_enb : 1; 1906 uint64_t vtest_enb : 1; 1907 uint64_t loop_enb : 1; 1908 uint64_t tx_bs_en : 1; 1909 uint64_t tx_bs_enh : 1; 1910 uint64_t tuning : 4; 1911 uint64_t hst_mode : 1; 1912 uint64_t dm_pulld : 1; 1913 uint64_t dp_pulld : 1; 1914 uint64_t tclk : 1; 1915 uint64_t usbp_bist : 1; 1916 uint64_t usbc_end : 1; 1917 uint64_t dma_bmode : 1; 1918 uint64_t txpreemphasistune : 1; 1919 uint64_t siddq : 1; 1920 uint64_t tdata_out : 4; 1921 uint64_t bist_err : 1; 1922 uint64_t bist_done : 1; 1923 uint64_t hsbist : 1; 1924 uint64_t fsbist : 1; 1925 uint64_t lsbist : 1; 1926 uint64_t drvvbus : 1; 1927 uint64_t portreset : 1; 1928 uint64_t otgdisable : 1; 1929 uint64_t otgtune : 3; 1930 uint64_t compdistune : 3; 1931 uint64_t sqrxtune : 3; 1932 uint64_t txhsxvtune : 2; 1933 uint64_t txfslstune : 4; 1934 uint64_t txvreftune : 4; 1935 uint64_t txrisetune : 1; 1936#endif 1937 } s; 1938 struct cvmx_usbnx_usbp_ctl_status_cn30xx { 1939#ifdef __BIG_ENDIAN_BITFIELD 1940 uint64_t reserved_38_63 : 26; 1941 uint64_t bist_done : 1; /**< PHY Bist Done. 1942 Asserted at the end of the PHY BIST sequence. */ 1943 uint64_t bist_err : 1; /**< PHY Bist Error. 1944 Indicates an internal error was detected during 1945 the BIST sequence. */ 1946 uint64_t tdata_out : 4; /**< PHY Test Data Out. 1947 Presents either internaly generated signals or 1948 test register contents, based upon the value of 1949 test_data_out_sel. */ 1950 uint64_t reserved_30_31 : 2; 1951 uint64_t dma_bmode : 1; /**< When set to 1 the L2C DMA address will be updated 1952 with byte-counts between packets. When set to 0 1953 the L2C DMA address is incremented to the next 1954 4-byte aligned address after adding byte-count. */ 1955 uint64_t usbc_end : 1; /**< Bigendian input to the USB Core. This should be 1956 set to '0' for operation. */ 1957 uint64_t usbp_bist : 1; /**< PHY, This is cleared '0' to run BIST on the USBP. */ 1958 uint64_t tclk : 1; /**< PHY Test Clock, used to load TDATA_IN to the USBP. */ 1959 uint64_t dp_pulld : 1; /**< PHY DP_PULLDOWN input to the USB-PHY. 1960 This signal enables the pull-down resistance on 1961 the D+ line. '1' pull down-resistance is connected 1962 to D+/ '0' pull down resistance is not connected 1963 to D+. When an A/B device is acting as a host 1964 (downstream-facing port), dp_pulldown and 1965 dm_pulldown are enabled. This must not toggle 1966 during normal opeartion. */ 1967 uint64_t dm_pulld : 1; /**< PHY DM_PULLDOWN input to the USB-PHY. 1968 This signal enables the pull-down resistance on 1969 the D- line. '1' pull down-resistance is connected 1970 to D-. '0' pull down resistance is not connected 1971 to D-. When an A/B device is acting as a host 1972 (downstream-facing port), dp_pulldown and 1973 dm_pulldown are enabled. This must not toggle 1974 during normal opeartion. */ 1975 uint64_t hst_mode : 1; /**< When '0' the USB is acting as HOST, when '1' 1976 USB is acting as device. This field needs to be 1977 set while the USB is in reset. */ 1978 uint64_t tuning : 4; /**< Transmitter Tuning for High-Speed Operation. 1979 Tunes the current supply and rise/fall output 1980 times for high-speed operation. 1981 [20:19] == 11: Current supply increased 1982 approximately 9% 1983 [20:19] == 10: Current supply increased 1984 approximately 4.5% 1985 [20:19] == 01: Design default. 1986 [20:19] == 00: Current supply decreased 1987 approximately 4.5% 1988 [22:21] == 11: Rise and fall times are increased. 1989 [22:21] == 10: Design default. 1990 [22:21] == 01: Rise and fall times are decreased. 1991 [22:21] == 00: Rise and fall times are decreased 1992 further as compared to the 01 setting. */ 1993 uint64_t tx_bs_enh : 1; /**< Transmit Bit Stuffing on [15:8]. 1994 Enables or disables bit stuffing on data[15:8] 1995 when bit-stuffing is enabled. */ 1996 uint64_t tx_bs_en : 1; /**< Transmit Bit Stuffing on [7:0]. 1997 Enables or disables bit stuffing on data[7:0] 1998 when bit-stuffing is enabled. */ 1999 uint64_t loop_enb : 1; /**< PHY Loopback Test Enable. 2000 '1': During data transmission the receive is 2001 enabled. 2002 '0': During data transmission the receive is 2003 disabled. 2004 Must be '0' for normal operation. */ 2005 uint64_t vtest_enb : 1; /**< Analog Test Pin Enable. 2006 '1' The PHY's analog_test pin is enabled for the 2007 input and output of applicable analog test signals. 2008 '0' THe analog_test pin is disabled. */ 2009 uint64_t bist_enb : 1; /**< Built-In Self Test Enable. 2010 Used to activate BIST in the PHY. */ 2011 uint64_t tdata_sel : 1; /**< Test Data Out Select. 2012 '1' test_data_out[3:0] (PHY) register contents 2013 are output. '0' internaly generated signals are 2014 output. */ 2015 uint64_t taddr_in : 4; /**< Mode Address for Test Interface. 2016 Specifies the register address for writing to or 2017 reading from the PHY test interface register. */ 2018 uint64_t tdata_in : 8; /**< Internal Testing Register Input Data and Select 2019 This is a test bus. Data is present on [3:0], 2020 and its corresponding select (enable) is present 2021 on bits [7:4]. */ 2022 uint64_t ate_reset : 1; /**< Reset input from automatic test equipment. 2023 This is a test signal. When the USB Core is 2024 powered up (not in Susned Mode), an automatic 2025 tester can use this to disable phy_clock and 2026 free_clk, then re-eanable them with an aligned 2027 phase. 2028 '1': The phy_clk and free_clk outputs are 2029 disabled. "0": The phy_clock and free_clk outputs 2030 are available within a specific period after the 2031 de-assertion. */ 2032#else 2033 uint64_t ate_reset : 1; 2034 uint64_t tdata_in : 8; 2035 uint64_t taddr_in : 4; 2036 uint64_t tdata_sel : 1; 2037 uint64_t bist_enb : 1; 2038 uint64_t vtest_enb : 1; 2039 uint64_t loop_enb : 1; 2040 uint64_t tx_bs_en : 1; 2041 uint64_t tx_bs_enh : 1; 2042 uint64_t tuning : 4; 2043 uint64_t hst_mode : 1; 2044 uint64_t dm_pulld : 1; 2045 uint64_t dp_pulld : 1; 2046 uint64_t tclk : 1; 2047 uint64_t usbp_bist : 1; 2048 uint64_t usbc_end : 1; 2049 uint64_t dma_bmode : 1; 2050 uint64_t reserved_30_31 : 2; 2051 uint64_t tdata_out : 4; 2052 uint64_t bist_err : 1; 2053 uint64_t bist_done : 1; 2054 uint64_t reserved_38_63 : 26; 2055#endif 2056 } cn30xx; 2057 struct cvmx_usbnx_usbp_ctl_status_cn30xx cn31xx; 2058 struct cvmx_usbnx_usbp_ctl_status_cn50xx { 2059#ifdef __BIG_ENDIAN_BITFIELD 2060 uint64_t txrisetune : 1; /**< HS Transmitter Rise/Fall Time Adjustment */ 2061 uint64_t txvreftune : 4; /**< HS DC Voltage Level Adjustment */ 2062 uint64_t txfslstune : 4; /**< FS/LS Source Impedence Adjustment */ 2063 uint64_t txhsxvtune : 2; /**< Transmitter High-Speed Crossover Adjustment */ 2064 uint64_t sqrxtune : 3; /**< Squelch Threshold Adjustment */ 2065 uint64_t compdistune : 3; /**< Disconnect Threshold Adjustment */ 2066 uint64_t otgtune : 3; /**< VBUS Valid Threshold Adjustment */ 2067 uint64_t otgdisable : 1; /**< OTG Block Disable */ 2068 uint64_t portreset : 1; /**< Per_Port Reset */ 2069 uint64_t drvvbus : 1; /**< Drive VBUS */ 2070 uint64_t lsbist : 1; /**< Low-Speed BIST Enable. */ 2071 uint64_t fsbist : 1; /**< Full-Speed BIST Enable. */ 2072 uint64_t hsbist : 1; /**< High-Speed BIST Enable. */ 2073 uint64_t bist_done : 1; /**< PHY Bist Done. 2074 Asserted at the end of the PHY BIST sequence. */ 2075 uint64_t bist_err : 1; /**< PHY Bist Error. 2076 Indicates an internal error was detected during 2077 the BIST sequence. */ 2078 uint64_t tdata_out : 4; /**< PHY Test Data Out. 2079 Presents either internaly generated signals or 2080 test register contents, based upon the value of 2081 test_data_out_sel. */ 2082 uint64_t reserved_31_31 : 1; 2083 uint64_t txpreemphasistune : 1; /**< HS Transmitter Pre-Emphasis Enable */ 2084 uint64_t dma_bmode : 1; /**< When set to 1 the L2C DMA address will be updated 2085 with byte-counts between packets. When set to 0 2086 the L2C DMA address is incremented to the next 2087 4-byte aligned address after adding byte-count. */ 2088 uint64_t usbc_end : 1; /**< Bigendian input to the USB Core. This should be 2089 set to '0' for operation. */ 2090 uint64_t usbp_bist : 1; /**< PHY, This is cleared '0' to run BIST on the USBP. */ 2091 uint64_t tclk : 1; /**< PHY Test Clock, used to load TDATA_IN to the USBP. */ 2092 uint64_t dp_pulld : 1; /**< PHY DP_PULLDOWN input to the USB-PHY. 2093 This signal enables the pull-down resistance on 2094 the D+ line. '1' pull down-resistance is connected 2095 to D+/ '0' pull down resistance is not connected 2096 to D+. When an A/B device is acting as a host 2097 (downstream-facing port), dp_pulldown and 2098 dm_pulldown are enabled. This must not toggle 2099 during normal opeartion. */ 2100 uint64_t dm_pulld : 1; /**< PHY DM_PULLDOWN input to the USB-PHY. 2101 This signal enables the pull-down resistance on 2102 the D- line. '1' pull down-resistance is connected 2103 to D-. '0' pull down resistance is not connected 2104 to D-. When an A/B device is acting as a host 2105 (downstream-facing port), dp_pulldown and 2106 dm_pulldown are enabled. This must not toggle 2107 during normal opeartion. */ 2108 uint64_t hst_mode : 1; /**< When '0' the USB is acting as HOST, when '1' 2109 USB is acting as device. This field needs to be 2110 set while the USB is in reset. */ 2111 uint64_t reserved_19_22 : 4; 2112 uint64_t tx_bs_enh : 1; /**< Transmit Bit Stuffing on [15:8]. 2113 Enables or disables bit stuffing on data[15:8] 2114 when bit-stuffing is enabled. */ 2115 uint64_t tx_bs_en : 1; /**< Transmit Bit Stuffing on [7:0]. 2116 Enables or disables bit stuffing on data[7:0] 2117 when bit-stuffing is enabled. */ 2118 uint64_t loop_enb : 1; /**< PHY Loopback Test Enable. 2119 '1': During data transmission the receive is 2120 enabled. 2121 '0': During data transmission the receive is 2122 disabled. 2123 Must be '0' for normal operation. */ 2124 uint64_t vtest_enb : 1; /**< Analog Test Pin Enable. 2125 '1' The PHY's analog_test pin is enabled for the 2126 input and output of applicable analog test signals. 2127 '0' THe analog_test pin is disabled. */ 2128 uint64_t bist_enb : 1; /**< Built-In Self Test Enable. 2129 Used to activate BIST in the PHY. */ 2130 uint64_t tdata_sel : 1; /**< Test Data Out Select. 2131 '1' test_data_out[3:0] (PHY) register contents 2132 are output. '0' internaly generated signals are 2133 output. */ 2134 uint64_t taddr_in : 4; /**< Mode Address for Test Interface. 2135 Specifies the register address for writing to or 2136 reading from the PHY test interface register. */ 2137 uint64_t tdata_in : 8; /**< Internal Testing Register Input Data and Select 2138 This is a test bus. Data is present on [3:0], 2139 and its corresponding select (enable) is present 2140 on bits [7:4]. */ 2141 uint64_t ate_reset : 1; /**< Reset input from automatic test equipment. 2142 This is a test signal. When the USB Core is 2143 powered up (not in Susned Mode), an automatic 2144 tester can use this to disable phy_clock and 2145 free_clk, then re-eanable them with an aligned 2146 phase. 2147 '1': The phy_clk and free_clk outputs are 2148 disabled. "0": The phy_clock and free_clk outputs 2149 are available within a specific period after the 2150 de-assertion. */ 2151#else 2152 uint64_t ate_reset : 1; 2153 uint64_t tdata_in : 8; 2154 uint64_t taddr_in : 4; 2155 uint64_t tdata_sel : 1; 2156 uint64_t bist_enb : 1; 2157 uint64_t vtest_enb : 1; 2158 uint64_t loop_enb : 1; 2159 uint64_t tx_bs_en : 1; 2160 uint64_t tx_bs_enh : 1; 2161 uint64_t reserved_19_22 : 4; 2162 uint64_t hst_mode : 1; 2163 uint64_t dm_pulld : 1; 2164 uint64_t dp_pulld : 1; 2165 uint64_t tclk : 1; 2166 uint64_t usbp_bist : 1; 2167 uint64_t usbc_end : 1; 2168 uint64_t dma_bmode : 1; 2169 uint64_t txpreemphasistune : 1; 2170 uint64_t reserved_31_31 : 1; 2171 uint64_t tdata_out : 4; 2172 uint64_t bist_err : 1; 2173 uint64_t bist_done : 1; 2174 uint64_t hsbist : 1; 2175 uint64_t fsbist : 1; 2176 uint64_t lsbist : 1; 2177 uint64_t drvvbus : 1; 2178 uint64_t portreset : 1; 2179 uint64_t otgdisable : 1; 2180 uint64_t otgtune : 3; 2181 uint64_t compdistune : 3; 2182 uint64_t sqrxtune : 3; 2183 uint64_t txhsxvtune : 2; 2184 uint64_t txfslstune : 4; 2185 uint64_t txvreftune : 4; 2186 uint64_t txrisetune : 1; 2187#endif 2188 } cn50xx; 2189 struct cvmx_usbnx_usbp_ctl_status_cn52xx { 2190#ifdef __BIG_ENDIAN_BITFIELD 2191 uint64_t txrisetune : 1; /**< HS Transmitter Rise/Fall Time Adjustment */ 2192 uint64_t txvreftune : 4; /**< HS DC Voltage Level Adjustment */ 2193 uint64_t txfslstune : 4; /**< FS/LS Source Impedence Adjustment */ 2194 uint64_t txhsxvtune : 2; /**< Transmitter High-Speed Crossover Adjustment */ 2195 uint64_t sqrxtune : 3; /**< Squelch Threshold Adjustment */ 2196 uint64_t compdistune : 3; /**< Disconnect Threshold Adjustment */ 2197 uint64_t otgtune : 3; /**< VBUS Valid Threshold Adjustment */ 2198 uint64_t otgdisable : 1; /**< OTG Block Disable */ 2199 uint64_t portreset : 1; /**< Per_Port Reset */ 2200 uint64_t drvvbus : 1; /**< Drive VBUS */ 2201 uint64_t lsbist : 1; /**< Low-Speed BIST Enable. */ 2202 uint64_t fsbist : 1; /**< Full-Speed BIST Enable. */ 2203 uint64_t hsbist : 1; /**< High-Speed BIST Enable. */ 2204 uint64_t bist_done : 1; /**< PHY Bist Done. 2205 Asserted at the end of the PHY BIST sequence. */ 2206 uint64_t bist_err : 1; /**< PHY Bist Error. 2207 Indicates an internal error was detected during 2208 the BIST sequence. */ 2209 uint64_t tdata_out : 4; /**< PHY Test Data Out. 2210 Presents either internaly generated signals or 2211 test register contents, based upon the value of 2212 test_data_out_sel. */ 2213 uint64_t siddq : 1; /**< Drives the USBP (USB-PHY) SIDDQ input. 2214 Normally should be set to zero. 2215 When customers have no intent to use USB PHY 2216 interface, they should: 2217 - still provide 3.3V to USB_VDD33, and 2218 - tie USB_REXT to 3.3V supply, and 2219 - set USBN*_USBP_CTL_STATUS[SIDDQ]=1 */ 2220 uint64_t txpreemphasistune : 1; /**< HS Transmitter Pre-Emphasis Enable */ 2221 uint64_t dma_bmode : 1; /**< When set to 1 the L2C DMA address will be updated 2222 with byte-counts between packets. When set to 0 2223 the L2C DMA address is incremented to the next 2224 4-byte aligned address after adding byte-count. */ 2225 uint64_t usbc_end : 1; /**< Bigendian input to the USB Core. This should be 2226 set to '0' for operation. */ 2227 uint64_t usbp_bist : 1; /**< PHY, This is cleared '0' to run BIST on the USBP. */ 2228 uint64_t tclk : 1; /**< PHY Test Clock, used to load TDATA_IN to the USBP. */ 2229 uint64_t dp_pulld : 1; /**< PHY DP_PULLDOWN input to the USB-PHY. 2230 This signal enables the pull-down resistance on 2231 the D+ line. '1' pull down-resistance is connected 2232 to D+/ '0' pull down resistance is not connected 2233 to D+. When an A/B device is acting as a host 2234 (downstream-facing port), dp_pulldown and 2235 dm_pulldown are enabled. This must not toggle 2236 during normal opeartion. */ 2237 uint64_t dm_pulld : 1; /**< PHY DM_PULLDOWN input to the USB-PHY. 2238 This signal enables the pull-down resistance on 2239 the D- line. '1' pull down-resistance is connected 2240 to D-. '0' pull down resistance is not connected 2241 to D-. When an A/B device is acting as a host 2242 (downstream-facing port), dp_pulldown and 2243 dm_pulldown are enabled. This must not toggle 2244 during normal opeartion. */ 2245 uint64_t hst_mode : 1; /**< When '0' the USB is acting as HOST, when '1' 2246 USB is acting as device. This field needs to be 2247 set while the USB is in reset. */ 2248 uint64_t reserved_19_22 : 4; 2249 uint64_t tx_bs_enh : 1; /**< Transmit Bit Stuffing on [15:8]. 2250 Enables or disables bit stuffing on data[15:8] 2251 when bit-stuffing is enabled. */ 2252 uint64_t tx_bs_en : 1; /**< Transmit Bit Stuffing on [7:0]. 2253 Enables or disables bit stuffing on data[7:0] 2254 when bit-stuffing is enabled. */ 2255 uint64_t loop_enb : 1; /**< PHY Loopback Test Enable. 2256 '1': During data transmission the receive is 2257 enabled. 2258 '0': During data transmission the receive is 2259 disabled. 2260 Must be '0' for normal operation. */ 2261 uint64_t vtest_enb : 1; /**< Analog Test Pin Enable. 2262 '1' The PHY's analog_test pin is enabled for the 2263 input and output of applicable analog test signals. 2264 '0' THe analog_test pin is disabled. */ 2265 uint64_t bist_enb : 1; /**< Built-In Self Test Enable. 2266 Used to activate BIST in the PHY. */ 2267 uint64_t tdata_sel : 1; /**< Test Data Out Select. 2268 '1' test_data_out[3:0] (PHY) register contents 2269 are output. '0' internaly generated signals are 2270 output. */ 2271 uint64_t taddr_in : 4; /**< Mode Address for Test Interface. 2272 Specifies the register address for writing to or 2273 reading from the PHY test interface register. */ 2274 uint64_t tdata_in : 8; /**< Internal Testing Register Input Data and Select 2275 This is a test bus. Data is present on [3:0], 2276 and its corresponding select (enable) is present 2277 on bits [7:4]. */ 2278 uint64_t ate_reset : 1; /**< Reset input from automatic test equipment. 2279 This is a test signal. When the USB Core is 2280 powered up (not in Susned Mode), an automatic 2281 tester can use this to disable phy_clock and 2282 free_clk, then re-eanable them with an aligned 2283 phase. 2284 '1': The phy_clk and free_clk outputs are 2285 disabled. "0": The phy_clock and free_clk outputs 2286 are available within a specific period after the 2287 de-assertion. */ 2288#else 2289 uint64_t ate_reset : 1; 2290 uint64_t tdata_in : 8; 2291 uint64_t taddr_in : 4; 2292 uint64_t tdata_sel : 1; 2293 uint64_t bist_enb : 1; 2294 uint64_t vtest_enb : 1; 2295 uint64_t loop_enb : 1; 2296 uint64_t tx_bs_en : 1; 2297 uint64_t tx_bs_enh : 1; 2298 uint64_t reserved_19_22 : 4; 2299 uint64_t hst_mode : 1; 2300 uint64_t dm_pulld : 1; 2301 uint64_t dp_pulld : 1; 2302 uint64_t tclk : 1; 2303 uint64_t usbp_bist : 1; 2304 uint64_t usbc_end : 1; 2305 uint64_t dma_bmode : 1; 2306 uint64_t txpreemphasistune : 1; 2307 uint64_t siddq : 1; 2308 uint64_t tdata_out : 4; 2309 uint64_t bist_err : 1; 2310 uint64_t bist_done : 1; 2311 uint64_t hsbist : 1; 2312 uint64_t fsbist : 1; 2313 uint64_t lsbist : 1; 2314 uint64_t drvvbus : 1; 2315 uint64_t portreset : 1; 2316 uint64_t otgdisable : 1; 2317 uint64_t otgtune : 3; 2318 uint64_t compdistune : 3; 2319 uint64_t sqrxtune : 3; 2320 uint64_t txhsxvtune : 2; 2321 uint64_t txfslstune : 4; 2322 uint64_t txvreftune : 4; 2323 uint64_t txrisetune : 1; 2324#endif 2325 } cn52xx; 2326 struct cvmx_usbnx_usbp_ctl_status_cn50xx cn52xxp1; 2327 struct cvmx_usbnx_usbp_ctl_status_cn52xx cn56xx; 2328 struct cvmx_usbnx_usbp_ctl_status_cn50xx cn56xxp1; 2329}; 2330typedef union cvmx_usbnx_usbp_ctl_status cvmx_usbnx_usbp_ctl_status_t; 2331 2332#endif 2333