1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Inc. nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41 42 43 44 45 46/** 47 * @file 48 * 49 * Support library for the hardware work queue timers. 50 * 51 * <hr>$Revision: 70030 $<hr> 52 */ 53#include "executive-config.h" 54#include "cvmx-config.h" 55#include "cvmx.h" 56#include "cvmx-sysinfo.h" 57#include "cvmx-tim.h" 58#include "cvmx-bootmem.h" 59 60/* CSR typedefs have been moved to cvmx-tim-defs.h */ 61 62/** 63 * Global structure holding the state of all timers. 64 */ 65CVMX_SHARED cvmx_tim_t cvmx_tim; 66 67 68#ifdef CVMX_ENABLE_TIMER_FUNCTIONS 69/** 70 * Setup a timer for use. Must be called before the timer 71 * can be used. 72 * 73 * @param tick Time between each bucket in microseconds. This must not be 74 * smaller than 1024/(clock frequency in MHz). 75 * @param max_ticks The maximum number of ticks the timer must be able 76 * to schedule in the future. There are guaranteed to be enough 77 * timer buckets such that: 78 * number of buckets >= max_ticks. 79 * @return Zero on success. Negative on error. Failures are possible 80 * if the number of buckets needed is too large or memory 81 * allocation fails for creating the buckets. 82 */ 83int cvmx_tim_setup(uint64_t tick, uint64_t max_ticks) 84{ 85 uint64_t timer_id; 86 int error = -1; 87 uint64_t tim_clock_hz = cvmx_clock_get_rate(CVMX_CLOCK_TIM); 88 uint64_t hw_tick_ns; 89 uint64_t hw_tick_ns_allowed; 90 uint64_t tick_ns = 1000 * tick; 91 int i; 92 uint32_t temp; 93 int timer_thr = 1024; 94 95 /* for the simulator */ 96 if (tim_clock_hz == 0) 97 tim_clock_hz = 800000000; 98 99 if (OCTEON_IS_MODEL(OCTEON_CN68XX)) 100 { 101 cvmx_tim_fr_rn_tt_t fr_tt; 102 fr_tt.u64 = cvmx_read_csr(CVMX_TIM_FR_RN_TT); 103 timer_thr = fr_tt.s.fr_rn_tt; 104 } 105 106 hw_tick_ns = timer_thr * 1000000000ull / tim_clock_hz; 107 /* 108 * Double the minimal allowed tick to 2 * HW tick. tick between 109 * (hw_tick_ns, 2*hw_tick_ns) will set config_ring1.s.interval 110 * to zero, or 1024 cycles. This is not enough time for the timer unit 111 * to fetch the bucket data, Resulting in timer ring error interrupt 112 * be always generated. Avoid such setting in software. 113 */ 114 hw_tick_ns_allowed = hw_tick_ns * 2; 115 116 /* Make sure the timers are stopped */ 117 cvmx_tim_stop(); 118 119 /* Reinitialize out timer state */ 120 memset(&cvmx_tim, 0, sizeof(cvmx_tim)); 121 122 if (tick_ns < hw_tick_ns_allowed) 123 { 124 cvmx_dprintf("ERROR: cvmx_tim_setup: Requested tick %lu(ns) is smaller than" 125 " the minimal ticks allowed by hardware %lu(ns)\n", 126 tick_ns, hw_tick_ns_allowed); 127 return error; 128 } 129 else if (tick_ns > 4194304 * hw_tick_ns) 130 { 131 cvmx_dprintf("ERROR: cvmx_tim_setup: Requested tick %lu(ns) is greater than" 132 " the max ticks %lu(ns)\n", tick_ns, hw_tick_ns); 133 return error; 134 } 135 136 for (i=2; i<20; i++) 137 { 138 if (tick_ns < (hw_tick_ns << i)) 139 break; 140 } 141 142 cvmx_tim.max_ticks = (uint32_t)max_ticks; 143 cvmx_tim.bucket_shift = (uint32_t)(i - 1 + 10); 144 cvmx_tim.tick_cycles = tick * tim_clock_hz / 1000000; 145 146 temp = (max_ticks * cvmx_tim.tick_cycles) >> cvmx_tim.bucket_shift; 147 148 /* round up to nearest power of 2 */ 149 temp -= 1; 150 temp = temp | (temp >> 1); 151 temp = temp | (temp >> 2); 152 temp = temp | (temp >> 4); 153 temp = temp | (temp >> 8); 154 temp = temp | (temp >> 16); 155 cvmx_tim.num_buckets = temp + 1; 156 157 /* ensure input params fall into permitted ranges */ 158 if ((cvmx_tim.num_buckets < 3) || cvmx_tim.num_buckets > 1048576) 159 { 160 cvmx_dprintf("ERROR: cvmx_tim_setup: num_buckets out of range\n"); 161 return error; 162 } 163 164 /* Allocate the timer buckets from hardware addressable memory */ 165 cvmx_tim.bucket = cvmx_bootmem_alloc(CVMX_TIM_NUM_TIMERS * cvmx_tim.num_buckets 166 * sizeof(cvmx_tim_bucket_entry_t), CVMX_CACHE_LINE_SIZE); 167 if (cvmx_tim.bucket == NULL) 168 { 169 cvmx_dprintf("ERROR: cvmx_tim_setup: allocation problem\n"); 170 return error; 171 } 172 memset(cvmx_tim.bucket, 0, CVMX_TIM_NUM_TIMERS * cvmx_tim.num_buckets * sizeof(cvmx_tim_bucket_entry_t)); 173 174 cvmx_tim.start_time = 0; 175 176 /* Loop through all timers */ 177 for (timer_id = 0; timer_id<CVMX_TIM_NUM_TIMERS; timer_id++) 178 { 179 int interval = ((1 << (cvmx_tim.bucket_shift - 10)) - 1); 180 cvmx_tim_bucket_entry_t *bucket = cvmx_tim.bucket + timer_id * cvmx_tim.num_buckets; 181 if (OCTEON_IS_MODEL(OCTEON_CN68XX)) 182 { 183 cvmx_tim_ringx_ctl0_t ring_ctl0; 184 cvmx_tim_ringx_ctl1_t ring_ctl1; 185 cvmx_tim_ringx_ctl2_t ring_ctl2; 186 cvmx_tim_reg_flags_t reg_flags; 187 188 /* Tell the hardware where about the bucket array */ 189 ring_ctl2.u64 = 0; 190 ring_ctl2.s.csize = CVMX_FPA_TIMER_POOL_SIZE / 8; 191 ring_ctl2.s.base = cvmx_ptr_to_phys(bucket) >> 5; 192 cvmx_write_csr(CVMX_TIM_RINGX_CTL2(timer_id), ring_ctl2.u64); 193 194 reg_flags.u64 = cvmx_read_csr(CVMX_TIM_REG_FLAGS); 195 ring_ctl1.u64 = 0; 196 ring_ctl1.s.cpool = ((reg_flags.s.ena_dfb == 0) ? CVMX_FPA_TIMER_POOL : 0); 197 ring_ctl1.s.bsize = cvmx_tim.num_buckets - 1; 198 cvmx_write_csr(CVMX_TIM_RINGX_CTL1(timer_id), ring_ctl1.u64); 199 200 ring_ctl0.u64 = 0; 201 ring_ctl0.s.timercount = interval + timer_id * interval / CVMX_TIM_NUM_TIMERS; 202 cvmx_write_csr(CVMX_TIM_RINGX_CTL0(timer_id), ring_ctl0.u64); 203 204 ring_ctl0.u64 = cvmx_read_csr(CVMX_TIM_RINGX_CTL0(timer_id)); 205 ring_ctl0.s.ena = 1; 206 ring_ctl0.s.interval = interval; 207 cvmx_write_csr(CVMX_TIM_RINGX_CTL0(timer_id), ring_ctl0.u64); 208 ring_ctl0.u64 = cvmx_read_csr(CVMX_TIM_RINGX_CTL0(timer_id)); 209 } 210 else 211 { 212 cvmx_tim_mem_ring0_t config_ring0; 213 cvmx_tim_mem_ring1_t config_ring1; 214 /* Tell the hardware where about the bucket array */ 215 config_ring0.u64 = 0; 216 config_ring0.s.first_bucket = cvmx_ptr_to_phys(bucket) >> 5; 217 config_ring0.s.num_buckets = cvmx_tim.num_buckets - 1; 218 config_ring0.s.ring = timer_id; 219 cvmx_write_csr(CVMX_TIM_MEM_RING0, config_ring0.u64); 220 221 /* Tell the hardware the size of each chunk block in pointers */ 222 config_ring1.u64 = 0; 223 config_ring1.s.enable = 1; 224 config_ring1.s.pool = CVMX_FPA_TIMER_POOL; 225 config_ring1.s.words_per_chunk = CVMX_FPA_TIMER_POOL_SIZE / 8; 226 config_ring1.s.interval = interval; 227 config_ring1.s.ring = timer_id; 228 cvmx_write_csr(CVMX_TIM_MEM_RING1, config_ring1.u64); 229 } 230 } 231 232 return 0; 233} 234#endif 235 236/** 237 * Start the hardware timer processing 238 */ 239void cvmx_tim_start(void) 240{ 241 cvmx_tim_control_t control; 242 243 control.u64 = cvmx_read_csr(CVMX_TIM_REG_FLAGS); 244 control.s.enable_dwb = 1; 245 control.s.enable_timers = 1; 246 247 /* Remember when we started the timers */ 248 cvmx_tim.start_time = cvmx_clock_get_count(CVMX_CLOCK_TIM); 249 cvmx_write_csr(CVMX_TIM_REG_FLAGS, control.u64); 250} 251 252 253/** 254 * Stop the hardware timer processing. Timers stay configured. 255 */ 256void cvmx_tim_stop(void) 257{ 258 cvmx_tim_control_t control; 259 control.u64 = cvmx_read_csr(CVMX_TIM_REG_FLAGS); 260 control.s.enable_dwb = 0; 261 control.s.enable_timers = 0; 262 cvmx_write_csr(CVMX_TIM_REG_FLAGS, control.u64); 263} 264 265 266/** 267 * Stop the timer. After this the timer must be setup again 268 * before use. 269 */ 270#ifdef CVMX_ENABLE_TIMER_FUNCTIONS 271void cvmx_tim_shutdown(void) 272{ 273 uint32_t bucket; 274 uint64_t timer_id; 275 uint64_t entries_per_chunk; 276 277 /* Make sure the timers are stopped */ 278 cvmx_tim_stop(); 279 280 entries_per_chunk = CVMX_FPA_TIMER_POOL_SIZE/8 - 1; 281 282 /* Now walk all buckets freeing the chunks */ 283 for (timer_id = 0; timer_id<CVMX_TIM_NUM_TIMERS; timer_id++) 284 { 285 for (bucket=0; bucket<cvmx_tim.num_buckets; bucket++) 286 { 287 uint64_t chunk_addr; 288 uint64_t next_chunk_addr; 289 cvmx_tim_bucket_entry_t *bucket_ptr = cvmx_tim.bucket + timer_id * cvmx_tim.num_buckets + bucket; 290 CVMX_PREFETCH128(CAST64(bucket_ptr)); /* prefetch the next cacheline for future buckets */ 291 292 /* Each bucket contains a list of chunks */ 293 chunk_addr = bucket_ptr->first_chunk_addr; 294 while (bucket_ptr->num_entries) 295 { 296#ifdef DEBUG 297 cvmx_dprintf("Freeing Timer Chunk 0x%llx\n", CAST64(chunk_addr)); 298#endif 299 /* Read next chunk pointer from end of the current chunk */ 300 next_chunk_addr = cvmx_read_csr(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, chunk_addr + CVMX_FPA_TIMER_POOL_SIZE - 8)); 301 302 cvmx_fpa_free(cvmx_phys_to_ptr(chunk_addr), CVMX_FPA_TIMER_POOL, 0); 303 chunk_addr = next_chunk_addr; 304 if (bucket_ptr->num_entries > entries_per_chunk) 305 bucket_ptr->num_entries -= entries_per_chunk; 306 else 307 bucket_ptr->num_entries = 0; 308 } 309 } 310 } 311} 312 313#endif 314