1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Inc. nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41 42 43 44 45 46/** 47 * @file 48 * 49 * Interface to RAID block. This is not available on all chips. 50 * 51 * <hr>$Revision: 70030 $<hr> 52 */ 53 54#ifndef __CVMX_RAID_H__ 55#define __CVMX_RAID_H__ 56 57#ifdef CVMX_BUILD_FOR_LINUX_KERNEL 58#include <asm/octeon/cvmx-rad-defs.h> 59#endif 60 61#ifdef __cplusplus 62extern "C" { 63#endif 64 65/** 66 * This structure defines the type of command words the RAID block 67 * will accept. 68 */ 69typedef union 70{ 71 uint64_t u64; 72 struct 73 { 74 uint64_t reserved_37_63 : 27; /**< Must be zero */ 75 uint64_t q_cmp : 1; /**< Indicates whether the Q pipe is in normal mode (CWORD[Q_CMP]=0) or in non-zero 76 byte detect mode (CWORD[Q_CMP]=1). 77 In non-zero byte detect mode, the Q OWORD[PTR] result is the non-zero detect 78 result, which indicates the position of the first non-zero byte in the pipe result bytes. 79 CWORD[Q_CMP] must not be set when CWORD[QOUT]=0, and must not be set 80 when CWORD[Q_XOR] is set. */ 81 uint64_t p_cmp : 1; /**< Indicates whether the P pipe is in normal mode (CWORD[P_CMP]=0) or in non-zero 82 byte detect mode (CWORD[P_CMP]=1). 83 In non-zero byte detect mode, the P OWORD[PTR] result is the non-zero detect 84 result, which indicates the position of the first non-zero byte in the pipe result bytes. 85 CWORD[P_CMP] must not be set when CWORD[POUT]=0, and must not be set 86 when CWORD[P_XOR] is set. */ 87 uint64_t q_xor : 1; /**< Indicates whether the Q output buffer bytes are the normal Q pipe result or the 88 normal Q pipe result exclusive-OR'ed with the P pipe result. 89 When CWORD[Q_XOR]=0 (and CWORD[Q_CMP]=0), the Q output buffer bytes are 90 the normal Q pipe result, which does not include the P pipe result in any way. 91 When CWORD[Q_XOR]=1, the Q output buffer bytes are the normal Q pipe result 92 exclusive-OR'ed with the P pipe result, as if the P pipe result were another Q IWORD 93 for the Q pipe with QMULT=1. 94 CWORD[Q_XOR] must not be set unless both CWORD[POUT,QOUT] are set, and 95 must not be set when CWORD[Q_CMP] is set. */ 96 uint64_t p_xor : 1; /**< Indicates whether the P output buffer bytes are the normal P pipe result or the 97 normal P pipe result exclusive-OR'ed with the Q pipe result. 98 When CWORD[P_XOR]=0 (and CWORD[P_CMP]=0), the P output buffer bytes are 99 the normal P pipe result, which does not include the Q pipe result in any way. 100 When CWORD[P_XOR]=1, the P output buffer bytes are the normal P pipe result 101 exclusive-OR'ed with the Q pipe result, as if the Q pipe result were another P 102 IWORD for the P pipe. 103 CWORD[P_XOR] must not be set unless both CWORD[POUT,QOUT] are set, and 104 must not be set when CWORD[P_CMP] is set. */ 105 uint64_t wqe : 1; /**< Indicates whether RAD submits a work queue entry or writes an L2/DRAM byte to 106 zero after completing the instruction. 107 When CWORD[WQE] is set and RESP[PTR]!=0, RAD adds the work queue entry 108 indicated by RESP[PTR] to the selected POW input queue after completing the 109 instruction. 110 When CWORD[WQE] is clear and RESP[PTR]!=0, RAD writes the L2/DRAM byte 111 indicated by RESP[PTR] to zero after completing the instruction. */ 112 uint64_t qout : 1; /**< Indicates whether the Q pipe is used by this instruction. 113 If CWORD[QOUT] is set, IWORD[QEN] must be set for at least one IWORD. 114 At least one of CWORD[QOUT,POUT] must be set. */ 115 uint64_t pout : 1; /**< Indicates whether the P pipe is used by this instruction. 116 If CWORD[POUT] is set, IWORD[PEN] must be set for at least one IWORD. 117 At least one of CWORD[QOUT,POUT] must be set. */ 118 uint64_t iword : 6; /**< Indicates the number of input buffers used. 119 1 <= CWORD[IWORD] <= 32. */ 120 uint64_t size : 24; /**< Indicates the size in bytes of all input buffers. When CWORD[Q_CMP,P_CMP]=0, 121 also indicates the size of the Q/P output buffers. 122 CWORD[SIZE] must be a multiple of 8B (i.e. <2:0> must be zero). */ 123 } cword; 124 struct 125 { 126 uint64_t reserved_58_63 : 6; /**< Must be zero */ 127 uint64_t fw : 1; /**< When set, indicates that RAD can modify any byte in any (128B) cache line touched 128 by L2/DRAM addresses OWORD[PTR] through OWORD[PTR]+CWORD[SIZE]�1. 129 Setting OWORD[FW] can improve hardware performance, as some DRAM loads can 130 be avoided on L2 cache misses. The Q OWORD[FW] must not be set when 131 CWORD[Q_CMP] is set, and the P OWORD[FW] must not be set when 132 CWORD[P_CMP] is set. */ 133 uint64_t nc : 1; /**< When set, indicates that RAD should not allocate L2 cache space for the P/Q data on 134 L2 cache misses. 135 OWORD[NC] should typically be clear, though setting OWORD[NC] can improve 136 performance in some circumstances, as the L2 cache will not be polluted by P/Q data. 137 The Q OWORD[NC] must not be set when CWORD[Q_CMP] is set, and the P 138 OWORD[NC] must not be set when CWORD[P_CMP] is set. */ 139 uint64_t reserved_40_55 : 16; /**< Must be zero */ 140 uint64_t addr : 40; /**< When CWORD[P_CMP,Q_CMP]=0, OWORD[PTR] indicates the starting address of 141 the L2/DRAM buffer that will receive the P/Q data. In the non-compare mode, the 142 output buffer receives all of the output buffer bytes. 143 When CWORD[P_CMP,Q_CMP]=1, the corresponding P/Q pipe is in compare mode, 144 and the only output of the pipe is the non-zero detect result. In this case, 145 OWORD[PTR] indicates the 8-byte location of the non-zero detect result. */ 146 } oword; 147 struct 148 { 149 uint64_t reserved_57_63 : 7; /**< Must be zero */ 150 uint64_t nc : 1; /**< When set, indicates that RAD should not allocate L2 cache space for this input buffer 151 data on L2 cache misses. 152 Setting IWORD[NC] may improve performance in some circumstances, as the L2 153 cache may not be polluted with input buffer data. */ 154 uint64_t reserved_50_55 : 6; /**< Must be zero */ 155 uint64_t qen : 1; /**< Indicates that this input buffer data should participate in the Q pipe result. 156 The Q pipe hardware multiplies each participating input byte by IWORD[QMULT] 157 before accumulating them by exclusive-OR'ing. 158 IWORD[QEN] must not be set when CWORD[QOUT] is not set. 159 If CWORD[QOUT] is set, IWORD[QEN] must be set for at least one IWORD. */ 160 uint64_t pen : 1; /**< Indicates that this input buffer data should participate in the P pipe result. 161 The P pipe hardware accumulates each participating input byte by bit-wise 162 exclusive-OR'ing it. 163 IWORD[PEN] must not be set when CWORD[POUT] is not set. 164 If CWORD[POUT] is set, IWORD[PEN] must be set for at least one IWORD. */ 165 uint64_t qmult : 8; /**< The Q pipe multiplier for the input buffer. Section 26.1 above describes the GF(28) 166 multiplication algorithm. 167 IWORD[QMULT] must be zero when IWORD[QEN] is not set. 168 IWORD[QMULT] must not be zero when IWORD[QEN] is set. 169 When IWORD[QMULT] is 1, the multiplication simplifies to the identity function, 170 and the Q pipe performs the same XOR function as the P pipe. */ 171 uint64_t addr : 40; /**< The starting address of the input buffer in L2/DRAM. 172 IWORD[PTR] must be naturally-aligned on an 8 byte boundary (i.e. <2:0> must be 173 zero). */ 174 } iword; 175} cvmx_raid_word_t; 176 177/** 178 * Initialize the RAID block 179 * 180 * @param polynomial Coefficients for the RAID polynomial 181 * 182 * @return Zero on success, negative on failure 183 */ 184int cvmx_raid_initialize(cvmx_rad_reg_polynomial_t polynomial); 185 186/** 187 * Shutdown the RAID block. RAID must be idle when 188 * this function is called. 189 * 190 * @return Zero on success, negative on failure 191 */ 192int cvmx_raid_shutdown(void); 193 194/** 195 * Submit a command to the RAID block 196 * 197 * @param num_words Number of command words to submit 198 * @param words Command words 199 * 200 * @return Zero on success, negative on failure 201 */ 202int cvmx_raid_submit(int num_words, cvmx_raid_word_t words[]); 203 204#ifdef __cplusplus 205} 206#endif 207 208#endif // __CVMX_CMD_QUEUE_H__ 209