cvmx-npi.h revision 210284 
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38
39
40
41
42
43
44/**
45 * @file
46 *
47 * PCI / PCIe packet engine related structures.
48 *
49 * <hr>$Revision: 41586 $<hr>
50 */
51
52#ifndef __CVMX_NPI_H__
53#define __CVMX_NPI_H__
54
55#ifdef	__cplusplus
56extern "C" {
57#endif
58
59/**
60 * PCI / PCIe packet instruction header format
61 */
62typedef union
63{
64    uint64_t u64;
65    struct
66    {
67#if __BYTE_ORDER == __BIG_ENDIAN
68        uint64_t            r :     1;      /**< Packet is RAW */
69        uint64_t            g :     1;      /**< Gather list is used */
70        uint64_t            dlengsz : 14;   /**< Data length / Gather list size */
71        uint64_t            fsz     : 6;    /**< Front data size */
72        uint64_t            qos     : 3;    /**< POW QoS queue */
73        uint64_t            grp     : 4;    /**< POW Group */
74        uint64_t            rs      : 1;    /**< Real short */
75        cvmx_pow_tag_type_t tt      : 2;    /**< POW Tag type */
76        uint64_t            tag     : 32;   /**< POW 32 bit tag */
77#else
78	uint64_t            tag     : 32;
79	cvmx_pow_tag_type_t tt      : 2;
80	uint64_t            rs      : 1;
81	uint64_t            grp     : 4;
82	uint64_t            qos     : 3;
83	uint64_t            fsz     : 6;
84	uint64_t            dlengsz : 14;
85	uint64_t            g :     1;
86	uint64_t            r :     1;
87#endif
88    } s;
89} cvmx_npi_inst_hdr_t;
90
91/**
92 * PCI / PCIe packet data pointer formats 0-3
93 */
94typedef union
95{
96    uint64_t dptr0;
97    struct
98    {
99#if __BYTE_ORDER == __BIG_ENDIAN
100        uint64_t    es      : 2;    /**< Endian swap mode */
101        uint64_t    ns      : 1;    /**< No snoop */
102        uint64_t    ro      : 1;    /**< Relaxed ordering */
103        uint64_t    addr    : 60;   /**< PCI/PCIe address */
104#else
105        uint64_t    addr    : 60;
106        uint64_t    ro      : 1;
107        uint64_t    ns      : 1;
108        uint64_t    es      : 2;
109#endif
110    } dptr1;
111    struct
112    {
113#if __BYTE_ORDER == __BIG_ENDIAN
114        uint64_t    pm      : 2;    /**< Parse mode */
115        uint64_t    sl      : 7;    /**< Skip length */
116        uint64_t    addr    : 55;   /**< PCI/PCIe address */
117#else
118        uint64_t    addr    : 55;
119        uint64_t    sl      : 7;
120        uint64_t    pm      : 2;
121#endif
122    } dptr2;
123    struct
124    {
125#if __BYTE_ORDER == __BIG_ENDIAN
126        uint64_t    es      : 2;    /**< Endian swap mode */
127        uint64_t    ns      : 1;    /**< No snoop */
128        uint64_t    ro      : 1;    /**< Relaxed ordering */
129        uint64_t    pm      : 2;    /**< Parse mode */
130        uint64_t    sl      : 7;    /**< Skip length */
131        uint64_t    addr    : 51;   /**< PCI/PCIe address */
132#else
133        uint64_t    addr    : 51;
134        uint64_t    sl      : 7;
135        uint64_t    pm      : 2;
136        uint64_t    ro      : 1;
137        uint64_t    ns      : 1;
138        uint64_t    es      : 2;
139#endif
140    } dptr3;
141} cvmx_npi_dptr_t;
142
143#ifdef	__cplusplus
144}
145#endif
146
147#endif  /* __CVMX_NPI_H__ */
148