1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Inc. nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * @file 43 * 44 * Interface to debug exception handler 45 * 46 * <hr>$Revision: $<hr> 47 */ 48 49#ifndef __CVMX_DEBUG_H__ 50#define __CVMX_DEBUG_H__ 51 52#include "cvmx-core.h" 53#include "cvmx-spinlock.h" 54 55 56#define CVMX_DEBUG_MAX_REQUEST_SIZE 1024 + 34 /* Enough room for setting memory of 512 bytes. */ 57#define CVMX_DEBUG_MAX_RESPONSE_SIZE 1024 + 5 58 59#define CVMX_DEBUG_GLOBALS_BLOCK_NAME "cvmx-debug-globals" 60#define CVMX_DEBUG_GLOBALS_VERSION 3 61 62#ifdef __cplusplus 63extern "C" { 64#endif 65 66void cvmx_debug_init(void); 67void cvmx_debug_finish(void); 68void cvmx_debug_trigger_exception(void); 69 70#ifdef CVMX_BUILD_FOR_TOOLCHAIN 71extern int __octeon_debug_booted; 72 73static inline int cvmx_debug_booted(void) 74{ 75 return __octeon_debug_booted; 76} 77 78#else 79 80static inline int cvmx_debug_booted(void) 81{ 82 return cvmx_sysinfo_get()->bootloader_config_flags & CVMX_BOOTINFO_CFG_FLAG_DEBUG; 83} 84#endif 85 86/* There are 64 TLB entries in CN5XXX and 32 TLB entries in CN3XXX and 87 128 TLB entries in CN6XXX. */ 88#define CVMX_DEBUG_N_TLB_ENTRIES 128 89 90/* Maximium number of hardware breakpoints/watchpoints allowed */ 91#define CVMX_DEBUG_MAX_OCTEON_HW_BREAKPOINTS 4 92 93typedef struct 94{ 95 volatile uint64_t remote_controlled; 96 uint64_t regs[32]; 97 uint64_t lo; 98 uint64_t hi; 99 100#define CVMX_DEBUG_BASIC_CONTEXT \ 101 F(remote_controlled); \ 102 { int i; \ 103 for (i = 0; i < 32; i++) \ 104 F(regs[i]); \ 105 } \ 106 F(lo); \ 107 F(hi); 108 109 struct { 110 uint64_t index; 111 uint64_t entrylo[2]; 112 uint64_t entryhi; 113 uint64_t pagemask; 114 uint64_t status; 115 uint64_t badvaddr; 116 uint64_t cause; 117 uint64_t depc; 118 uint64_t desave; 119 uint64_t debug; 120 uint64_t multicoredebug; 121 uint64_t perfval[2]; 122 uint64_t perfctrl[2]; 123 } cop0; 124 125#define CVMX_DEBUG_COP0_CONTEXT \ 126 F(cop0.index); \ 127 F(cop0.entrylo[0]); \ 128 F(cop0.entrylo[1]); \ 129 F(cop0.entryhi); \ 130 F(cop0.pagemask); \ 131 F(cop0.status); \ 132 F(cop0.badvaddr); \ 133 F(cop0.cause); \ 134 F(cop0.depc); \ 135 F(cop0.desave); \ 136 F(cop0.debug); \ 137 F(cop0.multicoredebug); \ 138 F(cop0.perfval[0]); \ 139 F(cop0.perfval[1]); \ 140 F(cop0.perfctrl[0]); \ 141 F(cop0.perfctrl[1]); 142 143 struct 144 { 145 uint64_t status; 146 uint64_t address[4]; 147 uint64_t address_mask[4]; 148 uint64_t asid[4]; 149 uint64_t control[4]; 150 } hw_ibp, hw_dbp; 151 152/* Hardware Instruction Break Point */ 153 154#define CVMX_DEBUG_HW_IBP_CONTEXT \ 155 F(hw_ibp.status); \ 156 F(hw_ibp.address[0]); \ 157 F(hw_ibp.address[1]); \ 158 F(hw_ibp.address[2]); \ 159 F(hw_ibp.address[3]); \ 160 F(hw_ibp.address_mask[0]); \ 161 F(hw_ibp.address_mask[1]); \ 162 F(hw_ibp.address_mask[2]); \ 163 F(hw_ibp.address_mask[3]); \ 164 F(hw_ibp.asid[0]); \ 165 F(hw_ibp.asid[1]); \ 166 F(hw_ibp.asid[2]); \ 167 F(hw_ibp.asid[3]); \ 168 F(hw_ibp.control[0]); \ 169 F(hw_ibp.control[1]); \ 170 F(hw_ibp.control[2]); \ 171 F(hw_ibp.control[3]); 172 173/* Hardware Data Break Point */ 174#define CVMX_DEBUG_HW_DBP_CONTEXT \ 175 F(hw_dbp.status); \ 176 F(hw_dbp.address[0]); \ 177 F(hw_dbp.address[1]); \ 178 F(hw_dbp.address[2]); \ 179 F(hw_dbp.address[3]); \ 180 F(hw_dbp.address_mask[0]); \ 181 F(hw_dbp.address_mask[1]); \ 182 F(hw_dbp.address_mask[2]); \ 183 F(hw_dbp.address_mask[3]); \ 184 F(hw_dbp.asid[0]); \ 185 F(hw_dbp.asid[1]); \ 186 F(hw_dbp.asid[2]); \ 187 F(hw_dbp.asid[3]); \ 188 F(hw_dbp.control[0]); \ 189 F(hw_dbp.control[1]); \ 190 F(hw_dbp.control[2]); \ 191 F(hw_dbp.control[3]); 192 193 194 struct cvmx_debug_tlb_t 195 { 196 uint64_t entryhi; 197 uint64_t pagemask; 198 uint64_t entrylo[2]; 199 uint64_t reserved; 200 } tlbs[CVMX_DEBUG_N_TLB_ENTRIES]; 201 202#define CVMX_DEBUG_TLB_CONTEXT \ 203 { int i; \ 204 for (i = 0; i < CVMX_DEBUG_N_TLB_ENTRIES; i++) \ 205 { \ 206 F(tlbs[i].entryhi); \ 207 F(tlbs[i].pagemask); \ 208 F(tlbs[i].entrylo[0]); \ 209 F(tlbs[i].entrylo[1]); \ 210 } \ 211 } 212 213} cvmx_debug_core_context_t; 214 215typedef struct cvmx_debug_tlb_t cvmx_debug_tlb_t; 216 217 218 219typedef enum cvmx_debug_comm_type_e 220{ 221 COMM_UART, 222 COMM_REMOTE, 223 COMM_SIZE 224}cvmx_debug_comm_type_t; 225 226typedef enum 227{ 228 COMMAND_NOP = 0, /**< Core doesn't need to do anything. Just stay in exception handler */ 229 COMMAND_STEP, /**< Core needs to perform a single instruction step */ 230 COMMAND_CONTINUE /**< Core need to start running. Doesn't return until some debug event occurs */ 231} cvmx_debug_command_t; 232 233/* Every field in this struct has to be uint32_t. */ 234typedef struct 235{ 236 uint32_t known_cores; 237 uint32_t step_isr; /**< True if we are going to step into ISR's. */ 238 uint32_t focus_switch; /**< Focus can be switched. */ 239 uint32_t core_finished; /**< True if a core has finished and not been processed yet. */ 240 uint32_t command; /**< Command for all cores (cvmx_debug_command_t) */ 241 uint32_t step_all; /**< True if step and continue should affect all cores. False, only the focus core is affected */ 242 uint32_t focus_core; /**< Core currently under control of the debugger */ 243 uint32_t active_cores; /**< Bitmask of cores that should stop on a breakpoint */ 244 uint32_t handler_cores; /**< Bitmask of cores currently running the exception handler */ 245 uint32_t ever_been_in_debug; /**< True if we have been ever been in the debugger stub at all. */ 246}__attribute__ ((aligned(sizeof(uint64_t)))) cvmx_debug_state_t; 247 248typedef int cvmx_debug_state_t_should_fit_inside_a_cache_block[sizeof(cvmx_debug_state_t)+sizeof(cvmx_spinlock_t)+4*sizeof(uint64_t) > 128 ? -1 : 1]; 249 250typedef struct cvmx_debug_globals_s 251{ 252 uint64_t version; /* This is always the first element of this struct */ 253 uint64_t comm_type; /* cvmx_debug_comm_type_t */ 254 volatile uint64_t comm_changed; /* cvmx_debug_comm_type_t+1 when someone wants to change it. */ 255 volatile uint64_t init_complete; 256 uint32_t tlb_entries; 257 uint32_t state[sizeof(cvmx_debug_state_t)/sizeof(uint32_t)]; 258 cvmx_spinlock_t lock; 259 260 volatile cvmx_debug_core_context_t contextes[CVMX_MAX_CORES]; 261} cvmx_debug_globals_t; 262 263typedef union 264{ 265 uint64_t u64; 266 struct 267 { 268 uint64_t rsrvd:32; /**< Unused */ 269 uint64_t dbd:1; /**< Indicates whether the last debug exception or 270 exception in Debug Mode occurred in a branch or 271 jump delay slot */ 272 uint64_t dm:1; /**< Indicates that the processor is operating in Debug 273 Mode: */ 274 uint64_t nodcr:1; /**< Indicates whether the dseg segment is present */ 275 uint64_t lsnm:1; /**< Controls access of loads/stores between the dseg 276 segment and remaining memory when the dseg 277 segment is present */ 278 uint64_t doze:1; /**< Indicates that the processor was in a low-power mode 279 when a debug exception occurred */ 280 uint64_t halt:1; /**< Indicates that the internal processor system bus clock 281 was stopped when the debug exception occurred */ 282 uint64_t countdm:1; /**< Controls or indicates the Count register behavior in 283 Debug Mode. Implementations can have fixed 284 behavior, in which case this bit is read-only (R), or 285 the implementation can allow this bit to control the 286 behavior, in which case this bit is read/write (R/W). 287 The reset value of this bit indicates the behavior after 288 reset, and depends on the implementation. 289 Encoding of the bit is: 290 - 0 Count register stopped in Debug Mode Count register is running in Debug 291 - 1 Mode 292 This bit is read-only (R) and reads as zero if not implemented. */ 293 uint64_t ibusep:1; /**< Indicates if a Bus Error exception is pending from an 294 instruction fetch. Set when an instruction fetch bus 295 error event occurs or a 1 is written to the bit by 296 software. Cleared when a Bus Error exception on an 297 instruction fetch is taken by the processor. If IBusEP 298 is set when IEXI is cleared, a Bus Error exception on 299 an instruction fetch is taken by the processor, and 300 IBusEP is cleared. 301 In Debug Mode, a Bus Error exception applies to a 302 Debug Mode Bus Error exception. 303 This bit is read-only (R) and reads as zero if not 304 implemented. */ 305 uint64_t mcheckp:1; /**< Indicates if a Machine Check exception is pending. 306 Set when a machine check event occurs or a 1 is 307 written to the bit by software. Cleared when a 308 Machine Check exception is taken by the processor. 309 If MCheckP is set when IEXI is cleared, a Machine 310 Check exception is taken by the processor, and 311 MCheckP is cleared. 312 In Debug Mode, a Machine Check exception applies 313 to a Debug Mode Machine Check exception. 314 This bit is read-only (R) and reads as zero if not 315 implemented. */ 316 uint64_t cacheep:1; /**< Indicates if a Cache Error is pending. Set when a 317 cache error event occurs or a 1 is written to the bit by 318 software. Cleared when a Cache Error exception is 319 taken by the processor. If CacheEP is set when IEXI 320 is cleared, a Cache Error exception is taken by the 321 processor, and CacheEP is cleared. 322 In Debug Mode, a Cache Error exception applies to a 323 Debug Mode Cache Error exception. 324 This bit is read-only (R) and reads as zero if not 325 implemented. */ 326 uint64_t dbusep:1; /**< Indicates if a Data Access Bus Error exception is 327 pending. Set when a data access bus error event 328 occurs or a 1 is written to the bit by software. Cleared 329 when a Bus Error exception on data access is taken by 330 the processor. If DBusEP is set when IEXI is cleared, 331 a Bus Error exception on data access is taken by the 332 processor, and DBusEP is cleared. 333 In Debug Mode, a Bus Error exception applies to a 334 Debug Mode Bus Error exception. 335 This bit is read-only (R) and reads as zero if not 336 implemented. */ 337 uint64_t iexi:1; /**< An Imprecise Error eXception Inhibit (IEXI) controls 338 exceptions taken due to imprecise error indications. 339 Set when the processor takes a debug exception or an 340 exception in Debug Mode occurs. Cleared by 341 execution of the DERET instruction. Otherwise 342 modifiable by Debug Mode software. 343 When IEXI is set, then the imprecise error exceptions 344 from bus errors on instruction fetches or data 345 accesses, cache errors, or machine checks are 346 inhibited and deferred until the bit is cleared. 347 This bit is read-only (R) and reads as zero if not 348 implemented. */ 349 uint64_t ddbsimpr:1; /**< Indicates that a Debug Data Break Store Imprecise 350 exception due to a store was the cause of the debug 351 exception, or that an imprecise data hardware break 352 due to a store was indicated after another debug 353 exception occurred. Cleared on exception in Debug 354 Mode. 355 - 0 No match of an imprecise data hardware breakpoint on store 356 - 1 Match of imprecise data hardware breakpoint on store 357 This bit is read-only (R) and reads as zero if not 358 implemented. */ 359 uint64_t ddblimpr:1; /**< Indicates that a Debug Data Break Load Imprecise 360 exception due to a load was the cause of the debug 361 exception, or that an imprecise data hardware break 362 due to a load was indicated after another debug 363 exception occurred. Cleared on exception in Debug 364 Mode. 365 - 0 No match of an imprecise data hardware breakpoint on load 366 - 1 Match of imprecise data hardware breakpoint on load 367 This bit is read-only (R) and reads as zero if not 368 implemented. */ 369 uint64_t ejtagver:3; /**< Provides the EJTAG version. 370 - 0 Version 1 and 2.0 371 - 1 Version 2.5 372 - 2 Version 2.6 373 - 3-7 Reserved */ 374 uint64_t dexccode:5; /**< Indicates the cause of the latest exception in Debug 375 Mode. 376 The field is encoded as the ExcCode field in the 377 Cause register for those exceptions that can occur in 378 Debug Mode (the encoding is shown in MIPS32 and 379 MIPS64 specifications), with addition of code 30 380 with the mnemonic CacheErr for cache errors and the 381 use of code 9 with mnemonic Bp for the SDBBP 382 instruction. 383 This value is undefined after a debug exception. */ 384 uint64_t nosst:1; /**< Indicates whether the single-step feature controllable 385 by the SSt bit is available in this implementation: 386 - 0 Single-step feature available 387 - 1 No single-step feature available 388 A minimum number of hardware instruction 389 breakpoints must be available if no single-step 390 feature is implemented in hardware. Refer to Section 391 4.8.1 on page 69 for more information. */ 392 uint64_t sst:1; /**< Controls whether single-step feature is enabled: 393 - 0 No enable of single-step feature 394 - 1 Single-step feature enabled 395 This bit is read-only (R) and reads as zero if not 396 implemented due to no single-step feature (NoSSt is 397 1). */ 398 uint64_t rsrvd2:2; /**< Must be zero */ 399 uint64_t dint:1; /**< Indicates that a Debug Interrupt exception occurred. 400 Cleared on exception in Debug Mode. 401 - 0 No Debug Interrupt exception 402 - 1 Debug Interrupt exception 403 This bit is read-only (R) and reads as zero if not 404 implemented. */ 405 uint64_t dib:1; /**< Indicates that a Debug Instruction Break exception 406 occurred. Cleared on exception in Debug Mode. 407 - 0 No Debug Instruction Break exception 408 - 1 Debug Instruction Break exception 409 This bit is read-only (R) and reads as zero if not 410 implemented. */ 411 uint64_t ddbs:1; /**< Indicates that a Debug Data Break Store exception 412 occurred on a store due to a precise data hardware 413 break. Cleared on exception in Debug Mode. 414 - 0 No Debug Data Break Store Exception 415 - 1 Debug Data Break Store Exception 416 This bit is read-only (R) and reads as zero if not 417 implemented. */ 418 uint64_t ddbl:1; /**< Indicates that a Debug Data Break Load exception 419 occurred on a load due to a precise data hardware 420 break. Cleared on exception in Debug Mode. 421 - 0 No Debug Data Break Store Exception 422 - 1 Debug Data Break Store Exception 423 This bit is read-only (R) and reads as zero if not 424 implemented. */ 425 uint64_t dbp:1; /**< Indicates that a Debug Breakpoint exception 426 occurred. Cleared on exception in Debug Mode. 427 - 0 No Debug Breakpoint exception 428 - 1 Debug Breakpoint exception */ 429 uint64_t dss:1; /**< Indicates that a Debug Single Step exception 430 occurred. Cleared on exception in Debug Mode. 431 - 0 No debug single-step exception 432 - 1 Debug single-step exception 433 This bit is read-only (R) and reads as zero if not 434 implemented. */ 435 } s; 436} cvmx_debug_register_t; 437 438 439typedef struct 440{ 441 void (*init)(void); 442 void (*install_break_handler)(void); 443 int needs_proxy; 444 int (*getpacket)(char *, size_t); 445 int (*putpacket)(char *); 446 void (*wait_for_resume)(volatile cvmx_debug_core_context_t *, cvmx_debug_state_t); 447 void (*change_core)(int, int); 448} cvmx_debug_comm_t; 449 450#ifdef __cplusplus 451} 452#endif 453 454#endif /* __CVMX_DEBUG_H__ */ 455