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MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41 42 43 44 45 46/** 47 * @file 48 * Definitions for enumerations used with Octeon CSRs. 49 * 50 * <hr>$Revision: 70030 $<hr> 51 * 52 */ 53#ifndef __CVMX_CSR_ENUMS_H__ 54#define __CVMX_CSR_ENUMS_H__ 55 56typedef enum { 57 CVMX_IPD_OPC_MODE_STT = 0LL, /* All blocks DRAM, not cached in L2 */ 58 CVMX_IPD_OPC_MODE_STF = 1LL, /* All blocks into L2 */ 59 CVMX_IPD_OPC_MODE_STF1_STT = 2LL, /* 1st block L2, rest DRAM */ 60 CVMX_IPD_OPC_MODE_STF2_STT = 3LL /* 1st, 2nd blocks L2, rest DRAM */ 61} cvmx_ipd_mode_t; 62 63 64/** 65 * Enumeration representing the amount of packet processing 66 * and validation performed by the input hardware. 67 */ 68typedef enum 69{ 70 CVMX_PIP_PORT_CFG_MODE_NONE = 0ull, /**< Packet input doesn't perform any 71 processing of the input packet. */ 72 CVMX_PIP_PORT_CFG_MODE_SKIPL2 = 1ull,/**< Full packet processing is performed 73 with pointer starting at the L2 74 (ethernet MAC) header. */ 75 CVMX_PIP_PORT_CFG_MODE_SKIPIP = 2ull /**< Input packets are assumed to be IP. 76 Results from non IP packets is 77 undefined. Pointers reference the 78 beginning of the IP header. */ 79} cvmx_pip_port_parse_mode_t; 80 81 82/** 83 * This enumeration controls how a QoS watcher matches a packet. 84 * 85 * @deprecated This enumeration was used with cvmx_pip_config_watcher which has 86 * been deprecated. 87 */ 88typedef enum 89{ 90 CVMX_PIP_QOS_WATCH_DISABLE = 0ull, /**< QoS watcher is diabled */ 91 CVMX_PIP_QOS_WATCH_PROTNH = 1ull, /**< QoS watcher will match based on the IP protocol */ 92 CVMX_PIP_QOS_WATCH_TCP = 2ull, /**< QoS watcher will match TCP packets to a specific destination port */ 93 CVMX_PIP_QOS_WATCH_UDP = 3ull /**< QoS watcher will match UDP packets to a specific destination port */ 94} cvmx_pip_qos_watch_types; 95 96/** 97 * This enumeration is used in PIP tag config to control how 98 * POW tags are generated by the hardware. 99 */ 100typedef enum 101{ 102 CVMX_PIP_TAG_MODE_TUPLE = 0ull, /**< Always use tuple tag algorithm. This is the only mode supported on Pass 1 */ 103 CVMX_PIP_TAG_MODE_MASK = 1ull, /**< Always use mask tag algorithm */ 104 CVMX_PIP_TAG_MODE_IP_OR_MASK = 2ull, /**< If packet is IP, use tuple else use mask */ 105 CVMX_PIP_TAG_MODE_TUPLE_XOR_MASK = 3ull /**< tuple XOR mask */ 106} cvmx_pip_tag_mode_t; 107 108/** 109 * Tag type definitions 110 */ 111typedef enum 112{ 113 CVMX_POW_TAG_TYPE_ORDERED = 0L, /**< Tag ordering is maintained */ 114 CVMX_POW_TAG_TYPE_ATOMIC = 1L, /**< Tag ordering is maintained, and at most one PP has the tag */ 115 CVMX_POW_TAG_TYPE_NULL = 2L, /**< The work queue entry from the order 116 - NEVER tag switch from NULL to NULL */ 117 CVMX_POW_TAG_TYPE_NULL_NULL = 3L /**< A tag switch to NULL, and there is no space reserved in POW 118 - NEVER tag switch to NULL_NULL 119 - NEVER tag switch from NULL_NULL 120 - NULL_NULL is entered at the beginning of time and on a deschedule. 121 - NULL_NULL can be exited by a new work request. A NULL_SWITCH load can also switch the state to NULL */ 122} cvmx_pow_tag_type_t; 123 124 125/** 126 * LCR bits 0 and 1 control the number of bits per character. See the following table for encodings: 127 * 128 * - 00 = 5 bits (bits 0-4 sent) 129 * - 01 = 6 bits (bits 0-5 sent) 130 * - 10 = 7 bits (bits 0-6 sent) 131 * - 11 = 8 bits (all bits sent) 132 */ 133typedef enum 134{ 135 CVMX_UART_BITS5 = 0, 136 CVMX_UART_BITS6 = 1, 137 CVMX_UART_BITS7 = 2, 138 CVMX_UART_BITS8 = 3 139} cvmx_uart_bits_t; 140 141 142/** 143 * Interrupt Priority Interrupt Interrupt Interrupt 144 * ID Level Type Source Reset By 145 * --------------------------------------------------------------------------------------------------------------------------------- 146 * 0001 - None None - 147 * 148 * 0110 Highest Receiver Line Overrun, parity, or framing errors or break Reading the Line Status Register 149 * Status interrupt 150 * 151 * 0100 Second Received Data Receiver data available (FIFOs disabled) or Reading the Receiver Buffer Register 152 * Available RX FIFO trigger level reached (FIFOs (FIFOs disabled) or the FIFO drops below 153 * enabled) the trigger level (FIFOs enabled) 154 * 155 * 1100 Second Character No characters in or out of the RX FIFO Reading the Receiver Buffer Register 156 * Timeout during the last 4 character times and there 157 * Indication is at least 1 character in it during this 158 * time 159 * 160 * 0010 Third Transmitter Transmitter Holding Register Empty Reading the Interrupt Identity Register 161 * Holding (Programmable THRE Mode disabled) or TX (if source of interrupt) or writing into 162 * Register FIFO at or below threshold (Programmable THR (FIFOs or THRE Mode disabled) or TX 163 * Empty THRE Mode enabled) FIFO above threshold (FIFOs and THRE 164 * Mode enabled) 165 * 166 * 0000 Fourth Modem Status Clear To Send (CTS) or Data Set Ready (DSR) Reading the Modem Status Register 167 * Changed or Ring Indicator (RI) or Data Center 168 * Detect (DCD) changed 169 * 170 * 0111 Fifth Busy Detect Software has tried to write to the Line Reading the UART Status Register 171 * Indication Control Register while the BUSY bit of the 172 * UART Status Register was set 173 */ 174typedef enum 175{ 176 CVMX_UART_IID_NONE = 1, 177 CVMX_UART_IID_RX_ERROR = 6, 178 CVMX_UART_IID_RX_DATA = 4, 179 CVMX_UART_IID_RX_TIMEOUT = 12, 180 CVMX_UART_IID_TX_EMPTY = 2, 181 CVMX_UART_IID_MODEM = 0, 182 CVMX_UART_IID_BUSY = 7 183} cvmx_uart_iid_t; 184 185#endif /* __CVMX_CSR_ENUMS_H__ */ 186