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39
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44
45
46/**
47 * @file
48 *
49 * Module to support operations on core such as TLB config, etc.
50 *
51 * <hr>$Revision: 70030 $<hr>
52 *
53 */
54
55#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
56#include <linux/module.h>
57#include <asm/octeon/cvmx.h>
58#include <asm/octeon/cvmx-core.h>
59#else
60#include "cvmx-config.h"
61#include "cvmx.h"
62#include "cvmx-core.h"
63#endif
64
65
66/**
67 * Adds a wired TLB entry, and returns the index of the entry added.
68 * Parameters are written to TLB registers without further processing.
69 *
70 * @param hi     HI register value
71 * @param lo0    lo0 register value
72 * @param lo1    lo1 register value
73 * @param page_mask   pagemask register value
74 *
75 * @return Success: TLB index used (0-31 Octeon, 0-63 Octeon+, or 0-127
76 *         Octeon2). Failure: -1
77 */
78int cvmx_core_add_wired_tlb_entry(uint64_t hi, uint64_t lo0, uint64_t lo1, cvmx_tlb_pagemask_t page_mask)
79{
80    uint32_t index;
81
82    CVMX_MF_TLB_WIRED(index);
83    if (index >= (unsigned int)cvmx_core_get_tlb_entries())
84    {
85        return(-1);
86    }
87    CVMX_MT_ENTRY_HIGH(hi);
88    CVMX_MT_ENTRY_LO_0(lo0);
89    CVMX_MT_ENTRY_LO_1(lo1);
90    CVMX_MT_PAGEMASK(page_mask);
91    CVMX_MT_TLB_INDEX(index);
92    CVMX_MT_TLB_WIRED(index + 1);
93    CVMX_EHB;
94    CVMX_TLBWI;
95    CVMX_EHB;
96    return(index);
97}
98
99
100
101/**
102 * Adds a fixed (wired) TLB mapping.  Returns TLB index used or -1 on error.
103 * This is a wrapper around cvmx_core_add_wired_tlb_entry()
104 *
105 * @param vaddr      Virtual address to map
106 * @param page0_addr page 0 physical address, with low 3 bits representing the DIRTY, VALID, and GLOBAL bits
107 * @param page1_addr page1 physical address, with low 3 bits representing the DIRTY, VALID, and GLOBAL bits
108 * @param page_mask  page mask.
109 *
110 * @return Success: TLB index used (0-31)
111 *         Failure: -1
112 */
113int cvmx_core_add_fixed_tlb_mapping_bits(uint64_t vaddr, uint64_t page0_addr, uint64_t page1_addr, cvmx_tlb_pagemask_t page_mask)
114{
115
116    if ((vaddr & (page_mask | 0x7ff))
117        || ((page0_addr & ~0x7ULL) & ((page_mask | 0x7ff) >> 1))
118        || ((page1_addr & ~0x7ULL) & ((page_mask | 0x7ff) >> 1)))
119    {
120        cvmx_dprintf("Error adding tlb mapping: invalid address alignment at vaddr: 0x%llx\n", (unsigned long long)vaddr);
121        return(-1);
122    }
123
124
125    return(cvmx_core_add_wired_tlb_entry(vaddr,
126                                         (page0_addr >> 6) | (page0_addr & 0x7),
127                                         (page1_addr >> 6) | (page1_addr & 0x7),
128                                         page_mask));
129
130}
131/**
132 * Adds a fixed (wired) TLB mapping.  Returns TLB index used or -1 on error.
133 * Assumes both pages are valid.  Use cvmx_core_add_fixed_tlb_mapping_bits for more control.
134 * This is a wrapper around cvmx_core_add_wired_tlb_entry()
135 *
136 * @param vaddr      Virtual address to map
137 * @param page0_addr page 0 physical address
138 * @param page1_addr page1 physical address
139 * @param page_mask  page mask.
140 *
141 * @return Success: TLB index used (0-31)
142 *         Failure: -1
143 */
144int cvmx_core_add_fixed_tlb_mapping(uint64_t vaddr, uint64_t page0_addr, uint64_t page1_addr, cvmx_tlb_pagemask_t page_mask)
145{
146
147    return(cvmx_core_add_fixed_tlb_mapping_bits(vaddr, page0_addr | TLB_DIRTY | TLB_VALID | TLB_GLOBAL, page1_addr | TLB_DIRTY | TLB_VALID | TLB_GLOBAL, page_mask));
148
149}
150
151/**
152 * Return number of TLB entries.
153 */
154int cvmx_core_get_tlb_entries(void)
155{
156    if (OCTEON_IS_MODEL(OCTEON_CN3XXX))
157        return 32;
158    else if (OCTEON_IS_MODEL(OCTEON_CN5XXX))
159        return 64;
160    else
161        return 128;
162}
163