cvmx-address.h revision 210284 
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38
39/**
40 * @file
41 * Typedefs and defines for working with Octeon physical addresses.
42 *
43 * <hr>$Revision: 38306 $<hr>
44*/
45#ifndef __CVMX_ADDRESS_H__
46#define __CVMX_ADDRESS_H__
47
48#ifdef	__cplusplus
49extern "C" {
50#endif
51
52typedef enum {
53   CVMX_MIPS_SPACE_XKSEG = 3LL,
54   CVMX_MIPS_SPACE_XKPHYS = 2LL,
55   CVMX_MIPS_SPACE_XSSEG = 1LL,
56   CVMX_MIPS_SPACE_XUSEG = 0LL
57} cvmx_mips_space_t;
58
59typedef enum {
60   CVMX_MIPS_XKSEG_SPACE_KSEG0 = 0LL,
61   CVMX_MIPS_XKSEG_SPACE_KSEG1 = 1LL,
62   CVMX_MIPS_XKSEG_SPACE_SSEG = 2LL,
63   CVMX_MIPS_XKSEG_SPACE_KSEG3 = 3LL
64} cvmx_mips_xkseg_space_t;
65
66// decodes <14:13> of a kseg3 window address
67typedef enum {
68   CVMX_ADD_WIN_SCR = 0L,
69   CVMX_ADD_WIN_DMA = 1L,   // see cvmx_add_win_dma_dec_t for further decode
70   CVMX_ADD_WIN_UNUSED = 2L,
71   CVMX_ADD_WIN_UNUSED2 = 3L
72} cvmx_add_win_dec_t;
73
74// decode within DMA space
75typedef enum {
76   CVMX_ADD_WIN_DMA_ADD = 0L,     // add store data to the write buffer entry, allocating it if necessary
77   CVMX_ADD_WIN_DMA_SENDMEM = 1L, // send out the write buffer entry to DRAM
78                                     // store data must be normal DRAM memory space address in this case
79   CVMX_ADD_WIN_DMA_SENDDMA = 2L, // send out the write buffer entry as an IOBDMA command
80                                     // see CVMX_ADD_WIN_DMA_SEND_DEC for data contents
81   CVMX_ADD_WIN_DMA_SENDIO = 3L,  // send out the write buffer entry as an IO write
82                                     // store data must be normal IO space address in this case
83   CVMX_ADD_WIN_DMA_SENDSINGLE = 4L, // send out a single-tick command on the NCB bus
84                                        // no write buffer data needed/used
85} cvmx_add_win_dma_dec_t;
86
87
88
89/**
90 *   Physical Address Decode
91 *
92 * Octeon-I HW never interprets this X (<39:36> reserved
93 * for future expansion), software should set to 0.
94 *
95 *  - 0x0 XXX0 0000 0000 to      DRAM         Cached
96 *  - 0x0 XXX0 0FFF FFFF
97 *
98 *  - 0x0 XXX0 1000 0000 to      Boot Bus     Uncached  (Converted to 0x1 00X0 1000 0000
99 *  - 0x0 XXX0 1FFF FFFF         + EJTAG                           to 0x1 00X0 1FFF FFFF)
100 *
101 *  - 0x0 XXX0 2000 0000 to      DRAM         Cached
102 *  - 0x0 XXXF FFFF FFFF
103 *
104 *  - 0x1 00X0 0000 0000 to      Boot Bus     Uncached
105 *  - 0x1 00XF FFFF FFFF
106 *
107 *  - 0x1 01X0 0000 0000 to      Other NCB    Uncached
108 *  - 0x1 FFXF FFFF FFFF         devices
109 *
110 * Decode of all Octeon addresses
111 */
112typedef union {
113
114   uint64_t         u64;
115
116   struct {
117      cvmx_mips_space_t          R   : 2;
118      uint64_t               offset :62;
119   } sva; // mapped or unmapped virtual address
120
121   struct {
122      uint64_t               zeroes :33;
123      uint64_t               offset :31;
124   } suseg; // mapped USEG virtual addresses (typically)
125
126   struct {
127      uint64_t                ones  :33;
128      cvmx_mips_xkseg_space_t   sp   : 2;
129      uint64_t               offset :29;
130   } sxkseg; // mapped or unmapped virtual address
131
132   struct {
133      cvmx_mips_space_t          R   : 2; // CVMX_MIPS_SPACE_XKPHYS in this case
134      uint64_t                 cca  : 3; // ignored by octeon
135      uint64_t                 mbz  :10;
136      uint64_t                  pa  :49; // physical address
137   } sxkphys; // physical address accessed through xkphys unmapped virtual address
138
139   struct {
140      uint64_t                 mbz  :15;
141      uint64_t                is_io : 1; // if set, the address is uncached and resides on MCB bus
142      uint64_t                 did  : 8; // the hardware ignores this field when is_io==0, else device ID
143      uint64_t                unaddr: 4; // the hardware ignores <39:36> in Octeon I
144      uint64_t               offset :36;
145   } sphys; // physical address
146
147   struct {
148      uint64_t               zeroes :24; // techically, <47:40> are dont-cares
149      uint64_t                unaddr: 4; // the hardware ignores <39:36> in Octeon I
150      uint64_t               offset :36;
151   } smem; // physical mem address
152
153   struct {
154      uint64_t                 mem_region  :2;
155      uint64_t                 mbz  :13;
156      uint64_t                is_io : 1; // 1 in this case
157      uint64_t                 did  : 8; // the hardware ignores this field when is_io==0, else device ID
158      uint64_t                unaddr: 4; // the hardware ignores <39:36> in Octeon I
159      uint64_t               offset :36;
160   } sio; // physical IO address
161
162   struct {
163      uint64_t                ones   : 49;
164      cvmx_add_win_dec_t   csrdec : 2;    // CVMX_ADD_WIN_SCR (0) in this case
165      uint64_t                addr   : 13;
166   } sscr; // scratchpad virtual address - accessed through a window at the end of kseg3
167
168   // there should only be stores to IOBDMA space, no loads
169   struct {
170      uint64_t                ones   : 49;
171      cvmx_add_win_dec_t   csrdec : 2;    // CVMX_ADD_WIN_DMA (1) in this case
172      uint64_t                unused2: 3;
173      cvmx_add_win_dma_dec_t type : 3;
174      uint64_t                addr   : 7;
175   } sdma; // IOBDMA virtual address - accessed through a window at the end of kseg3
176
177   struct {
178      uint64_t                didspace : 24;
179      uint64_t                unused   : 40;
180   } sfilldidspace;
181
182} cvmx_addr_t;
183
184/* These macros for used by 32 bit applications */
185
186#define CVMX_MIPS32_SPACE_KSEG0 1l
187#define CVMX_ADD_SEG32(segment, add)          (((int32_t)segment << 31) | (int32_t)(add))
188
189/* Currently all IOs are performed using XKPHYS addressing. Linux uses the
190    CvmMemCtl register to enable XKPHYS addressing to IO space from user mode.
191    Future OSes may need to change the upper bits of IO addresses. The
192    following define controls the upper two bits for all IO addresses generated
193    by the simple executive library */
194#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS
195
196/* These macros simplify the process of creating common IO addresses */
197#define CVMX_ADD_SEG(segment, add)          ((((uint64_t)segment) << 62) | (add))
198#ifndef CVMX_ADD_IO_SEG
199#define CVMX_ADD_IO_SEG(add)                CVMX_ADD_SEG(CVMX_IO_SEG, (add))
200#endif
201#define CVMX_ADDR_DIDSPACE(did)             (((CVMX_IO_SEG) << 22) | ((1ULL) << 8) | (did))
202#define CVMX_ADDR_DID(did)                  (CVMX_ADDR_DIDSPACE(did) << 40)
203#define CVMX_FULL_DID(did,subdid)           (((did) << 3) | (subdid))
204
205
206// from include/ncb_rsl_id.v
207#define CVMX_OCT_DID_MIS 0ULL   // misc stuff
208#define CVMX_OCT_DID_GMX0 1ULL
209#define CVMX_OCT_DID_GMX1 2ULL
210#define CVMX_OCT_DID_PCI 3ULL
211#define CVMX_OCT_DID_KEY 4ULL
212#define CVMX_OCT_DID_FPA 5ULL
213#define CVMX_OCT_DID_DFA 6ULL
214#define CVMX_OCT_DID_ZIP 7ULL
215#define CVMX_OCT_DID_RNG 8ULL
216#define CVMX_OCT_DID_IPD 9ULL
217#define CVMX_OCT_DID_PKT 10ULL
218#define CVMX_OCT_DID_TIM 11ULL
219#define CVMX_OCT_DID_TAG 12ULL
220// the rest are not on the IO bus
221#define CVMX_OCT_DID_L2C 16ULL
222#define CVMX_OCT_DID_LMC 17ULL
223#define CVMX_OCT_DID_SPX0 18ULL
224#define CVMX_OCT_DID_SPX1 19ULL
225#define CVMX_OCT_DID_PIP 20ULL
226#define CVMX_OCT_DID_ASX0 22ULL
227#define CVMX_OCT_DID_ASX1 23ULL
228#define CVMX_OCT_DID_IOB 30ULL
229
230#define CVMX_OCT_DID_PKT_SEND       CVMX_FULL_DID(CVMX_OCT_DID_PKT,2ULL)
231#define CVMX_OCT_DID_TAG_SWTAG      CVMX_FULL_DID(CVMX_OCT_DID_TAG,0ULL)
232#define CVMX_OCT_DID_TAG_TAG1       CVMX_FULL_DID(CVMX_OCT_DID_TAG,1ULL)
233#define CVMX_OCT_DID_TAG_TAG2       CVMX_FULL_DID(CVMX_OCT_DID_TAG,2ULL)
234#define CVMX_OCT_DID_TAG_TAG3       CVMX_FULL_DID(CVMX_OCT_DID_TAG,3ULL)
235#define CVMX_OCT_DID_TAG_NULL_RD    CVMX_FULL_DID(CVMX_OCT_DID_TAG,4ULL)
236#define CVMX_OCT_DID_TAG_CSR        CVMX_FULL_DID(CVMX_OCT_DID_TAG,7ULL)
237#define CVMX_OCT_DID_FAU_FAI        CVMX_FULL_DID(CVMX_OCT_DID_IOB,0ULL)
238#define CVMX_OCT_DID_TIM_CSR        CVMX_FULL_DID(CVMX_OCT_DID_TIM,0ULL)
239#define CVMX_OCT_DID_KEY_RW         CVMX_FULL_DID(CVMX_OCT_DID_KEY,0ULL)
240#define CVMX_OCT_DID_PCI_6          CVMX_FULL_DID(CVMX_OCT_DID_PCI,6ULL)
241#define CVMX_OCT_DID_MIS_BOO        CVMX_FULL_DID(CVMX_OCT_DID_MIS,0ULL)
242#define CVMX_OCT_DID_PCI_RML        CVMX_FULL_DID(CVMX_OCT_DID_PCI,0ULL)
243#define CVMX_OCT_DID_IPD_CSR        CVMX_FULL_DID(CVMX_OCT_DID_IPD,7ULL)
244#define CVMX_OCT_DID_DFA_CSR        CVMX_FULL_DID(CVMX_OCT_DID_DFA,7ULL)
245#define CVMX_OCT_DID_MIS_CSR        CVMX_FULL_DID(CVMX_OCT_DID_MIS,7ULL)
246#define CVMX_OCT_DID_ZIP_CSR        CVMX_FULL_DID(CVMX_OCT_DID_ZIP,0ULL)
247
248#ifdef	__cplusplus
249}
250#endif
251
252#endif /* __CVMX_ADDRESS_H__ */
253
254