1/***********************license start*************** 2 * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights 3 * reserved. 4 * 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 13 * * Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 18 * * Neither the name of Cavium Inc. nor the names of 19 * its contributors may be used to endorse or promote products 20 * derived from this software without specific prior written 21 * permission. 22 23 * This Software, including technical data, may be subject to U.S. export control 24 * laws, including the U.S. Export Administration Act and its associated 25 * regulations, and may be subject to export or import regulations in other 26 * countries. 27 28 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29 * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30 * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31 * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32 * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34 * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35 * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36 * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37 * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38 ***********************license end**************************************/ 39 40 41/** 42 * @file 43 * Typedefs and defines for working with Octeon physical addresses. 44 * 45 * <hr>$Revision: 38306 $<hr> 46*/ 47#ifndef __CVMX_ADDRESS_H__ 48#define __CVMX_ADDRESS_H__ 49 50#ifndef CVMX_BUILD_FOR_LINUX_KERNEL 51#include "cvmx-abi.h" 52#endif 53 54#ifdef __cplusplus 55extern "C" { 56#endif 57 58typedef enum { 59 CVMX_MIPS_SPACE_XKSEG = 3LL, 60 CVMX_MIPS_SPACE_XKPHYS = 2LL, 61 CVMX_MIPS_SPACE_XSSEG = 1LL, 62 CVMX_MIPS_SPACE_XUSEG = 0LL 63} cvmx_mips_space_t; 64 65typedef enum { 66 CVMX_MIPS_XKSEG_SPACE_KSEG0 = 0LL, 67 CVMX_MIPS_XKSEG_SPACE_KSEG1 = 1LL, 68 CVMX_MIPS_XKSEG_SPACE_SSEG = 2LL, 69 CVMX_MIPS_XKSEG_SPACE_KSEG3 = 3LL 70} cvmx_mips_xkseg_space_t; 71 72 /* decodes <14:13> of a kseg3 window address */ 73typedef enum { 74 CVMX_ADD_WIN_SCR = 0L, 75 CVMX_ADD_WIN_DMA = 1L, /* see cvmx_add_win_dma_dec_t for further decode */ 76 CVMX_ADD_WIN_UNUSED = 2L, 77 CVMX_ADD_WIN_UNUSED2 = 3L 78} cvmx_add_win_dec_t; 79 80 /* decode within DMA space */ 81typedef enum { 82 CVMX_ADD_WIN_DMA_ADD = 0L, /* add store data to the write buffer entry, allocating it if necessary */ 83 CVMX_ADD_WIN_DMA_SENDMEM = 1L, /* send out the write buffer entry to DRAM */ 84 /* store data must be normal DRAM memory space address in this case */ 85 CVMX_ADD_WIN_DMA_SENDDMA = 2L, /* send out the write buffer entry as an IOBDMA command */ 86 /* see CVMX_ADD_WIN_DMA_SEND_DEC for data contents */ 87 CVMX_ADD_WIN_DMA_SENDIO = 3L, /* send out the write buffer entry as an IO write */ 88 /* store data must be normal IO space address in this case */ 89 CVMX_ADD_WIN_DMA_SENDSINGLE = 4L, /* send out a single-tick command on the NCB bus */ 90 /* no write buffer data needed/used */ 91} cvmx_add_win_dma_dec_t; 92 93/** 94 * Physical Address Decode 95 * 96 * Octeon-I HW never interprets this X (<39:36> reserved 97 * for future expansion), software should set to 0. 98 * 99 * - 0x0 XXX0 0000 0000 to DRAM Cached 100 * - 0x0 XXX0 0FFF FFFF 101 * 102 * - 0x0 XXX0 1000 0000 to Boot Bus Uncached (Converted to 0x1 00X0 1000 0000 103 * - 0x0 XXX0 1FFF FFFF + EJTAG to 0x1 00X0 1FFF FFFF) 104 * 105 * - 0x0 XXX0 2000 0000 to DRAM Cached 106 * - 0x0 XXXF FFFF FFFF 107 * 108 * - 0x1 00X0 0000 0000 to Boot Bus Uncached 109 * - 0x1 00XF FFFF FFFF 110 * 111 * - 0x1 01X0 0000 0000 to Other NCB Uncached 112 * - 0x1 FFXF FFFF FFFF devices 113 * 114 * Decode of all Octeon addresses 115 */ 116typedef union { 117 118 uint64_t u64; 119 120 struct { 121 cvmx_mips_space_t R : 2; 122 uint64_t offset :62; 123 } sva; /* mapped or unmapped virtual address */ 124 125 struct { 126 uint64_t zeroes :33; 127 uint64_t offset :31; 128 } suseg; /* mapped USEG virtual addresses (typically) */ 129 130 struct { 131 uint64_t ones :33; 132 cvmx_mips_xkseg_space_t sp : 2; 133 uint64_t offset :29; 134 } sxkseg; /* mapped or unmapped virtual address */ 135 136 struct { 137 cvmx_mips_space_t R : 2; /* CVMX_MIPS_SPACE_XKPHYS in this case */ 138 uint64_t cca : 3; /* ignored by octeon */ 139 uint64_t mbz :10; 140 uint64_t pa :49; /* physical address */ 141 } sxkphys; /* physical address accessed through xkphys unmapped virtual address */ 142 143 struct { 144 uint64_t mbz :15; 145 uint64_t is_io : 1; /* if set, the address is uncached and resides on MCB bus */ 146 uint64_t did : 8; /* the hardware ignores this field when is_io==0, else device ID */ 147 uint64_t unaddr: 4; /* the hardware ignores <39:36> in Octeon I */ 148 uint64_t offset :36; 149 } sphys; /* physical address */ 150 151 struct { 152 uint64_t zeroes :24; /* techically, <47:40> are dont-cares */ 153 uint64_t unaddr: 4; /* the hardware ignores <39:36> in Octeon I */ 154 uint64_t offset :36; 155 } smem; /* physical mem address */ 156 157 struct { 158 uint64_t mem_region :2; 159 uint64_t mbz :13; 160 uint64_t is_io : 1; /* 1 in this case */ 161 uint64_t did : 8; /* the hardware ignores this field when is_io==0, else device ID */ 162 uint64_t unaddr: 4; /* the hardware ignores <39:36> in Octeon I */ 163 uint64_t offset :36; 164 } sio; /* physical IO address */ 165 166 struct { 167 uint64_t ones : 49; 168 cvmx_add_win_dec_t csrdec : 2; /* CVMX_ADD_WIN_SCR (0) in this case */ 169 uint64_t addr : 13; 170 } sscr; /* scratchpad virtual address - accessed through a window at the end of kseg3 */ 171 172 /* there should only be stores to IOBDMA space, no loads */ 173 struct { 174 uint64_t ones : 49; 175 cvmx_add_win_dec_t csrdec : 2; /* CVMX_ADD_WIN_DMA (1) in this case */ 176 uint64_t unused2: 3; 177 cvmx_add_win_dma_dec_t type : 3; 178 uint64_t addr : 7; 179 } sdma; /* IOBDMA virtual address - accessed through a window at the end of kseg3 */ 180 181 struct { 182 uint64_t didspace : 24; 183 uint64_t unused : 40; 184 } sfilldidspace; 185 186} cvmx_addr_t; 187 188/* These macros for used by 32 bit applications */ 189 190#define CVMX_MIPS32_SPACE_KSEG0 1l 191#define CVMX_ADD_SEG32(segment, add) (((int32_t)segment << 31) | (int32_t)(add)) 192 193/* Currently all IOs are performed using XKPHYS addressing. Linux uses the 194 CvmMemCtl register to enable XKPHYS addressing to IO space from user mode. 195 Future OSes may need to change the upper bits of IO addresses. The 196 following define controls the upper two bits for all IO addresses generated 197 by the simple executive library */ 198#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS 199 200/* These macros simplify the process of creating common IO addresses */ 201#define CVMX_ADD_SEG(segment, add) ((((uint64_t)segment) << 62) | (add)) 202#ifndef CVMX_ADD_IO_SEG 203#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add)) 204#endif 205#define CVMX_ADDR_DIDSPACE(did) (((CVMX_IO_SEG) << 22) | ((1ULL) << 8) | (did)) 206#define CVMX_ADDR_DID(did) (CVMX_ADDR_DIDSPACE(did) << 40) 207#define CVMX_FULL_DID(did,subdid) (((did) << 3) | (subdid)) 208 209 210 /* from include/ncb_rsl_id.v */ 211#define CVMX_OCT_DID_MIS 0ULL /* misc stuff */ 212#define CVMX_OCT_DID_GMX0 1ULL 213#define CVMX_OCT_DID_GMX1 2ULL 214#define CVMX_OCT_DID_PCI 3ULL 215#define CVMX_OCT_DID_KEY 4ULL 216#define CVMX_OCT_DID_FPA 5ULL 217#define CVMX_OCT_DID_DFA 6ULL 218#define CVMX_OCT_DID_ZIP 7ULL 219#define CVMX_OCT_DID_RNG 8ULL 220#define CVMX_OCT_DID_IPD 9ULL 221#define CVMX_OCT_DID_PKT 10ULL 222#define CVMX_OCT_DID_TIM 11ULL 223#define CVMX_OCT_DID_TAG 12ULL 224 /* the rest are not on the IO bus */ 225#define CVMX_OCT_DID_L2C 16ULL 226#define CVMX_OCT_DID_LMC 17ULL 227#define CVMX_OCT_DID_SPX0 18ULL 228#define CVMX_OCT_DID_SPX1 19ULL 229#define CVMX_OCT_DID_PIP 20ULL 230#define CVMX_OCT_DID_ASX0 22ULL 231#define CVMX_OCT_DID_ASX1 23ULL 232#define CVMX_OCT_DID_IOB 30ULL 233 234#define CVMX_OCT_DID_PKT_SEND CVMX_FULL_DID(CVMX_OCT_DID_PKT,2ULL) 235#define CVMX_OCT_DID_TAG_SWTAG CVMX_FULL_DID(CVMX_OCT_DID_TAG,0ULL) 236#define CVMX_OCT_DID_TAG_TAG1 CVMX_FULL_DID(CVMX_OCT_DID_TAG,1ULL) 237#define CVMX_OCT_DID_TAG_TAG2 CVMX_FULL_DID(CVMX_OCT_DID_TAG,2ULL) 238#define CVMX_OCT_DID_TAG_TAG3 CVMX_FULL_DID(CVMX_OCT_DID_TAG,3ULL) 239#define CVMX_OCT_DID_TAG_NULL_RD CVMX_FULL_DID(CVMX_OCT_DID_TAG,4ULL) 240#define CVMX_OCT_DID_TAG_TAG5 CVMX_FULL_DID(CVMX_OCT_DID_TAG,5ULL) 241#define CVMX_OCT_DID_TAG_CSR CVMX_FULL_DID(CVMX_OCT_DID_TAG,7ULL) 242#define CVMX_OCT_DID_FAU_FAI CVMX_FULL_DID(CVMX_OCT_DID_IOB,0ULL) 243#define CVMX_OCT_DID_TIM_CSR CVMX_FULL_DID(CVMX_OCT_DID_TIM,0ULL) 244#define CVMX_OCT_DID_KEY_RW CVMX_FULL_DID(CVMX_OCT_DID_KEY,0ULL) 245#define CVMX_OCT_DID_PCI_6 CVMX_FULL_DID(CVMX_OCT_DID_PCI,6ULL) 246#define CVMX_OCT_DID_MIS_BOO CVMX_FULL_DID(CVMX_OCT_DID_MIS,0ULL) 247#define CVMX_OCT_DID_PCI_RML CVMX_FULL_DID(CVMX_OCT_DID_PCI,0ULL) 248#define CVMX_OCT_DID_IPD_CSR CVMX_FULL_DID(CVMX_OCT_DID_IPD,7ULL) 249#define CVMX_OCT_DID_DFA_CSR CVMX_FULL_DID(CVMX_OCT_DID_DFA,7ULL) 250#define CVMX_OCT_DID_MIS_CSR CVMX_FULL_DID(CVMX_OCT_DID_MIS,7ULL) 251#define CVMX_OCT_DID_ZIP_CSR CVMX_FULL_DID(CVMX_OCT_DID_ZIP,0ULL) 252 253#ifndef CVMX_BUILD_FOR_LINUX_KERNEL 254#ifdef CVMX_ABI_N32 255#define UNMAPPED_PTR(x) ( (1U << 31) | x ) 256#else 257#define UNMAPPED_PTR(x) ( (1ULL << 63) | x ) 258#endif 259#endif 260 261#ifdef __cplusplus 262} 263#endif 264 265#endif /* __CVMX_ADDRESS_H__ */ 266 267