ar9300_misc.c revision 250003
151974Smsmith/* 251974Smsmith * Copyright (c) 2013 Qualcomm Atheros, Inc. 365245Smsmith * 465245Smsmith * Permission to use, copy, modify, and/or distribute this software for any 551974Smsmith * purpose with or without fee is hereby granted, provided that the above 651974Smsmith * copyright notice and this permission notice appear in all copies. 751974Smsmith * 851974Smsmith * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 951974Smsmith * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 1051974Smsmith * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 1151974Smsmith * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 1251974Smsmith * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 1351974Smsmith * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 1451974Smsmith * PERFORMANCE OF THIS SOFTWARE. 1551974Smsmith */ 1651974Smsmith 1751974Smsmith#include "opt_ah.h" 1851974Smsmith 1951974Smsmith#ifdef AH_SUPPORT_AR9300 2051974Smsmith 2151974Smsmith#include "ah.h" 2251974Smsmith#include "ah_internal.h" 2351974Smsmith#include "ah_devid.h" 2451974Smsmith#ifdef AH_DEBUG 2551974Smsmith#include "ah_desc.h" /* NB: for HAL_PHYERR* */ 2651974Smsmith#endif 27119418Sobrien 28139749Simp#include "ar9300/ar9300.h" 29106225Semoore#include "ar9300/ar9300reg.h" 30106225Semoore#include "ar9300/ar9300phy.h" 31106225Semoore 32106225Semoore 33106225Semoorevoid 34106225Semoorear9300_get_hw_hangs(struct ath_hal *ah, hal_hw_hangs_t *hangs) 35106225Semoore{ 36106225Semoore struct ath_hal_9300 *ahp = AH9300(ah); 37106225Semoore *hangs = 0; 38106225Semoore 39106225Semoore if (ar9300_get_capability(ah, HAL_CAP_BB_RIFS_HANG, 0, AH_NULL) == HAL_OK) { 40106225Semoore *hangs |= HAL_RIFS_BB_HANG_WAR; 41105419Semoore } 42106225Semoore if (ar9300_get_capability(ah, HAL_CAP_BB_DFS_HANG, 0, AH_NULL) == HAL_OK) { 43105419Semoore *hangs |= HAL_DFS_BB_HANG_WAR; 44105419Semoore } 45106225Semoore if (ar9300_get_capability(ah, HAL_CAP_BB_RX_CLEAR_STUCK_HANG, 0, AH_NULL) 46106225Semoore == HAL_OK) 47106225Semoore { 48106225Semoore *hangs |= HAL_RX_STUCK_LOW_BB_HANG_WAR; 49106225Semoore } 50106225Semoore if (ar9300_get_capability(ah, HAL_CAP_MAC_HANG, 0, AH_NULL) == HAL_OK) { 51106225Semoore *hangs |= HAL_MAC_HANG_WAR; 52106225Semoore } 53106225Semoore if (ar9300_get_capability(ah, HAL_CAP_PHYRESTART_CLR_WAR, 0, AH_NULL) 54106225Semoore == HAL_OK) 55106225Semoore { 5651974Smsmith *hangs |= HAL_PHYRESTART_CLR_WAR; 5751974Smsmith } 58119418Sobrien 59119418Sobrien ahp->ah_hang_wars = *hangs; 60119418Sobrien} 6151974Smsmith 6251974Smsmithstatic u_int 6351974Smsmithar9300_mac_to_usec(struct ath_hal *ah, u_int clks) 6451974Smsmith{ 6551974Smsmith HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan; 6651974Smsmith 6751974Smsmith if (chan && IS_CHAN_HT40(chan)) { 68129879Sphk return (ath_hal_mac_usec(ah, clks) / 2); 6951974Smsmith } else { 7065245Smsmith return (ath_hal_mac_usec(ah, clks)); 7151974Smsmith } 7251974Smsmith} 7351974Smsmith 7451974Smsmithu_int 7551974Smsmithar9300_mac_to_clks(struct ath_hal *ah, u_int usecs) 7651974Smsmith{ 7751974Smsmith HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan; 7851974Smsmith 7951974Smsmith if (chan && IS_CHAN_HT40(chan)) { 8065245Smsmith return (ath_hal_mac_clks(ah, usecs) * 2); 8151974Smsmith } else { 8251974Smsmith return (ath_hal_mac_clks(ah, usecs)); 8351974Smsmith } 8451974Smsmith} 8551974Smsmith 8651974Smsmithvoid 87111441Sphkar9300_get_mac_address(struct ath_hal *ah, u_int8_t *mac) 88111441Sphk{ 8951974Smsmith struct ath_hal_9300 *ahp = AH9300(ah); 9051974Smsmith 9165245Smsmith OS_MEMCPY(mac, ahp->ah_macaddr, IEEE80211_ADDR_LEN); 9251974Smsmith} 9365245Smsmith 9451974SmsmithHAL_BOOL 9551974Smsmithar9300_set_mac_address(struct ath_hal *ah, const u_int8_t *mac) 9651974Smsmith{ 9751974Smsmith struct ath_hal_9300 *ahp = AH9300(ah); 9851974Smsmith 9951974Smsmith OS_MEMCPY(ahp->ah_macaddr, mac, IEEE80211_ADDR_LEN); 10051974Smsmith return AH_TRUE; 10151974Smsmith} 10251974Smsmith 10351974Smsmithvoid 10451974Smsmithar9300_get_bss_id_mask(struct ath_hal *ah, u_int8_t *mask) 10551974Smsmith{ 10651974Smsmith struct ath_hal_9300 *ahp = AH9300(ah); 10751974Smsmith 10851974Smsmith OS_MEMCPY(mask, ahp->ah_bssid_mask, IEEE80211_ADDR_LEN); 10951974Smsmith} 11051974Smsmith 111111441SphkHAL_BOOL 11251974Smsmithar9300_set_bss_id_mask(struct ath_hal *ah, const u_int8_t *mask) 113111441Sphk{ 114105419Semoore struct ath_hal_9300 *ahp = AH9300(ah); 115105419Semoore 116105419Semoore /* save it since it must be rewritten on reset */ 11751974Smsmith OS_MEMCPY(ahp->ah_bssid_mask, mask, IEEE80211_ADDR_LEN); 11865245Smsmith 119105419Semoore OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssid_mask)); 12051974Smsmith OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssid_mask + 4)); 12151974Smsmith return AH_TRUE; 12251974Smsmith} 12351974Smsmith 12451974Smsmith/* 12551974Smsmith * Attempt to change the cards operating regulatory domain to the given value 12651974Smsmith * Returns: A_EINVAL for an unsupported regulatory domain. 127105419Semoore * A_HARDWARE for an unwritable EEPROM or bad EEPROM version 128105419Semoore */ 129105419SemooreHAL_BOOL 130105419Semoorear9300_set_regulatory_domain(struct ath_hal *ah, 131105419Semoore u_int16_t reg_domain, HAL_STATUS *status) 132105419Semoore{ 133105419Semoore HAL_STATUS ecode; 134105419Semoore 135105419Semoore if (AH_PRIVATE(ah)->ah_current_rd == 0) { 136105419Semoore AH_PRIVATE(ah)->ah_current_rd = reg_domain; 137105419Semoore return AH_TRUE; 138125975Sphk } 139125975Sphk ecode = HAL_EIO; 140125975Sphk 141125975Sphk#if tbd 142105419Semoorebad: 14351974Smsmith#endif 14451974Smsmith if (status) { 14551974Smsmith *status = ecode; 146120988Sps } 147120988Sps return AH_FALSE; 148120988Sps} 14951974Smsmith 150120988Sps/* 151120988Sps * Return the wireless modes (a,b,g,t) supported by hardware. 152120988Sps * 153120988Sps * This value is what is actually supported by the hardware 154120988Sps * and is unaffected by regulatory/country code settings. 155120988Sps * 156120988Sps */ 157120988Spsu_int 158120988Spsar9300_get_wireless_modes(struct ath_hal *ah) 159120988Sps{ 160120988Sps return AH_PRIVATE(ah)->ah_caps.hal_wireless_modes; 161126116Scperciva} 162126116Scperciva 163120988Sps/* 164120988Sps * Set the interrupt and GPIO values so the ISR can disable RF 165120988Sps * on a switch signal. Assumes GPIO port and interrupt polarity 166120988Sps * are set prior to call. 167120988Sps */ 168120988Spsvoid 169120988Spsar9300_enable_rf_kill(struct ath_hal *ah) 170120988Sps{ 171120988Sps /* TODO - can this really be above the hal on the GPIO interface for 172120988Sps * TODO - the client only? 173120988Sps */ 17451974Smsmith struct ath_hal_9300 *ahp = AH9300(ah); 17551974Smsmith 17651974Smsmith if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { 17751974Smsmith /* Check RF kill GPIO before set/clear RFSILENT bits. */ 17851974Smsmith if (ar9300_gpio_get(ah, ahp->ah_gpio_select) == ahp->ah_polarity) { 17951974Smsmith OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_RFSILENT), 18051974Smsmith AR_RFSILENT_FORCE); 18165245Smsmith OS_REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB); 18251974Smsmith } 183111441Sphk else { 18451974Smsmith OS_REG_CLR_BIT(ah, AR_HOSTIF_REG(ah, AR_RFSILENT), 18551974Smsmith AR_RFSILENT_FORCE); 18651974Smsmith OS_REG_CLR_BIT(ah, AR_PHY_TEST, RFSILENT_BB); 18765245Smsmith } 18851974Smsmith } 18951974Smsmith else { 19051974Smsmith /* Connect rfsilent_bb_l to baseband */ 19165245Smsmith OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), 19251974Smsmith AR_GPIO_INPUT_EN_VAL_RFSILENT_BB); 19351974Smsmith 19451974Smsmith /* Set input mux for rfsilent_bb_l to GPIO #0 */ 19565245Smsmith OS_REG_CLR_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2), 19651974Smsmith AR_GPIO_INPUT_MUX2_RFSILENT); 19751974Smsmith OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2), 19851974Smsmith (ahp->ah_gpio_select & 0x0f) << 4); 19951974Smsmith 20065245Smsmith /* 20165245Smsmith * Configure the desired GPIO port for input and 20251974Smsmith * enable baseband rf silence 20351974Smsmith */ 20451974Smsmith ath_hal_gpio_cfg_input(ah, ahp->ah_gpio_select); 20551974Smsmith OS_REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB); 20651974Smsmith } 20751974Smsmith 20865245Smsmith /* 20951974Smsmith * If radio disable switch connection to GPIO bit x is enabled 21065245Smsmith * program GPIO interrupt. 21158883Smsmith * If rfkill bit on eeprom is 1, setupeeprommap routine has already 21265245Smsmith * verified that it is a later version of eeprom, it has a place for 21365245Smsmith * rfkill bit and it is set to 1, indicating that GPIO bit x hardware 21465245Smsmith * connection is present. 21558883Smsmith */ 21665245Smsmith /* 21758883Smsmith * RFKill uses polling not interrupt, 21851974Smsmith * disable interrupt to avoid Eee PC 2.6.21.4 hang up issue 219105419Semoore */ 22051974Smsmith if (ath_hal_hasrfkill_int(ah)) { 22151974Smsmith if (ahp->ah_gpio_bit == ar9300_gpio_get(ah, ahp->ah_gpio_select)) { 22251974Smsmith /* switch already closed, set to interrupt upon open */ 22351974Smsmith ar9300_gpio_set_intr(ah, ahp->ah_gpio_select, !ahp->ah_gpio_bit); 22451974Smsmith } else { 22551974Smsmith ar9300_gpio_set_intr(ah, ahp->ah_gpio_select, ahp->ah_gpio_bit); 22665245Smsmith } 227105419Semoore } 228105419Semoore} 22951974Smsmith 23051974Smsmith/* 23151974Smsmith * Change the LED blinking pattern to correspond to the connectivity 23251974Smsmith */ 23351974Smsmithvoid 23451974Smsmithar9300_set_led_state(struct ath_hal *ah, HAL_LED_STATE state) 23551974Smsmith{ 23651974Smsmith static const u_int32_t ledbits[8] = { 23751974Smsmith AR_CFG_LED_ASSOC_NONE, /* HAL_LED_RESET */ 23865245Smsmith AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_INIT */ 23951974Smsmith AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_READY */ 24051974Smsmith AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_SCAN */ 24151974Smsmith AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_AUTH */ 24251974Smsmith AR_CFG_LED_ASSOC_ACTIVE, /* HAL_LED_ASSOC */ 24351974Smsmith AR_CFG_LED_ASSOC_ACTIVE, /* HAL_LED_RUN */ 24452274Smsmith AR_CFG_LED_ASSOC_NONE, 24551974Smsmith }; 24652784Smsmith 24751974Smsmith OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_ASSOC_CTL, ledbits[state]); 24865245Smsmith} 24965245Smsmith 25051974Smsmith/* 251125975Sphk * Sets the Power LED on the cardbus without affecting the Network LED. 252125975Sphk */ 253125975Sphkvoid 254125975Sphkar9300_set_power_led_state(struct ath_hal *ah, u_int8_t enabled) 255125975Sphk{ 256125975Sphk u_int32_t val; 257125975Sphk 258125975Sphk val = enabled ? AR_CFG_LED_MODE_POWER_ON : AR_CFG_LED_MODE_POWER_OFF; 259125975Sphk OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_POWER, val); 260125975Sphk} 26165245Smsmith 26251974Smsmith/* 26365245Smsmith * Sets the Network LED on the cardbus without affecting the Power LED. 26451974Smsmith */ 26551974Smsmithvoid 26651974Smsmithar9300_set_network_led_state(struct ath_hal *ah, u_int8_t enabled) 26751974Smsmith{ 26851974Smsmith u_int32_t val; 26951974Smsmith 27051974Smsmith val = enabled ? AR_CFG_LED_MODE_NETWORK_ON : AR_CFG_LED_MODE_NETWORK_OFF; 27151974Smsmith OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_NETWORK, val); 27251974Smsmith} 27365245Smsmith 27451974Smsmith/* 275125975Sphk * Change association related fields programmed into the hardware. 27665245Smsmith * Writing a valid BSSID to the hardware effectively enables the hardware 27765245Smsmith * to synchronize its TSF to the correct beacons and receive frames coming 27865245Smsmith * from that BSSID. It is called by the SME JOIN operation. 27965245Smsmith */ 28065245Smsmithvoid 28165245Smsmithar9300_write_associd(struct ath_hal *ah, const u_int8_t *bssid, 282125975Sphk u_int16_t assoc_id) 28365245Smsmith{ 28451974Smsmith struct ath_hal_9300 *ahp = AH9300(ah); 28551974Smsmith 28651974Smsmith /* save bssid and assoc_id for restore on reset */ 287 OS_MEMCPY(ahp->ah_bssid, bssid, IEEE80211_ADDR_LEN); 288 ahp->ah_assoc_id = assoc_id; 289 290 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid)); 291 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4) | 292 ((assoc_id & 0x3fff) << AR_BSS_ID1_AID_S)); 293} 294 295/* 296 * Get the current hardware tsf for stamlme 297 */ 298u_int64_t 299ar9300_get_tsf64(struct ath_hal *ah) 300{ 301 u_int64_t tsf; 302 303 /* XXX sync multi-word read? */ 304 tsf = OS_REG_READ(ah, AR_TSF_U32); 305 tsf = (tsf << 32) | OS_REG_READ(ah, AR_TSF_L32); 306 return tsf; 307} 308 309void 310ar9300_set_tsf64(struct ath_hal *ah, u_int64_t tsf) 311{ 312 OS_REG_WRITE(ah, AR_TSF_L32, (tsf & 0xffffffff)); 313 OS_REG_WRITE(ah, AR_TSF_U32, ((tsf >> 32) & 0xffffffff)); 314} 315 316/* 317 * Get the current hardware tsf for stamlme 318 */ 319u_int32_t 320ar9300_get_tsf32(struct ath_hal *ah) 321{ 322 return OS_REG_READ(ah, AR_TSF_L32); 323} 324 325u_int32_t 326ar9300_get_tsf2_32(struct ath_hal *ah) 327{ 328 return OS_REG_READ(ah, AR_TSF2_L32); 329} 330 331/* 332 * Reset the current hardware tsf for stamlme. 333 */ 334void 335ar9300_reset_tsf(struct ath_hal *ah) 336{ 337 int count; 338 339 count = 0; 340 while (OS_REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) { 341 count++; 342 if (count > 10) { 343 HALDEBUG(ah, HAL_DEBUG_RESET, 344 "%s: AR_SLP32_TSF_WRITE_STATUS limit exceeded\n", __func__); 345 break; 346 } 347 OS_DELAY(10); 348 } 349 OS_REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 350} 351 352/* 353 * Set or clear hardware basic rate bit 354 * Set hardware basic rate set if basic rate is found 355 * and basic rate is equal or less than 2Mbps 356 */ 357void 358ar9300_set_basic_rate(struct ath_hal *ah, HAL_RATE_SET *rs) 359{ 360 HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan; 361 u_int32_t reg; 362 u_int8_t xset; 363 int i; 364 365 if (chan == AH_NULL || !IS_CHAN_CCK(chan)) { 366 return; 367 } 368 xset = 0; 369 for (i = 0; i < rs->rs_count; i++) { 370 u_int8_t rset = rs->rs_rates[i]; 371 /* Basic rate defined? */ 372 if ((rset & 0x80) && (rset &= 0x7f) >= xset) { 373 xset = rset; 374 } 375 } 376 /* 377 * Set the h/w bit to reflect whether or not the basic 378 * rate is found to be equal or less than 2Mbps. 379 */ 380 reg = OS_REG_READ(ah, AR_STA_ID1); 381 if (xset && xset / 2 <= 2) { 382 OS_REG_WRITE(ah, AR_STA_ID1, reg | AR_STA_ID1_BASE_RATE_11B); 383 } else { 384 OS_REG_WRITE(ah, AR_STA_ID1, reg &~ AR_STA_ID1_BASE_RATE_11B); 385 } 386} 387 388/* 389 * Grab a semi-random value from hardware registers - may not 390 * change often 391 */ 392u_int32_t 393ar9300_get_random_seed(struct ath_hal *ah) 394{ 395 u_int32_t nf; 396 397 nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff; 398 if (nf & 0x100) { 399 nf = 0 - ((nf ^ 0x1ff) + 1); 400 } 401 return (OS_REG_READ(ah, AR_TSF_U32) ^ 402 OS_REG_READ(ah, AR_TSF_L32) ^ nf); 403} 404 405/* 406 * Detect if our card is present 407 */ 408HAL_BOOL 409ar9300_detect_card_present(struct ath_hal *ah) 410{ 411 u_int16_t mac_version, mac_rev; 412 u_int32_t v; 413 414 /* 415 * Read the Silicon Revision register and compare that 416 * to what we read at attach time. If the same, we say 417 * a card/device is present. 418 */ 419 v = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV)) & AR_SREV_ID; 420 if (v == 0xFF) { 421 /* new SREV format */ 422 v = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV)); 423 /* 424 * Include 6-bit Chip Type (masked to 0) to differentiate 425 * from pre-Sowl versions 426 */ 427 mac_version = (v & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 428 mac_rev = MS(v, AR_SREV_REVISION2); 429 } else { 430 mac_version = MS(v, AR_SREV_VERSION); 431 mac_rev = v & AR_SREV_REVISION; 432 } 433 return (AH_PRIVATE(ah)->ah_macVersion == mac_version && 434 AH_PRIVATE(ah)->ah_macRev == mac_rev); 435} 436 437/* 438 * Update MIB Counters 439 */ 440void 441ar9300_update_mib_mac_stats(struct ath_hal *ah) 442{ 443 struct ath_hal_9300 *ahp = AH9300(ah); 444 HAL_MIB_STATS* stats = &ahp->ah_stats.ast_mibstats; 445 446 stats->ackrcv_bad += OS_REG_READ(ah, AR_ACK_FAIL); 447 stats->rts_bad += OS_REG_READ(ah, AR_RTS_FAIL); 448 stats->fcs_bad += OS_REG_READ(ah, AR_FCS_FAIL); 449 stats->rts_good += OS_REG_READ(ah, AR_RTS_OK); 450 stats->beacons += OS_REG_READ(ah, AR_BEACON_CNT); 451} 452 453void 454ar9300_get_mib_mac_stats(struct ath_hal *ah, HAL_MIB_STATS* stats) 455{ 456 struct ath_hal_9300 *ahp = AH9300(ah); 457 HAL_MIB_STATS* istats = &ahp->ah_stats.ast_mibstats; 458 459 stats->ackrcv_bad = istats->ackrcv_bad; 460 stats->rts_bad = istats->rts_bad; 461 stats->fcs_bad = istats->fcs_bad; 462 stats->rts_good = istats->rts_good; 463 stats->beacons = istats->beacons; 464} 465 466/* 467 * Detect if the HW supports spreading a CCK signal on channel 14 468 */ 469HAL_BOOL 470ar9300_is_japan_channel_spread_supported(struct ath_hal *ah) 471{ 472 return AH_TRUE; 473} 474 475/* 476 * Get the rssi of frame curently being received. 477 */ 478u_int32_t 479ar9300_get_cur_rssi(struct ath_hal *ah) 480{ 481 /* XXX return (OS_REG_READ(ah, AR_PHY_CURRENT_RSSI) & 0xff); */ 482 /* get combined RSSI */ 483 return (OS_REG_READ(ah, AR_PHY_RSSI_3) & 0xff); 484} 485 486#if ATH_GEN_RANDOMNESS 487/* 488 * Get the rssi value from BB on ctl chain0. 489 */ 490u_int32_t 491ar9300_get_rssi_chain0(struct ath_hal *ah) 492{ 493 /* get ctl chain0 RSSI */ 494 return OS_REG_READ(ah, AR_PHY_RSSI_0) & 0xff; 495} 496#endif 497 498u_int 499ar9300_get_def_antenna(struct ath_hal *ah) 500{ 501 return (OS_REG_READ(ah, AR_DEF_ANTENNA) & 0x7); 502} 503 504/* Setup coverage class */ 505void 506ar9300_set_coverage_class(struct ath_hal *ah, u_int8_t coverageclass, int now) 507{ 508} 509 510void 511ar9300_set_def_antenna(struct ath_hal *ah, u_int antenna) 512{ 513 OS_REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 514} 515 516HAL_BOOL 517ar9300_set_antenna_switch(struct ath_hal *ah, 518 HAL_ANT_SETTING settings, HAL_CHANNEL *chan, u_int8_t *tx_chainmask, 519 u_int8_t *rx_chainmask, u_int8_t *antenna_cfgd) 520{ 521 struct ath_hal_9300 *ahp = AH9300(ah); 522 523 /* 524 * Owl does not support diversity or changing antennas. 525 * 526 * Instead this API and function are defined differently for AR9300. 527 * To support Tablet PC's, this interface allows the system 528 * to dramatically reduce the TX power on a particular chain. 529 * 530 * Based on the value of (redefined) diversity_control, the 531 * reset code will decrease power on chain 0 or chain 1/2. 532 * 533 * Based on the value of bit 0 of antenna_switch_swap, 534 * the mapping between OID call and chain is defined as: 535 * 0: map A -> 0, B -> 1; 536 * 1: map A -> 1, B -> 0; 537 * 538 * NOTE: 539 * The devices that use this OID should use a tx_chain_mask and 540 * tx_chain_select_legacy setting of 5 or 3 if ANTENNA_FIXED_B is 541 * used in order to ensure an active transmit antenna. This 542 * API will allow the host to turn off the only transmitting 543 * antenna to ensure the antenna closest to the user's body is 544 * powered-down. 545 */ 546 /* 547 * Set antenna control for use during reset sequence by 548 * ar9300_decrease_chain_power() 549 */ 550 ahp->ah_diversity_control = settings; 551 552 return AH_TRUE; 553} 554 555HAL_BOOL 556ar9300_is_sleep_after_beacon_broken(struct ath_hal *ah) 557{ 558 return AH_TRUE; 559} 560 561HAL_BOOL 562ar9300_set_slot_time(struct ath_hal *ah, u_int us) 563{ 564 struct ath_hal_9300 *ahp = AH9300(ah); 565 if (us < HAL_SLOT_TIME_9 || us > ar9300_mac_to_usec(ah, 0xffff)) { 566 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: bad slot time %u\n", __func__, us); 567 ahp->ah_slot_time = (u_int) -1; /* restore default handling */ 568 return AH_FALSE; 569 } else { 570 /* convert to system clocks */ 571 OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ar9300_mac_to_clks(ah, us)); 572 ahp->ah_slot_time = us; 573 return AH_TRUE; 574 } 575} 576 577HAL_BOOL 578ar9300_set_ack_timeout(struct ath_hal *ah, u_int us) 579{ 580 struct ath_hal_9300 *ahp = AH9300(ah); 581 582 if (us > ar9300_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) { 583 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: bad ack timeout %u\n", __func__, us); 584 ahp->ah_ack_timeout = (u_int) -1; /* restore default handling */ 585 return AH_FALSE; 586 } else { 587 /* convert to system clocks */ 588 OS_REG_RMW_FIELD(ah, 589 AR_TIME_OUT, AR_TIME_OUT_ACK, ar9300_mac_to_clks(ah, us)); 590 ahp->ah_ack_timeout = us; 591 return AH_TRUE; 592 } 593} 594 595u_int 596ar9300_get_ack_timeout(struct ath_hal *ah) 597{ 598 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK); 599 return ar9300_mac_to_usec(ah, clks); /* convert from system clocks */ 600} 601 602HAL_STATUS 603ar9300_set_quiet(struct ath_hal *ah, u_int32_t period, u_int32_t duration, 604 u_int32_t next_start, HAL_QUIET_FLAG flag) 605{ 606 HAL_STATUS status = HAL_EIO; 607 u_int32_t tsf = 0, j, next_start_us = 0; 608 if (flag & HAL_QUIET_ENABLE) { 609 for (j = 0; j < 2; j++) { 610 next_start_us = TU_TO_USEC(next_start); 611 tsf = OS_REG_READ(ah, AR_TSF_L32); 612 if ((!next_start) || (flag & HAL_QUIET_ADD_CURRENT_TSF)) { 613 next_start_us += tsf; 614 } 615 if (flag & HAL_QUIET_ADD_SWBA_RESP_TIME) { 616 next_start_us += 617 AH_PRIVATE(ah)->ah_config.ath_hal_sw_beacon_response_time; 618 } 619 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1); 620 OS_REG_WRITE(ah, AR_QUIET2, SM(duration, AR_QUIET2_QUIET_DUR)); 621 OS_REG_WRITE(ah, AR_QUIET_PERIOD, TU_TO_USEC(period)); 622 OS_REG_WRITE(ah, AR_NEXT_QUIET_TIMER, next_start_us); 623 OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 624 if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == tsf >> 10) { 625 status = HAL_OK; 626 break; 627 } 628 HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: TSF have moved " 629 "while trying to set quiet time TSF: 0x%08x\n", __func__, tsf); 630 /* TSF shouldn't count twice or reg access is taking forever */ 631 HALASSERT(j < 1); 632 } 633 } else { 634 OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 635 status = HAL_OK; 636 } 637 638 return status; 639} 640#ifdef ATH_SUPPORT_DFS 641void 642ar9300_cac_tx_quiet(struct ath_hal *ah, HAL_BOOL enable) 643{ 644 u32 reg1, reg2; 645 646 reg1 = OS_REG_READ(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE)); 647 reg2 = OS_REG_READ(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1)); 648 AH9300(ah)->ah_cac_quiet_enabled = enable; 649 650 if (enable) { 651 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE), 652 reg1 | AR_PCU_FORCE_QUIET_COLL); 653 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1), 654 reg2 & ~AR_QUIET1_QUIET_ACK_CTS_ENABLE); 655 } else { 656 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE), 657 reg1 & ~AR_PCU_FORCE_QUIET_COLL); 658 OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1), 659 reg2 | AR_QUIET1_QUIET_ACK_CTS_ENABLE); 660 } 661} 662#endif /* ATH_SUPPORT_DFS */ 663 664void 665ar9300_set_pcu_config(struct ath_hal *ah) 666{ 667 ar9300_set_operating_mode(ah, AH_PRIVATE(ah)->ah_opmode); 668} 669 670HAL_STATUS 671ar9300_get_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type, 672 u_int32_t capability, u_int32_t *result) 673{ 674 struct ath_hal_9300 *ahp = AH9300(ah); 675 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 676 677 switch (type) { 678 case HAL_CAP_CIPHER: /* cipher handled in hardware */ 679 switch (capability) { 680 case HAL_CIPHER_AES_CCM: 681 case HAL_CIPHER_AES_OCB: 682 case HAL_CIPHER_TKIP: 683 case HAL_CIPHER_WEP: 684 case HAL_CIPHER_MIC: 685 case HAL_CIPHER_CLR: 686 return HAL_OK; 687 default: 688 return HAL_ENOTSUPP; 689 } 690 case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */ 691 switch (capability) { 692 case 0: /* hardware capability */ 693 return HAL_OK; 694 case 1: 695 return (ahp->ah_sta_id1_defaults & 696 AR_STA_ID1_CRPT_MIC_ENABLE) ? HAL_OK : HAL_ENXIO; 697 default: 698 return HAL_ENOTSUPP; 699 } 700 case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */ 701 /* XXX check rev when new parts are available */ 702 return (ahp->ah_misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ? 703 HAL_ENXIO : HAL_OK; 704 case HAL_CAP_WME_TKIPMIC: 705 /* hardware can do TKIP MIC when WMM is turned on */ 706 return HAL_OK; 707 case HAL_CAP_PHYCOUNTERS: /* hardware PHY error counters */ 708 return HAL_OK; 709 case HAL_CAP_DIVERSITY: /* hardware supports fast diversity */ 710 switch (capability) { 711 case 0: /* hardware capability */ 712 return HAL_OK; 713 case 1: /* current setting */ 714 return (OS_REG_READ(ah, AR_PHY_CCK_DETECT) & 715 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ? 716 HAL_OK : HAL_ENXIO; 717 } 718 return HAL_EINVAL; 719 case HAL_CAP_TPC: 720 switch (capability) { 721 case 0: /* hardware capability */ 722 return HAL_OK; 723 case 1: 724 return AH_PRIVATE(ah)->ah_config.ath_hal_desc_tpc ? 725 HAL_OK : HAL_ENXIO; 726 } 727 return HAL_OK; 728 case HAL_CAP_PHYDIAG: /* radar pulse detection capability */ 729 return HAL_OK; 730 case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */ 731 switch (capability) { 732 case 0: /* hardware capability */ 733 return HAL_OK; 734 case 1: 735 if (OS_REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) { 736 /* 737 * Owl and Merlin have problems in mcast key search. 738 * Disable this cap. in Ad-hoc mode. see Bug 25776 and 739 * 26802 740 */ 741 return HAL_ENXIO; 742 } else { 743 return (ahp->ah_sta_id1_defaults & 744 AR_STA_ID1_MCAST_KSRCH) ? HAL_OK : HAL_ENXIO; 745 } 746 } 747 return HAL_EINVAL; 748 case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */ 749 switch (capability) { 750 case 0: /* hardware capability */ 751 return p_cap->hal_tsf_add_support ? HAL_OK : HAL_ENOTSUPP; 752 case 1: 753 return (ahp->ah_misc_mode & AR_PCU_TX_ADD_TSF) ? 754 HAL_OK : HAL_ENXIO; 755 } 756 return HAL_EINVAL; 757 case HAL_CAP_RFSILENT: /* rfsilent support */ 758 if (capability == 3) { /* rfkill interrupt */ 759 /* 760 * XXX: Interrupt-based notification of RF Kill state 761 * changes not working yet. Report that this feature 762 * is not supported so that polling is used instead. 763 */ 764 return (HAL_ENOTSUPP); 765 } 766 return ath_hal_getcapability(ah, type, capability, result); 767 case HAL_CAP_4ADDR_AGGR: 768 return HAL_OK; 769 case HAL_CAP_BB_RIFS_HANG: 770 return HAL_ENOTSUPP; 771 case HAL_CAP_BB_DFS_HANG: 772 return HAL_ENOTSUPP; 773 case HAL_CAP_BB_RX_CLEAR_STUCK_HANG: 774 /* Track chips that are known to have BB hangs related 775 * to rx_clear stuck low. 776 */ 777 return HAL_ENOTSUPP; 778 case HAL_CAP_MAC_HANG: 779 /* Track chips that are known to have MAC hangs. 780 */ 781 return HAL_OK; 782 case HAL_CAP_RIFS_RX_ENABLED: 783 /* Is RIFS RX currently enabled */ 784 return (ahp->ah_rifs_enabled == AH_TRUE) ? HAL_OK : HAL_ENOTSUPP; 785 case HAL_CAP_ANT_CFG_2GHZ: 786 *result = p_cap->hal_num_ant_cfg_2ghz; 787 return HAL_OK; 788 case HAL_CAP_ANT_CFG_5GHZ: 789 *result = p_cap->hal_num_ant_cfg_5ghz; 790 return HAL_OK; 791 case HAL_CAP_RX_STBC: 792 *result = p_cap->hal_rx_stbc_support; 793 return HAL_OK; 794 case HAL_CAP_TX_STBC: 795 *result = p_cap->hal_tx_stbc_support; 796 return HAL_OK; 797 case HAL_CAP_LDPC: 798 *result = p_cap->hal_ldpc_support; 799 return HAL_OK; 800 case HAL_CAP_DYNAMIC_SMPS: 801 return HAL_OK; 802 case HAL_CAP_DS: 803 return (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah) || 804 (p_cap->hal_tx_chain_mask & 0x3) != 0x3 || 805 (p_cap->hal_rx_chain_mask & 0x3) != 0x3) ? 806 HAL_ENOTSUPP : HAL_OK; 807 case HAL_CAP_TS: 808 return (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah) || 809 (p_cap->hal_tx_chain_mask & 0x7) != 0x7 || 810 (p_cap->hal_rx_chain_mask & 0x7) != 0x7) ? 811 HAL_ENOTSUPP : HAL_OK; 812 case HAL_CAP_OL_PWRCTRL: 813 return (ar9300_eeprom_get(ahp, EEP_OL_PWRCTRL)) ? 814 HAL_OK : HAL_ENOTSUPP; 815 case HAL_CAP_CRDC: 816#if ATH_SUPPORT_CRDC 817 return (AR_SREV_WASP(ah) && 818 AH_PRIVATE(ah)->ah_config.ath_hal_crdc_enable) ? 819 HAL_OK : HAL_ENOTSUPP; 820#else 821 return HAL_ENOTSUPP; 822#endif 823 case HAL_CAP_MAX_WEP_TKIP_HT20_TX_RATEKBPS: 824 *result = (u_int32_t)(-1); 825 return HAL_OK; 826 case HAL_CAP_MAX_WEP_TKIP_HT40_TX_RATEKBPS: 827 *result = (u_int32_t)(-1); 828 return HAL_OK; 829 case HAL_CAP_BB_PANIC_WATCHDOG: 830 return HAL_OK; 831 case HAL_CAP_PHYRESTART_CLR_WAR: 832 if ((AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_OSPREY) && 833 (AH_PRIVATE((ah))->ah_macRev < AR_SREV_REVISION_AR9580_10)) 834 { 835 return HAL_OK; 836 } 837 else 838 { 839 return HAL_ENOTSUPP; 840 } 841 case HAL_CAP_ENTERPRISE_MODE: 842 *result = ahp->ah_enterprise_mode >> 16; 843 /* 844 * WAR for EV 77658 - Add delimiters to first sub-frame when using 845 * RTS/CTS with aggregation and non-enterprise Osprey. 846 * 847 * Bug fixed in AR9580/Peacock, Wasp1.1 and later 848 */ 849 if ((ahp->ah_enterprise_mode && AR_ENT_OTP_MIN_PKT_SIZE_DISABLE) && 850 !AR_SREV_AR9580_10_OR_LATER(ah) && (!AR_SREV_WASP(ah) || 851 AR_SREV_WASP_10(ah))) { 852 *result |= AH_ENT_RTSCTS_DELIM_WAR; 853 } 854 return HAL_OK; 855 case HAL_CAP_LDPCWAR: 856 /* WAR for RIFS+LDPC issue is required for all chips currently 857 * supported by ar9300 HAL. 858 */ 859 return HAL_OK; 860 case HAL_CAP_ENABLE_APM: 861 *result = p_cap->hal_enable_apm; 862 return HAL_OK; 863 case HAL_CAP_PCIE_LCR_EXTSYNC_EN: 864 return (p_cap->hal_pcie_lcr_extsync_en == AH_TRUE) ? HAL_OK : HAL_ENOTSUPP; 865 case HAL_CAP_PCIE_LCR_OFFSET: 866 *result = p_cap->hal_pcie_lcr_offset; 867 return HAL_OK; 868 case HAL_CAP_SMARTANTENNA: 869 /* FIXME A request is pending with h/w team to add feature bit in 870 * caldata to detect if board has smart antenna or not, once added 871 * we need to fix his piece of code to read and return value without 872 * any compile flags 873 */ 874#if UMAC_SUPPORT_SMARTANTENNA 875 /* enable smart antenna for Peacock, Wasp and scorpion 876 for future chips need to modify */ 877 if (AR_SREV_AR9580_10(ah) || (AR_SREV_WASP(ah)) || AR_SREV_SCORPION(ah)) { 878 return HAL_OK; 879 } else { 880 return HAL_ENOTSUPP; 881 } 882#else 883 return HAL_ENOTSUPP; 884#endif 885 886#ifdef ATH_TRAFFIC_FAST_RECOVER 887 case HAL_CAP_TRAFFIC_FAST_RECOVER: 888 if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_WASP_11(ah)) { 889 return HAL_OK; 890 } else { 891 return HAL_ENOTSUPP; 892 } 893#endif 894 default: 895 return ath_hal_getcapability(ah, type, capability, result); 896 } 897} 898 899HAL_BOOL 900ar9300_set_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type, 901 u_int32_t capability, u_int32_t setting, HAL_STATUS *status) 902{ 903 struct ath_hal_9300 *ahp = AH9300(ah); 904 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 905 u_int32_t v; 906 907 switch (type) { 908 case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */ 909 if (setting) { 910 ahp->ah_sta_id1_defaults |= AR_STA_ID1_CRPT_MIC_ENABLE; 911 } else { 912 ahp->ah_sta_id1_defaults &= ~AR_STA_ID1_CRPT_MIC_ENABLE; 913 } 914 return AH_TRUE; 915 case HAL_CAP_DIVERSITY: 916 v = OS_REG_READ(ah, AR_PHY_CCK_DETECT); 917 if (setting) { 918 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; 919 } else { 920 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; 921 } 922 OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, v); 923 return AH_TRUE; 924 case HAL_CAP_DIAG: /* hardware diagnostic support */ 925 /* 926 * NB: could split this up into virtual capabilities, 927 * (e.g. 1 => ACK, 2 => CTS, etc.) but it hardly 928 * seems worth the additional complexity. 929 */ 930#ifdef AH_DEBUG 931 AH_PRIVATE(ah)->ah_diagreg = setting; 932#else 933 AH_PRIVATE(ah)->ah_diagreg = setting & 0x6; /* ACK+CTS */ 934#endif 935 OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg); 936 return AH_TRUE; 937 case HAL_CAP_TPC: 938 AH_PRIVATE(ah)->ah_config.ath_hal_desc_tpc = (setting != 0); 939 return AH_TRUE; 940 case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */ 941 if (setting) { 942 ahp->ah_sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH; 943 } else { 944 ahp->ah_sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH; 945 } 946 return AH_TRUE; 947 case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */ 948 if (p_cap->hal_tsf_add_support) { 949 if (setting) { 950 ahp->ah_misc_mode |= AR_PCU_TX_ADD_TSF; 951 } else { 952 ahp->ah_misc_mode &= ~AR_PCU_TX_ADD_TSF; 953 } 954 return AH_TRUE; 955 } 956 return AH_FALSE; 957 case HAL_CAP_RXBUFSIZE: /* set MAC receive buffer size */ 958 ahp->rx_buf_size = setting & AR_DATABUF_MASK; 959 OS_REG_WRITE(ah, AR_DATABUF, ahp->rx_buf_size); 960 return AH_TRUE; 961 962 /* fall thru... */ 963 default: 964 return ath_hal_setcapability(ah, type, capability, setting, status); 965 } 966} 967 968#ifdef AH_DEBUG 969static void 970ar9300_print_reg(struct ath_hal *ah, u_int32_t args) 971{ 972 u_int32_t i = 0; 973 974 /* Read 0x80d0 to trigger pcie analyzer */ 975 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 976 "0x%04x 0x%08x\n", 0x80d0, OS_REG_READ(ah, 0x80d0)); 977 978 if (args & HAL_DIAG_PRINT_REG_COUNTER) { 979 struct ath_hal_9300 *ahp = AH9300(ah); 980 u_int32_t tf, rf, rc, cc; 981 982 tf = OS_REG_READ(ah, AR_TFCNT); 983 rf = OS_REG_READ(ah, AR_RFCNT); 984 rc = OS_REG_READ(ah, AR_RCCNT); 985 cc = OS_REG_READ(ah, AR_CCCNT); 986 987 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 988 "AR_TFCNT Diff= 0x%x\n", tf - ahp->last_tf); 989 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 990 "AR_RFCNT Diff= 0x%x\n", rf - ahp->last_rf); 991 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 992 "AR_RCCNT Diff= 0x%x\n", rc - ahp->last_rc); 993 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 994 "AR_CCCNT Diff= 0x%x\n", cc - ahp->last_cc); 995 996 ahp->last_tf = tf; 997 ahp->last_rf = rf; 998 ahp->last_rc = rc; 999 ahp->last_cc = cc; 1000 1001 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1002 "DMADBG0 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_0)); 1003 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1004 "DMADBG1 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_1)); 1005 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1006 "DMADBG2 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_2)); 1007 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1008 "DMADBG3 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_3)); 1009 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1010 "DMADBG4 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_4)); 1011 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1012 "DMADBG5 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_5)); 1013 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1014 "DMADBG6 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_6)); 1015 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1016 "DMADBG7 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_7)); 1017 } 1018 1019 if (args & HAL_DIAG_PRINT_REG_ALL) { 1020 for (i = 0x8; i <= 0xB8; i += sizeof(u_int32_t)) { 1021 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1022 i, OS_REG_READ(ah, i)); 1023 } 1024 1025 for (i = 0x800; i <= (0x800 + (10 << 2)); i += sizeof(u_int32_t)) { 1026 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1027 i, OS_REG_READ(ah, i)); 1028 } 1029 1030 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1031 "0x%04x 0x%08x\n", 0x840, OS_REG_READ(ah, i)); 1032 1033 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1034 "0x%04x 0x%08x\n", 0x880, OS_REG_READ(ah, i)); 1035 1036 for (i = 0x8C0; i <= (0x8C0 + (10 << 2)); i += sizeof(u_int32_t)) { 1037 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1038 i, OS_REG_READ(ah, i)); 1039 } 1040 1041 for (i = 0x1F00; i <= 0x1F04; i += sizeof(u_int32_t)) { 1042 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1043 i, OS_REG_READ(ah, i)); 1044 } 1045 1046 for (i = 0x4000; i <= 0x408C; i += sizeof(u_int32_t)) { 1047 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1048 i, OS_REG_READ(ah, i)); 1049 } 1050 1051 for (i = 0x5000; i <= 0x503C; i += sizeof(u_int32_t)) { 1052 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1053 i, OS_REG_READ(ah, i)); 1054 } 1055 1056 for (i = 0x7040; i <= 0x7058; i += sizeof(u_int32_t)) { 1057 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1058 i, OS_REG_READ(ah, i)); 1059 } 1060 1061 for (i = 0x8000; i <= 0x8098; i += sizeof(u_int32_t)) { 1062 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1063 i, OS_REG_READ(ah, i)); 1064 } 1065 1066 for (i = 0x80D4; i <= 0x8200; i += sizeof(u_int32_t)) { 1067 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1068 i, OS_REG_READ(ah, i)); 1069 } 1070 1071 for (i = 0x8240; i <= 0x97FC; i += sizeof(u_int32_t)) { 1072 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1073 i, OS_REG_READ(ah, i)); 1074 } 1075 1076 for (i = 0x9800; i <= 0x99f0; i += sizeof(u_int32_t)) { 1077 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1078 i, OS_REG_READ(ah, i)); 1079 } 1080 1081 for (i = 0x9c10; i <= 0x9CFC; i += sizeof(u_int32_t)) { 1082 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1083 i, OS_REG_READ(ah, i)); 1084 } 1085 1086 for (i = 0xA200; i <= 0xA26C; i += sizeof(u_int32_t)) { 1087 HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1088 i, OS_REG_READ(ah, i)); 1089 } 1090 } 1091} 1092#endif 1093 1094HAL_BOOL 1095ar9300_get_diag_state(struct ath_hal *ah, int request, 1096 const void *args, u_int32_t argsize, 1097 void **result, u_int32_t *resultsize) 1098{ 1099 struct ath_hal_9300 *ahp = AH9300(ah); 1100 1101 (void) ahp; 1102 if (ath_hal_getdiagstate(ah, request, args, argsize, result, resultsize)) { 1103 return AH_TRUE; 1104 } 1105 switch (request) { 1106#ifdef AH_PRIVATE_DIAG 1107 case HAL_DIAG_EEPROM: 1108 *result = &ahp->ah_eeprom; 1109 *resultsize = sizeof(HAL_EEPROM); 1110 return AH_TRUE; 1111 1112#if 0 /* XXX - TODO */ 1113 case HAL_DIAG_EEPROM_EXP_11A: 1114 case HAL_DIAG_EEPROM_EXP_11B: 1115 case HAL_DIAG_EEPROM_EXP_11G: 1116 pe = &ahp->ah_mode_power_array2133[request - HAL_DIAG_EEPROM_EXP_11A]; 1117 *result = pe->p_channels; 1118 *resultsize = (*result == AH_NULL) ? 0 : 1119 roundup(sizeof(u_int16_t) * pe->num_channels, 1120 sizeof(u_int32_t)) + 1121 sizeof(EXPN_DATA_PER_CHANNEL_2133) * pe->num_channels; 1122 return AH_TRUE; 1123#endif 1124 case HAL_DIAG_RFGAIN: 1125 *result = &ahp->ah_gain_values; 1126 *resultsize = sizeof(GAIN_VALUES); 1127 return AH_TRUE; 1128 case HAL_DIAG_RFGAIN_CURSTEP: 1129 *result = (void *) ahp->ah_gain_values.curr_step; 1130 *resultsize = (*result == AH_NULL) ? 1131 0 : sizeof(GAIN_OPTIMIZATION_STEP); 1132 return AH_TRUE; 1133#if 0 /* XXX - TODO */ 1134 case HAL_DIAG_PCDAC: 1135 *result = ahp->ah_pcdac_table; 1136 *resultsize = ahp->ah_pcdac_table_size; 1137 return AH_TRUE; 1138#endif 1139 case HAL_DIAG_ANI_CURRENT: 1140 *result = ar9300_ani_get_current_state(ah); 1141 *resultsize = (*result == AH_NULL) ? 1142 0 : sizeof(struct ar9300_ani_state); 1143 return AH_TRUE; 1144 case HAL_DIAG_ANI_STATS: 1145 *result = ar9300_ani_get_current_stats(ah); 1146 *resultsize = (*result == AH_NULL) ? 1147 0 : sizeof(struct ar9300_stats); 1148 return AH_TRUE; 1149 case HAL_DIAG_ANI_CMD: 1150 if (argsize != 2*sizeof(u_int32_t)) { 1151 return AH_FALSE; 1152 } 1153 ar9300_ani_control( 1154 ah, ((const u_int32_t *)args)[0], ((const u_int32_t *)args)[1]); 1155 return AH_TRUE; 1156 case HAL_DIAG_TXCONT: 1157 /*AR9300_CONTTXMODE(ah, (struct ath_desc *)args, argsize );*/ 1158 return AH_TRUE; 1159#endif /* AH_PRIVATE_DIAG */ 1160 case HAL_DIAG_CHANNELS: 1161 *result = &(ahp->ah_priv.ah_channels[0]); 1162 *resultsize = 1163 sizeof(ahp->ah_priv.ah_channels[0]) * ahp->ah_priv.priv.ah_nchan; 1164 return AH_TRUE; 1165#ifdef AH_DEBUG 1166 case HAL_DIAG_PRINT_REG: 1167 ar9300_print_reg(ah, *((const u_int32_t *)args)); 1168 return AH_TRUE; 1169#endif 1170 default: 1171 break; 1172 } 1173 1174 return AH_FALSE; 1175} 1176 1177void 1178ar9300_dma_reg_dump(struct ath_hal *ah) 1179{ 1180#ifdef AH_DEBUG 1181#define NUM_DMA_DEBUG_REGS 8 1182#define NUM_QUEUES 10 1183 1184 u_int32_t val[NUM_DMA_DEBUG_REGS]; 1185 int qcu_offset = 0, dcu_offset = 0; 1186 u_int32_t *qcu_base = &val[0], *dcu_base = &val[4], reg; 1187 int i, j, k; 1188 int16_t nfarray[NUM_NF_READINGS]; 1189 HAL_NFCAL_HIST_FULL *h = AH_HOME_CHAN_NFCAL_HIST(ah); 1190 1191 /* selecting DMA OBS 8 */ 1192 OS_REG_WRITE(ah, AR_MACMISC, 1193 ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) | 1194 (AR_MACMISC_MISC_OBS_BUS_1 << AR_MACMISC_MISC_OBS_BUS_MSB_S))); 1195 1196 ath_hal_printf(ah, "Raw DMA Debug values:\n"); 1197 for (i = 0; i < NUM_DMA_DEBUG_REGS; i++) { 1198 if (i % 4 == 0) { 1199 ath_hal_printf(ah, "\n"); 1200 } 1201 1202 val[i] = OS_REG_READ(ah, AR_DMADBG_0 + (i * sizeof(u_int32_t))); 1203 ath_hal_printf(ah, "%d: %08x ", i, val[i]); 1204 } 1205 1206 ath_hal_printf(ah, "\n\n"); 1207 ath_hal_printf(ah, "Num QCU: chain_st fsp_ok fsp_st DCU: chain_st\n"); 1208 1209 for (i = 0; i < NUM_QUEUES; i++, qcu_offset += 4, dcu_offset += 5) { 1210 if (i == 8) { 1211 /* only 8 QCU entries in val[0] */ 1212 qcu_offset = 0; 1213 qcu_base++; 1214 } 1215 1216 if (i == 6) { 1217 /* only 6 DCU entries in val[4] */ 1218 dcu_offset = 0; 1219 dcu_base++; 1220 } 1221 1222 ath_hal_printf(ah, 1223 "%2d %2x %1x %2x %2x\n", 1224 i, 1225 (*qcu_base & (0x7 << qcu_offset)) >> qcu_offset, 1226 (*qcu_base & (0x8 << qcu_offset)) >> (qcu_offset + 3), 1227 val[2] & (0x7 << (i * 3)) >> (i * 3), 1228 (*dcu_base & (0x1f << dcu_offset)) >> dcu_offset); 1229 } 1230 1231 ath_hal_printf(ah, "\n"); 1232 ath_hal_printf(ah, 1233 "qcu_stitch state: %2x qcu_fetch state: %2x\n", 1234 (val[3] & 0x003c0000) >> 18, (val[3] & 0x03c00000) >> 22); 1235 ath_hal_printf(ah, 1236 "qcu_complete state: %2x dcu_complete state: %2x\n", 1237 (val[3] & 0x1c000000) >> 26, (val[6] & 0x3)); 1238 ath_hal_printf(ah, 1239 "dcu_arb state: %2x dcu_fp state: %2x\n", 1240 (val[5] & 0x06000000) >> 25, (val[5] & 0x38000000) >> 27); 1241 ath_hal_printf(ah, 1242 "chan_idle_dur: %3d chan_idle_dur_valid: %1d\n", 1243 (val[6] & 0x000003fc) >> 2, (val[6] & 0x00000400) >> 10); 1244 ath_hal_printf(ah, 1245 "txfifo_valid_0: %1d txfifo_valid_1: %1d\n", 1246 (val[6] & 0x00000800) >> 11, (val[6] & 0x00001000) >> 12); 1247 ath_hal_printf(ah, 1248 "txfifo_dcu_num_0: %2d txfifo_dcu_num_1: %2d\n", 1249 (val[6] & 0x0001e000) >> 13, (val[6] & 0x001e0000) >> 17); 1250 ath_hal_printf(ah, "pcu observe 0x%x \n", OS_REG_READ(ah, AR_OBS_BUS_1)); 1251 ath_hal_printf(ah, "AR_CR 0x%x \n", OS_REG_READ(ah, AR_CR)); 1252 1253 ar9300_upload_noise_floor(ah, 1, nfarray); 1254 ath_hal_printf(ah, "2G:\n"); 1255 ath_hal_printf(ah, "Min CCA Out:\n"); 1256 ath_hal_printf(ah, "\t\tChain 0\t\tChain 1\t\tChain 2\n"); 1257 ath_hal_printf(ah, "Control:\t%8d\t%8d\t%8d\n", 1258 nfarray[0], nfarray[1], nfarray[2]); 1259 ath_hal_printf(ah, "Extension:\t%8d\t%8d\t%8d\n\n", 1260 nfarray[3], nfarray[4], nfarray[5]); 1261 1262 ar9300_upload_noise_floor(ah, 0, nfarray); 1263 ath_hal_printf(ah, "5G:\n"); 1264 ath_hal_printf(ah, "Min CCA Out:\n"); 1265 ath_hal_printf(ah, "\t\tChain 0\t\tChain 1\t\tChain 2\n"); 1266 ath_hal_printf(ah, "Control:\t%8d\t%8d\t%8d\n", 1267 nfarray[0], nfarray[1], nfarray[2]); 1268 ath_hal_printf(ah, "Extension:\t%8d\t%8d\t%8d\n\n", 1269 nfarray[3], nfarray[4], nfarray[5]); 1270 1271 for (i = 0; i < NUM_NF_READINGS; i++) { 1272 ath_hal_printf(ah, "%s Chain %d NF History:\n", 1273 ((i < 3) ? "Control " : "Extension "), i%3); 1274 for (j = 0, k = h->base.curr_index; 1275 j < HAL_NF_CAL_HIST_LEN_FULL; 1276 j++, k++) { 1277 ath_hal_printf(ah, "Element %d: %d\n", 1278 j, h->nf_cal_buffer[k % HAL_NF_CAL_HIST_LEN_FULL][i]); 1279 } 1280 ath_hal_printf(ah, "Last Programmed NF: %d\n\n", h->base.priv_nf[i]); 1281 } 1282 1283 reg = OS_REG_READ(ah, AR_PHY_FIND_SIG_LOW); 1284 ath_hal_printf(ah, "FIRStep Low = 0x%x (%d)\n", 1285 MS(reg, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW), 1286 MS(reg, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW)); 1287 reg = OS_REG_READ(ah, AR_PHY_DESIRED_SZ); 1288 ath_hal_printf(ah, "Total Desired = 0x%x (%d)\n", 1289 MS(reg, AR_PHY_DESIRED_SZ_TOT_DES), 1290 MS(reg, AR_PHY_DESIRED_SZ_TOT_DES)); 1291 ath_hal_printf(ah, "ADC Desired = 0x%x (%d)\n", 1292 MS(reg, AR_PHY_DESIRED_SZ_ADC), 1293 MS(reg, AR_PHY_DESIRED_SZ_ADC)); 1294 reg = OS_REG_READ(ah, AR_PHY_FIND_SIG); 1295 ath_hal_printf(ah, "FIRStep = 0x%x (%d)\n", 1296 MS(reg, AR_PHY_FIND_SIG_FIRSTEP), 1297 MS(reg, AR_PHY_FIND_SIG_FIRSTEP)); 1298 reg = OS_REG_READ(ah, AR_PHY_AGC); 1299 ath_hal_printf(ah, "Coarse High = 0x%x (%d)\n", 1300 MS(reg, AR_PHY_AGC_COARSE_HIGH), 1301 MS(reg, AR_PHY_AGC_COARSE_HIGH)); 1302 ath_hal_printf(ah, "Coarse Low = 0x%x (%d)\n", 1303 MS(reg, AR_PHY_AGC_COARSE_LOW), 1304 MS(reg, AR_PHY_AGC_COARSE_LOW)); 1305 ath_hal_printf(ah, "Coarse Power Constant = 0x%x (%d)\n", 1306 MS(reg, AR_PHY_AGC_COARSE_PWR_CONST), 1307 MS(reg, AR_PHY_AGC_COARSE_PWR_CONST)); 1308 reg = OS_REG_READ(ah, AR_PHY_TIMING5); 1309 ath_hal_printf(ah, "Enable Cyclic Power Thresh = %d\n", 1310 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1_ENABLE)); 1311 ath_hal_printf(ah, "Cyclic Power Thresh = 0x%x (%d)\n", 1312 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1), 1313 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1)); 1314 ath_hal_printf(ah, "Cyclic Power Thresh 1A= 0x%x (%d)\n", 1315 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1A), 1316 MS(reg, AR_PHY_TIMING5_CYCPWR_THR1A)); 1317 reg = OS_REG_READ(ah, AR_PHY_DAG_CTRLCCK); 1318 ath_hal_printf(ah, "Barker RSSI Thresh Enable = %d\n", 1319 MS(reg, AR_PHY_DAG_CTRLCCK_EN_RSSI_THR)); 1320 ath_hal_printf(ah, "Barker RSSI Thresh = 0x%x (%d)\n", 1321 MS(reg, AR_PHY_DAG_CTRLCCK_RSSI_THR), 1322 MS(reg, AR_PHY_DAG_CTRLCCK_RSSI_THR)); 1323 1324 1325 /* Step 1a: Set bit 23 of register 0xa360 to 0 */ 1326 reg = OS_REG_READ(ah, 0xa360); 1327 reg &= ~0x00800000; 1328 OS_REG_WRITE(ah, 0xa360, reg); 1329 1330 /* Step 2a: Set register 0xa364 to 0x1000 */ 1331 reg = 0x1000; 1332 OS_REG_WRITE(ah, 0xa364, reg); 1333 1334 /* Step 3a: Read bits 17:0 of register 0x9c20 */ 1335 reg = OS_REG_READ(ah, 0x9c20); 1336 reg &= 0x0003ffff; 1337 ath_hal_printf(ah, 1338 "%s: Test Control Status [0x1000] 0x9c20[17:0] = 0x%x\n", 1339 __func__, reg); 1340 1341 /* Step 1b: Set bit 23 of register 0xa360 to 0 */ 1342 reg = OS_REG_READ(ah, 0xa360); 1343 reg &= ~0x00800000; 1344 OS_REG_WRITE(ah, 0xa360, reg); 1345 1346 /* Step 2b: Set register 0xa364 to 0x1400 */ 1347 reg = 0x1400; 1348 OS_REG_WRITE(ah, 0xa364, reg); 1349 1350 /* Step 3b: Read bits 17:0 of register 0x9c20 */ 1351 reg = OS_REG_READ(ah, 0x9c20); 1352 reg &= 0x0003ffff; 1353 ath_hal_printf(ah, 1354 "%s: Test Control Status [0x1400] 0x9c20[17:0] = 0x%x\n", 1355 __func__, reg); 1356 1357 /* Step 1c: Set bit 23 of register 0xa360 to 0 */ 1358 reg = OS_REG_READ(ah, 0xa360); 1359 reg &= ~0x00800000; 1360 OS_REG_WRITE(ah, 0xa360, reg); 1361 1362 /* Step 2c: Set register 0xa364 to 0x3C00 */ 1363 reg = 0x3c00; 1364 OS_REG_WRITE(ah, 0xa364, reg); 1365 1366 /* Step 3c: Read bits 17:0 of register 0x9c20 */ 1367 reg = OS_REG_READ(ah, 0x9c20); 1368 reg &= 0x0003ffff; 1369 ath_hal_printf(ah, 1370 "%s: Test Control Status [0x3C00] 0x9c20[17:0] = 0x%x\n", 1371 __func__, reg); 1372 1373 /* Step 1d: Set bit 24 of register 0xa360 to 0 */ 1374 reg = OS_REG_READ(ah, 0xa360); 1375 reg &= ~0x001040000; 1376 OS_REG_WRITE(ah, 0xa360, reg); 1377 1378 /* Step 2d: Set register 0xa364 to 0x5005D */ 1379 reg = 0x5005D; 1380 OS_REG_WRITE(ah, 0xa364, reg); 1381 1382 /* Step 3d: Read bits 17:0 of register 0xa368 */ 1383 reg = OS_REG_READ(ah, 0xa368); 1384 reg &= 0x0003ffff; 1385 ath_hal_printf(ah, 1386 "%s: Test Control Status [0x5005D] 0xa368[17:0] = 0x%x\n", 1387 __func__, reg); 1388 1389 /* Step 1e: Set bit 24 of register 0xa360 to 0 */ 1390 reg = OS_REG_READ(ah, 0xa360); 1391 reg &= ~0x001040000; 1392 OS_REG_WRITE(ah, 0xa360, reg); 1393 1394 /* Step 2e: Set register 0xa364 to 0x7005D */ 1395 reg = 0x7005D; 1396 OS_REG_WRITE(ah, 0xa364, reg); 1397 1398 /* Step 3e: Read bits 17:0 of register 0xa368 */ 1399 reg = OS_REG_READ(ah, 0xa368); 1400 reg &= 0x0003ffff; 1401 ath_hal_printf(ah, 1402 "%s: Test Control Status [0x7005D] 0xa368[17:0] = 0x%x\n", 1403 __func__, reg); 1404 1405 /* Step 1f: Set bit 24 of register 0xa360 to 0 */ 1406 reg = OS_REG_READ(ah, 0xa360); 1407 reg &= ~0x001000000; 1408 reg |= 0x40000; 1409 OS_REG_WRITE(ah, 0xa360, reg); 1410 1411 /* Step 2f: Set register 0xa364 to 0x3005D */ 1412 reg = 0x3005D; 1413 OS_REG_WRITE(ah, 0xa364, reg); 1414 1415 /* Step 3f: Read bits 17:0 of register 0xa368 */ 1416 reg = OS_REG_READ(ah, 0xa368); 1417 reg &= 0x0003ffff; 1418 ath_hal_printf(ah, 1419 "%s: Test Control Status [0x3005D] 0xa368[17:0] = 0x%x\n", 1420 __func__, reg); 1421 1422 /* Step 1g: Set bit 24 of register 0xa360 to 0 */ 1423 reg = OS_REG_READ(ah, 0xa360); 1424 reg &= ~0x001000000; 1425 reg |= 0x40000; 1426 OS_REG_WRITE(ah, 0xa360, reg); 1427 1428 /* Step 2g: Set register 0xa364 to 0x6005D */ 1429 reg = 0x6005D; 1430 OS_REG_WRITE(ah, 0xa364, reg); 1431 1432 /* Step 3g: Read bits 17:0 of register 0xa368 */ 1433 reg = OS_REG_READ(ah, 0xa368); 1434 reg &= 0x0003ffff; 1435 ath_hal_printf(ah, 1436 "%s: Test Control Status [0x6005D] 0xa368[17:0] = 0x%x\n", 1437 __func__, reg); 1438#endif /* AH_DEBUG */ 1439} 1440 1441/* 1442 * Return the busy for rx_frame, rx_clear, and tx_frame 1443 */ 1444u_int32_t 1445ar9300_get_mib_cycle_counts_pct(struct ath_hal *ah, u_int32_t *rxc_pcnt, 1446 u_int32_t *rxf_pcnt, u_int32_t *txf_pcnt) 1447{ 1448 struct ath_hal_9300 *ahp = AH9300(ah); 1449 u_int32_t good = 1; 1450 1451 u_int32_t rc = OS_REG_READ(ah, AR_RCCNT); 1452 u_int32_t rf = OS_REG_READ(ah, AR_RFCNT); 1453 u_int32_t tf = OS_REG_READ(ah, AR_TFCNT); 1454 u_int32_t cc = OS_REG_READ(ah, AR_CCCNT); /* read cycles last */ 1455 1456 if (ahp->ah_cycles == 0 || ahp->ah_cycles > cc) { 1457 /* 1458 * Cycle counter wrap (or initial call); it's not possible 1459 * to accurately calculate a value because the registers 1460 * right shift rather than wrap--so punt and return 0. 1461 */ 1462 HALDEBUG(ah, HAL_DEBUG_CHANNEL, 1463 "%s: cycle counter wrap. ExtBusy = 0\n", __func__); 1464 good = 0; 1465 } else { 1466 u_int32_t cc_d = cc - ahp->ah_cycles; 1467 u_int32_t rc_d = rc - ahp->ah_rx_clear; 1468 u_int32_t rf_d = rf - ahp->ah_rx_frame; 1469 u_int32_t tf_d = tf - ahp->ah_tx_frame; 1470 1471 if (cc_d != 0) { 1472 *rxc_pcnt = rc_d * 100 / cc_d; 1473 *rxf_pcnt = rf_d * 100 / cc_d; 1474 *txf_pcnt = tf_d * 100 / cc_d; 1475 } else { 1476 good = 0; 1477 } 1478 } 1479 1480 ahp->ah_cycles = cc; 1481 ahp->ah_rx_frame = rf; 1482 ahp->ah_rx_clear = rc; 1483 ahp->ah_tx_frame = tf; 1484 1485 return good; 1486} 1487 1488/* 1489 * Return approximation of extension channel busy over an time interval 1490 * 0% (clear) -> 100% (busy) 1491 * -1 for invalid estimate 1492 */ 1493int8_t 1494ar9300_get_11n_ext_busy(struct ath_hal *ah) 1495{ 1496 /* 1497 * Overflow condition to check before multiplying to get % 1498 * (x * 100 > 0xFFFFFFFF ) => (x > 0x28F5C28) 1499 */ 1500#define OVERFLOW_LIMIT 0x28F5C28 1501#define ERROR_CODE -1 1502 1503 struct ath_hal_9300 *ahp = AH9300(ah); 1504 u_int32_t busy = 0; /* percentage */ 1505 int8_t busyper = 0; 1506 u_int32_t cycle_count, ctl_busy, ext_busy; 1507 1508 /* cycle_count will always be the first to wrap; therefore, read it last 1509 * This sequence of reads is not atomic, and MIB counter wrap 1510 * could happen during it ? 1511 */ 1512 ctl_busy = OS_REG_READ(ah, AR_RCCNT); 1513 ext_busy = OS_REG_READ(ah, AR_EXTRCCNT); 1514 cycle_count = OS_REG_READ(ah, AR_CCCNT); 1515 1516 if ((ahp->ah_cycle_count == 0) || (ahp->ah_cycle_count > cycle_count) || 1517 (ahp->ah_ctl_busy > ctl_busy) || (ahp->ah_ext_busy > ext_busy)) 1518 { 1519 /* 1520 * Cycle counter wrap (or initial call); it's not possible 1521 * to accurately calculate a value because the registers 1522 * right shift rather than wrap--so punt and return 0. 1523 */ 1524 busyper = ERROR_CODE; 1525 HALDEBUG(ah, HAL_DEBUG_CHANNEL, 1526 "%s: cycle counter wrap. ExtBusy = 0\n", __func__); 1527 } else { 1528 u_int32_t cycle_delta = cycle_count - ahp->ah_cycle_count; 1529 u_int32_t ext_busy_delta = ext_busy - ahp->ah_ext_busy; 1530 1531 /* 1532 * Compute extension channel busy percentage 1533 * Overflow condition: 0xFFFFFFFF < ext_busy_delta * 100 1534 * Underflow condition/Divide-by-zero: check that cycle_delta >> 7 != 0 1535 * Will never happen, since (ext_busy_delta < cycle_delta) always, 1536 * and shift necessitated by large ext_busy_delta. 1537 * Due to timing difference to read the registers and counter overflow, 1538 * it may still happen that cycle_delta >> 7 = 0. 1539 * 1540 */ 1541 if (cycle_delta) { 1542 if (ext_busy_delta > OVERFLOW_LIMIT) { 1543 if (cycle_delta >> 7) { 1544 busy = ((ext_busy_delta >> 7) * 100) / (cycle_delta >> 7); 1545 } else { 1546 busyper = ERROR_CODE; 1547 } 1548 } else { 1549 busy = (ext_busy_delta * 100) / cycle_delta; 1550 } 1551 } else { 1552 busyper = ERROR_CODE; 1553 } 1554 1555 if (busy > 100) { 1556 busy = 100; 1557 } 1558 if ( busyper != ERROR_CODE ) { 1559 busyper = busy; 1560 } 1561 } 1562 1563 ahp->ah_cycle_count = cycle_count; 1564 ahp->ah_ctl_busy = ctl_busy; 1565 ahp->ah_ext_busy = ext_busy; 1566 1567 return busyper; 1568#undef OVERFLOW_LIMIT 1569#undef ERROR_CODE 1570} 1571 1572/* BB Panic Watchdog declarations */ 1573#define HAL_BB_PANIC_WD_HT20_FACTOR 74 /* 0.74 */ 1574#define HAL_BB_PANIC_WD_HT40_FACTOR 37 /* 0.37 */ 1575 1576void 1577ar9300_config_bb_panic_watchdog(struct ath_hal *ah) 1578{ 1579#define HAL_BB_PANIC_IDLE_TIME_OUT 0x0a8c0000 1580 HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan; 1581 u_int32_t idle_tmo_ms = AH_PRIVATE(ah)->ah_bb_panic_timeout_ms; 1582 u_int32_t val, idle_count; 1583 1584 if (idle_tmo_ms != 0) { 1585 /* enable IRQ, disable chip-reset for BB panic */ 1586 val = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2) & 1587 AR_PHY_BB_PANIC_CNTL2_MASK; 1588 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_2, 1589 (val | AR_PHY_BB_PANIC_IRQ_ENABLE) & ~AR_PHY_BB_PANIC_RST_ENABLE); 1590 /* bound limit to 10 secs */ 1591 if (idle_tmo_ms > 10000) { 1592 idle_tmo_ms = 10000; 1593 } 1594 if (chan != AH_NULL && IS_CHAN_HT40(chan)) { 1595 idle_count = (100 * idle_tmo_ms) / HAL_BB_PANIC_WD_HT40_FACTOR; 1596 } else { 1597 idle_count = (100 * idle_tmo_ms) / HAL_BB_PANIC_WD_HT20_FACTOR; 1598 } 1599 /* 1600 * enable panic in non-IDLE mode, 1601 * disable in IDLE mode, 1602 * set idle time-out 1603 */ 1604 1605 // EV92527 : Enable IDLE mode panic 1606 1607 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_1, 1608 AR_PHY_BB_PANIC_NON_IDLE_ENABLE | 1609 AR_PHY_BB_PANIC_IDLE_ENABLE | 1610 (AR_PHY_BB_PANIC_IDLE_MASK & HAL_BB_PANIC_IDLE_TIME_OUT) | 1611 (AR_PHY_BB_PANIC_NON_IDLE_MASK & (idle_count << 2))); 1612 } else { 1613 /* disable IRQ, disable chip-reset for BB panic */ 1614 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_2, 1615 OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2) & 1616 ~(AR_PHY_BB_PANIC_RST_ENABLE | AR_PHY_BB_PANIC_IRQ_ENABLE)); 1617 /* disable panic in non-IDLE mode, disable in IDLE mode */ 1618 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_1, 1619 OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_1) & 1620 ~(AR_PHY_BB_PANIC_NON_IDLE_ENABLE | AR_PHY_BB_PANIC_IDLE_ENABLE)); 1621 } 1622 1623 HALDEBUG(ah, HAL_DEBUG_RF_PARAM, "%s: %s BB Panic Watchdog tmo=%ums\n", 1624 __func__, idle_tmo_ms ? "Enabled" : "Disabled", idle_tmo_ms); 1625#undef HAL_BB_PANIC_IDLE_TIME_OUT 1626} 1627 1628 1629void 1630ar9300_handle_bb_panic(struct ath_hal *ah) 1631{ 1632 u_int32_t status; 1633 /* 1634 * we want to avoid printing in ISR context so we save 1635 * panic watchdog status to be printed later in DPC context 1636 */ 1637 AH_PRIVATE(ah)->ah_bb_panic_last_status = status = 1638 OS_REG_READ(ah, AR_PHY_PANIC_WD_STATUS); 1639 /* 1640 * panic watchdog timer should reset on status read 1641 * but to make sure we write 0 to the watchdog status bit 1642 */ 1643 OS_REG_WRITE(ah, AR_PHY_PANIC_WD_STATUS, status & ~AR_PHY_BB_WD_STATUS_CLR); 1644} 1645 1646int 1647ar9300_get_bb_panic_info(struct ath_hal *ah, struct hal_bb_panic_info *bb_panic) 1648{ 1649 bb_panic->status = AH_PRIVATE(ah)->ah_bb_panic_last_status; 1650 1651 /* 1652 * For signature 04000539 do not print anything. 1653 * This is a very common occurence as a compromise between 1654 * BB Panic and AH_FALSE detects (EV71009). It indicates 1655 * radar hang, which can be cleared by reprogramming 1656 * radar related register and does not requre a chip reset 1657 */ 1658 1659 /* Suppress BB Status mesg following signature */ 1660 switch (bb_panic->status) { 1661 case 0x04000539: 1662 case 0x04008009: 1663 case 0x04000b09: 1664 case 0x1300000a: 1665 return -1; 1666 } 1667 1668 bb_panic->tsf = ar9300_get_tsf32(ah); 1669 bb_panic->wd = MS(bb_panic->status, AR_PHY_BB_WD_STATUS); 1670 bb_panic->det = MS(bb_panic->status, AR_PHY_BB_WD_DET_HANG); 1671 bb_panic->rdar = MS(bb_panic->status, AR_PHY_BB_WD_RADAR_SM); 1672 bb_panic->r_odfm = MS(bb_panic->status, AR_PHY_BB_WD_RX_OFDM_SM); 1673 bb_panic->r_cck = MS(bb_panic->status, AR_PHY_BB_WD_RX_CCK_SM); 1674 bb_panic->t_odfm = MS(bb_panic->status, AR_PHY_BB_WD_TX_OFDM_SM); 1675 bb_panic->t_cck = MS(bb_panic->status, AR_PHY_BB_WD_TX_CCK_SM); 1676 bb_panic->agc = MS(bb_panic->status, AR_PHY_BB_WD_AGC_SM); 1677 bb_panic->src = MS(bb_panic->status, AR_PHY_BB_WD_SRCH_SM); 1678 bb_panic->phy_panic_wd_ctl1 = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_1); 1679 bb_panic->phy_panic_wd_ctl2 = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2); 1680 bb_panic->phy_gen_ctrl = OS_REG_READ(ah, AR_PHY_GEN_CTRL); 1681 bb_panic->rxc_pcnt = bb_panic->rxf_pcnt = bb_panic->txf_pcnt = 0; 1682 bb_panic->cycles = ar9300_get_mib_cycle_counts_pct(ah, 1683 &bb_panic->rxc_pcnt, 1684 &bb_panic->rxf_pcnt, 1685 &bb_panic->txf_pcnt); 1686 1687 if (AH_PRIVATE(ah)->ah_config.ath_hal_show_bb_panic) { 1688 ath_hal_printf(ah, "\n==== BB update: BB status=0x%08x, " 1689 "tsf=0x%08x ====\n", bb_panic->status, bb_panic->tsf); 1690 ath_hal_printf(ah, "** BB state: wd=%u det=%u rdar=%u rOFDM=%d " 1691 "rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n", 1692 bb_panic->wd, bb_panic->det, bb_panic->rdar, 1693 bb_panic->r_odfm, bb_panic->r_cck, bb_panic->t_odfm, 1694 bb_panic->t_cck, bb_panic->agc, bb_panic->src); 1695 ath_hal_printf(ah, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n", 1696 bb_panic->phy_panic_wd_ctl1, bb_panic->phy_panic_wd_ctl2); 1697 ath_hal_printf(ah, "** BB mode: BB_gen_controls=0x%08x **\n", 1698 bb_panic->phy_gen_ctrl); 1699 if (bb_panic->cycles) { 1700 ath_hal_printf(ah, "** BB busy times: rx_clear=%d%%, " 1701 "rx_frame=%d%%, tx_frame=%d%% **\n", bb_panic->rxc_pcnt, 1702 bb_panic->rxf_pcnt, bb_panic->txf_pcnt); 1703 } 1704 ath_hal_printf(ah, "==== BB update: done ====\n\n"); 1705 } 1706 1707 return 0; //The returned data will be stored for athstats to retrieve it 1708} 1709 1710/* set the reason for HAL reset */ 1711void 1712ar9300_set_hal_reset_reason(struct ath_hal *ah, u_int8_t resetreason) 1713{ 1714 AH_PRIVATE(ah)->ah_reset_reason = resetreason; 1715} 1716 1717/* 1718 * Configure 20/40 operation 1719 * 1720 * 20/40 = joint rx clear (control and extension) 1721 * 20 = rx clear (control) 1722 * 1723 * - NOTE: must stop MAC (tx) and requeue 40 MHz packets as 20 MHz 1724 * when changing from 20/40 => 20 only 1725 */ 1726void 1727ar9300_set_11n_mac2040(struct ath_hal *ah, HAL_HT_MACMODE mode) 1728{ 1729 u_int32_t macmode; 1730 1731 /* Configure MAC for 20/40 operation */ 1732 if (mode == HAL_HT_MACMODE_2040 && 1733 !AH_PRIVATE(ah)->ah_config.ath_hal_cwm_ignore_ext_cca) { 1734 macmode = AR_2040_JOINED_RX_CLEAR; 1735 } else { 1736 macmode = 0; 1737 } 1738 OS_REG_WRITE(ah, AR_2040_MODE, macmode); 1739} 1740 1741/* 1742 * Get Rx clear (control/extension channel) 1743 * 1744 * Returns active low (busy) for ctrl/ext channel 1745 * Owl 2.0 1746 */ 1747HAL_HT_RXCLEAR 1748ar9300_get_11n_rx_clear(struct ath_hal *ah) 1749{ 1750 HAL_HT_RXCLEAR rxclear = 0; 1751 u_int32_t val; 1752 1753 val = OS_REG_READ(ah, AR_DIAG_SW); 1754 1755 /* control channel */ 1756 if (val & AR_DIAG_RX_CLEAR_CTL_LOW) { 1757 rxclear |= HAL_RX_CLEAR_CTL_LOW; 1758 } 1759 /* extension channel */ 1760 if (val & AR_DIAG_RX_CLEAR_EXT_LOW) { 1761 rxclear |= HAL_RX_CLEAR_EXT_LOW; 1762 } 1763 return rxclear; 1764} 1765 1766/* 1767 * Set Rx clear (control/extension channel) 1768 * 1769 * Useful for forcing the channel to appear busy for 1770 * debugging/diagnostics 1771 * Owl 2.0 1772 */ 1773void 1774ar9300_set_11n_rx_clear(struct ath_hal *ah, HAL_HT_RXCLEAR rxclear) 1775{ 1776 /* control channel */ 1777 if (rxclear & HAL_RX_CLEAR_CTL_LOW) { 1778 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_CTL_LOW); 1779 } else { 1780 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_CTL_LOW); 1781 } 1782 /* extension channel */ 1783 if (rxclear & HAL_RX_CLEAR_EXT_LOW) { 1784 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_EXT_LOW); 1785 } else { 1786 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_EXT_LOW); 1787 } 1788} 1789 1790 1791/* 1792 * HAL support code for force ppm tracking workaround. 1793 */ 1794 1795u_int32_t 1796ar9300_ppm_get_rssi_dump(struct ath_hal *ah) 1797{ 1798 u_int32_t retval; 1799 u_int32_t off1; 1800 u_int32_t off2; 1801 1802 if (OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) & AR_PHY_SWAP_ALT_CHAIN) { 1803 off1 = 0x2000; 1804 off2 = 0x1000; 1805 } else { 1806 off1 = 0x1000; 1807 off2 = 0x2000; 1808 } 1809 1810 retval = ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 )) << 0) | 1811 ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 + off1)) << 8) | 1812 ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 + off2)) << 16); 1813 1814 return retval; 1815} 1816 1817u_int32_t 1818ar9300_ppm_force(struct ath_hal *ah) 1819{ 1820 u_int32_t data_fine; 1821 u_int32_t data4; 1822 //u_int32_t off1; 1823 //u_int32_t off2; 1824 HAL_BOOL signed_val = AH_FALSE; 1825 1826// if (OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) & AR_PHY_SWAP_ALT_CHAIN) { 1827// off1 = 0x2000; 1828// off2 = 0x1000; 1829// } else { 1830// off1 = 0x1000; 1831// off2 = 0x2000; 1832// } 1833 data_fine = 1834 AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK & 1835 OS_REG_READ(ah, AR_PHY_CHNINFO_GAINDIFF); 1836 1837 /* 1838 * bit [11-0] is new ppm value. bit 11 is the signed bit. 1839 * So check value from bit[10:0]. 1840 * Now get the abs val of the ppm value read in bit[0:11]. 1841 * After that do bound check on abs value. 1842 * if value is off limit, CAP the value and and restore signed bit. 1843 */ 1844 if (data_fine & AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_SIGNED_BIT) 1845 { 1846 /* get the positive value */ 1847 data_fine = (~data_fine + 1) & AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK; 1848 signed_val = AH_TRUE; 1849 } 1850 if (data_fine > AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT) 1851 { 1852 HALDEBUG(ah, HAL_DEBUG_REG_IO, 1853 "%s Correcting ppm out of range %x\n", 1854 __func__, (data_fine & 0x7ff)); 1855 data_fine = AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT; 1856 } 1857 /* 1858 * Restore signed value if changed above. 1859 * Use typecast to avoid compilation errors 1860 */ 1861 if (signed_val) { 1862 data_fine = (-(int32_t)data_fine) & 1863 AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK; 1864 } 1865 1866 /* write value */ 1867 data4 = OS_REG_READ(ah, AR_PHY_TIMING2) & 1868 ~(AR_PHY_TIMING2_USE_FORCE_PPM | AR_PHY_TIMING2_FORCE_PPM_VAL); 1869 OS_REG_WRITE(ah, AR_PHY_TIMING2, 1870 data4 | data_fine | AR_PHY_TIMING2_USE_FORCE_PPM); 1871 1872 return data_fine; 1873} 1874 1875void 1876ar9300_ppm_un_force(struct ath_hal *ah) 1877{ 1878 u_int32_t data4; 1879 1880 data4 = OS_REG_READ(ah, AR_PHY_TIMING2) & ~AR_PHY_TIMING2_USE_FORCE_PPM; 1881 OS_REG_WRITE(ah, AR_PHY_TIMING2, data4); 1882} 1883 1884u_int32_t 1885ar9300_ppm_arm_trigger(struct ath_hal *ah) 1886{ 1887 u_int32_t val; 1888 u_int32_t ret; 1889 1890 val = OS_REG_READ(ah, AR_PHY_CHAN_INFO_MEMORY); 1891 ret = OS_REG_READ(ah, AR_TSF_L32); 1892 OS_REG_WRITE(ah, AR_PHY_CHAN_INFO_MEMORY, 1893 val | AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK); 1894 1895 /* return low word of TSF at arm time */ 1896 return ret; 1897} 1898 1899int 1900ar9300_ppm_get_trigger(struct ath_hal *ah) 1901{ 1902 if (OS_REG_READ(ah, AR_PHY_CHAN_INFO_MEMORY) & 1903 AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK) 1904 { 1905 /* has not triggered yet, return AH_FALSE */ 1906 return 0; 1907 } 1908 1909 /* else triggered, return AH_TRUE */ 1910 return 1; 1911} 1912 1913void 1914ar9300_mark_phy_inactive(struct ath_hal *ah) 1915{ 1916 OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 1917} 1918 1919/* DEBUG */ 1920u_int32_t 1921ar9300_ppm_get_force_state(struct ath_hal *ah) 1922{ 1923 return 1924 OS_REG_READ(ah, AR_PHY_TIMING2) & 1925 (AR_PHY_TIMING2_USE_FORCE_PPM | AR_PHY_TIMING2_FORCE_PPM_VAL); 1926} 1927 1928/* 1929 * Return the Cycle counts for rx_frame, rx_clear, and tx_frame 1930 */ 1931void 1932ar9300_get_mib_cycle_counts(struct ath_hal *ah, HAL_COUNTERS* p_cnts) 1933{ 1934 p_cnts->tx_frame_count = OS_REG_READ(ah, AR_TFCNT); 1935 p_cnts->rx_frame_count = OS_REG_READ(ah, AR_RFCNT); 1936 p_cnts->rx_clear_count = OS_REG_READ(ah, AR_RCCNT); 1937 p_cnts->cycle_count = OS_REG_READ(ah, AR_CCCNT); 1938 p_cnts->is_tx_active = (OS_REG_READ(ah, AR_TFCNT) == 1939 p_cnts->tx_frame_count) ? AH_FALSE : AH_TRUE; 1940 p_cnts->is_rx_active = (OS_REG_READ(ah, AR_RFCNT) == 1941 p_cnts->rx_frame_count) ? AH_FALSE : AH_TRUE; 1942} 1943 1944void 1945ar9300_clear_mib_counters(struct ath_hal *ah) 1946{ 1947 u_int32_t reg_val; 1948 1949 reg_val = OS_REG_READ(ah, AR_MIBC); 1950 OS_REG_WRITE(ah, AR_MIBC, reg_val | AR_MIBC_CMC); 1951 OS_REG_WRITE(ah, AR_MIBC, reg_val & ~AR_MIBC_CMC); 1952} 1953 1954 1955/* Enable or Disable RIFS Rx capability as part of SW WAR for Bug 31602 */ 1956HAL_BOOL 1957ar9300_set_rifs_delay(struct ath_hal *ah, HAL_BOOL enable) 1958{ 1959 struct ath_hal_9300 *ahp = AH9300(ah); 1960 HAL_BOOL is_chan_2g = IS_CHAN_2GHZ(AH_PRIVATE(ah)->ah_curchan); 1961 u_int32_t tmp = 0; 1962 1963 if (enable) { 1964 if (ahp->ah_rifs_enabled == AH_TRUE) { 1965 return AH_TRUE; 1966 } 1967 1968 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, ahp->ah_rifs_reg[0]); 1969 OS_REG_WRITE(ah, AR_PHY_RIFS_SRCH, 1970 ahp->ah_rifs_reg[1]); 1971 1972 ahp->ah_rifs_enabled = AH_TRUE; 1973 OS_MEMZERO(ahp->ah_rifs_reg, sizeof(ahp->ah_rifs_reg)); 1974 } else { 1975 if (ahp->ah_rifs_enabled == AH_TRUE) { 1976 ahp->ah_rifs_reg[0] = OS_REG_READ(ah, 1977 AR_PHY_SEARCH_START_DELAY); 1978 ahp->ah_rifs_reg[1] = OS_REG_READ(ah, AR_PHY_RIFS_SRCH); 1979 } 1980 /* Change rifs init delay to 0 */ 1981 OS_REG_WRITE(ah, AR_PHY_RIFS_SRCH, 1982 (ahp->ah_rifs_reg[1] & ~(AR_PHY_RIFS_INIT_DELAY))); 1983 tmp = 0xfffff000 & OS_REG_READ(ah, AR_PHY_SEARCH_START_DELAY); 1984 if (is_chan_2g) { 1985 if (IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) { 1986 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 500); 1987 } else { /* Sowl 2G HT-20 default is 0x134 for search start delay */ 1988 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 250); 1989 } 1990 } else { 1991 if (IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) { 1992 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 0x370); 1993 } else { /* Sowl 5G HT-20 default is 0x1b8 for search start delay */ 1994 OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 0x1b8); 1995 } 1996 } 1997 1998 ahp->ah_rifs_enabled = AH_FALSE; 1999 } 2000 return AH_TRUE; 2001 2002} /* ar9300_set_rifs_delay () */ 2003 2004/* Set the current RIFS Rx setting */ 2005HAL_BOOL 2006ar9300_set_11n_rx_rifs(struct ath_hal *ah, HAL_BOOL enable) 2007{ 2008 /* Non-Owl 11n chips */ 2009 if ((ath_hal_getcapability(ah, HAL_CAP_RIFS_RX, 0, AH_NULL) == HAL_OK)) { 2010 if (ar9300_get_capability(ah, HAL_CAP_LDPCWAR, 0, AH_NULL) == HAL_OK) { 2011 return ar9300_set_rifs_delay(ah, enable); 2012 } 2013 return AH_FALSE; 2014 } 2015 2016 return AH_TRUE; 2017} /* ar9300_set_11n_rx_rifs () */ 2018 2019static hal_mac_hangs_t 2020ar9300_compare_dbg_hang(struct ath_hal *ah, mac_dbg_regs_t mac_dbg, 2021 hal_mac_hang_check_t hang_check, hal_mac_hangs_t hangs, u_int8_t *dcu_chain) 2022{ 2023 int i = 0; 2024 hal_mac_hangs_t found_hangs = 0; 2025 2026 if (hangs & dcu_chain_state) { 2027 for (i = 0; i < 6; i++) { 2028 if (((mac_dbg.dma_dbg_4 >> (5 * i)) & 0x1f) == 2029 hang_check.dcu_chain_state) 2030 { 2031 found_hangs |= dcu_chain_state; 2032 *dcu_chain = i; 2033 } 2034 } 2035 for (i = 0; i < 4; i++) { 2036 if (((mac_dbg.dma_dbg_5 >> (5 * i)) & 0x1f) == 2037 hang_check.dcu_chain_state) 2038 { 2039 found_hangs |= dcu_chain_state; 2040 *dcu_chain = i + 6; 2041 } 2042 } 2043 } 2044 2045 if (hangs & dcu_complete_state) { 2046 if ((mac_dbg.dma_dbg_6 & 0x3) == hang_check.dcu_complete_state) { 2047 found_hangs |= dcu_complete_state; 2048 } 2049 } 2050 2051 return found_hangs; 2052 2053} /* end - ar9300_compare_dbg_hang */ 2054 2055#define NUM_STATUS_READS 50 2056HAL_BOOL 2057ar9300_detect_mac_hang(struct ath_hal *ah) 2058{ 2059 struct ath_hal_9300 *ahp = AH9300(ah); 2060 mac_dbg_regs_t mac_dbg; 2061 hal_mac_hang_check_t hang_sig1_val = {0x6, 0x1, 0, 0, 0, 0, 0, 0}; 2062 hal_mac_hangs_t hang_sig1 = (dcu_chain_state | dcu_complete_state); 2063 int i = 0; 2064 u_int8_t dcu_chain = 0, current_dcu_chain_state, shift_val; 2065 2066 if (!(ahp->ah_hang_wars & HAL_MAC_HANG_WAR)) { 2067 return AH_FALSE; 2068 } 2069 2070 OS_MEMZERO(&mac_dbg, sizeof(mac_dbg)); 2071 2072 mac_dbg.dma_dbg_4 = OS_REG_READ(ah, AR_DMADBG_4); 2073 mac_dbg.dma_dbg_5 = OS_REG_READ(ah, AR_DMADBG_5); 2074 mac_dbg.dma_dbg_6 = OS_REG_READ(ah, AR_DMADBG_6); 2075 2076 HALDEBUG(ah, HAL_DEBUG_DFS, " dma regs: %X %X %X \n", 2077 mac_dbg.dma_dbg_4, mac_dbg.dma_dbg_5, 2078 mac_dbg.dma_dbg_6); 2079 2080 if (hang_sig1 != 2081 ar9300_compare_dbg_hang(ah, mac_dbg, 2082 hang_sig1_val, hang_sig1, &dcu_chain)) 2083 { 2084 HALDEBUG(ah, HAL_DEBUG_DFS, " hang sig1 not found \n"); 2085 return AH_FALSE; 2086 } 2087 2088 shift_val = (dcu_chain >= 6) ? (dcu_chain-6) : (dcu_chain); 2089 shift_val *= 5; 2090 2091 for (i = 1; i <= NUM_STATUS_READS; i++) { 2092 if (dcu_chain < 6) { 2093 mac_dbg.dma_dbg_4 = OS_REG_READ(ah, AR_DMADBG_4); 2094 current_dcu_chain_state = 2095 ((mac_dbg.dma_dbg_4 >> shift_val) & 0x1f); 2096 } else { 2097 mac_dbg.dma_dbg_5 = OS_REG_READ(ah, AR_DMADBG_5); 2098 current_dcu_chain_state = ((mac_dbg.dma_dbg_5 >> shift_val) & 0x1f); 2099 } 2100 mac_dbg.dma_dbg_6 = OS_REG_READ(ah, AR_DMADBG_6); 2101 2102 if (((mac_dbg.dma_dbg_6 & 0x3) != hang_sig1_val.dcu_complete_state) 2103 || (current_dcu_chain_state != hang_sig1_val.dcu_chain_state)) { 2104 return AH_FALSE; 2105 } 2106 } 2107 HALDEBUG(ah, HAL_DEBUG_DFS, "%s sig5count=%d sig6count=%d ", __func__, 2108 ahp->ah_hang[MAC_HANG_SIG1], ahp->ah_hang[MAC_HANG_SIG2]); 2109 ahp->ah_hang[MAC_HANG_SIG1]++; 2110 return AH_TRUE; 2111 2112} /* end - ar9300_detect_mac_hang */ 2113 2114/* Determine if the baseband is hung by reading the Observation Bus Register */ 2115HAL_BOOL 2116ar9300_detect_bb_hang(struct ath_hal *ah) 2117{ 2118#define N(a) (sizeof(a) / sizeof(a[0])) 2119 struct ath_hal_9300 *ahp = AH9300(ah); 2120 u_int32_t hang_sig = 0; 2121 int i = 0; 2122 /* Check the PCU Observation Bus 1 register (0x806c) NUM_STATUS_READS times 2123 * 2124 * 4 known BB hang signatures - 2125 * [1] bits 8,9,11 are 0. State machine state (bits 25-31) is 0x1E 2126 * [2] bits 8,9 are 1, bit 11 is 0. State machine state (bits 25-31) is 0x52 2127 * [3] bits 8,9 are 1, bit 11 is 0. State machine state (bits 25-31) is 0x18 2128 * [4] bit 10 is 1, bit 11 is 0. WEP state (bits 12-17) is 0x2, 2129 * Rx State (bits 20-24) is 0x7. 2130 */ 2131 hal_hw_hang_check_t hang_list [] = 2132 { 2133 /* Offset Reg Value Reg Mask Hang Offset */ 2134 {AR_OBS_BUS_1, 0x1E000000, 0x7E000B00, BB_HANG_SIG1}, 2135 {AR_OBS_BUS_1, 0x52000B00, 0x7E000B00, BB_HANG_SIG2}, 2136 {AR_OBS_BUS_1, 0x18000B00, 0x7E000B00, BB_HANG_SIG3}, 2137 {AR_OBS_BUS_1, 0x00702400, 0x7E7FFFEF, BB_HANG_SIG4} 2138 }; 2139 2140 if (!(ahp->ah_hang_wars & (HAL_RIFS_BB_HANG_WAR | 2141 HAL_DFS_BB_HANG_WAR | 2142 HAL_RX_STUCK_LOW_BB_HANG_WAR))) { 2143 return AH_FALSE; 2144 } 2145 2146 hang_sig = OS_REG_READ(ah, AR_OBS_BUS_1); 2147 for (i = 1; i <= NUM_STATUS_READS; i++) { 2148 if (hang_sig != OS_REG_READ(ah, AR_OBS_BUS_1)) { 2149 return AH_FALSE; 2150 } 2151 } 2152 2153 for (i = 0; i < N(hang_list); i++) { 2154 if ((hang_sig & hang_list[i].hang_mask) == hang_list[i].hang_val) { 2155 ahp->ah_hang[hang_list[i].hang_offset]++; 2156 HALDEBUG(ah, HAL_DEBUG_DFS, "%s sig1count=%d sig2count=%d " 2157 "sig3count=%d sig4count=%d\n", __func__, 2158 ahp->ah_hang[BB_HANG_SIG1], ahp->ah_hang[BB_HANG_SIG2], 2159 ahp->ah_hang[BB_HANG_SIG3], ahp->ah_hang[BB_HANG_SIG4]); 2160 return AH_TRUE; 2161 } 2162 } 2163 2164 HALDEBUG(ah, HAL_DEBUG_DFS, "%s Found an unknown BB hang signature! " 2165 "<0x806c>=0x%x\n", __func__, hang_sig); 2166 2167 return AH_FALSE; 2168 2169#undef N 2170} /* end - ar9300_detect_bb_hang () */ 2171 2172#undef NUM_STATUS_READS 2173 2174HAL_STATUS 2175ar9300_select_ant_config(struct ath_hal *ah, u_int32_t cfg) 2176{ 2177 struct ath_hal_9300 *ahp = AH9300(ah); 2178 HAL_CHANNEL_INTERNAL *chan = AH_PRIVATE(ah)->ah_curchan; 2179 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 2180 u_int16_t ant_config; 2181 u_int32_t hal_num_ant_config; 2182 2183 hal_num_ant_config = IS_CHAN_2GHZ(chan) ? 2184 p_cap->hal_num_ant_cfg_2ghz : p_cap->hal_num_ant_cfg_5ghz; 2185 2186 if (cfg < hal_num_ant_config) { 2187 if (HAL_OK == ar9300_eeprom_get_ant_cfg(ahp, chan, cfg, &ant_config)) { 2188 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config); 2189 return HAL_OK; 2190 } 2191 } 2192 2193 return HAL_EINVAL; 2194} 2195 2196/* 2197 * Functions to get/set DCS mode 2198 */ 2199void 2200ar9300_set_dcs_mode(struct ath_hal *ah, u_int32_t mode) 2201{ 2202 AH_PRIVATE(ah)->ah_dcs_enable = mode; 2203} 2204 2205u_int32_t 2206ar9300_get_dcs_mode(struct ath_hal *ah) 2207{ 2208 return AH_PRIVATE(ah)->ah_dcs_enable; 2209} 2210 2211#ifdef ATH_BT_COEX 2212void 2213ar9300_set_bt_coex_info(struct ath_hal *ah, HAL_BT_COEX_INFO *btinfo) 2214{ 2215 struct ath_hal_9300 *ahp = AH9300(ah); 2216 2217 ahp->ah_bt_module = btinfo->bt_module; 2218 ahp->ah_bt_coex_config_type = btinfo->bt_coex_config; 2219 ahp->ah_bt_active_gpio_select = btinfo->bt_gpio_bt_active; 2220 ahp->ah_bt_priority_gpio_select = btinfo->bt_gpio_bt_priority; 2221 ahp->ah_wlan_active_gpio_select = btinfo->bt_gpio_wlan_active; 2222 ahp->ah_bt_active_polarity = btinfo->bt_active_polarity; 2223 ahp->ah_bt_coex_single_ant = btinfo->bt_single_ant; 2224 ahp->ah_bt_wlan_isolation = btinfo->bt_isolation; 2225} 2226 2227void 2228ar9300_bt_coex_config(struct ath_hal *ah, HAL_BT_COEX_CONFIG *btconf) 2229{ 2230 struct ath_hal_9300 *ahp = AH9300(ah); 2231 HAL_BOOL rx_clear_polarity; 2232 2233 /* 2234 * For Kiwi and Osprey, the polarity of rx_clear is active high. 2235 * The bt_rxclear_polarity flag from ath_dev needs to be inverted. 2236 */ 2237 rx_clear_polarity = !btconf->bt_rxclear_polarity; 2238 2239 ahp->ah_bt_coex_mode = (ahp->ah_bt_coex_mode & AR_BT_QCU_THRESH) | 2240 SM(btconf->bt_time_extend, AR_BT_TIME_EXTEND) | 2241 SM(btconf->bt_txstate_extend, AR_BT_TXSTATE_EXTEND) | 2242 SM(btconf->bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) | 2243 SM(btconf->bt_mode, AR_BT_MODE) | 2244 SM(btconf->bt_quiet_collision, AR_BT_QUIET) | 2245 SM(rx_clear_polarity, AR_BT_RX_CLEAR_POLARITY) | 2246 SM(btconf->bt_priority_time, AR_BT_PRIORITY_TIME) | 2247 SM(btconf->bt_first_slot_time, AR_BT_FIRST_SLOT_TIME); 2248 2249 ahp->ah_bt_coex_mode2 |= SM(btconf->bt_hold_rxclear, AR_BT_HOLD_RX_CLEAR); 2250 2251 if (ahp->ah_bt_coex_single_ant == AH_FALSE) { 2252 /* Enable ACK to go out even though BT has higher priority. */ 2253 ahp->ah_bt_coex_mode2 |= AR_BT_DISABLE_BT_ANT; 2254 } 2255} 2256 2257void 2258ar9300_bt_coex_set_qcu_thresh(struct ath_hal *ah, int qnum) 2259{ 2260 struct ath_hal_9300 *ahp = AH9300(ah); 2261 2262 /* clear the old value, then set the new value */ 2263 ahp->ah_bt_coex_mode &= ~AR_BT_QCU_THRESH; 2264 ahp->ah_bt_coex_mode |= SM(qnum, AR_BT_QCU_THRESH); 2265} 2266 2267void 2268ar9300_bt_coex_set_weights(struct ath_hal *ah, u_int32_t stomp_type) 2269{ 2270 struct ath_hal_9300 *ahp = AH9300(ah); 2271 2272 ahp->ah_bt_coex_bt_weight[0] = AR9300_BT_WGHT; 2273 ahp->ah_bt_coex_bt_weight[1] = AR9300_BT_WGHT; 2274 ahp->ah_bt_coex_bt_weight[2] = AR9300_BT_WGHT; 2275 ahp->ah_bt_coex_bt_weight[3] = AR9300_BT_WGHT; 2276 2277 switch (stomp_type) { 2278 case HAL_BT_COEX_STOMP_ALL: 2279 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_ALL_WLAN_WGHT0; 2280 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_ALL_WLAN_WGHT1; 2281 break; 2282 case HAL_BT_COEX_STOMP_LOW: 2283 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_LOW_WLAN_WGHT0; 2284 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_LOW_WLAN_WGHT1; 2285 break; 2286 case HAL_BT_COEX_STOMP_ALL_FORCE: 2287 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_ALL_FORCE_WLAN_WGHT0; 2288 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_ALL_FORCE_WLAN_WGHT1; 2289 break; 2290 case HAL_BT_COEX_STOMP_LOW_FORCE: 2291 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_LOW_FORCE_WLAN_WGHT0; 2292 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_LOW_FORCE_WLAN_WGHT1; 2293 break; 2294 case HAL_BT_COEX_STOMP_NONE: 2295 case HAL_BT_COEX_NO_STOMP: 2296 ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_NONE_WLAN_WGHT0; 2297 ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_NONE_WLAN_WGHT1; 2298 break; 2299 default: 2300 /* There is a force_weight from registry */ 2301 ahp->ah_bt_coex_wlan_weight[0] = stomp_type; 2302 ahp->ah_bt_coex_wlan_weight[1] = stomp_type; 2303 break; 2304 } 2305} 2306 2307void 2308ar9300_bt_coex_setup_bmiss_thresh(struct ath_hal *ah, u_int32_t thresh) 2309{ 2310 struct ath_hal_9300 *ahp = AH9300(ah); 2311 2312 /* clear the old value, then set the new value */ 2313 ahp->ah_bt_coex_mode2 &= ~AR_BT_BCN_MISS_THRESH; 2314 ahp->ah_bt_coex_mode2 |= SM(thresh, AR_BT_BCN_MISS_THRESH); 2315} 2316 2317static void 2318ar9300_bt_coex_antenna_diversity(struct ath_hal *ah, u_int32_t value) 2319{ 2320 struct ath_hal_9300 *ahp = AH9300(ah); 2321#if ATH_ANT_DIV_COMB 2322 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 2323 HAL_CHANNEL *chan = (HAL_CHANNEL *) ahpriv->ah_curchan; 2324#endif 2325 2326 if (ahp->ah_bt_coex_flag & HAL_BT_COEX_FLAG_ANT_DIV_ALLOW) 2327 { 2328 if (ahp->ah_diversity_control == HAL_ANT_VARIABLE) 2329 { 2330 /* Config antenna diversity */ 2331#if ATH_ANT_DIV_COMB 2332 ar9300_ant_ctrl_set_lna_div_use_bt_ant(ah, value, chan); 2333#endif 2334 } 2335 } 2336} 2337 2338 2339void 2340ar9300_bt_coex_set_parameter(struct ath_hal *ah, u_int32_t type, 2341 u_int32_t value) 2342{ 2343 struct ath_hal_9300 *ahp = AH9300(ah); 2344 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 2345 2346 switch (type) { 2347 case HAL_BT_COEX_SET_ACK_PWR: 2348 if (value) { 2349 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_LOW_ACK_PWR; 2350 } else { 2351 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_LOW_ACK_PWR; 2352 } 2353 ar9300_set_tx_power_limit(ah, ahpriv->ah_power_limit, 2354 ahpriv->ah_extra_txpow, 0); 2355 break; 2356 2357 case HAL_BT_COEX_ANTENNA_DIVERSITY: 2358 if (AR_SREV_POSEIDON(ah)) { 2359 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_ANT_DIV_ALLOW; 2360 if (value) { 2361 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_ANT_DIV_ENABLE; 2362 } 2363 else { 2364 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_ANT_DIV_ENABLE; 2365 } 2366 ar9300_bt_coex_antenna_diversity(ah, value); 2367 } 2368 break; 2369 case HAL_BT_COEX_LOWER_TX_PWR: 2370 if (value) { 2371 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_LOWER_TX_PWR; 2372 } 2373 else { 2374 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_LOWER_TX_PWR; 2375 } 2376 ar9300_set_tx_power_limit(ah, ahpriv->ah_power_limit, 2377 ahpriv->ah_extra_txpow, 0); 2378 break; 2379#if ATH_SUPPORT_MCI 2380 case HAL_BT_COEX_MCI_MAX_TX_PWR: 2381 if ((ahpriv->ah_config.ath_hal_mci_config & 2382 ATH_MCI_CONFIG_CONCUR_TX) == ATH_MCI_CONCUR_TX_SHARED_CHN) 2383 { 2384 if (value) { 2385 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR; 2386 ahp->ah_mci_concur_tx_en = AH_TRUE; 2387 } 2388 else { 2389 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR; 2390 ahp->ah_mci_concur_tx_en = AH_FALSE; 2391 } 2392 ar9300_set_tx_power_limit(ah, ahpriv->ah_power_limit, 2393 ahpriv->ah_extra_txpow, 0); 2394 } 2395 HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) concur_tx_en = %d\n", 2396 ahp->ah_mci_concur_tx_en); 2397 break; 2398 case HAL_BT_COEX_MCI_FTP_STOMP_RX: 2399 if (value) { 2400 ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX; 2401 } 2402 else { 2403 ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX; 2404 } 2405 break; 2406#endif 2407 default: 2408 break; 2409 } 2410} 2411 2412void 2413ar9300_bt_coex_disable(struct ath_hal *ah) 2414{ 2415 struct ath_hal_9300 *ahp = AH9300(ah); 2416 2417 /* Always drive rx_clear_external output as 0 */ 2418 ath_hal_gpio_cfg_output(ah, ahp->ah_wlan_active_gpio_select, 2419 HAL_GPIO_OUTPUT_MUX_AS_OUTPUT); 2420 2421 if (ahp->ah_bt_coex_single_ant == AH_TRUE) { 2422 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1); 2423 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0); 2424 } 2425 2426 OS_REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE); 2427 OS_REG_WRITE(ah, AR_BT_COEX_MODE2, 0); 2428 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, 0); 2429 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, 0); 2430 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS0, 0); 2431 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS1, 0); 2432 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS2, 0); 2433 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS3, 0); 2434 2435 ahp->ah_bt_coex_enabled = AH_FALSE; 2436} 2437 2438int 2439ar9300_bt_coex_enable(struct ath_hal *ah) 2440{ 2441 struct ath_hal_9300 *ahp = AH9300(ah); 2442 2443 /* Program coex mode and weight registers to actually enable coex */ 2444 OS_REG_WRITE(ah, AR_BT_COEX_MODE, ahp->ah_bt_coex_mode); 2445 OS_REG_WRITE(ah, AR_BT_COEX_MODE2, ahp->ah_bt_coex_mode2); 2446 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, ahp->ah_bt_coex_wlan_weight[0]); 2447 OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, ahp->ah_bt_coex_wlan_weight[1]); 2448 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS0, ahp->ah_bt_coex_bt_weight[0]); 2449 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS1, ahp->ah_bt_coex_bt_weight[1]); 2450 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS2, ahp->ah_bt_coex_bt_weight[2]); 2451 OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS3, ahp->ah_bt_coex_bt_weight[3]); 2452 2453 if (ahp->ah_bt_coex_flag & HAL_BT_COEX_FLAG_LOW_ACK_PWR) { 2454 OS_REG_WRITE(ah, AR_TPC, HAL_BT_COEX_LOW_ACK_POWER); 2455 } else { 2456 OS_REG_WRITE(ah, AR_TPC, HAL_BT_COEX_HIGH_ACK_POWER); 2457 } 2458 2459 OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1); 2460 if (ahp->ah_bt_coex_single_ant == AH_TRUE) { 2461 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 1); 2462 } else { 2463 OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0); 2464 } 2465 2466 if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_3WIRE) { 2467 /* For 3-wire, configure the desired GPIO port for rx_clear */ 2468 ath_hal_gpio_cfg_output(ah, 2469 ahp->ah_wlan_active_gpio_select, 2470 HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE); 2471 } 2472 else if ((ahp->ah_bt_coex_config_type >= HAL_BT_COEX_CFG_2WIRE_2CH) && 2473 (ahp->ah_bt_coex_config_type <= HAL_BT_COEX_CFG_2WIRE_CH0)) 2474 { 2475 /* For 2-wire, configure the desired GPIO port for TX_FRAME output */ 2476 ath_hal_gpio_cfg_output(ah, 2477 ahp->ah_wlan_active_gpio_select, 2478 HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME); 2479 } 2480 2481 /* 2482 * Enable a weak pull down on BT_ACTIVE. 2483 * When BT device is disabled, BT_ACTIVE might be floating. 2484 */ 2485 OS_REG_RMW(ah, AR_HOSTIF_REG(ah, AR_GPIO_PDPU), 2486 (AR_GPIO_PULL_DOWN << (ahp->ah_bt_active_gpio_select * 2)), 2487 (AR_GPIO_PDPU_OPTION << (ahp->ah_bt_active_gpio_select * 2))); 2488 2489 ahp->ah_bt_coex_enabled = AH_TRUE; 2490 2491 return 0; 2492} 2493 2494u_int32_t ar9300_get_bt_active_gpio(struct ath_hal *ah, u_int32_t reg) 2495{ 2496 return 0; 2497} 2498 2499u_int32_t ar9300_get_wlan_active_gpio(struct ath_hal *ah, u_int32_t reg,u_int32_t bOn) 2500{ 2501 return bOn; 2502} 2503 2504void 2505ar9300_init_bt_coex(struct ath_hal *ah) 2506{ 2507 struct ath_hal_9300 *ahp = AH9300(ah); 2508 2509 if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_3WIRE) { 2510 OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), 2511 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB | 2512 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB)); 2513 2514 /* 2515 * Set input mux for bt_prority_async and 2516 * bt_active_async to GPIO pins 2517 */ 2518 OS_REG_RMW_FIELD(ah, 2519 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1), 2520 AR_GPIO_INPUT_MUX1_BT_ACTIVE, 2521 ahp->ah_bt_active_gpio_select); 2522 OS_REG_RMW_FIELD(ah, 2523 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1), 2524 AR_GPIO_INPUT_MUX1_BT_PRIORITY, 2525 ahp->ah_bt_priority_gpio_select); 2526 2527 /* Configure the desired GPIO ports for input */ 2528 ath_hal_gpio_cfg_input(ah, ahp->ah_bt_active_gpio_select); 2529 ath_hal_gpio_cfg_input(ah, ahp->ah_bt_priority_gpio_select); 2530 2531 if (ahp->ah_bt_coex_enabled) { 2532 ar9300_bt_coex_enable(ah); 2533 } else { 2534 ar9300_bt_coex_disable(ah); 2535 } 2536 } 2537 else if ((ahp->ah_bt_coex_config_type >= HAL_BT_COEX_CFG_2WIRE_2CH) && 2538 (ahp->ah_bt_coex_config_type <= HAL_BT_COEX_CFG_2WIRE_CH0)) 2539 { 2540 /* 2-wire */ 2541 if (ahp->ah_bt_coex_enabled) { 2542 /* Connect bt_active_async to baseband */ 2543 OS_REG_CLR_BIT(ah, 2544 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), 2545 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF | 2546 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF)); 2547 OS_REG_SET_BIT(ah, 2548 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), 2549 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB); 2550 2551 /* 2552 * Set input mux for bt_prority_async and 2553 * bt_active_async to GPIO pins 2554 */ 2555 OS_REG_RMW_FIELD(ah, 2556 AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1), 2557 AR_GPIO_INPUT_MUX1_BT_ACTIVE, 2558 ahp->ah_bt_active_gpio_select); 2559 2560 /* Configure the desired GPIO ports for input */ 2561 ath_hal_gpio_cfg_input(ah, ahp->ah_bt_active_gpio_select); 2562 2563 /* Enable coexistence on initialization */ 2564 ar9300_bt_coex_enable(ah); 2565 } 2566 } 2567#if ATH_SUPPORT_MCI 2568 else if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_MCI) { 2569 if (ahp->ah_bt_coex_enabled) { 2570 ar9300_mci_bt_coex_enable(ah); 2571 } 2572 else { 2573 ar9300_mci_bt_coex_disable(ah); 2574 } 2575 } 2576#endif /* ATH_SUPPORT_MCI */ 2577} 2578 2579#endif /* ATH_BT_COEX */ 2580 2581HAL_STATUS ar9300_set_proxy_sta(struct ath_hal *ah, HAL_BOOL enable) 2582{ 2583 u_int32_t val; 2584 int wasp_mm_rev; 2585 2586#define AR_SOC_RST_REVISION_ID 0xB8060090 2587#define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) 2588 wasp_mm_rev = (REG_READ(AR_SOC_RST_REVISION_ID) & 2589 AR_SREV_REVISION_WASP_MINOR_MINOR_MASK) >> 2590 AR_SREV_REVISION_WASP_MINOR_MINOR_SHIFT; 2591#undef AR_SOC_RST_REVISION_ID 2592#undef REG_READ 2593 2594 /* 2595 * Azimuth (ProxySTA) Mode is only supported correctly by 2596 * Peacock or WASP 1.3.0.1 or later (hopefully) chips. 2597 * 2598 * Enable this feature for Scorpion at this time. The silicon 2599 * still needs to be validated. 2600 */ 2601 if (!(AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_AR9580) && 2602 !(AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_SCORPION) && 2603 !((AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_WASP) && 2604 ((AH_PRIVATE((ah))->ah_macRev > AR_SREV_REVISION_WASP_13) || 2605 (AH_PRIVATE((ah))->ah_macRev == AR_SREV_REVISION_WASP_13 && 2606 wasp_mm_rev >= 0 /* 1 */)))) 2607 { 2608 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "%s error: current chip (ver 0x%x, " 2609 "rev 0x%x, minor minor rev 0x%x) cannot support Azimuth Mode\n", 2610 __func__, AH_PRIVATE((ah))->ah_macVersion, 2611 AH_PRIVATE((ah))->ah_macRev, wasp_mm_rev); 2612 return HAL_ENOTSUPP; 2613 } 2614 2615 OS_REG_WRITE(ah, 2616 AR_MAC_PCU_LOGIC_ANALYZER, AR_MAC_PCU_LOGIC_ANALYZER_PSTABUG75996); 2617 2618 /* turn on mode bit[24] for proxy sta */ 2619 OS_REG_WRITE(ah, AR_PCU_MISC_MODE2, 2620 OS_REG_READ(ah, AR_PCU_MISC_MODE2) | AR_PCU_MISC_MODE2_PROXY_STA); 2621 2622 val = OS_REG_READ(ah, AR_AZIMUTH_MODE); 2623 if (enable) { 2624 val |= AR_AZIMUTH_KEY_SEARCH_AD1 | 2625 AR_AZIMUTH_CTS_MATCH_TX_AD2 | 2626 AR_AZIMUTH_BA_USES_AD1; 2627 /* turn off filter pass hold (bit 9) */ 2628 val &= ~AR_AZIMUTH_FILTER_PASS_HOLD; 2629 } else { 2630 val &= ~(AR_AZIMUTH_KEY_SEARCH_AD1 | 2631 AR_AZIMUTH_CTS_MATCH_TX_AD2 | 2632 AR_AZIMUTH_BA_USES_AD1); 2633 } 2634 OS_REG_WRITE(ah, AR_AZIMUTH_MODE, val); 2635 2636 /* enable promiscous mode */ 2637 OS_REG_WRITE(ah, AR_RX_FILTER, 2638 OS_REG_READ(ah, AR_RX_FILTER) | HAL_RX_FILTER_PROM); 2639 /* enable promiscous in azimuth mode */ 2640 OS_REG_WRITE(ah, AR_PCU_MISC_MODE2, AR_PCU_MISC_MODE2_PROM_VC_MODE); 2641 OS_REG_WRITE(ah, AR_MAC_PCU_LOGIC_ANALYZER, AR_MAC_PCU_LOGIC_ANALYZER_VC_MODE); 2642 2643 /* turn on filter pass hold (bit 9) */ 2644 OS_REG_WRITE(ah, AR_AZIMUTH_MODE, 2645 OS_REG_READ(ah, AR_AZIMUTH_MODE) | AR_AZIMUTH_FILTER_PASS_HOLD); 2646 2647 return HAL_OK; 2648} 2649 2650void ar9300_mat_enable(struct ath_hal *ah, int enable) 2651{ 2652 /* 2653 * MAT (s/w ProxySTA) implementation requires to turn off interrupt 2654 * mitigation and turn on key search always for better performance. 2655 */ 2656 struct ath_hal_9300 *ahp = AH9300(ah); 2657 struct ath_hal_private *ap = AH_PRIVATE(ah); 2658 2659 ahp->ah_intr_mitigation_rx = !enable; 2660 if (ahp->ah_intr_mitigation_rx) { 2661 /* 2662 * Enable Interrupt Mitigation for Rx. 2663 * If no build-specific limits for the rx interrupt mitigation 2664 * timer have been specified, use conservative defaults. 2665 */ 2666 #ifndef AH_RIMT_VAL_LAST 2667 #define AH_RIMT_LAST_MICROSEC 500 2668 #endif 2669 #ifndef AH_RIMT_VAL_FIRST 2670 #define AH_RIMT_FIRST_MICROSEC 2000 2671 #endif 2672 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, AH_RIMT_LAST_MICROSEC); 2673 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, AH_RIMT_FIRST_MICROSEC); 2674 } else { 2675 OS_REG_WRITE(ah, AR_RIMT, 0); 2676 } 2677 2678 ap->ah_enable_keysearch_always = !!enable; 2679 ar9300_enable_keysearch_always(ah, ap->ah_enable_keysearch_always); 2680} 2681 2682 2683void ar9300_enable_tpc(struct ath_hal *ah) 2684{ 2685 u_int32_t val = 0; 2686 2687 AH_PRIVATE(ah)->ah_config.ath_hal_desc_tpc = 1; 2688 2689 /* Enable TPC */ 2690 OS_REG_RMW_FIELD(ah, AR_PHY_PWRTX_MAX, AR_PHY_PER_PACKET_POWERTX_MAX, 1); 2691 2692 /* 2693 * Disable per chain power reduction since we are already 2694 * accounting for this in our calculations 2695 */ 2696 val = OS_REG_READ(ah, AR_PHY_POWER_TX_SUB); 2697 if (AR_SREV_WASP(ah)) { 2698 OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB, 2699 val & AR_PHY_POWER_TX_SUB_2_DISABLE); 2700 } else { 2701 OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB, 2702 val & AR_PHY_POWER_TX_SUB_3_DISABLE); 2703 } 2704} 2705 2706 2707/* 2708 * ar9300_force_tsf_sync 2709 * This function forces the TSF sync to the given bssid, this is implemented 2710 * as a temp hack to get the AoW demo, and is primarily used in the WDS client 2711 * mode of operation, where we sync the TSF to RootAP TSF values 2712 */ 2713void 2714ar9300_force_tsf_sync(struct ath_hal *ah, const u_int8_t *bssid, 2715 u_int16_t assoc_id) 2716{ 2717 ar9300_set_operating_mode(ah, HAL_M_STA); 2718 ar9300_write_associd(ah, bssid, assoc_id); 2719} 2720 2721void ar9300_chk_rssi_update_tx_pwr(struct ath_hal *ah, int rssi) 2722{ 2723 struct ath_hal_9300 *ahp = AH9300(ah); 2724 u_int32_t temp_obdb_reg_val = 0, temp_tcp_reg_val; 2725 u_int32_t temp_powertx_rate9_reg_val; 2726 int8_t olpc_power_offset = 0; 2727 int8_t tmp_olpc_val = 0; 2728 HAL_RSSI_TX_POWER old_greentx_status; 2729 u_int8_t target_power_val_t[ar9300_rate_size]; 2730 int8_t tmp_rss1_thr1, tmp_rss1_thr2; 2731 2732 if ((AH_PRIVATE(ah)->ah_opmode != HAL_M_STA) || 2733 !AH_PRIVATE(ah)->ah_config.ath_hal_sta_update_tx_pwr_enable) { 2734 return; 2735 } 2736 2737 old_greentx_status = AH_PRIVATE(ah)->green_tx_status; 2738 if (ahp->ah_hw_green_tx_enable) { 2739 tmp_rss1_thr1 = AR9485_HW_GREEN_TX_THRES1_DB; 2740 tmp_rss1_thr2 = AR9485_HW_GREEN_TX_THRES2_DB; 2741 } else { 2742 tmp_rss1_thr1 = WB225_SW_GREEN_TX_THRES1_DB; 2743 tmp_rss1_thr2 = WB225_SW_GREEN_TX_THRES2_DB; 2744 } 2745 2746 if ((AH_PRIVATE(ah)->ah_config.ath_hal_sta_update_tx_pwr_enable_S1) 2747 && (rssi > tmp_rss1_thr1)) 2748 { 2749 if (old_greentx_status != HAL_RSSI_TX_POWER_SHORT) { 2750 AH_PRIVATE(ah)->green_tx_status = HAL_RSSI_TX_POWER_SHORT; 2751 } 2752 } else if (AH_PRIVATE(ah)->ah_config.ath_hal_sta_update_tx_pwr_enable_S2 2753 && (rssi > tmp_rss1_thr2)) 2754 { 2755 if (old_greentx_status != HAL_RSSI_TX_POWER_MIDDLE) { 2756 AH_PRIVATE(ah)->green_tx_status = HAL_RSSI_TX_POWER_MIDDLE; 2757 } 2758 } else if (AH_PRIVATE(ah)->ah_config.ath_hal_sta_update_tx_pwr_enable_S3) { 2759 if (old_greentx_status != HAL_RSSI_TX_POWER_LONG) { 2760 AH_PRIVATE(ah)->green_tx_status = HAL_RSSI_TX_POWER_LONG; 2761 } 2762 } 2763 2764 /* If status is not change, don't do anything */ 2765 if (old_greentx_status == AH_PRIVATE(ah)->green_tx_status) { 2766 return; 2767 } 2768 2769 /* for Poseidon which ath_hal_sta_update_tx_pwr_enable is enabled */ 2770 if ((AH_PRIVATE(ah)->green_tx_status != HAL_RSSI_TX_POWER_NONE) 2771 && AR_SREV_POSEIDON(ah)) 2772 { 2773 if (ahp->ah_hw_green_tx_enable) { 2774 switch (AH_PRIVATE(ah)->green_tx_status) { 2775 case HAL_RSSI_TX_POWER_SHORT: 2776 /* 1. TxPower Config */ 2777 OS_MEMCPY(target_power_val_t, ar9485_hw_gtx_tp_distance_short, 2778 sizeof(target_power_val_t)); 2779 /* 1.1 Store OLPC Delta Calibration Offset*/ 2780 olpc_power_offset = 0; 2781 /* 2. Store OB/DB */ 2782 /* 3. Store TPC settting */ 2783 temp_tcp_reg_val = (SM(14, AR_TPC_ACK) | 2784 SM(14, AR_TPC_CTS) | 2785 SM(14, AR_TPC_CHIRP) | 2786 SM(14, AR_TPC_RPT)); 2787 /* 4. Store BB_powertx_rate9 value */ 2788 temp_powertx_rate9_reg_val = 2789 AR9485_BBPWRTXRATE9_HW_GREEN_TX_SHORT_VALUE; 2790 break; 2791 case HAL_RSSI_TX_POWER_MIDDLE: 2792 /* 1. TxPower Config */ 2793 OS_MEMCPY(target_power_val_t, ar9485_hw_gtx_tp_distance_middle, 2794 sizeof(target_power_val_t)); 2795 /* 1.1 Store OLPC Delta Calibration Offset*/ 2796 olpc_power_offset = 0; 2797 /* 2. Store OB/DB */ 2798 /* 3. Store TPC settting */ 2799 temp_tcp_reg_val = (SM(18, AR_TPC_ACK) | 2800 SM(18, AR_TPC_CTS) | 2801 SM(18, AR_TPC_CHIRP) | 2802 SM(18, AR_TPC_RPT)); 2803 /* 4. Store BB_powertx_rate9 value */ 2804 temp_powertx_rate9_reg_val = 2805 AR9485_BBPWRTXRATE9_HW_GREEN_TX_MIDDLE_VALUE; 2806 break; 2807 case HAL_RSSI_TX_POWER_LONG: 2808 default: 2809 /* 1. TxPower Config */ 2810 OS_MEMCPY(target_power_val_t, ahp->ah_default_tx_power, 2811 sizeof(target_power_val_t)); 2812 /* 1.1 Store OLPC Delta Calibration Offset*/ 2813 olpc_power_offset = 0; 2814 /* 2. Store OB/DB1/DB2 */ 2815 /* 3. Store TPC settting */ 2816 temp_tcp_reg_val = 2817 AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC]; 2818 /* 4. Store BB_powertx_rate9 value */ 2819 temp_powertx_rate9_reg_val = 2820 AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9]; 2821 break; 2822 } 2823 } else { 2824 switch (AH_PRIVATE(ah)->green_tx_status) { 2825 case HAL_RSSI_TX_POWER_SHORT: 2826 /* 1. TxPower Config */ 2827 OS_MEMCPY(target_power_val_t, wb225_sw_gtx_tp_distance_short, 2828 sizeof(target_power_val_t)); 2829 /* 1.1 Store OLPC Delta Calibration Offset*/ 2830 olpc_power_offset = 2831 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_SHORT_VALUE] - 2832 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE]; 2833 /* 2. Store OB/DB */ 2834 temp_obdb_reg_val = 2835 AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB]; 2836 temp_obdb_reg_val &= ~(AR_PHY_65NM_CH0_TXRF2_DB2G | 2837 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK | 2838 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK | 2839 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM); 2840 temp_obdb_reg_val |= (SM(5, AR_PHY_65NM_CH0_TXRF2_DB2G) | 2841 SM(WB225_OB_GREEN_TX_SHORT_VALUE, 2842 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK) | 2843 SM(WB225_OB_GREEN_TX_SHORT_VALUE, 2844 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK) | 2845 SM(WB225_OB_GREEN_TX_SHORT_VALUE, 2846 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM)); 2847 /* 3. Store TPC settting */ 2848 temp_tcp_reg_val = (SM(6, AR_TPC_ACK) | 2849 SM(6, AR_TPC_CTS) | 2850 SM(6, AR_TPC_CHIRP) | 2851 SM(6, AR_TPC_RPT)); 2852 /* 4. Store BB_powertx_rate9 value */ 2853 temp_powertx_rate9_reg_val = 2854 WB225_BBPWRTXRATE9_SW_GREEN_TX_SHORT_VALUE; 2855 break; 2856 case HAL_RSSI_TX_POWER_MIDDLE: 2857 /* 1. TxPower Config */ 2858 OS_MEMCPY(target_power_val_t, wb225_sw_gtx_tp_distance_middle, 2859 sizeof(target_power_val_t)); 2860 /* 1.1 Store OLPC Delta Calibration Offset*/ 2861 olpc_power_offset = 2862 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_MIDDLE_VALUE] - 2863 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE]; 2864 /* 2. Store OB/DB */ 2865 temp_obdb_reg_val = 2866 AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB]; 2867 temp_obdb_reg_val &= ~(AR_PHY_65NM_CH0_TXRF2_DB2G | 2868 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK | 2869 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK | 2870 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM); 2871 temp_obdb_reg_val |= (SM(5, AR_PHY_65NM_CH0_TXRF2_DB2G) | 2872 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE, 2873 AR_PHY_65NM_CH0_TXRF2_OB2G_CCK) | 2874 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE, 2875 AR_PHY_65NM_CH0_TXRF2_OB2G_PSK) | 2876 SM(WB225_OB_GREEN_TX_MIDDLE_VALUE, 2877 AR_PHY_65NM_CH0_TXRF2_OB2G_QAM)); 2878 /* 3. Store TPC settting */ 2879 temp_tcp_reg_val = (SM(14, AR_TPC_ACK) | 2880 SM(14, AR_TPC_CTS) | 2881 SM(14, AR_TPC_CHIRP) | 2882 SM(14, AR_TPC_RPT)); 2883 /* 4. Store BB_powertx_rate9 value */ 2884 temp_powertx_rate9_reg_val = 2885 WB225_BBPWRTXRATE9_SW_GREEN_TX_MIDDLE_VALUE; 2886 break; 2887 case HAL_RSSI_TX_POWER_LONG: 2888 default: 2889 /* 1. TxPower Config */ 2890 OS_MEMCPY(target_power_val_t, ahp->ah_default_tx_power, 2891 sizeof(target_power_val_t)); 2892 /* 1.1 Store OLPC Delta Calibration Offset*/ 2893 olpc_power_offset = 2894 wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_LONG_VALUE] - 2895 wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE]; 2896 /* 2. Store OB/DB1/DB2 */ 2897 temp_obdb_reg_val = 2898 AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB]; 2899 /* 3. Store TPC settting */ 2900 temp_tcp_reg_val = 2901 AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC]; 2902 /* 4. Store BB_powertx_rate9 value */ 2903 temp_powertx_rate9_reg_val = 2904 AH_PRIVATE(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9]; 2905 break; 2906 } 2907 } 2908 /* 1.1 Do OLPC Delta Calibration Offset */ 2909 tmp_olpc_val = 2910 (int8_t) AH_PRIVATE(ah)->ah_db2[POSEIDON_STORED_REG_G2_OLPC_OFFSET]; 2911 tmp_olpc_val += olpc_power_offset; 2912 OS_REG_RMW(ah, AR_PHY_TPC_11_B0, 2913 (tmp_olpc_val << AR_PHY_TPC_OLPC_GAIN_DELTA_S), 2914 AR_PHY_TPC_OLPC_GAIN_DELTA); 2915 2916 /* 1.2 TxPower Config */ 2917 ar9300_transmit_power_reg_write(ah, target_power_val_t); 2918 /* 2. Config OB/DB */ 2919 if (!ahp->ah_hw_green_tx_enable) { 2920 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF2, temp_obdb_reg_val); 2921 } 2922 /* 3. config TPC settting */ 2923 OS_REG_WRITE(ah, AR_TPC, temp_tcp_reg_val); 2924 /* 4. config BB_powertx_rate9 value */ 2925 OS_REG_WRITE(ah, AR_PHY_BB_POWERTX_RATE9, temp_powertx_rate9_reg_val); 2926 } 2927} 2928 2929void 2930ar9300_get_vow_stats( 2931 struct ath_hal *ah, HAL_VOWSTATS* p_stats, u_int8_t vow_reg_flags) 2932{ 2933 if (vow_reg_flags & AR_REG_TX_FRM_CNT) { 2934 p_stats->tx_frame_count = OS_REG_READ(ah, AR_TFCNT); 2935 } 2936 if (vow_reg_flags & AR_REG_RX_FRM_CNT) { 2937 p_stats->rx_frame_count = OS_REG_READ(ah, AR_RFCNT); 2938 } 2939 if (vow_reg_flags & AR_REG_RX_CLR_CNT) { 2940 p_stats->rx_clear_count = OS_REG_READ(ah, AR_RCCNT); 2941 } 2942 if (vow_reg_flags & AR_REG_CYCLE_CNT) { 2943 p_stats->cycle_count = OS_REG_READ(ah, AR_CCCNT); 2944 } 2945 if (vow_reg_flags & AR_REG_EXT_CYCLE_CNT) { 2946 p_stats->ext_cycle_count = OS_REG_READ(ah, AR_EXTRCCNT); 2947 } 2948} 2949/* 2950 * ar9300_is_skip_paprd_by_greentx 2951 * 2952 * This function check if we need to skip PAPRD tuning 2953 * when GreenTx in specific state. 2954 */ 2955HAL_BOOL 2956ar9300_is_skip_paprd_by_greentx(struct ath_hal *ah) 2957{ 2958 if (AR_SREV_POSEIDON(ah) && 2959 AH_PRIVATE(ah)->ah_config.ath_hal_sta_update_tx_pwr_enable && 2960 ((AH_PRIVATE(ah)->green_tx_status == HAL_RSSI_TX_POWER_SHORT) || 2961 (AH_PRIVATE(ah)->green_tx_status == HAL_RSSI_TX_POWER_MIDDLE))) 2962 { 2963 return AH_TRUE; 2964 } 2965 return AH_FALSE; 2966} 2967 2968void 2969ar9300_control_signals_for_green_tx_mode(struct ath_hal *ah) 2970{ 2971 unsigned int valid_obdb_0_b0 = 0x2d; // 5,5 - dB[0:2],oB[5:3] 2972 unsigned int valid_obdb_1_b0 = 0x25; // 4,5 - dB[0:2],oB[5:3] 2973 unsigned int valid_obdb_2_b0 = 0x1d; // 3,5 - dB[0:2],oB[5:3] 2974 unsigned int valid_obdb_3_b0 = 0x15; // 2,5 - dB[0:2],oB[5:3] 2975 unsigned int valid_obdb_4_b0 = 0xd; // 1,5 - dB[0:2],oB[5:3] 2976 struct ath_hal_9300 *ahp = AH9300(ah); 2977 2978 if (AR_SREV_POSEIDON(ah) && ahp->ah_hw_green_tx_enable) { 2979 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, 2980 AR_PHY_PAPRD_VALID_OBDB_0, valid_obdb_0_b0); 2981 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, 2982 AR_PHY_PAPRD_VALID_OBDB_1, valid_obdb_1_b0); 2983 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, 2984 AR_PHY_PAPRD_VALID_OBDB_2, valid_obdb_2_b0); 2985 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, 2986 AR_PHY_PAPRD_VALID_OBDB_3, valid_obdb_3_b0); 2987 OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, 2988 AR_PHY_PAPRD_VALID_OBDB_4, valid_obdb_4_b0); 2989 } 2990} 2991 2992void ar9300_hwgreentx_set_pal_spare(struct ath_hal *ah, int value) 2993{ 2994 struct ath_hal_9300 *ahp = AH9300(ah); 2995 2996 if (AR_SREV_POSEIDON(ah) && ahp->ah_hw_green_tx_enable) { 2997 if ((value == 0) || (value == 1)) { 2998 OS_REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_TXRF3, 2999 AR_PHY_65NM_CH0_TXRF3_OLD_PAL_SPARE, value); 3000 } 3001 } 3002} 3003 3004void ar9300_reset_hw_beacon_proc_crc(struct ath_hal *ah) 3005{ 3006 OS_REG_SET_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_RESET_CRC); 3007} 3008 3009int32_t ar9300_get_hw_beacon_rssi(struct ath_hal *ah) 3010{ 3011 int32_t val = OS_REG_READ_FIELD(ah, AR_BCN_RSSI_AVE, AR_BCN_RSSI_AVE_VAL); 3012 3013 /* RSSI format is 8.4. Ignore lowest four bits */ 3014 val = val >> 4; 3015 return val; 3016} 3017 3018void ar9300_set_hw_beacon_rssi_threshold(struct ath_hal *ah, 3019 u_int32_t rssi_threshold) 3020{ 3021 struct ath_hal_9300 *ahp = AH9300(ah); 3022 3023 OS_REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_VAL, rssi_threshold); 3024 3025 /* save value for restoring after chip reset */ 3026 ahp->ah_beacon_rssi_threshold = rssi_threshold; 3027} 3028 3029void ar9300_reset_hw_beacon_rssi(struct ath_hal *ah) 3030{ 3031 OS_REG_SET_BIT(ah, AR_RSSI_THR, AR_RSSI_BCN_RSSI_RST); 3032} 3033 3034void ar9300_set_hw_beacon_proc(struct ath_hal *ah, HAL_BOOL on) 3035{ 3036 if (on) { 3037 OS_REG_SET_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_CRC_ENABLE | 3038 AR_HWBCNPROC1_EXCLUDE_TIM_ELM); 3039 } 3040 else { 3041 OS_REG_CLR_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_CRC_ENABLE | 3042 AR_HWBCNPROC1_EXCLUDE_TIM_ELM); 3043 } 3044} 3045/* 3046 * Gets the contents of the specified key cache entry. 3047 */ 3048HAL_BOOL 3049ar9300_print_keycache(struct ath_hal *ah) 3050{ 3051 3052 const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 3053 u_int32_t key0, key1, key2, key3, key4; 3054 u_int32_t mac_hi, mac_lo; 3055 u_int16_t entry = 0; 3056 u_int32_t valid = 0; 3057 u_int32_t key_type; 3058 3059 ath_hal_printf(ah, "Slot Key\t\t\t Valid Type Mac \n"); 3060 3061 for (entry = 0 ; entry < p_cap->hal_key_cache_size; entry++) { 3062 key0 = OS_REG_READ(ah, AR_KEYTABLE_KEY0(entry)); 3063 key1 = OS_REG_READ(ah, AR_KEYTABLE_KEY1(entry)); 3064 key2 = OS_REG_READ(ah, AR_KEYTABLE_KEY2(entry)); 3065 key3 = OS_REG_READ(ah, AR_KEYTABLE_KEY3(entry)); 3066 key4 = OS_REG_READ(ah, AR_KEYTABLE_KEY4(entry)); 3067 3068 key_type = OS_REG_READ(ah, AR_KEYTABLE_TYPE(entry)); 3069 3070 mac_lo = OS_REG_READ(ah, AR_KEYTABLE_MAC0(entry)); 3071 mac_hi = OS_REG_READ(ah, AR_KEYTABLE_MAC1(entry)); 3072 3073 if (mac_hi & AR_KEYTABLE_VALID) { 3074 valid = 1; 3075 } else { 3076 valid = 0; 3077 } 3078 3079 if ((mac_hi != 0) && (mac_lo != 0)) { 3080 mac_hi &= ~0x8000; 3081 mac_hi <<= 1; 3082 mac_hi |= ((mac_lo & (1 << 31) )) >> 31; 3083 mac_lo <<= 1; 3084 } 3085 3086 ath_hal_printf(ah, 3087 "%03d " 3088 "%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x" 3089 " %02d %02d " 3090 "%02x:%02x:%02x:%02x:%02x:%02x \n", 3091 entry, 3092 (key0 << 24) >> 24, (key0 << 16) >> 24, 3093 (key0 << 8) >> 24, key0 >> 24, 3094 (key1 << 24) >> 24, (key1 << 16) >> 24, 3095 //(key1 << 8) >> 24, key1 >> 24, 3096 (key2 << 24) >> 24, (key2 << 16) >> 24, 3097 (key2 << 8) >> 24, key2 >> 24, 3098 (key3 << 24) >> 24, (key3 << 16) >> 24, 3099 //(key3 << 8) >> 24, key3 >> 24, 3100 (key4 << 24) >> 24, (key4 << 16) >> 24, 3101 (key4 << 8) >> 24, key4 >> 24, 3102 valid, key_type, 3103 (mac_lo << 24) >> 24, (mac_lo << 16) >> 24, (mac_lo << 8) >> 24, 3104 (mac_lo) >> 24, (mac_hi << 24) >> 24, (mac_hi << 16) >> 24 ); 3105 } 3106 3107 return AH_TRUE; 3108} 3109 3110/* enable/disable smart antenna mode */ 3111HAL_BOOL ar9300_set_smart_antenna(struct ath_hal *ah, HAL_BOOL enable) 3112{ 3113 struct ath_hal_9300 *ahp = AH9300(ah); 3114 3115 if (enable) { 3116 OS_REG_SET_BIT(ah, AR_XRTO, AR_ENABLE_SMARTANTENNA); 3117 } else { 3118 OS_REG_CLR_BIT(ah, AR_XRTO, AR_ENABLE_SMARTANTENNA); 3119 } 3120 3121 /* if scropion and smart antenna is enabled, write swcom1 with 0x440 3122 * and swcom2 with 0 3123 * FIXME Ideally these registers need to be made read from caldata. 3124 * Until the calibration team gets them, keep them along with board 3125 * configuration. 3126 */ 3127 if (enable && AR_SREV_SCORPION(ah) && 3128 (HAL_OK == ar9300_get_capability(ah, HAL_CAP_SMARTANTENNA, 0,0))) { 3129 3130 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, 0x440); 3131 OS_REG_WRITE(ah, AR_PHY_SWITCH_COM_2, 0); 3132 } 3133 3134 ahp->ah_smartantenna_enable = enable; 3135 return 1; 3136} 3137 3138#ifdef ATH_TX99_DIAG 3139#ifndef ATH_SUPPORT_HTC 3140void 3141ar9300_tx99_channel_pwr_update(struct ath_hal *ah, HAL_CHANNEL *c, 3142 u_int32_t txpower) 3143{ 3144#define PWR_MAS(_r, _s) (((_r) & 0x3f) << (_s)) 3145 static int16_t p_pwr_array[ar9300_rate_size] = { 0 }; 3146 int32_t i; 3147 3148 /* The max power is limited to 63 */ 3149 if (txpower <= AR9300_MAX_RATE_POWER) { 3150 for (i = 0; i < ar9300_rate_size; i++) { 3151 p_pwr_array[i] = txpower; 3152 } 3153 } else { 3154 for (i = 0; i < ar9300_rate_size; i++) { 3155 p_pwr_array[i] = AR9300_MAX_RATE_POWER; 3156 } 3157 } 3158 3159 OS_REG_WRITE(ah, 0xa458, 0); 3160 3161 /* Write the OFDM power per rate set */ 3162 /* 6 (LSB), 9, 12, 18 (MSB) */ 3163 OS_REG_WRITE(ah, 0xa3c0, 3164 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 24) 3165 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 16) 3166 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 8) 3167 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0) 3168 ); 3169 /* 24 (LSB), 36, 48, 54 (MSB) */ 3170 OS_REG_WRITE(ah, 0xa3c4, 3171 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_54], 24) 3172 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_48], 16) 3173 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_36], 8) 3174 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0) 3175 ); 3176 3177 /* Write the CCK power per rate set */ 3178 /* 1L (LSB), reserved, 2L, 2S (MSB) */ 3179 OS_REG_WRITE(ah, 0xa3c8, 3180 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 24) 3181 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 16) 3182 /* | PWR_MAS(txPowerTimes2, 8) */ /* this is reserved for Osprey */ 3183 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0) 3184 ); 3185 /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */ 3186 OS_REG_WRITE(ah, 0xa3cc, 3187 PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_11S], 24) 3188 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_11L], 16) 3189 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_5S], 8) 3190 | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0) 3191 ); 3192 3193 /* Write the HT20 power per rate set */ 3194 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */ 3195 OS_REG_WRITE(ah, 0xa3d0, 3196 PWR_MAS(p_pwr_array[ALL_TARGET_HT20_5], 24) 3197 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_4], 16) 3198 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_1_3_9_11_17_19], 8) 3199 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_0_8_16], 0) 3200 ); 3201 3202 /* 6 (LSB), 7, 12, 13 (MSB) */ 3203 OS_REG_WRITE(ah, 0xa3d4, 3204 PWR_MAS(p_pwr_array[ALL_TARGET_HT20_13], 24) 3205 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_12], 16) 3206 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_7], 8) 3207 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_6], 0) 3208 ); 3209 3210 /* 14 (LSB), 15, 20, 21 */ 3211 OS_REG_WRITE(ah, 0xa3e4, 3212 PWR_MAS(p_pwr_array[ALL_TARGET_HT20_21], 24) 3213 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_20], 16) 3214 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_15], 8) 3215 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_14], 0) 3216 ); 3217 3218 /* Mixed HT20 and HT40 rates */ 3219 /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */ 3220 OS_REG_WRITE(ah, 0xa3e8, 3221 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_23], 24) 3222 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_22], 16) 3223 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_23], 8) 3224 | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_22], 0) 3225 ); 3226 3227 /* Write the HT40 power per rate set */ 3228 /* correct PAR difference between HT40 and HT20/LEGACY */ 3229 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */ 3230 OS_REG_WRITE(ah, 0xa3d8, 3231 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_5], 24) 3232 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_4], 16) 3233 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_1_3_9_11_17_19], 8) 3234 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_0_8_16], 0) 3235 ); 3236 3237 /* 6 (LSB), 7, 12, 13 (MSB) */ 3238 OS_REG_WRITE(ah, 0xa3dc, 3239 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_13], 24) 3240 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_12], 16) 3241 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_7], 8) 3242 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_6], 0) 3243 ); 3244 3245 /* 14 (LSB), 15, 20, 21 */ 3246 OS_REG_WRITE(ah, 0xa3ec, 3247 PWR_MAS(p_pwr_array[ALL_TARGET_HT40_21], 24) 3248 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_20], 16) 3249 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_15], 8) 3250 | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_14], 0) 3251 ); 3252#undef PWR_MAS 3253} 3254 3255void 3256ar9300_tx99_chainmsk_setup(struct ath_hal *ah, int tx_chainmask) 3257{ 3258 if (tx_chainmask == 0x5) { 3259 OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP, 3260 OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | AR_PHY_SWAP_ALT_CHAIN); 3261 } 3262 OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, tx_chainmask); 3263 OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, tx_chainmask); 3264 3265 OS_REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask); 3266 if (tx_chainmask == 0x5) { 3267 OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP, 3268 OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | AR_PHY_SWAP_ALT_CHAIN); 3269 } 3270} 3271 3272void 3273ar9300_tx99_set_single_carrier(struct ath_hal *ah, int tx_chain_mask, 3274 int chtype) 3275{ 3276 OS_REG_WRITE(ah, 0x98a4, OS_REG_READ(ah, 0x98a4) | (0x7ff << 11) | 0x7ff); 3277 OS_REG_WRITE(ah, 0xa364, OS_REG_READ(ah, 0xa364) | (1 << 7) | (1 << 1)); 3278 OS_REG_WRITE(ah, 0xa350, 3279 (OS_REG_READ(ah, 0xa350) | (1 << 31) | (1 << 15)) & ~(1 << 13)); 3280 3281 /* 11G mode */ 3282 if (!chtype) { 3283 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, 3284 OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) | (0x1 << 3) | (0x1 << 2)); 3285 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3286 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, 3287 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4)); 3288 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, 3289 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) 3290 | (0x1 << 26) | (0x7 << 24)) 3291 & ~(0x1 << 22)); 3292 } else { 3293 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, 3294 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4)); 3295 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, 3296 (OS_REG_READ(ah, AR_HORNET_CH0_TOP2) 3297 | (0x1 << 26) | (0x7 << 24)) 3298 & ~(0x1 << 22)); 3299 } 3300 3301 /* chain zero */ 3302 if ((tx_chain_mask & 0x01) == 0x01) { 3303 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX1, 3304 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX1) 3305 | (0x1 << 31) | (0x5 << 15) 3306 | (0x3 << 9)) & ~(0x1 << 27) 3307 & ~(0x1 << 12)); 3308 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, 3309 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) 3310 | (0x1 << 12) | (0x1 << 10) 3311 | (0x1 << 9) | (0x1 << 8) 3312 | (0x1 << 7)) & ~(0x1 << 11)); 3313 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, 3314 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) 3315 | (0x1 << 29) | (0x1 << 25) 3316 | (0x1 << 23) | (0x1 << 19) 3317 | (0x1 << 10) | (0x1 << 9) 3318 | (0x1 << 8) | (0x1 << 3)) 3319 & ~(0x1 << 28)& ~(0x1 << 24) 3320 & ~(0x1 << 22)& ~(0x1 << 7)); 3321 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, 3322 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) 3323 | (0x1 << 23))& ~(0x1 << 21)); 3324 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB1, 3325 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB1) 3326 | (0x1 << 12) | (0x1 << 10) 3327 | (0x1 << 9) | (0x1 << 8) 3328 | (0x1 << 6) | (0x1 << 5) 3329 | (0x1 << 4) | (0x1 << 3) 3330 | (0x1 << 2)); 3331 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB2, 3332 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB2) | (0x1 << 31)); 3333 } 3334 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3335 /* chain one */ 3336 if ((tx_chain_mask & 0x02) == 0x02 ) { 3337 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX1, 3338 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX1) 3339 | (0x1 << 31) | (0x5 << 15) 3340 | (0x3 << 9)) & ~(0x1 << 27) 3341 & ~(0x1 << 12)); 3342 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, 3343 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) 3344 | (0x1 << 12) | (0x1 << 10) 3345 | (0x1 << 9) | (0x1 << 8) 3346 | (0x1 << 7)) & ~(0x1 << 11)); 3347 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, 3348 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) 3349 | (0x1 << 29) | (0x1 << 25) 3350 | (0x1 << 23) | (0x1 << 19) 3351 | (0x1 << 10) | (0x1 << 9) 3352 | (0x1 << 8) | (0x1 << 3)) 3353 & ~(0x1 << 28)& ~(0x1 << 24) 3354 & ~(0x1 << 22)& ~(0x1 << 7)); 3355 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, 3356 (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) 3357 | (0x1 << 23))& ~(0x1 << 21)); 3358 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB1, 3359 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB1) 3360 | (0x1 << 12) | (0x1 << 10) 3361 | (0x1 << 9) | (0x1 << 8) 3362 | (0x1 << 6) | (0x1 << 5) 3363 | (0x1 << 4) | (0x1 << 3) 3364 | (0x1 << 2)); 3365 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB2, 3366 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB2) | (0x1 << 31)); 3367 } 3368 } 3369 if (AR_SREV_OSPREY(ah)) { 3370 /* chain two */ 3371 if ((tx_chain_mask & 0x04) == 0x04 ) { 3372 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX1, 3373 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX1) 3374 | (0x1 << 31) | (0x5 << 15) 3375 | (0x3 << 9)) & ~(0x1 << 27) 3376 & ~(0x1 << 12)); 3377 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, 3378 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) 3379 | (0x1 << 12) | (0x1 << 10) 3380 | (0x1 << 9) | (0x1 << 8) 3381 | (0x1 << 7)) & ~(0x1 << 11)); 3382 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, 3383 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) 3384 | (0x1 << 29) | (0x1 << 25) 3385 | (0x1 << 23) | (0x1 << 19) 3386 | (0x1 << 10) | (0x1 << 9) 3387 | (0x1 << 8) | (0x1 << 3)) 3388 & ~(0x1 << 28)& ~(0x1 << 24) 3389 & ~(0x1 << 22)& ~(0x1 << 7)); 3390 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, 3391 (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) 3392 | (0x1 << 23))& ~(0x1 << 21)); 3393 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB1, 3394 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB1) 3395 | (0x1 << 12) | (0x1 << 10) 3396 | (0x1 << 9) | (0x1 << 8) 3397 | (0x1 << 6) | (0x1 << 5) 3398 | (0x1 << 4) | (0x1 << 3) 3399 | (0x1 << 2)); 3400 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB2, 3401 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB2) | (0x1 << 31)); 3402 } 3403 } 3404 3405 OS_REG_WRITE(ah, 0xa28c, 0x11111); 3406 OS_REG_WRITE(ah, 0xa288, 0x111); 3407 } else { 3408 /* chain zero */ 3409 if ((tx_chain_mask & 0x01) == 0x01) { 3410 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX1, 3411 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX1) 3412 | (0x1 << 31) | (0x1 << 27) 3413 | (0x3 << 23) | (0x1 << 19) 3414 | (0x1 << 15) | (0x3 << 9)) 3415 & ~(0x1 << 12)); 3416 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, 3417 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) 3418 | (0x1 << 12) | (0x1 << 10) 3419 | (0x1 << 9) | (0x1 << 8) 3420 | (0x1 << 7) | (0x1 << 3) 3421 | (0x1 << 2) | (0x1 << 1)) 3422 & ~(0x1 << 11)& ~(0x1 << 0)); 3423 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, 3424 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) 3425 | (0x1 << 29) | (0x1 << 25) 3426 | (0x1 << 23) | (0x1 << 19) 3427 | (0x1 << 10) | (0x1 << 9) 3428 | (0x1 << 8) | (0x1 << 3)) 3429 & ~(0x1 << 28)& ~(0x1 << 24) 3430 & ~(0x1 << 22)& ~(0x1 << 7)); 3431 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, 3432 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) 3433 | (0x1 << 23))& ~(0x1 << 21)); 3434 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF2, 3435 OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF2) 3436 | (0x3 << 3) | (0x3 << 0)); 3437 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF3, 3438 (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF3) 3439 | (0x3 << 29) | (0x3 << 26) 3440 | (0x2 << 23) | (0x2 << 20) 3441 | (0x2 << 17))& ~(0x1 << 14)); 3442 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB1, 3443 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB1) 3444 | (0x1 << 12) | (0x1 << 10) 3445 | (0x1 << 9) | (0x1 << 8) 3446 | (0x1 << 6) | (0x1 << 5) 3447 | (0x1 << 4) | (0x1 << 3) 3448 | (0x1 << 2)); 3449 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB2, 3450 OS_REG_READ(ah, AR_PHY_65NM_CH0_BB2) | (0x1 << 31)); 3451 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3452 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, 3453 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4)); 3454 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, 3455 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) 3456 | (0x1 << 26) | (0x7 << 24) 3457 | (0x3 << 22)); 3458 } else { 3459 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, 3460 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4)); 3461 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, 3462 OS_REG_READ(ah, AR_HORNET_CH0_TOP2) 3463 | (0x1 << 26) | (0x7 << 24) 3464 | (0x3 << 22)); 3465 } 3466 3467 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3468 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, 3469 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) 3470 | (0x1 << 3) | (0x1 << 2) 3471 | (0x1 << 1)) & ~(0x1 << 0)); 3472 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, 3473 OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) 3474 | (0x1 << 19) | (0x1 << 3)); 3475 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, 3476 OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) | (0x1 << 23)); 3477 } 3478 if (AR_SREV_OSPREY(ah)) { 3479 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, 3480 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) 3481 | (0x1 << 3) | (0x1 << 2) 3482 | (0x1 << 1)) & ~(0x1 << 0)); 3483 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, 3484 OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) 3485 | (0x1 << 19) | (0x1 << 3)); 3486 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, 3487 OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) | (0x1 << 23)); 3488 } 3489 } 3490 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3491 /* chain one */ 3492 if ((tx_chain_mask & 0x02) == 0x02 ) { 3493 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, 3494 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) 3495 | (0x1 << 3) | (0x1 << 2) 3496 | (0x1 << 1)) & ~(0x1 << 0)); 3497 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, 3498 OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) 3499 | (0x1 << 19) | (0x1 << 3)); 3500 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, 3501 OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) | (0x1 << 23)); 3502 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3503 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, 3504 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4)); 3505 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, 3506 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) 3507 | (0x1 << 26) | (0x7 << 24) 3508 | (0x3 << 22)); 3509 } else { 3510 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, 3511 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4)); 3512 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, 3513 OS_REG_READ(ah, AR_HORNET_CH0_TOP2) 3514 | (0x1 << 26) | (0x7 << 24) 3515 | (0x3 << 22)); 3516 } 3517 3518 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX1, 3519 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX1) 3520 | (0x1 << 31) | (0x1 << 27) 3521 | (0x3 << 23) | (0x1 << 19) 3522 | (0x1 << 15) | (0x3 << 9)) 3523 & ~(0x1 << 12)); 3524 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, 3525 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) 3526 | (0x1 << 12) | (0x1 << 10) 3527 | (0x1 << 9) | (0x1 << 8) 3528 | (0x1 << 7) | (0x1 << 3) 3529 | (0x1 << 2) | (0x1 << 1)) 3530 & ~(0x1 << 11)& ~(0x1 << 0)); 3531 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, 3532 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) 3533 | (0x1 << 29) | (0x1 << 25) 3534 | (0x1 << 23) | (0x1 << 19) 3535 | (0x1 << 10) | (0x1 << 9) 3536 | (0x1 << 8) | (0x1 << 3)) 3537 & ~(0x1 << 28)& ~(0x1 << 24) 3538 & ~(0x1 << 22)& ~(0x1 << 7)); 3539 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, 3540 (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) 3541 | (0x1 << 23))& ~(0x1 << 21)); 3542 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF2, 3543 OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF2) 3544 | (0x3 << 3) | (0x3 << 0)); 3545 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF3, 3546 (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF3) 3547 | (0x3 << 29) | (0x3 << 26) 3548 | (0x2 << 23) | (0x2 << 20) 3549 | (0x2 << 17))& ~(0x1 << 14)); 3550 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB1, 3551 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB1) 3552 | (0x1 << 12) | (0x1 << 10) 3553 | (0x1 << 9) | (0x1 << 8) 3554 | (0x1 << 6) | (0x1 << 5) 3555 | (0x1 << 4) | (0x1 << 3) 3556 | (0x1 << 2)); 3557 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB2, 3558 OS_REG_READ(ah, AR_PHY_65NM_CH1_BB2) | (0x1 << 31)); 3559 3560 if (AR_SREV_OSPREY(ah)) { 3561 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, 3562 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) 3563 | (0x1 << 3) | (0x1 << 2) 3564 | (0x1 << 1)) & ~(0x1 << 0)); 3565 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, 3566 OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) 3567 | (0x1 << 19) | (0x1 << 3)); 3568 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, 3569 OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) | (0x1 << 23)); 3570 } 3571 } 3572 } 3573 if (AR_SREV_OSPREY(ah)) { 3574 /* chain two */ 3575 if ((tx_chain_mask & 0x04) == 0x04 ) { 3576 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, 3577 (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) 3578 | (0x1 << 3) | (0x1 << 2) 3579 | (0x1 << 1)) & ~(0x1 << 0)); 3580 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, 3581 OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) 3582 | (0x1 << 19) | (0x1 << 3)); 3583 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, 3584 OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) | (0x1 << 23)); 3585 if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3586 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, 3587 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4)); 3588 OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, 3589 OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) 3590 | (0x1 << 26) | (0x7 << 24) 3591 | (0x3 << 22)); 3592 } else { 3593 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, 3594 OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4)); 3595 OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, 3596 OS_REG_READ(ah, AR_HORNET_CH0_TOP2) 3597 | (0x1 << 26) | (0x7 << 24) 3598 | (0x3 << 22)); 3599 } 3600 3601 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, 3602 (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) 3603 | (0x1 << 3) | (0x1 << 2) 3604 | (0x1 << 1)) & ~(0x1 << 0)); 3605 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, 3606 OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) 3607 | (0x1 << 19) | (0x1 << 3)); 3608 OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, 3609 OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) | (0x1 << 23)); 3610 3611 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX1, 3612 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX1) 3613 | (0x1 << 31) | (0x1 << 27) 3614 | (0x3 << 23) | (0x1 << 19) 3615 | (0x1 << 15) | (0x3 << 9)) 3616 & ~(0x1 << 12)); 3617 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, 3618 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) 3619 | (0x1 << 12) | (0x1 << 10) 3620 | (0x1 << 9) | (0x1 << 8) 3621 | (0x1 << 7) | (0x1 << 3) 3622 | (0x1 << 2) | (0x1 << 1)) 3623 & ~(0x1 << 11)& ~(0x1 << 0)); 3624 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, 3625 (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) 3626 | (0x1 << 29) | (0x1 << 25) 3627 | (0x1 << 23) | (0x1 << 19) 3628 | (0x1 << 10) | (0x1 << 9) 3629 | (0x1 << 8) | (0x1 << 3)) 3630 & ~(0x1 << 28)& ~(0x1 << 24) 3631 & ~(0x1 << 22)& ~(0x1 << 7)); 3632 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, 3633 (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) 3634 | (0x1 << 23))& ~(0x1 << 21)); 3635 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF2, 3636 OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF2) 3637 | (0x3 << 3) | (0x3 << 0)); 3638 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF3, 3639 (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF3) 3640 | (0x3 << 29) | (0x3 << 26) 3641 | (0x2 << 23) | (0x2 << 20) 3642 | (0x2 << 17))& ~(0x1 << 14)); 3643 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB1, 3644 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB1) 3645 | (0x1 << 12) | (0x1 << 10) 3646 | (0x1 << 9) | (0x1 << 8) 3647 | (0x1 << 6) | (0x1 << 5) 3648 | (0x1 << 4) | (0x1 << 3) 3649 | (0x1 << 2)); 3650 OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB2, 3651 OS_REG_READ(ah, AR_PHY_65NM_CH2_BB2) | (0x1 << 31)); 3652 } 3653 } 3654 3655 OS_REG_WRITE(ah, 0xa28c, 0x22222); 3656 OS_REG_WRITE(ah, 0xa288, 0x222); 3657 } 3658} 3659 3660void 3661ar9300_tx99_start(struct ath_hal *ah, u_int8_t *data) 3662{ 3663 u_int32_t val; 3664 u_int32_t qnum = (u_int32_t)data; 3665 3666 /* Disable AGC to A2 */ 3667 OS_REG_WRITE(ah, AR_PHY_TEST, (OS_REG_READ(ah, AR_PHY_TEST) | PHY_AGC_CLR)); 3668 OS_REG_WRITE(ah, 0x9864, OS_REG_READ(ah, 0x9864) | 0x7f000); 3669 OS_REG_WRITE(ah, 0x9924, OS_REG_READ(ah, 0x9924) | 0x7f00fe); 3670 OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) &~ AR_DIAG_RX_DIS); 3671 3672 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* set receive disable */ 3673 /* set CW_MIN and CW_MAX both to 0, AIFS=2 */ 3674 OS_REG_WRITE(ah, AR_DLCL_IFS(qnum), 0); 3675 OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); /* 50 OK */ 3676 OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20); 3677 /* 200 ok for HT20, 400 ok for HT40 */ 3678 OS_REG_WRITE(ah, AR_TIME_OUT, 0x00000400); 3679 OS_REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff); 3680 3681 /* set QCU modes to early termination */ 3682 val = OS_REG_READ(ah, AR_QMISC(qnum)); 3683 OS_REG_WRITE(ah, AR_QMISC(qnum), val | AR_Q_MISC_DCU_EARLY_TERM_REQ); 3684} 3685 3686void 3687ar9300_tx99_stop(struct ath_hal *ah) 3688{ 3689 /* this should follow the setting of start */ 3690 OS_REG_WRITE(ah, AR_PHY_TEST, OS_REG_READ(ah, AR_PHY_TEST) &~ PHY_AGC_CLR); 3691 OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_RX_DIS); 3692} 3693#endif /* ATH_TX99_DIAG */ 3694#endif /* ATH_SUPPORT_HTC */ 3695 3696HAL_BOOL 3697ar9300Get3StreamSignature(struct ath_hal *ah) 3698{ 3699 return AH_FALSE; 3700} 3701 3702HAL_BOOL 3703ar9300ForceVCS(struct ath_hal *ah) 3704{ 3705 return AH_FALSE; 3706} 3707 3708HAL_BOOL 3709ar9300SetDfs3StreamFix(struct ath_hal *ah, u_int32_t val) 3710{ 3711 return AH_FALSE; 3712} 3713 3714#endif /* AH_SUPPORT_AR9300 */ 3715