1250003Sadrian/* 2250003Sadrian * Copyright (c) 2013 Qualcomm Atheros, Inc. 3250003Sadrian * 4250003Sadrian * Permission to use, copy, modify, and/or distribute this software for any 5250003Sadrian * purpose with or without fee is hereby granted, provided that the above 6250003Sadrian * copyright notice and this permission notice appear in all copies. 7250003Sadrian * 8250003Sadrian * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH 9250003Sadrian * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY 10250003Sadrian * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, 11250003Sadrian * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 12250003Sadrian * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR 13250003Sadrian * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 14250003Sadrian * PERFORMANCE OF THIS SOFTWARE. 15250003Sadrian */ 16250003Sadrian 17250003Sadrian#include "opt_ah.h" 18250003Sadrian 19250003Sadrian#include "ah.h" 20250003Sadrian#include "ah_internal.h" 21250003Sadrian#include "ah_devid.h" 22250003Sadrian#ifdef AH_DEBUG 23250003Sadrian#include "ah_desc.h" /* NB: for HAL_PHYERR* */ 24250003Sadrian#endif 25250003Sadrian 26250003Sadrian#include "ar9300/ar9300.h" 27250003Sadrian#include "ar9300/ar9300reg.h" 28250003Sadrian#include "ar9300/ar9300phy.h" 29250003Sadrian 30250003Sadrian 31250003Sadrianvoid 32250003Sadrianar9300_get_hw_hangs(struct ath_hal *ah, hal_hw_hangs_t *hangs) 33250003Sadrian{ 34250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 35250003Sadrian *hangs = 0; 36250003Sadrian 37250003Sadrian if (ar9300_get_capability(ah, HAL_CAP_BB_RIFS_HANG, 0, AH_NULL) == HAL_OK) { 38250003Sadrian *hangs |= HAL_RIFS_BB_HANG_WAR; 39250003Sadrian } 40250003Sadrian if (ar9300_get_capability(ah, HAL_CAP_BB_DFS_HANG, 0, AH_NULL) == HAL_OK) { 41250003Sadrian *hangs |= HAL_DFS_BB_HANG_WAR; 42250003Sadrian } 43250003Sadrian if (ar9300_get_capability(ah, HAL_CAP_BB_RX_CLEAR_STUCK_HANG, 0, AH_NULL) 44250003Sadrian == HAL_OK) 45250003Sadrian { 46250003Sadrian *hangs |= HAL_RX_STUCK_LOW_BB_HANG_WAR; 47250003Sadrian } 48250003Sadrian if (ar9300_get_capability(ah, HAL_CAP_MAC_HANG, 0, AH_NULL) == HAL_OK) { 49250003Sadrian *hangs |= HAL_MAC_HANG_WAR; 50250003Sadrian } 51250003Sadrian if (ar9300_get_capability(ah, HAL_CAP_PHYRESTART_CLR_WAR, 0, AH_NULL) 52250003Sadrian == HAL_OK) 53250003Sadrian { 54250003Sadrian *hangs |= HAL_PHYRESTART_CLR_WAR; 55250003Sadrian } 56250003Sadrian 57250003Sadrian ahp->ah_hang_wars = *hangs; 58250003Sadrian} 59250003Sadrian 60250008Sadrian/* 61250008Sadrian * XXX FreeBSD: the HAL version of ath_hal_mac_usec() knows about 62250008Sadrian * HT20, HT40, fast-clock, turbo mode, etc. 63250008Sadrian */ 64250003Sadrianstatic u_int 65250003Sadrianar9300_mac_to_usec(struct ath_hal *ah, u_int clks) 66250003Sadrian{ 67250008Sadrian#if 0 68250008Sadrian const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 69250003Sadrian 70250008Sadrian if (chan && IEEE80211_IS_CHAN_HT40(chan)) { 71250003Sadrian return (ath_hal_mac_usec(ah, clks) / 2); 72250003Sadrian } else { 73250003Sadrian return (ath_hal_mac_usec(ah, clks)); 74250003Sadrian } 75250008Sadrian#endif 76250008Sadrian return (ath_hal_mac_usec(ah, clks)); 77250003Sadrian} 78250003Sadrian 79250003Sadrianu_int 80250003Sadrianar9300_mac_to_clks(struct ath_hal *ah, u_int usecs) 81250003Sadrian{ 82250008Sadrian#if 0 83250008Sadrian const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 84250003Sadrian 85250008Sadrian if (chan && IEEE80211_IS_CHAN_HT40(chan)) { 86250003Sadrian return (ath_hal_mac_clks(ah, usecs) * 2); 87250003Sadrian } else { 88250003Sadrian return (ath_hal_mac_clks(ah, usecs)); 89250003Sadrian } 90250008Sadrian#endif 91250008Sadrian return (ath_hal_mac_clks(ah, usecs)); 92250003Sadrian} 93250003Sadrian 94250003Sadrianvoid 95250003Sadrianar9300_get_mac_address(struct ath_hal *ah, u_int8_t *mac) 96250003Sadrian{ 97250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 98250003Sadrian 99250003Sadrian OS_MEMCPY(mac, ahp->ah_macaddr, IEEE80211_ADDR_LEN); 100250003Sadrian} 101250003Sadrian 102250003SadrianHAL_BOOL 103250003Sadrianar9300_set_mac_address(struct ath_hal *ah, const u_int8_t *mac) 104250003Sadrian{ 105250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 106250003Sadrian 107250003Sadrian OS_MEMCPY(ahp->ah_macaddr, mac, IEEE80211_ADDR_LEN); 108250003Sadrian return AH_TRUE; 109250003Sadrian} 110250003Sadrian 111250003Sadrianvoid 112250003Sadrianar9300_get_bss_id_mask(struct ath_hal *ah, u_int8_t *mask) 113250003Sadrian{ 114250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 115250003Sadrian 116250003Sadrian OS_MEMCPY(mask, ahp->ah_bssid_mask, IEEE80211_ADDR_LEN); 117250003Sadrian} 118250003Sadrian 119250003SadrianHAL_BOOL 120250003Sadrianar9300_set_bss_id_mask(struct ath_hal *ah, const u_int8_t *mask) 121250003Sadrian{ 122250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 123250003Sadrian 124250003Sadrian /* save it since it must be rewritten on reset */ 125250003Sadrian OS_MEMCPY(ahp->ah_bssid_mask, mask, IEEE80211_ADDR_LEN); 126250003Sadrian 127250003Sadrian OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssid_mask)); 128250003Sadrian OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssid_mask + 4)); 129250003Sadrian return AH_TRUE; 130250003Sadrian} 131250003Sadrian 132250003Sadrian/* 133250003Sadrian * Attempt to change the cards operating regulatory domain to the given value 134250003Sadrian * Returns: A_EINVAL for an unsupported regulatory domain. 135250003Sadrian * A_HARDWARE for an unwritable EEPROM or bad EEPROM version 136250003Sadrian */ 137250003SadrianHAL_BOOL 138250003Sadrianar9300_set_regulatory_domain(struct ath_hal *ah, 139250003Sadrian u_int16_t reg_domain, HAL_STATUS *status) 140250003Sadrian{ 141250003Sadrian HAL_STATUS ecode; 142250003Sadrian 143250008Sadrian if (AH_PRIVATE(ah)->ah_currentRD == 0) { 144250008Sadrian AH_PRIVATE(ah)->ah_currentRD = reg_domain; 145250003Sadrian return AH_TRUE; 146250003Sadrian } 147250003Sadrian ecode = HAL_EIO; 148250003Sadrian 149250008Sadrian#if 0 150250003Sadrianbad: 151250003Sadrian#endif 152250003Sadrian if (status) { 153250003Sadrian *status = ecode; 154250003Sadrian } 155250003Sadrian return AH_FALSE; 156250003Sadrian} 157250003Sadrian 158250003Sadrian/* 159250003Sadrian * Return the wireless modes (a,b,g,t) supported by hardware. 160250003Sadrian * 161250003Sadrian * This value is what is actually supported by the hardware 162250003Sadrian * and is unaffected by regulatory/country code settings. 163250003Sadrian * 164250003Sadrian */ 165250003Sadrianu_int 166250003Sadrianar9300_get_wireless_modes(struct ath_hal *ah) 167250003Sadrian{ 168250008Sadrian return AH_PRIVATE(ah)->ah_caps.halWirelessModes; 169250003Sadrian} 170250003Sadrian 171250003Sadrian/* 172250003Sadrian * Set the interrupt and GPIO values so the ISR can disable RF 173250003Sadrian * on a switch signal. Assumes GPIO port and interrupt polarity 174250003Sadrian * are set prior to call. 175250003Sadrian */ 176250003Sadrianvoid 177250003Sadrianar9300_enable_rf_kill(struct ath_hal *ah) 178250003Sadrian{ 179250003Sadrian /* TODO - can this really be above the hal on the GPIO interface for 180250003Sadrian * TODO - the client only? 181250003Sadrian */ 182250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 183250003Sadrian 184250003Sadrian if (AR_SREV_JUPITER(ah) || AR_SREV_APHRODITE(ah)) { 185250003Sadrian /* Check RF kill GPIO before set/clear RFSILENT bits. */ 186250003Sadrian if (ar9300_gpio_get(ah, ahp->ah_gpio_select) == ahp->ah_polarity) { 187250003Sadrian OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_RFSILENT), 188250003Sadrian AR_RFSILENT_FORCE); 189250003Sadrian OS_REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB); 190250003Sadrian } 191250003Sadrian else { 192250003Sadrian OS_REG_CLR_BIT(ah, AR_HOSTIF_REG(ah, AR_RFSILENT), 193250003Sadrian AR_RFSILENT_FORCE); 194250003Sadrian OS_REG_CLR_BIT(ah, AR_PHY_TEST, RFSILENT_BB); 195250003Sadrian } 196250003Sadrian } 197250003Sadrian else { 198250003Sadrian /* Connect rfsilent_bb_l to baseband */ 199250003Sadrian OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), 200250003Sadrian AR_GPIO_INPUT_EN_VAL_RFSILENT_BB); 201250003Sadrian 202250003Sadrian /* Set input mux for rfsilent_bb_l to GPIO #0 */ 203250003Sadrian OS_REG_CLR_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2), 204250003Sadrian AR_GPIO_INPUT_MUX2_RFSILENT); 205250003Sadrian OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX2), 206250003Sadrian (ahp->ah_gpio_select & 0x0f) << 4); 207250003Sadrian 208250003Sadrian /* 209250003Sadrian * Configure the desired GPIO port for input and 210250003Sadrian * enable baseband rf silence 211250003Sadrian */ 212250008Sadrian ath_hal_gpioCfgInput(ah, ahp->ah_gpio_select); 213250003Sadrian OS_REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB); 214250003Sadrian } 215250003Sadrian 216250003Sadrian /* 217250003Sadrian * If radio disable switch connection to GPIO bit x is enabled 218250003Sadrian * program GPIO interrupt. 219250003Sadrian * If rfkill bit on eeprom is 1, setupeeprommap routine has already 220250003Sadrian * verified that it is a later version of eeprom, it has a place for 221250003Sadrian * rfkill bit and it is set to 1, indicating that GPIO bit x hardware 222250003Sadrian * connection is present. 223250003Sadrian */ 224250003Sadrian /* 225250003Sadrian * RFKill uses polling not interrupt, 226250003Sadrian * disable interrupt to avoid Eee PC 2.6.21.4 hang up issue 227250003Sadrian */ 228250003Sadrian if (ath_hal_hasrfkill_int(ah)) { 229250003Sadrian if (ahp->ah_gpio_bit == ar9300_gpio_get(ah, ahp->ah_gpio_select)) { 230250003Sadrian /* switch already closed, set to interrupt upon open */ 231250003Sadrian ar9300_gpio_set_intr(ah, ahp->ah_gpio_select, !ahp->ah_gpio_bit); 232250003Sadrian } else { 233250003Sadrian ar9300_gpio_set_intr(ah, ahp->ah_gpio_select, ahp->ah_gpio_bit); 234250003Sadrian } 235250003Sadrian } 236250003Sadrian} 237250003Sadrian 238250003Sadrian/* 239250003Sadrian * Change the LED blinking pattern to correspond to the connectivity 240250003Sadrian */ 241250003Sadrianvoid 242250003Sadrianar9300_set_led_state(struct ath_hal *ah, HAL_LED_STATE state) 243250003Sadrian{ 244250003Sadrian static const u_int32_t ledbits[8] = { 245250003Sadrian AR_CFG_LED_ASSOC_NONE, /* HAL_LED_RESET */ 246250003Sadrian AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_INIT */ 247250003Sadrian AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_READY */ 248250003Sadrian AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_SCAN */ 249250003Sadrian AR_CFG_LED_ASSOC_PENDING, /* HAL_LED_AUTH */ 250250003Sadrian AR_CFG_LED_ASSOC_ACTIVE, /* HAL_LED_ASSOC */ 251250003Sadrian AR_CFG_LED_ASSOC_ACTIVE, /* HAL_LED_RUN */ 252250003Sadrian AR_CFG_LED_ASSOC_NONE, 253250003Sadrian }; 254250003Sadrian 255250003Sadrian OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_ASSOC_CTL, ledbits[state]); 256250003Sadrian} 257250003Sadrian 258250003Sadrian/* 259250003Sadrian * Sets the Power LED on the cardbus without affecting the Network LED. 260250003Sadrian */ 261250003Sadrianvoid 262250003Sadrianar9300_set_power_led_state(struct ath_hal *ah, u_int8_t enabled) 263250003Sadrian{ 264250003Sadrian u_int32_t val; 265250003Sadrian 266250003Sadrian val = enabled ? AR_CFG_LED_MODE_POWER_ON : AR_CFG_LED_MODE_POWER_OFF; 267250003Sadrian OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_POWER, val); 268250003Sadrian} 269250003Sadrian 270250003Sadrian/* 271250003Sadrian * Sets the Network LED on the cardbus without affecting the Power LED. 272250003Sadrian */ 273250003Sadrianvoid 274250003Sadrianar9300_set_network_led_state(struct ath_hal *ah, u_int8_t enabled) 275250003Sadrian{ 276250003Sadrian u_int32_t val; 277250003Sadrian 278250003Sadrian val = enabled ? AR_CFG_LED_MODE_NETWORK_ON : AR_CFG_LED_MODE_NETWORK_OFF; 279250003Sadrian OS_REG_RMW_FIELD(ah, AR_CFG_LED, AR_CFG_LED_NETWORK, val); 280250003Sadrian} 281250003Sadrian 282250003Sadrian/* 283250003Sadrian * Change association related fields programmed into the hardware. 284250003Sadrian * Writing a valid BSSID to the hardware effectively enables the hardware 285250003Sadrian * to synchronize its TSF to the correct beacons and receive frames coming 286250003Sadrian * from that BSSID. It is called by the SME JOIN operation. 287250003Sadrian */ 288250003Sadrianvoid 289250003Sadrianar9300_write_associd(struct ath_hal *ah, const u_int8_t *bssid, 290250003Sadrian u_int16_t assoc_id) 291250003Sadrian{ 292250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 293250003Sadrian 294250003Sadrian /* save bssid and assoc_id for restore on reset */ 295250003Sadrian OS_MEMCPY(ahp->ah_bssid, bssid, IEEE80211_ADDR_LEN); 296250003Sadrian ahp->ah_assoc_id = assoc_id; 297250003Sadrian 298250003Sadrian OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid)); 299250003Sadrian OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4) | 300250003Sadrian ((assoc_id & 0x3fff) << AR_BSS_ID1_AID_S)); 301250003Sadrian} 302250003Sadrian 303250003Sadrian/* 304250003Sadrian * Get the current hardware tsf for stamlme 305250003Sadrian */ 306250003Sadrianu_int64_t 307250003Sadrianar9300_get_tsf64(struct ath_hal *ah) 308250003Sadrian{ 309250003Sadrian u_int64_t tsf; 310250003Sadrian 311250003Sadrian /* XXX sync multi-word read? */ 312250003Sadrian tsf = OS_REG_READ(ah, AR_TSF_U32); 313250003Sadrian tsf = (tsf << 32) | OS_REG_READ(ah, AR_TSF_L32); 314250003Sadrian return tsf; 315250003Sadrian} 316250003Sadrian 317250003Sadrianvoid 318250003Sadrianar9300_set_tsf64(struct ath_hal *ah, u_int64_t tsf) 319250003Sadrian{ 320250003Sadrian OS_REG_WRITE(ah, AR_TSF_L32, (tsf & 0xffffffff)); 321250003Sadrian OS_REG_WRITE(ah, AR_TSF_U32, ((tsf >> 32) & 0xffffffff)); 322250003Sadrian} 323250003Sadrian 324250003Sadrian/* 325250003Sadrian * Get the current hardware tsf for stamlme 326250003Sadrian */ 327250003Sadrianu_int32_t 328250003Sadrianar9300_get_tsf32(struct ath_hal *ah) 329250003Sadrian{ 330250003Sadrian return OS_REG_READ(ah, AR_TSF_L32); 331250003Sadrian} 332250003Sadrian 333250003Sadrianu_int32_t 334250003Sadrianar9300_get_tsf2_32(struct ath_hal *ah) 335250003Sadrian{ 336250003Sadrian return OS_REG_READ(ah, AR_TSF2_L32); 337250003Sadrian} 338250003Sadrian 339250003Sadrian/* 340250003Sadrian * Reset the current hardware tsf for stamlme. 341250003Sadrian */ 342250003Sadrianvoid 343250003Sadrianar9300_reset_tsf(struct ath_hal *ah) 344250003Sadrian{ 345250003Sadrian int count; 346250003Sadrian 347250003Sadrian count = 0; 348250003Sadrian while (OS_REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) { 349250003Sadrian count++; 350250003Sadrian if (count > 10) { 351250003Sadrian HALDEBUG(ah, HAL_DEBUG_RESET, 352250003Sadrian "%s: AR_SLP32_TSF_WRITE_STATUS limit exceeded\n", __func__); 353250003Sadrian break; 354250003Sadrian } 355250003Sadrian OS_DELAY(10); 356250003Sadrian } 357250003Sadrian OS_REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 358250003Sadrian} 359250003Sadrian 360250003Sadrian/* 361250003Sadrian * Set or clear hardware basic rate bit 362250003Sadrian * Set hardware basic rate set if basic rate is found 363250003Sadrian * and basic rate is equal or less than 2Mbps 364250003Sadrian */ 365250003Sadrianvoid 366250003Sadrianar9300_set_basic_rate(struct ath_hal *ah, HAL_RATE_SET *rs) 367250003Sadrian{ 368250008Sadrian const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 369250003Sadrian u_int32_t reg; 370250003Sadrian u_int8_t xset; 371250003Sadrian int i; 372250003Sadrian 373250008Sadrian if (chan == AH_NULL || !IEEE80211_IS_CHAN_CCK(chan)) { 374250003Sadrian return; 375250003Sadrian } 376250003Sadrian xset = 0; 377250003Sadrian for (i = 0; i < rs->rs_count; i++) { 378250003Sadrian u_int8_t rset = rs->rs_rates[i]; 379250003Sadrian /* Basic rate defined? */ 380250003Sadrian if ((rset & 0x80) && (rset &= 0x7f) >= xset) { 381250003Sadrian xset = rset; 382250003Sadrian } 383250003Sadrian } 384250003Sadrian /* 385250003Sadrian * Set the h/w bit to reflect whether or not the basic 386250003Sadrian * rate is found to be equal or less than 2Mbps. 387250003Sadrian */ 388250003Sadrian reg = OS_REG_READ(ah, AR_STA_ID1); 389250003Sadrian if (xset && xset / 2 <= 2) { 390250003Sadrian OS_REG_WRITE(ah, AR_STA_ID1, reg | AR_STA_ID1_BASE_RATE_11B); 391250003Sadrian } else { 392250003Sadrian OS_REG_WRITE(ah, AR_STA_ID1, reg &~ AR_STA_ID1_BASE_RATE_11B); 393250003Sadrian } 394250003Sadrian} 395250003Sadrian 396250003Sadrian/* 397250003Sadrian * Grab a semi-random value from hardware registers - may not 398250003Sadrian * change often 399250003Sadrian */ 400250003Sadrianu_int32_t 401250003Sadrianar9300_get_random_seed(struct ath_hal *ah) 402250003Sadrian{ 403250003Sadrian u_int32_t nf; 404250003Sadrian 405250003Sadrian nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff; 406250003Sadrian if (nf & 0x100) { 407250003Sadrian nf = 0 - ((nf ^ 0x1ff) + 1); 408250003Sadrian } 409250003Sadrian return (OS_REG_READ(ah, AR_TSF_U32) ^ 410250003Sadrian OS_REG_READ(ah, AR_TSF_L32) ^ nf); 411250003Sadrian} 412250003Sadrian 413250003Sadrian/* 414250003Sadrian * Detect if our card is present 415250003Sadrian */ 416250003SadrianHAL_BOOL 417250003Sadrianar9300_detect_card_present(struct ath_hal *ah) 418250003Sadrian{ 419250003Sadrian u_int16_t mac_version, mac_rev; 420250003Sadrian u_int32_t v; 421250003Sadrian 422250003Sadrian /* 423250003Sadrian * Read the Silicon Revision register and compare that 424250003Sadrian * to what we read at attach time. If the same, we say 425250003Sadrian * a card/device is present. 426250003Sadrian */ 427250003Sadrian v = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV)) & AR_SREV_ID; 428250003Sadrian if (v == 0xFF) { 429250003Sadrian /* new SREV format */ 430250003Sadrian v = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_SREV)); 431250003Sadrian /* 432250003Sadrian * Include 6-bit Chip Type (masked to 0) to differentiate 433250003Sadrian * from pre-Sowl versions 434250003Sadrian */ 435250003Sadrian mac_version = (v & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S; 436250003Sadrian mac_rev = MS(v, AR_SREV_REVISION2); 437250003Sadrian } else { 438250003Sadrian mac_version = MS(v, AR_SREV_VERSION); 439250003Sadrian mac_rev = v & AR_SREV_REVISION; 440250003Sadrian } 441250003Sadrian return (AH_PRIVATE(ah)->ah_macVersion == mac_version && 442250003Sadrian AH_PRIVATE(ah)->ah_macRev == mac_rev); 443250003Sadrian} 444250003Sadrian 445250003Sadrian/* 446250003Sadrian * Update MIB Counters 447250003Sadrian */ 448250003Sadrianvoid 449250003Sadrianar9300_update_mib_mac_stats(struct ath_hal *ah) 450250003Sadrian{ 451250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 452250003Sadrian HAL_MIB_STATS* stats = &ahp->ah_stats.ast_mibstats; 453250003Sadrian 454250003Sadrian stats->ackrcv_bad += OS_REG_READ(ah, AR_ACK_FAIL); 455250003Sadrian stats->rts_bad += OS_REG_READ(ah, AR_RTS_FAIL); 456250003Sadrian stats->fcs_bad += OS_REG_READ(ah, AR_FCS_FAIL); 457250003Sadrian stats->rts_good += OS_REG_READ(ah, AR_RTS_OK); 458250003Sadrian stats->beacons += OS_REG_READ(ah, AR_BEACON_CNT); 459250003Sadrian} 460250003Sadrian 461250003Sadrianvoid 462250003Sadrianar9300_get_mib_mac_stats(struct ath_hal *ah, HAL_MIB_STATS* stats) 463250003Sadrian{ 464250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 465250003Sadrian HAL_MIB_STATS* istats = &ahp->ah_stats.ast_mibstats; 466250003Sadrian 467250003Sadrian stats->ackrcv_bad = istats->ackrcv_bad; 468250003Sadrian stats->rts_bad = istats->rts_bad; 469250003Sadrian stats->fcs_bad = istats->fcs_bad; 470250003Sadrian stats->rts_good = istats->rts_good; 471250003Sadrian stats->beacons = istats->beacons; 472250003Sadrian} 473250003Sadrian 474250003Sadrian/* 475250003Sadrian * Detect if the HW supports spreading a CCK signal on channel 14 476250003Sadrian */ 477250003SadrianHAL_BOOL 478250003Sadrianar9300_is_japan_channel_spread_supported(struct ath_hal *ah) 479250003Sadrian{ 480250003Sadrian return AH_TRUE; 481250003Sadrian} 482250003Sadrian 483250003Sadrian/* 484250003Sadrian * Get the rssi of frame curently being received. 485250003Sadrian */ 486250003Sadrianu_int32_t 487250003Sadrianar9300_get_cur_rssi(struct ath_hal *ah) 488250003Sadrian{ 489250003Sadrian /* XXX return (OS_REG_READ(ah, AR_PHY_CURRENT_RSSI) & 0xff); */ 490250003Sadrian /* get combined RSSI */ 491250003Sadrian return (OS_REG_READ(ah, AR_PHY_RSSI_3) & 0xff); 492250003Sadrian} 493250003Sadrian 494250003Sadrian#if ATH_GEN_RANDOMNESS 495250003Sadrian/* 496250003Sadrian * Get the rssi value from BB on ctl chain0. 497250003Sadrian */ 498250003Sadrianu_int32_t 499250003Sadrianar9300_get_rssi_chain0(struct ath_hal *ah) 500250003Sadrian{ 501250003Sadrian /* get ctl chain0 RSSI */ 502250003Sadrian return OS_REG_READ(ah, AR_PHY_RSSI_0) & 0xff; 503250003Sadrian} 504250003Sadrian#endif 505250003Sadrian 506250003Sadrianu_int 507250003Sadrianar9300_get_def_antenna(struct ath_hal *ah) 508250003Sadrian{ 509250003Sadrian return (OS_REG_READ(ah, AR_DEF_ANTENNA) & 0x7); 510250003Sadrian} 511250003Sadrian 512250003Sadrian/* Setup coverage class */ 513250003Sadrianvoid 514250003Sadrianar9300_set_coverage_class(struct ath_hal *ah, u_int8_t coverageclass, int now) 515250003Sadrian{ 516250003Sadrian} 517250003Sadrian 518250003Sadrianvoid 519250003Sadrianar9300_set_def_antenna(struct ath_hal *ah, u_int antenna) 520250003Sadrian{ 521250003Sadrian OS_REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7)); 522250003Sadrian} 523250003Sadrian 524250003SadrianHAL_BOOL 525250003Sadrianar9300_set_antenna_switch(struct ath_hal *ah, 526250008Sadrian HAL_ANT_SETTING settings, const struct ieee80211_channel *chan, 527250008Sadrian u_int8_t *tx_chainmask, u_int8_t *rx_chainmask, u_int8_t *antenna_cfgd) 528250003Sadrian{ 529250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 530250003Sadrian 531250003Sadrian /* 532250003Sadrian * Owl does not support diversity or changing antennas. 533250003Sadrian * 534250003Sadrian * Instead this API and function are defined differently for AR9300. 535250003Sadrian * To support Tablet PC's, this interface allows the system 536250003Sadrian * to dramatically reduce the TX power on a particular chain. 537250003Sadrian * 538250003Sadrian * Based on the value of (redefined) diversity_control, the 539250003Sadrian * reset code will decrease power on chain 0 or chain 1/2. 540250003Sadrian * 541250003Sadrian * Based on the value of bit 0 of antenna_switch_swap, 542250003Sadrian * the mapping between OID call and chain is defined as: 543250003Sadrian * 0: map A -> 0, B -> 1; 544250003Sadrian * 1: map A -> 1, B -> 0; 545250003Sadrian * 546250003Sadrian * NOTE: 547250003Sadrian * The devices that use this OID should use a tx_chain_mask and 548250003Sadrian * tx_chain_select_legacy setting of 5 or 3 if ANTENNA_FIXED_B is 549250003Sadrian * used in order to ensure an active transmit antenna. This 550250003Sadrian * API will allow the host to turn off the only transmitting 551250003Sadrian * antenna to ensure the antenna closest to the user's body is 552250003Sadrian * powered-down. 553250003Sadrian */ 554250003Sadrian /* 555250003Sadrian * Set antenna control for use during reset sequence by 556250003Sadrian * ar9300_decrease_chain_power() 557250003Sadrian */ 558250003Sadrian ahp->ah_diversity_control = settings; 559250003Sadrian 560250003Sadrian return AH_TRUE; 561250003Sadrian} 562250003Sadrian 563250003SadrianHAL_BOOL 564250003Sadrianar9300_is_sleep_after_beacon_broken(struct ath_hal *ah) 565250003Sadrian{ 566250003Sadrian return AH_TRUE; 567250003Sadrian} 568250003Sadrian 569250003SadrianHAL_BOOL 570250003Sadrianar9300_set_slot_time(struct ath_hal *ah, u_int us) 571250003Sadrian{ 572250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 573250003Sadrian if (us < HAL_SLOT_TIME_9 || us > ar9300_mac_to_usec(ah, 0xffff)) { 574250003Sadrian HALDEBUG(ah, HAL_DEBUG_RESET, "%s: bad slot time %u\n", __func__, us); 575250003Sadrian ahp->ah_slot_time = (u_int) -1; /* restore default handling */ 576250003Sadrian return AH_FALSE; 577250003Sadrian } else { 578250003Sadrian /* convert to system clocks */ 579250003Sadrian OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ar9300_mac_to_clks(ah, us)); 580250003Sadrian ahp->ah_slot_time = us; 581250003Sadrian return AH_TRUE; 582250003Sadrian } 583250003Sadrian} 584250003Sadrian 585250003SadrianHAL_BOOL 586250003Sadrianar9300_set_ack_timeout(struct ath_hal *ah, u_int us) 587250003Sadrian{ 588250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 589250003Sadrian 590250003Sadrian if (us > ar9300_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) { 591250003Sadrian HALDEBUG(ah, HAL_DEBUG_RESET, "%s: bad ack timeout %u\n", __func__, us); 592250003Sadrian ahp->ah_ack_timeout = (u_int) -1; /* restore default handling */ 593250003Sadrian return AH_FALSE; 594250003Sadrian } else { 595250003Sadrian /* convert to system clocks */ 596250003Sadrian OS_REG_RMW_FIELD(ah, 597250003Sadrian AR_TIME_OUT, AR_TIME_OUT_ACK, ar9300_mac_to_clks(ah, us)); 598250003Sadrian ahp->ah_ack_timeout = us; 599250003Sadrian return AH_TRUE; 600250003Sadrian } 601250003Sadrian} 602250003Sadrian 603250003Sadrianu_int 604250003Sadrianar9300_get_ack_timeout(struct ath_hal *ah) 605250003Sadrian{ 606250003Sadrian u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK); 607250003Sadrian return ar9300_mac_to_usec(ah, clks); /* convert from system clocks */ 608250003Sadrian} 609250003Sadrian 610250003SadrianHAL_STATUS 611250003Sadrianar9300_set_quiet(struct ath_hal *ah, u_int32_t period, u_int32_t duration, 612250003Sadrian u_int32_t next_start, HAL_QUIET_FLAG flag) 613250003Sadrian{ 614250008Sadrian#define TU_TO_USEC(_tu) ((_tu) << 10) 615250003Sadrian HAL_STATUS status = HAL_EIO; 616250003Sadrian u_int32_t tsf = 0, j, next_start_us = 0; 617250003Sadrian if (flag & HAL_QUIET_ENABLE) { 618250003Sadrian for (j = 0; j < 2; j++) { 619250003Sadrian next_start_us = TU_TO_USEC(next_start); 620250003Sadrian tsf = OS_REG_READ(ah, AR_TSF_L32); 621250003Sadrian if ((!next_start) || (flag & HAL_QUIET_ADD_CURRENT_TSF)) { 622250003Sadrian next_start_us += tsf; 623250003Sadrian } 624250003Sadrian if (flag & HAL_QUIET_ADD_SWBA_RESP_TIME) { 625250003Sadrian next_start_us += 626250008Sadrian ah->ah_config.ah_sw_beacon_response_time; 627250003Sadrian } 628250003Sadrian OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1); 629250003Sadrian OS_REG_WRITE(ah, AR_QUIET2, SM(duration, AR_QUIET2_QUIET_DUR)); 630250003Sadrian OS_REG_WRITE(ah, AR_QUIET_PERIOD, TU_TO_USEC(period)); 631250003Sadrian OS_REG_WRITE(ah, AR_NEXT_QUIET_TIMER, next_start_us); 632250003Sadrian OS_REG_SET_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 633250003Sadrian if ((OS_REG_READ(ah, AR_TSF_L32) >> 10) == tsf >> 10) { 634250003Sadrian status = HAL_OK; 635250003Sadrian break; 636250003Sadrian } 637250003Sadrian HALDEBUG(ah, HAL_DEBUG_QUEUE, "%s: TSF have moved " 638250003Sadrian "while trying to set quiet time TSF: 0x%08x\n", __func__, tsf); 639250003Sadrian /* TSF shouldn't count twice or reg access is taking forever */ 640250003Sadrian HALASSERT(j < 1); 641250003Sadrian } 642250003Sadrian } else { 643250003Sadrian OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN); 644250003Sadrian status = HAL_OK; 645250003Sadrian } 646250003Sadrian 647250003Sadrian return status; 648250008Sadrian#undef TU_TO_USEC 649250003Sadrian} 650250003Sadrian#ifdef ATH_SUPPORT_DFS 651250003Sadrianvoid 652250003Sadrianar9300_cac_tx_quiet(struct ath_hal *ah, HAL_BOOL enable) 653250003Sadrian{ 654250003Sadrian u32 reg1, reg2; 655250003Sadrian 656250003Sadrian reg1 = OS_REG_READ(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE)); 657250003Sadrian reg2 = OS_REG_READ(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1)); 658250003Sadrian AH9300(ah)->ah_cac_quiet_enabled = enable; 659250003Sadrian 660250003Sadrian if (enable) { 661250003Sadrian OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE), 662250003Sadrian reg1 | AR_PCU_FORCE_QUIET_COLL); 663250003Sadrian OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1), 664250003Sadrian reg2 & ~AR_QUIET1_QUIET_ACK_CTS_ENABLE); 665250003Sadrian } else { 666250003Sadrian OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_MISC_MODE), 667250003Sadrian reg1 & ~AR_PCU_FORCE_QUIET_COLL); 668250003Sadrian OS_REG_WRITE(ah, AR_MAC_PCU_OFFSET(MAC_PCU_QUIET_TIME_1), 669250003Sadrian reg2 | AR_QUIET1_QUIET_ACK_CTS_ENABLE); 670250003Sadrian } 671250003Sadrian} 672250003Sadrian#endif /* ATH_SUPPORT_DFS */ 673250003Sadrian 674250003Sadrianvoid 675250003Sadrianar9300_set_pcu_config(struct ath_hal *ah) 676250003Sadrian{ 677250003Sadrian ar9300_set_operating_mode(ah, AH_PRIVATE(ah)->ah_opmode); 678250003Sadrian} 679250003Sadrian 680250003SadrianHAL_STATUS 681250003Sadrianar9300_get_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type, 682250003Sadrian u_int32_t capability, u_int32_t *result) 683250003Sadrian{ 684250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 685250003Sadrian const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 686250003Sadrian 687250003Sadrian switch (type) { 688250003Sadrian case HAL_CAP_CIPHER: /* cipher handled in hardware */ 689250003Sadrian switch (capability) { 690250003Sadrian case HAL_CIPHER_AES_CCM: 691250003Sadrian case HAL_CIPHER_AES_OCB: 692250003Sadrian case HAL_CIPHER_TKIP: 693250003Sadrian case HAL_CIPHER_WEP: 694250003Sadrian case HAL_CIPHER_MIC: 695250003Sadrian case HAL_CIPHER_CLR: 696250003Sadrian return HAL_OK; 697250003Sadrian default: 698250003Sadrian return HAL_ENOTSUPP; 699250003Sadrian } 700250003Sadrian case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */ 701250003Sadrian switch (capability) { 702250003Sadrian case 0: /* hardware capability */ 703250003Sadrian return HAL_OK; 704250003Sadrian case 1: 705250003Sadrian return (ahp->ah_sta_id1_defaults & 706250003Sadrian AR_STA_ID1_CRPT_MIC_ENABLE) ? HAL_OK : HAL_ENXIO; 707250003Sadrian default: 708250003Sadrian return HAL_ENOTSUPP; 709250003Sadrian } 710250003Sadrian case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */ 711250008Sadrian switch (capability) { 712250008Sadrian case 0: /* hardware capability */ 713250008Sadrian return p_cap->halTkipMicTxRxKeySupport ? HAL_ENXIO : HAL_OK; 714250008Sadrian case 1: /* current setting */ 715250008Sadrian return (ahp->ah_misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ? 716250008Sadrian HAL_ENXIO : HAL_OK; 717250008Sadrian default: 718250008Sadrian return HAL_ENOTSUPP; 719250008Sadrian } 720250003Sadrian case HAL_CAP_WME_TKIPMIC: 721250003Sadrian /* hardware can do TKIP MIC when WMM is turned on */ 722250003Sadrian return HAL_OK; 723250003Sadrian case HAL_CAP_PHYCOUNTERS: /* hardware PHY error counters */ 724250003Sadrian return HAL_OK; 725250003Sadrian case HAL_CAP_DIVERSITY: /* hardware supports fast diversity */ 726250003Sadrian switch (capability) { 727250003Sadrian case 0: /* hardware capability */ 728250003Sadrian return HAL_OK; 729250003Sadrian case 1: /* current setting */ 730250003Sadrian return (OS_REG_READ(ah, AR_PHY_CCK_DETECT) & 731250003Sadrian AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ? 732250003Sadrian HAL_OK : HAL_ENXIO; 733250003Sadrian } 734250003Sadrian return HAL_EINVAL; 735250003Sadrian case HAL_CAP_TPC: 736250003Sadrian switch (capability) { 737250003Sadrian case 0: /* hardware capability */ 738250003Sadrian return HAL_OK; 739250003Sadrian case 1: 740250008Sadrian return ah->ah_config.ath_hal_desc_tpc ? 741250003Sadrian HAL_OK : HAL_ENXIO; 742250003Sadrian } 743250003Sadrian return HAL_OK; 744250003Sadrian case HAL_CAP_PHYDIAG: /* radar pulse detection capability */ 745250003Sadrian return HAL_OK; 746250003Sadrian case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */ 747250003Sadrian switch (capability) { 748250003Sadrian case 0: /* hardware capability */ 749250003Sadrian return HAL_OK; 750250003Sadrian case 1: 751250003Sadrian if (OS_REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) { 752250003Sadrian /* 753250003Sadrian * Owl and Merlin have problems in mcast key search. 754250003Sadrian * Disable this cap. in Ad-hoc mode. see Bug 25776 and 755250003Sadrian * 26802 756250003Sadrian */ 757250003Sadrian return HAL_ENXIO; 758250003Sadrian } else { 759250003Sadrian return (ahp->ah_sta_id1_defaults & 760250003Sadrian AR_STA_ID1_MCAST_KSRCH) ? HAL_OK : HAL_ENXIO; 761250003Sadrian } 762250003Sadrian } 763250003Sadrian return HAL_EINVAL; 764250003Sadrian case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */ 765250003Sadrian switch (capability) { 766250003Sadrian case 0: /* hardware capability */ 767250008Sadrian return p_cap->halTsfAddSupport ? HAL_OK : HAL_ENOTSUPP; 768250003Sadrian case 1: 769250003Sadrian return (ahp->ah_misc_mode & AR_PCU_TX_ADD_TSF) ? 770250003Sadrian HAL_OK : HAL_ENXIO; 771250003Sadrian } 772250003Sadrian return HAL_EINVAL; 773250003Sadrian case HAL_CAP_RFSILENT: /* rfsilent support */ 774250003Sadrian if (capability == 3) { /* rfkill interrupt */ 775250003Sadrian /* 776250003Sadrian * XXX: Interrupt-based notification of RF Kill state 777250003Sadrian * changes not working yet. Report that this feature 778250003Sadrian * is not supported so that polling is used instead. 779250003Sadrian */ 780250003Sadrian return (HAL_ENOTSUPP); 781250003Sadrian } 782250003Sadrian return ath_hal_getcapability(ah, type, capability, result); 783250003Sadrian case HAL_CAP_4ADDR_AGGR: 784250003Sadrian return HAL_OK; 785250003Sadrian case HAL_CAP_BB_RIFS_HANG: 786250003Sadrian return HAL_ENOTSUPP; 787250003Sadrian case HAL_CAP_BB_DFS_HANG: 788250003Sadrian return HAL_ENOTSUPP; 789250003Sadrian case HAL_CAP_BB_RX_CLEAR_STUCK_HANG: 790250003Sadrian /* Track chips that are known to have BB hangs related 791250003Sadrian * to rx_clear stuck low. 792250003Sadrian */ 793250003Sadrian return HAL_ENOTSUPP; 794250003Sadrian case HAL_CAP_MAC_HANG: 795250003Sadrian /* Track chips that are known to have MAC hangs. 796250003Sadrian */ 797250003Sadrian return HAL_OK; 798250003Sadrian case HAL_CAP_RIFS_RX_ENABLED: 799250003Sadrian /* Is RIFS RX currently enabled */ 800250003Sadrian return (ahp->ah_rifs_enabled == AH_TRUE) ? HAL_OK : HAL_ENOTSUPP; 801250008Sadrian#if 0 802250003Sadrian case HAL_CAP_ANT_CFG_2GHZ: 803250008Sadrian *result = p_cap->halNumAntCfg2Ghz; 804250003Sadrian return HAL_OK; 805250003Sadrian case HAL_CAP_ANT_CFG_5GHZ: 806250008Sadrian *result = p_cap->halNumAntCfg5Ghz; 807250003Sadrian return HAL_OK; 808250003Sadrian case HAL_CAP_RX_STBC: 809250003Sadrian *result = p_cap->hal_rx_stbc_support; 810250003Sadrian return HAL_OK; 811250003Sadrian case HAL_CAP_TX_STBC: 812250003Sadrian *result = p_cap->hal_tx_stbc_support; 813250003Sadrian return HAL_OK; 814250008Sadrian#endif 815250003Sadrian case HAL_CAP_LDPC: 816250008Sadrian *result = p_cap->halLDPCSupport; 817250003Sadrian return HAL_OK; 818250003Sadrian case HAL_CAP_DYNAMIC_SMPS: 819250003Sadrian return HAL_OK; 820250003Sadrian case HAL_CAP_DS: 821250003Sadrian return (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah) || 822250008Sadrian (p_cap->halTxChainMask & 0x3) != 0x3 || 823250008Sadrian (p_cap->halRxChainMask & 0x3) != 0x3) ? 824250003Sadrian HAL_ENOTSUPP : HAL_OK; 825250003Sadrian case HAL_CAP_TS: 826250003Sadrian return (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_APHRODITE(ah) || 827250008Sadrian (p_cap->halTxChainMask & 0x7) != 0x7 || 828250008Sadrian (p_cap->halRxChainMask & 0x7) != 0x7) ? 829250003Sadrian HAL_ENOTSUPP : HAL_OK; 830250003Sadrian case HAL_CAP_OL_PWRCTRL: 831250003Sadrian return (ar9300_eeprom_get(ahp, EEP_OL_PWRCTRL)) ? 832250003Sadrian HAL_OK : HAL_ENOTSUPP; 833250003Sadrian case HAL_CAP_CRDC: 834250003Sadrian#if ATH_SUPPORT_CRDC 835250003Sadrian return (AR_SREV_WASP(ah) && 836250008Sadrian ah->ah_config.ath_hal_crdc_enable) ? 837250003Sadrian HAL_OK : HAL_ENOTSUPP; 838250003Sadrian#else 839250003Sadrian return HAL_ENOTSUPP; 840250003Sadrian#endif 841250008Sadrian#if 0 842250003Sadrian case HAL_CAP_MAX_WEP_TKIP_HT20_TX_RATEKBPS: 843250003Sadrian *result = (u_int32_t)(-1); 844250003Sadrian return HAL_OK; 845250003Sadrian case HAL_CAP_MAX_WEP_TKIP_HT40_TX_RATEKBPS: 846250003Sadrian *result = (u_int32_t)(-1); 847250003Sadrian return HAL_OK; 848250008Sadrian#endif 849250003Sadrian case HAL_CAP_BB_PANIC_WATCHDOG: 850250003Sadrian return HAL_OK; 851250003Sadrian case HAL_CAP_PHYRESTART_CLR_WAR: 852250003Sadrian if ((AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_OSPREY) && 853250003Sadrian (AH_PRIVATE((ah))->ah_macRev < AR_SREV_REVISION_AR9580_10)) 854250003Sadrian { 855250003Sadrian return HAL_OK; 856250003Sadrian } 857250003Sadrian else 858250003Sadrian { 859250003Sadrian return HAL_ENOTSUPP; 860250003Sadrian } 861250003Sadrian case HAL_CAP_ENTERPRISE_MODE: 862250003Sadrian *result = ahp->ah_enterprise_mode >> 16; 863250003Sadrian /* 864250003Sadrian * WAR for EV 77658 - Add delimiters to first sub-frame when using 865250003Sadrian * RTS/CTS with aggregation and non-enterprise Osprey. 866250003Sadrian * 867250003Sadrian * Bug fixed in AR9580/Peacock, Wasp1.1 and later 868250003Sadrian */ 869250008Sadrian if ((ahp->ah_enterprise_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE) && 870250003Sadrian !AR_SREV_AR9580_10_OR_LATER(ah) && (!AR_SREV_WASP(ah) || 871250003Sadrian AR_SREV_WASP_10(ah))) { 872250003Sadrian *result |= AH_ENT_RTSCTS_DELIM_WAR; 873250003Sadrian } 874250003Sadrian return HAL_OK; 875250003Sadrian case HAL_CAP_LDPCWAR: 876250003Sadrian /* WAR for RIFS+LDPC issue is required for all chips currently 877250003Sadrian * supported by ar9300 HAL. 878250003Sadrian */ 879250003Sadrian return HAL_OK; 880250003Sadrian case HAL_CAP_ENABLE_APM: 881250008Sadrian *result = p_cap->halApmEnable; 882250003Sadrian return HAL_OK; 883250003Sadrian case HAL_CAP_PCIE_LCR_EXTSYNC_EN: 884250003Sadrian return (p_cap->hal_pcie_lcr_extsync_en == AH_TRUE) ? HAL_OK : HAL_ENOTSUPP; 885250003Sadrian case HAL_CAP_PCIE_LCR_OFFSET: 886250003Sadrian *result = p_cap->hal_pcie_lcr_offset; 887250003Sadrian return HAL_OK; 888250003Sadrian case HAL_CAP_SMARTANTENNA: 889250003Sadrian /* FIXME A request is pending with h/w team to add feature bit in 890250003Sadrian * caldata to detect if board has smart antenna or not, once added 891250003Sadrian * we need to fix his piece of code to read and return value without 892250003Sadrian * any compile flags 893250003Sadrian */ 894250003Sadrian#if UMAC_SUPPORT_SMARTANTENNA 895250003Sadrian /* enable smart antenna for Peacock, Wasp and scorpion 896250003Sadrian for future chips need to modify */ 897250003Sadrian if (AR_SREV_AR9580_10(ah) || (AR_SREV_WASP(ah)) || AR_SREV_SCORPION(ah)) { 898250003Sadrian return HAL_OK; 899250003Sadrian } else { 900250003Sadrian return HAL_ENOTSUPP; 901250003Sadrian } 902250003Sadrian#else 903250003Sadrian return HAL_ENOTSUPP; 904250003Sadrian#endif 905250003Sadrian 906250003Sadrian#ifdef ATH_TRAFFIC_FAST_RECOVER 907250003Sadrian case HAL_CAP_TRAFFIC_FAST_RECOVER: 908250003Sadrian if (AR_SREV_HORNET(ah) || AR_SREV_POSEIDON(ah) || AR_SREV_WASP_11(ah)) { 909250003Sadrian return HAL_OK; 910250003Sadrian } else { 911250003Sadrian return HAL_ENOTSUPP; 912250003Sadrian } 913250003Sadrian#endif 914250003Sadrian default: 915250003Sadrian return ath_hal_getcapability(ah, type, capability, result); 916250003Sadrian } 917250003Sadrian} 918250003Sadrian 919250003SadrianHAL_BOOL 920250003Sadrianar9300_set_capability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type, 921250003Sadrian u_int32_t capability, u_int32_t setting, HAL_STATUS *status) 922250003Sadrian{ 923250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 924250003Sadrian const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 925250003Sadrian u_int32_t v; 926250003Sadrian 927250003Sadrian switch (type) { 928250008Sadrian case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */ 929250008Sadrian if (! p_cap->halTkipMicTxRxKeySupport) 930250008Sadrian return AH_FALSE; 931250008Sadrian 932250008Sadrian if (setting) 933250008Sadrian ahp->ah_misc_mode &= ~AR_PCU_MIC_NEW_LOC_ENA; 934250008Sadrian else 935250008Sadrian ahp->ah_misc_mode |= AR_PCU_MIC_NEW_LOC_ENA; 936250008Sadrian 937250008Sadrian OS_REG_WRITE(ah, AR_PCU_MISC, ahp->ah_misc_mode); 938250008Sadrian return AH_TRUE; 939250008Sadrian 940250003Sadrian case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */ 941250003Sadrian if (setting) { 942250003Sadrian ahp->ah_sta_id1_defaults |= AR_STA_ID1_CRPT_MIC_ENABLE; 943250003Sadrian } else { 944250003Sadrian ahp->ah_sta_id1_defaults &= ~AR_STA_ID1_CRPT_MIC_ENABLE; 945250003Sadrian } 946250003Sadrian return AH_TRUE; 947250003Sadrian case HAL_CAP_DIVERSITY: 948250003Sadrian v = OS_REG_READ(ah, AR_PHY_CCK_DETECT); 949250003Sadrian if (setting) { 950250003Sadrian v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; 951250003Sadrian } else { 952250003Sadrian v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV; 953250003Sadrian } 954250003Sadrian OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, v); 955250003Sadrian return AH_TRUE; 956250003Sadrian case HAL_CAP_DIAG: /* hardware diagnostic support */ 957250003Sadrian /* 958250003Sadrian * NB: could split this up into virtual capabilities, 959250003Sadrian * (e.g. 1 => ACK, 2 => CTS, etc.) but it hardly 960250003Sadrian * seems worth the additional complexity. 961250003Sadrian */ 962250003Sadrian#ifdef AH_DEBUG 963250003Sadrian AH_PRIVATE(ah)->ah_diagreg = setting; 964250003Sadrian#else 965250003Sadrian AH_PRIVATE(ah)->ah_diagreg = setting & 0x6; /* ACK+CTS */ 966250003Sadrian#endif 967250003Sadrian OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg); 968250003Sadrian return AH_TRUE; 969250003Sadrian case HAL_CAP_TPC: 970250008Sadrian ah->ah_config.ath_hal_desc_tpc = (setting != 0); 971250003Sadrian return AH_TRUE; 972250003Sadrian case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */ 973250003Sadrian if (setting) { 974250003Sadrian ahp->ah_sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH; 975250003Sadrian } else { 976250003Sadrian ahp->ah_sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH; 977250003Sadrian } 978250003Sadrian return AH_TRUE; 979250003Sadrian case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */ 980250008Sadrian if (p_cap->halTsfAddSupport) { 981250003Sadrian if (setting) { 982250003Sadrian ahp->ah_misc_mode |= AR_PCU_TX_ADD_TSF; 983250003Sadrian } else { 984250003Sadrian ahp->ah_misc_mode &= ~AR_PCU_TX_ADD_TSF; 985250003Sadrian } 986250003Sadrian return AH_TRUE; 987250003Sadrian } 988250003Sadrian return AH_FALSE; 989250003Sadrian case HAL_CAP_RXBUFSIZE: /* set MAC receive buffer size */ 990250003Sadrian ahp->rx_buf_size = setting & AR_DATABUF_MASK; 991250003Sadrian OS_REG_WRITE(ah, AR_DATABUF, ahp->rx_buf_size); 992250003Sadrian return AH_TRUE; 993250003Sadrian 994250003Sadrian /* fall thru... */ 995250003Sadrian default: 996250003Sadrian return ath_hal_setcapability(ah, type, capability, setting, status); 997250003Sadrian } 998250003Sadrian} 999250003Sadrian 1000250003Sadrian#ifdef AH_DEBUG 1001250003Sadrianstatic void 1002250003Sadrianar9300_print_reg(struct ath_hal *ah, u_int32_t args) 1003250003Sadrian{ 1004250003Sadrian u_int32_t i = 0; 1005250003Sadrian 1006250003Sadrian /* Read 0x80d0 to trigger pcie analyzer */ 1007250003Sadrian HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1008250003Sadrian "0x%04x 0x%08x\n", 0x80d0, OS_REG_READ(ah, 0x80d0)); 1009250003Sadrian 1010250003Sadrian if (args & HAL_DIAG_PRINT_REG_COUNTER) { 1011250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 1012250003Sadrian u_int32_t tf, rf, rc, cc; 1013250003Sadrian 1014250003Sadrian tf = OS_REG_READ(ah, AR_TFCNT); 1015250003Sadrian rf = OS_REG_READ(ah, AR_RFCNT); 1016250003Sadrian rc = OS_REG_READ(ah, AR_RCCNT); 1017250003Sadrian cc = OS_REG_READ(ah, AR_CCCNT); 1018250003Sadrian 1019250003Sadrian HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1020250003Sadrian "AR_TFCNT Diff= 0x%x\n", tf - ahp->last_tf); 1021250003Sadrian HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1022250003Sadrian "AR_RFCNT Diff= 0x%x\n", rf - ahp->last_rf); 1023250003Sadrian HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1024250003Sadrian "AR_RCCNT Diff= 0x%x\n", rc - ahp->last_rc); 1025250003Sadrian HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1026250003Sadrian "AR_CCCNT Diff= 0x%x\n", cc - ahp->last_cc); 1027250003Sadrian 1028250003Sadrian ahp->last_tf = tf; 1029250003Sadrian ahp->last_rf = rf; 1030250003Sadrian ahp->last_rc = rc; 1031250003Sadrian ahp->last_cc = cc; 1032250003Sadrian 1033250003Sadrian HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1034250003Sadrian "DMADBG0 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_0)); 1035250003Sadrian HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1036250003Sadrian "DMADBG1 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_1)); 1037250003Sadrian HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1038250003Sadrian "DMADBG2 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_2)); 1039250003Sadrian HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1040250003Sadrian "DMADBG3 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_3)); 1041250003Sadrian HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1042250003Sadrian "DMADBG4 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_4)); 1043250003Sadrian HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1044250003Sadrian "DMADBG5 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_5)); 1045250003Sadrian HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1046250003Sadrian "DMADBG6 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_6)); 1047250003Sadrian HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1048250003Sadrian "DMADBG7 = 0x%x\n", OS_REG_READ(ah, AR_DMADBG_7)); 1049250003Sadrian } 1050250003Sadrian 1051250003Sadrian if (args & HAL_DIAG_PRINT_REG_ALL) { 1052250003Sadrian for (i = 0x8; i <= 0xB8; i += sizeof(u_int32_t)) { 1053250003Sadrian HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1054250003Sadrian i, OS_REG_READ(ah, i)); 1055250003Sadrian } 1056250003Sadrian 1057250003Sadrian for (i = 0x800; i <= (0x800 + (10 << 2)); i += sizeof(u_int32_t)) { 1058250003Sadrian HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1059250003Sadrian i, OS_REG_READ(ah, i)); 1060250003Sadrian } 1061250003Sadrian 1062250003Sadrian HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1063250003Sadrian "0x%04x 0x%08x\n", 0x840, OS_REG_READ(ah, i)); 1064250003Sadrian 1065250003Sadrian HALDEBUG(ah, HAL_DEBUG_PRINT_REG, 1066250003Sadrian "0x%04x 0x%08x\n", 0x880, OS_REG_READ(ah, i)); 1067250003Sadrian 1068250003Sadrian for (i = 0x8C0; i <= (0x8C0 + (10 << 2)); i += sizeof(u_int32_t)) { 1069250003Sadrian HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1070250003Sadrian i, OS_REG_READ(ah, i)); 1071250003Sadrian } 1072250003Sadrian 1073250003Sadrian for (i = 0x1F00; i <= 0x1F04; i += sizeof(u_int32_t)) { 1074250003Sadrian HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1075250003Sadrian i, OS_REG_READ(ah, i)); 1076250003Sadrian } 1077250003Sadrian 1078250003Sadrian for (i = 0x4000; i <= 0x408C; i += sizeof(u_int32_t)) { 1079250003Sadrian HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1080250003Sadrian i, OS_REG_READ(ah, i)); 1081250003Sadrian } 1082250003Sadrian 1083250003Sadrian for (i = 0x5000; i <= 0x503C; i += sizeof(u_int32_t)) { 1084250003Sadrian HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1085250003Sadrian i, OS_REG_READ(ah, i)); 1086250003Sadrian } 1087250003Sadrian 1088250003Sadrian for (i = 0x7040; i <= 0x7058; i += sizeof(u_int32_t)) { 1089250003Sadrian HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1090250003Sadrian i, OS_REG_READ(ah, i)); 1091250003Sadrian } 1092250003Sadrian 1093250003Sadrian for (i = 0x8000; i <= 0x8098; i += sizeof(u_int32_t)) { 1094250003Sadrian HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1095250003Sadrian i, OS_REG_READ(ah, i)); 1096250003Sadrian } 1097250003Sadrian 1098250003Sadrian for (i = 0x80D4; i <= 0x8200; i += sizeof(u_int32_t)) { 1099250003Sadrian HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1100250003Sadrian i, OS_REG_READ(ah, i)); 1101250003Sadrian } 1102250003Sadrian 1103250003Sadrian for (i = 0x8240; i <= 0x97FC; i += sizeof(u_int32_t)) { 1104250003Sadrian HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1105250003Sadrian i, OS_REG_READ(ah, i)); 1106250003Sadrian } 1107250003Sadrian 1108250003Sadrian for (i = 0x9800; i <= 0x99f0; i += sizeof(u_int32_t)) { 1109250003Sadrian HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1110250003Sadrian i, OS_REG_READ(ah, i)); 1111250003Sadrian } 1112250003Sadrian 1113250003Sadrian for (i = 0x9c10; i <= 0x9CFC; i += sizeof(u_int32_t)) { 1114250003Sadrian HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1115250003Sadrian i, OS_REG_READ(ah, i)); 1116250003Sadrian } 1117250003Sadrian 1118250003Sadrian for (i = 0xA200; i <= 0xA26C; i += sizeof(u_int32_t)) { 1119250003Sadrian HALDEBUG(ah, HAL_DEBUG_PRINT_REG, "0x%04x 0x%08x\n", 1120250003Sadrian i, OS_REG_READ(ah, i)); 1121250003Sadrian } 1122250003Sadrian } 1123250003Sadrian} 1124250003Sadrian#endif 1125250003Sadrian 1126250003SadrianHAL_BOOL 1127250003Sadrianar9300_get_diag_state(struct ath_hal *ah, int request, 1128250003Sadrian const void *args, u_int32_t argsize, 1129250003Sadrian void **result, u_int32_t *resultsize) 1130250003Sadrian{ 1131250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 1132250003Sadrian 1133250003Sadrian (void) ahp; 1134250003Sadrian if (ath_hal_getdiagstate(ah, request, args, argsize, result, resultsize)) { 1135250003Sadrian return AH_TRUE; 1136250003Sadrian } 1137250003Sadrian switch (request) { 1138250003Sadrian#ifdef AH_PRIVATE_DIAG 1139250003Sadrian case HAL_DIAG_EEPROM: 1140250003Sadrian *result = &ahp->ah_eeprom; 1141250129Sadrian *resultsize = sizeof(ar9300_eeprom_t); 1142250003Sadrian return AH_TRUE; 1143250003Sadrian 1144250003Sadrian#if 0 /* XXX - TODO */ 1145250003Sadrian case HAL_DIAG_EEPROM_EXP_11A: 1146250003Sadrian case HAL_DIAG_EEPROM_EXP_11B: 1147250003Sadrian case HAL_DIAG_EEPROM_EXP_11G: 1148250003Sadrian pe = &ahp->ah_mode_power_array2133[request - HAL_DIAG_EEPROM_EXP_11A]; 1149250003Sadrian *result = pe->p_channels; 1150250003Sadrian *resultsize = (*result == AH_NULL) ? 0 : 1151250003Sadrian roundup(sizeof(u_int16_t) * pe->num_channels, 1152250003Sadrian sizeof(u_int32_t)) + 1153250003Sadrian sizeof(EXPN_DATA_PER_CHANNEL_2133) * pe->num_channels; 1154250003Sadrian return AH_TRUE; 1155250003Sadrian#endif 1156250003Sadrian case HAL_DIAG_RFGAIN: 1157250003Sadrian *result = &ahp->ah_gain_values; 1158250003Sadrian *resultsize = sizeof(GAIN_VALUES); 1159250003Sadrian return AH_TRUE; 1160250003Sadrian case HAL_DIAG_RFGAIN_CURSTEP: 1161250003Sadrian *result = (void *) ahp->ah_gain_values.curr_step; 1162250003Sadrian *resultsize = (*result == AH_NULL) ? 1163250003Sadrian 0 : sizeof(GAIN_OPTIMIZATION_STEP); 1164250003Sadrian return AH_TRUE; 1165250003Sadrian#if 0 /* XXX - TODO */ 1166250003Sadrian case HAL_DIAG_PCDAC: 1167250003Sadrian *result = ahp->ah_pcdac_table; 1168250003Sadrian *resultsize = ahp->ah_pcdac_table_size; 1169250003Sadrian return AH_TRUE; 1170250003Sadrian#endif 1171250003Sadrian case HAL_DIAG_ANI_CURRENT: 1172250003Sadrian *result = ar9300_ani_get_current_state(ah); 1173250003Sadrian *resultsize = (*result == AH_NULL) ? 1174250003Sadrian 0 : sizeof(struct ar9300_ani_state); 1175250003Sadrian return AH_TRUE; 1176250003Sadrian case HAL_DIAG_ANI_STATS: 1177250003Sadrian *result = ar9300_ani_get_current_stats(ah); 1178250003Sadrian *resultsize = (*result == AH_NULL) ? 1179250003Sadrian 0 : sizeof(struct ar9300_stats); 1180250003Sadrian return AH_TRUE; 1181250003Sadrian case HAL_DIAG_ANI_CMD: 1182250003Sadrian if (argsize != 2*sizeof(u_int32_t)) { 1183250003Sadrian return AH_FALSE; 1184250003Sadrian } 1185250003Sadrian ar9300_ani_control( 1186250003Sadrian ah, ((const u_int32_t *)args)[0], ((const u_int32_t *)args)[1]); 1187250003Sadrian return AH_TRUE; 1188250130Sadrian#if 0 1189250003Sadrian case HAL_DIAG_TXCONT: 1190250003Sadrian /*AR9300_CONTTXMODE(ah, (struct ath_desc *)args, argsize );*/ 1191250003Sadrian return AH_TRUE; 1192250130Sadrian#endif /* 0 */ 1193250003Sadrian#endif /* AH_PRIVATE_DIAG */ 1194250003Sadrian case HAL_DIAG_CHANNELS: 1195250008Sadrian#if 0 1196250003Sadrian *result = &(ahp->ah_priv.ah_channels[0]); 1197250003Sadrian *resultsize = 1198250003Sadrian sizeof(ahp->ah_priv.ah_channels[0]) * ahp->ah_priv.priv.ah_nchan; 1199250008Sadrian#endif 1200250003Sadrian return AH_TRUE; 1201250003Sadrian#ifdef AH_DEBUG 1202250003Sadrian case HAL_DIAG_PRINT_REG: 1203250003Sadrian ar9300_print_reg(ah, *((const u_int32_t *)args)); 1204250003Sadrian return AH_TRUE; 1205250003Sadrian#endif 1206250003Sadrian default: 1207250003Sadrian break; 1208250003Sadrian } 1209250003Sadrian 1210250003Sadrian return AH_FALSE; 1211250003Sadrian} 1212250003Sadrian 1213250003Sadrianvoid 1214250003Sadrianar9300_dma_reg_dump(struct ath_hal *ah) 1215250003Sadrian{ 1216250003Sadrian#ifdef AH_DEBUG 1217250003Sadrian#define NUM_DMA_DEBUG_REGS 8 1218250003Sadrian#define NUM_QUEUES 10 1219250003Sadrian 1220250003Sadrian u_int32_t val[NUM_DMA_DEBUG_REGS]; 1221250003Sadrian int qcu_offset = 0, dcu_offset = 0; 1222250003Sadrian u_int32_t *qcu_base = &val[0], *dcu_base = &val[4], reg; 1223250003Sadrian int i, j, k; 1224250008Sadrian int16_t nfarray[HAL_NUM_NF_READINGS]; 1225250008Sadrian#ifdef ATH_NF_PER_CHAN 1226250008Sadrian HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, AH_PRIVATE(ah)->ah_curchan); 1227250008Sadrian#endif /* ATH_NF_PER_CHAN */ 1228250008Sadrian HAL_NFCAL_HIST_FULL *h = AH_HOME_CHAN_NFCAL_HIST(ah, ichan); 1229250003Sadrian 1230250003Sadrian /* selecting DMA OBS 8 */ 1231250003Sadrian OS_REG_WRITE(ah, AR_MACMISC, 1232250003Sadrian ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) | 1233250003Sadrian (AR_MACMISC_MISC_OBS_BUS_1 << AR_MACMISC_MISC_OBS_BUS_MSB_S))); 1234250003Sadrian 1235250003Sadrian ath_hal_printf(ah, "Raw DMA Debug values:\n"); 1236250003Sadrian for (i = 0; i < NUM_DMA_DEBUG_REGS; i++) { 1237250003Sadrian if (i % 4 == 0) { 1238250003Sadrian ath_hal_printf(ah, "\n"); 1239250003Sadrian } 1240250003Sadrian 1241250003Sadrian val[i] = OS_REG_READ(ah, AR_DMADBG_0 + (i * sizeof(u_int32_t))); 1242250003Sadrian ath_hal_printf(ah, "%d: %08x ", i, val[i]); 1243250003Sadrian } 1244250003Sadrian 1245250003Sadrian ath_hal_printf(ah, "\n\n"); 1246250003Sadrian ath_hal_printf(ah, "Num QCU: chain_st fsp_ok fsp_st DCU: chain_st\n"); 1247250003Sadrian 1248250003Sadrian for (i = 0; i < NUM_QUEUES; i++, qcu_offset += 4, dcu_offset += 5) { 1249250003Sadrian if (i == 8) { 1250250003Sadrian /* only 8 QCU entries in val[0] */ 1251250003Sadrian qcu_offset = 0; 1252250003Sadrian qcu_base++; 1253250003Sadrian } 1254250003Sadrian 1255250003Sadrian if (i == 6) { 1256250003Sadrian /* only 6 DCU entries in val[4] */ 1257250003Sadrian dcu_offset = 0; 1258250003Sadrian dcu_base++; 1259250003Sadrian } 1260250003Sadrian 1261250003Sadrian ath_hal_printf(ah, 1262250003Sadrian "%2d %2x %1x %2x %2x\n", 1263250003Sadrian i, 1264250003Sadrian (*qcu_base & (0x7 << qcu_offset)) >> qcu_offset, 1265250003Sadrian (*qcu_base & (0x8 << qcu_offset)) >> (qcu_offset + 3), 1266250003Sadrian val[2] & (0x7 << (i * 3)) >> (i * 3), 1267250003Sadrian (*dcu_base & (0x1f << dcu_offset)) >> dcu_offset); 1268250003Sadrian } 1269250003Sadrian 1270250003Sadrian ath_hal_printf(ah, "\n"); 1271250003Sadrian ath_hal_printf(ah, 1272250003Sadrian "qcu_stitch state: %2x qcu_fetch state: %2x\n", 1273250003Sadrian (val[3] & 0x003c0000) >> 18, (val[3] & 0x03c00000) >> 22); 1274250003Sadrian ath_hal_printf(ah, 1275250003Sadrian "qcu_complete state: %2x dcu_complete state: %2x\n", 1276250003Sadrian (val[3] & 0x1c000000) >> 26, (val[6] & 0x3)); 1277250003Sadrian ath_hal_printf(ah, 1278250003Sadrian "dcu_arb state: %2x dcu_fp state: %2x\n", 1279250003Sadrian (val[5] & 0x06000000) >> 25, (val[5] & 0x38000000) >> 27); 1280250003Sadrian ath_hal_printf(ah, 1281250003Sadrian "chan_idle_dur: %3d chan_idle_dur_valid: %1d\n", 1282250003Sadrian (val[6] & 0x000003fc) >> 2, (val[6] & 0x00000400) >> 10); 1283250003Sadrian ath_hal_printf(ah, 1284250003Sadrian "txfifo_valid_0: %1d txfifo_valid_1: %1d\n", 1285250003Sadrian (val[6] & 0x00000800) >> 11, (val[6] & 0x00001000) >> 12); 1286250003Sadrian ath_hal_printf(ah, 1287250003Sadrian "txfifo_dcu_num_0: %2d txfifo_dcu_num_1: %2d\n", 1288250003Sadrian (val[6] & 0x0001e000) >> 13, (val[6] & 0x001e0000) >> 17); 1289250003Sadrian ath_hal_printf(ah, "pcu observe 0x%x \n", OS_REG_READ(ah, AR_OBS_BUS_1)); 1290250003Sadrian ath_hal_printf(ah, "AR_CR 0x%x \n", OS_REG_READ(ah, AR_CR)); 1291250003Sadrian 1292250003Sadrian ar9300_upload_noise_floor(ah, 1, nfarray); 1293250003Sadrian ath_hal_printf(ah, "2G:\n"); 1294250003Sadrian ath_hal_printf(ah, "Min CCA Out:\n"); 1295250003Sadrian ath_hal_printf(ah, "\t\tChain 0\t\tChain 1\t\tChain 2\n"); 1296250003Sadrian ath_hal_printf(ah, "Control:\t%8d\t%8d\t%8d\n", 1297250003Sadrian nfarray[0], nfarray[1], nfarray[2]); 1298250003Sadrian ath_hal_printf(ah, "Extension:\t%8d\t%8d\t%8d\n\n", 1299250003Sadrian nfarray[3], nfarray[4], nfarray[5]); 1300250003Sadrian 1301250003Sadrian ar9300_upload_noise_floor(ah, 0, nfarray); 1302250003Sadrian ath_hal_printf(ah, "5G:\n"); 1303250003Sadrian ath_hal_printf(ah, "Min CCA Out:\n"); 1304250003Sadrian ath_hal_printf(ah, "\t\tChain 0\t\tChain 1\t\tChain 2\n"); 1305250003Sadrian ath_hal_printf(ah, "Control:\t%8d\t%8d\t%8d\n", 1306250003Sadrian nfarray[0], nfarray[1], nfarray[2]); 1307250003Sadrian ath_hal_printf(ah, "Extension:\t%8d\t%8d\t%8d\n\n", 1308250003Sadrian nfarray[3], nfarray[4], nfarray[5]); 1309250003Sadrian 1310250008Sadrian for (i = 0; i < HAL_NUM_NF_READINGS; i++) { 1311250003Sadrian ath_hal_printf(ah, "%s Chain %d NF History:\n", 1312250003Sadrian ((i < 3) ? "Control " : "Extension "), i%3); 1313250003Sadrian for (j = 0, k = h->base.curr_index; 1314250003Sadrian j < HAL_NF_CAL_HIST_LEN_FULL; 1315250003Sadrian j++, k++) { 1316250003Sadrian ath_hal_printf(ah, "Element %d: %d\n", 1317250003Sadrian j, h->nf_cal_buffer[k % HAL_NF_CAL_HIST_LEN_FULL][i]); 1318250003Sadrian } 1319250003Sadrian ath_hal_printf(ah, "Last Programmed NF: %d\n\n", h->base.priv_nf[i]); 1320250003Sadrian } 1321250003Sadrian 1322250003Sadrian reg = OS_REG_READ(ah, AR_PHY_FIND_SIG_LOW); 1323250003Sadrian ath_hal_printf(ah, "FIRStep Low = 0x%x (%d)\n", 1324250003Sadrian MS(reg, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW), 1325250003Sadrian MS(reg, AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW)); 1326250003Sadrian reg = OS_REG_READ(ah, AR_PHY_DESIRED_SZ); 1327250003Sadrian ath_hal_printf(ah, "Total Desired = 0x%x (%d)\n", 1328250003Sadrian MS(reg, AR_PHY_DESIRED_SZ_TOT_DES), 1329250003Sadrian MS(reg, AR_PHY_DESIRED_SZ_TOT_DES)); 1330250003Sadrian ath_hal_printf(ah, "ADC Desired = 0x%x (%d)\n", 1331250003Sadrian MS(reg, AR_PHY_DESIRED_SZ_ADC), 1332250003Sadrian MS(reg, AR_PHY_DESIRED_SZ_ADC)); 1333250003Sadrian reg = OS_REG_READ(ah, AR_PHY_FIND_SIG); 1334250003Sadrian ath_hal_printf(ah, "FIRStep = 0x%x (%d)\n", 1335250003Sadrian MS(reg, AR_PHY_FIND_SIG_FIRSTEP), 1336250003Sadrian MS(reg, AR_PHY_FIND_SIG_FIRSTEP)); 1337250003Sadrian reg = OS_REG_READ(ah, AR_PHY_AGC); 1338250003Sadrian ath_hal_printf(ah, "Coarse High = 0x%x (%d)\n", 1339250003Sadrian MS(reg, AR_PHY_AGC_COARSE_HIGH), 1340250003Sadrian MS(reg, AR_PHY_AGC_COARSE_HIGH)); 1341250003Sadrian ath_hal_printf(ah, "Coarse Low = 0x%x (%d)\n", 1342250003Sadrian MS(reg, AR_PHY_AGC_COARSE_LOW), 1343250003Sadrian MS(reg, AR_PHY_AGC_COARSE_LOW)); 1344250003Sadrian ath_hal_printf(ah, "Coarse Power Constant = 0x%x (%d)\n", 1345250003Sadrian MS(reg, AR_PHY_AGC_COARSE_PWR_CONST), 1346250003Sadrian MS(reg, AR_PHY_AGC_COARSE_PWR_CONST)); 1347250003Sadrian reg = OS_REG_READ(ah, AR_PHY_TIMING5); 1348250003Sadrian ath_hal_printf(ah, "Enable Cyclic Power Thresh = %d\n", 1349250003Sadrian MS(reg, AR_PHY_TIMING5_CYCPWR_THR1_ENABLE)); 1350250003Sadrian ath_hal_printf(ah, "Cyclic Power Thresh = 0x%x (%d)\n", 1351250003Sadrian MS(reg, AR_PHY_TIMING5_CYCPWR_THR1), 1352250003Sadrian MS(reg, AR_PHY_TIMING5_CYCPWR_THR1)); 1353250003Sadrian ath_hal_printf(ah, "Cyclic Power Thresh 1A= 0x%x (%d)\n", 1354250003Sadrian MS(reg, AR_PHY_TIMING5_CYCPWR_THR1A), 1355250003Sadrian MS(reg, AR_PHY_TIMING5_CYCPWR_THR1A)); 1356250003Sadrian reg = OS_REG_READ(ah, AR_PHY_DAG_CTRLCCK); 1357250003Sadrian ath_hal_printf(ah, "Barker RSSI Thresh Enable = %d\n", 1358250003Sadrian MS(reg, AR_PHY_DAG_CTRLCCK_EN_RSSI_THR)); 1359250003Sadrian ath_hal_printf(ah, "Barker RSSI Thresh = 0x%x (%d)\n", 1360250003Sadrian MS(reg, AR_PHY_DAG_CTRLCCK_RSSI_THR), 1361250003Sadrian MS(reg, AR_PHY_DAG_CTRLCCK_RSSI_THR)); 1362250003Sadrian 1363250003Sadrian 1364250003Sadrian /* Step 1a: Set bit 23 of register 0xa360 to 0 */ 1365250003Sadrian reg = OS_REG_READ(ah, 0xa360); 1366250003Sadrian reg &= ~0x00800000; 1367250003Sadrian OS_REG_WRITE(ah, 0xa360, reg); 1368250003Sadrian 1369250003Sadrian /* Step 2a: Set register 0xa364 to 0x1000 */ 1370250003Sadrian reg = 0x1000; 1371250003Sadrian OS_REG_WRITE(ah, 0xa364, reg); 1372250003Sadrian 1373250003Sadrian /* Step 3a: Read bits 17:0 of register 0x9c20 */ 1374250003Sadrian reg = OS_REG_READ(ah, 0x9c20); 1375250003Sadrian reg &= 0x0003ffff; 1376250003Sadrian ath_hal_printf(ah, 1377250003Sadrian "%s: Test Control Status [0x1000] 0x9c20[17:0] = 0x%x\n", 1378250003Sadrian __func__, reg); 1379250003Sadrian 1380250003Sadrian /* Step 1b: Set bit 23 of register 0xa360 to 0 */ 1381250003Sadrian reg = OS_REG_READ(ah, 0xa360); 1382250003Sadrian reg &= ~0x00800000; 1383250003Sadrian OS_REG_WRITE(ah, 0xa360, reg); 1384250003Sadrian 1385250003Sadrian /* Step 2b: Set register 0xa364 to 0x1400 */ 1386250003Sadrian reg = 0x1400; 1387250003Sadrian OS_REG_WRITE(ah, 0xa364, reg); 1388250003Sadrian 1389250003Sadrian /* Step 3b: Read bits 17:0 of register 0x9c20 */ 1390250003Sadrian reg = OS_REG_READ(ah, 0x9c20); 1391250003Sadrian reg &= 0x0003ffff; 1392250003Sadrian ath_hal_printf(ah, 1393250003Sadrian "%s: Test Control Status [0x1400] 0x9c20[17:0] = 0x%x\n", 1394250003Sadrian __func__, reg); 1395250003Sadrian 1396250003Sadrian /* Step 1c: Set bit 23 of register 0xa360 to 0 */ 1397250003Sadrian reg = OS_REG_READ(ah, 0xa360); 1398250003Sadrian reg &= ~0x00800000; 1399250003Sadrian OS_REG_WRITE(ah, 0xa360, reg); 1400250003Sadrian 1401250003Sadrian /* Step 2c: Set register 0xa364 to 0x3C00 */ 1402250003Sadrian reg = 0x3c00; 1403250003Sadrian OS_REG_WRITE(ah, 0xa364, reg); 1404250003Sadrian 1405250003Sadrian /* Step 3c: Read bits 17:0 of register 0x9c20 */ 1406250003Sadrian reg = OS_REG_READ(ah, 0x9c20); 1407250003Sadrian reg &= 0x0003ffff; 1408250003Sadrian ath_hal_printf(ah, 1409250003Sadrian "%s: Test Control Status [0x3C00] 0x9c20[17:0] = 0x%x\n", 1410250003Sadrian __func__, reg); 1411250003Sadrian 1412250003Sadrian /* Step 1d: Set bit 24 of register 0xa360 to 0 */ 1413250003Sadrian reg = OS_REG_READ(ah, 0xa360); 1414250003Sadrian reg &= ~0x001040000; 1415250003Sadrian OS_REG_WRITE(ah, 0xa360, reg); 1416250003Sadrian 1417250003Sadrian /* Step 2d: Set register 0xa364 to 0x5005D */ 1418250003Sadrian reg = 0x5005D; 1419250003Sadrian OS_REG_WRITE(ah, 0xa364, reg); 1420250003Sadrian 1421250003Sadrian /* Step 3d: Read bits 17:0 of register 0xa368 */ 1422250003Sadrian reg = OS_REG_READ(ah, 0xa368); 1423250003Sadrian reg &= 0x0003ffff; 1424250003Sadrian ath_hal_printf(ah, 1425250003Sadrian "%s: Test Control Status [0x5005D] 0xa368[17:0] = 0x%x\n", 1426250003Sadrian __func__, reg); 1427250003Sadrian 1428250003Sadrian /* Step 1e: Set bit 24 of register 0xa360 to 0 */ 1429250003Sadrian reg = OS_REG_READ(ah, 0xa360); 1430250003Sadrian reg &= ~0x001040000; 1431250003Sadrian OS_REG_WRITE(ah, 0xa360, reg); 1432250003Sadrian 1433250003Sadrian /* Step 2e: Set register 0xa364 to 0x7005D */ 1434250003Sadrian reg = 0x7005D; 1435250003Sadrian OS_REG_WRITE(ah, 0xa364, reg); 1436250003Sadrian 1437250003Sadrian /* Step 3e: Read bits 17:0 of register 0xa368 */ 1438250003Sadrian reg = OS_REG_READ(ah, 0xa368); 1439250003Sadrian reg &= 0x0003ffff; 1440250003Sadrian ath_hal_printf(ah, 1441250003Sadrian "%s: Test Control Status [0x7005D] 0xa368[17:0] = 0x%x\n", 1442250003Sadrian __func__, reg); 1443250003Sadrian 1444250003Sadrian /* Step 1f: Set bit 24 of register 0xa360 to 0 */ 1445250003Sadrian reg = OS_REG_READ(ah, 0xa360); 1446250003Sadrian reg &= ~0x001000000; 1447250003Sadrian reg |= 0x40000; 1448250003Sadrian OS_REG_WRITE(ah, 0xa360, reg); 1449250003Sadrian 1450250003Sadrian /* Step 2f: Set register 0xa364 to 0x3005D */ 1451250003Sadrian reg = 0x3005D; 1452250003Sadrian OS_REG_WRITE(ah, 0xa364, reg); 1453250003Sadrian 1454250003Sadrian /* Step 3f: Read bits 17:0 of register 0xa368 */ 1455250003Sadrian reg = OS_REG_READ(ah, 0xa368); 1456250003Sadrian reg &= 0x0003ffff; 1457250003Sadrian ath_hal_printf(ah, 1458250003Sadrian "%s: Test Control Status [0x3005D] 0xa368[17:0] = 0x%x\n", 1459250003Sadrian __func__, reg); 1460250003Sadrian 1461250003Sadrian /* Step 1g: Set bit 24 of register 0xa360 to 0 */ 1462250003Sadrian reg = OS_REG_READ(ah, 0xa360); 1463250003Sadrian reg &= ~0x001000000; 1464250003Sadrian reg |= 0x40000; 1465250003Sadrian OS_REG_WRITE(ah, 0xa360, reg); 1466250003Sadrian 1467250003Sadrian /* Step 2g: Set register 0xa364 to 0x6005D */ 1468250003Sadrian reg = 0x6005D; 1469250003Sadrian OS_REG_WRITE(ah, 0xa364, reg); 1470250003Sadrian 1471250003Sadrian /* Step 3g: Read bits 17:0 of register 0xa368 */ 1472250003Sadrian reg = OS_REG_READ(ah, 0xa368); 1473250003Sadrian reg &= 0x0003ffff; 1474250003Sadrian ath_hal_printf(ah, 1475250003Sadrian "%s: Test Control Status [0x6005D] 0xa368[17:0] = 0x%x\n", 1476250003Sadrian __func__, reg); 1477250003Sadrian#endif /* AH_DEBUG */ 1478250003Sadrian} 1479250003Sadrian 1480250003Sadrian/* 1481250003Sadrian * Return the busy for rx_frame, rx_clear, and tx_frame 1482250003Sadrian */ 1483250003Sadrianu_int32_t 1484250003Sadrianar9300_get_mib_cycle_counts_pct(struct ath_hal *ah, u_int32_t *rxc_pcnt, 1485250003Sadrian u_int32_t *rxf_pcnt, u_int32_t *txf_pcnt) 1486250003Sadrian{ 1487250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 1488250003Sadrian u_int32_t good = 1; 1489250003Sadrian 1490250003Sadrian u_int32_t rc = OS_REG_READ(ah, AR_RCCNT); 1491250003Sadrian u_int32_t rf = OS_REG_READ(ah, AR_RFCNT); 1492250003Sadrian u_int32_t tf = OS_REG_READ(ah, AR_TFCNT); 1493250003Sadrian u_int32_t cc = OS_REG_READ(ah, AR_CCCNT); /* read cycles last */ 1494250003Sadrian 1495250003Sadrian if (ahp->ah_cycles == 0 || ahp->ah_cycles > cc) { 1496250003Sadrian /* 1497250003Sadrian * Cycle counter wrap (or initial call); it's not possible 1498250003Sadrian * to accurately calculate a value because the registers 1499250003Sadrian * right shift rather than wrap--so punt and return 0. 1500250003Sadrian */ 1501250003Sadrian HALDEBUG(ah, HAL_DEBUG_CHANNEL, 1502250003Sadrian "%s: cycle counter wrap. ExtBusy = 0\n", __func__); 1503250003Sadrian good = 0; 1504250003Sadrian } else { 1505250003Sadrian u_int32_t cc_d = cc - ahp->ah_cycles; 1506250003Sadrian u_int32_t rc_d = rc - ahp->ah_rx_clear; 1507250003Sadrian u_int32_t rf_d = rf - ahp->ah_rx_frame; 1508250003Sadrian u_int32_t tf_d = tf - ahp->ah_tx_frame; 1509250003Sadrian 1510250003Sadrian if (cc_d != 0) { 1511250003Sadrian *rxc_pcnt = rc_d * 100 / cc_d; 1512250003Sadrian *rxf_pcnt = rf_d * 100 / cc_d; 1513250003Sadrian *txf_pcnt = tf_d * 100 / cc_d; 1514250003Sadrian } else { 1515250003Sadrian good = 0; 1516250003Sadrian } 1517250003Sadrian } 1518250003Sadrian 1519250003Sadrian ahp->ah_cycles = cc; 1520250003Sadrian ahp->ah_rx_frame = rf; 1521250003Sadrian ahp->ah_rx_clear = rc; 1522250003Sadrian ahp->ah_tx_frame = tf; 1523250003Sadrian 1524250003Sadrian return good; 1525250003Sadrian} 1526250003Sadrian 1527250003Sadrian/* 1528250003Sadrian * Return approximation of extension channel busy over an time interval 1529250003Sadrian * 0% (clear) -> 100% (busy) 1530250003Sadrian * -1 for invalid estimate 1531250003Sadrian */ 1532250008Sadrianuint32_t 1533250003Sadrianar9300_get_11n_ext_busy(struct ath_hal *ah) 1534250003Sadrian{ 1535250003Sadrian /* 1536250003Sadrian * Overflow condition to check before multiplying to get % 1537250003Sadrian * (x * 100 > 0xFFFFFFFF ) => (x > 0x28F5C28) 1538250003Sadrian */ 1539250003Sadrian#define OVERFLOW_LIMIT 0x28F5C28 1540250003Sadrian#define ERROR_CODE -1 1541250003Sadrian 1542250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 1543250003Sadrian u_int32_t busy = 0; /* percentage */ 1544250003Sadrian int8_t busyper = 0; 1545250003Sadrian u_int32_t cycle_count, ctl_busy, ext_busy; 1546250003Sadrian 1547250003Sadrian /* cycle_count will always be the first to wrap; therefore, read it last 1548250003Sadrian * This sequence of reads is not atomic, and MIB counter wrap 1549250003Sadrian * could happen during it ? 1550250003Sadrian */ 1551250003Sadrian ctl_busy = OS_REG_READ(ah, AR_RCCNT); 1552250003Sadrian ext_busy = OS_REG_READ(ah, AR_EXTRCCNT); 1553250003Sadrian cycle_count = OS_REG_READ(ah, AR_CCCNT); 1554250003Sadrian 1555250003Sadrian if ((ahp->ah_cycle_count == 0) || (ahp->ah_cycle_count > cycle_count) || 1556250003Sadrian (ahp->ah_ctl_busy > ctl_busy) || (ahp->ah_ext_busy > ext_busy)) 1557250003Sadrian { 1558250003Sadrian /* 1559250003Sadrian * Cycle counter wrap (or initial call); it's not possible 1560250003Sadrian * to accurately calculate a value because the registers 1561250003Sadrian * right shift rather than wrap--so punt and return 0. 1562250003Sadrian */ 1563250003Sadrian busyper = ERROR_CODE; 1564250003Sadrian HALDEBUG(ah, HAL_DEBUG_CHANNEL, 1565250003Sadrian "%s: cycle counter wrap. ExtBusy = 0\n", __func__); 1566250003Sadrian } else { 1567250003Sadrian u_int32_t cycle_delta = cycle_count - ahp->ah_cycle_count; 1568250003Sadrian u_int32_t ext_busy_delta = ext_busy - ahp->ah_ext_busy; 1569250003Sadrian 1570250003Sadrian /* 1571250003Sadrian * Compute extension channel busy percentage 1572250003Sadrian * Overflow condition: 0xFFFFFFFF < ext_busy_delta * 100 1573250003Sadrian * Underflow condition/Divide-by-zero: check that cycle_delta >> 7 != 0 1574250003Sadrian * Will never happen, since (ext_busy_delta < cycle_delta) always, 1575250003Sadrian * and shift necessitated by large ext_busy_delta. 1576250003Sadrian * Due to timing difference to read the registers and counter overflow, 1577250003Sadrian * it may still happen that cycle_delta >> 7 = 0. 1578250003Sadrian * 1579250003Sadrian */ 1580250003Sadrian if (cycle_delta) { 1581250003Sadrian if (ext_busy_delta > OVERFLOW_LIMIT) { 1582250003Sadrian if (cycle_delta >> 7) { 1583250003Sadrian busy = ((ext_busy_delta >> 7) * 100) / (cycle_delta >> 7); 1584250003Sadrian } else { 1585250003Sadrian busyper = ERROR_CODE; 1586250003Sadrian } 1587250003Sadrian } else { 1588250003Sadrian busy = (ext_busy_delta * 100) / cycle_delta; 1589250003Sadrian } 1590250003Sadrian } else { 1591250003Sadrian busyper = ERROR_CODE; 1592250003Sadrian } 1593250003Sadrian 1594250003Sadrian if (busy > 100) { 1595250003Sadrian busy = 100; 1596250003Sadrian } 1597250003Sadrian if ( busyper != ERROR_CODE ) { 1598250003Sadrian busyper = busy; 1599250003Sadrian } 1600250003Sadrian } 1601250003Sadrian 1602250003Sadrian ahp->ah_cycle_count = cycle_count; 1603250003Sadrian ahp->ah_ctl_busy = ctl_busy; 1604250003Sadrian ahp->ah_ext_busy = ext_busy; 1605250003Sadrian 1606250003Sadrian return busyper; 1607250003Sadrian#undef OVERFLOW_LIMIT 1608250003Sadrian#undef ERROR_CODE 1609250003Sadrian} 1610250003Sadrian 1611250003Sadrian/* BB Panic Watchdog declarations */ 1612250003Sadrian#define HAL_BB_PANIC_WD_HT20_FACTOR 74 /* 0.74 */ 1613250003Sadrian#define HAL_BB_PANIC_WD_HT40_FACTOR 37 /* 0.37 */ 1614250003Sadrian 1615250003Sadrianvoid 1616250003Sadrianar9300_config_bb_panic_watchdog(struct ath_hal *ah) 1617250003Sadrian{ 1618250003Sadrian#define HAL_BB_PANIC_IDLE_TIME_OUT 0x0a8c0000 1619250008Sadrian const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 1620250008Sadrian u_int32_t idle_tmo_ms = AH9300(ah)->ah_bb_panic_timeout_ms; 1621250003Sadrian u_int32_t val, idle_count; 1622250003Sadrian 1623250003Sadrian if (idle_tmo_ms != 0) { 1624250003Sadrian /* enable IRQ, disable chip-reset for BB panic */ 1625250003Sadrian val = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2) & 1626250003Sadrian AR_PHY_BB_PANIC_CNTL2_MASK; 1627250003Sadrian OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_2, 1628250003Sadrian (val | AR_PHY_BB_PANIC_IRQ_ENABLE) & ~AR_PHY_BB_PANIC_RST_ENABLE); 1629250003Sadrian /* bound limit to 10 secs */ 1630250003Sadrian if (idle_tmo_ms > 10000) { 1631250003Sadrian idle_tmo_ms = 10000; 1632250003Sadrian } 1633250008Sadrian if (chan != AH_NULL && IEEE80211_IS_CHAN_HT40(chan)) { 1634250003Sadrian idle_count = (100 * idle_tmo_ms) / HAL_BB_PANIC_WD_HT40_FACTOR; 1635250003Sadrian } else { 1636250003Sadrian idle_count = (100 * idle_tmo_ms) / HAL_BB_PANIC_WD_HT20_FACTOR; 1637250003Sadrian } 1638250003Sadrian /* 1639250003Sadrian * enable panic in non-IDLE mode, 1640250003Sadrian * disable in IDLE mode, 1641250003Sadrian * set idle time-out 1642250003Sadrian */ 1643250003Sadrian 1644250003Sadrian // EV92527 : Enable IDLE mode panic 1645250003Sadrian 1646250003Sadrian OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_1, 1647250003Sadrian AR_PHY_BB_PANIC_NON_IDLE_ENABLE | 1648250003Sadrian AR_PHY_BB_PANIC_IDLE_ENABLE | 1649250003Sadrian (AR_PHY_BB_PANIC_IDLE_MASK & HAL_BB_PANIC_IDLE_TIME_OUT) | 1650250003Sadrian (AR_PHY_BB_PANIC_NON_IDLE_MASK & (idle_count << 2))); 1651250003Sadrian } else { 1652250003Sadrian /* disable IRQ, disable chip-reset for BB panic */ 1653250003Sadrian OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_2, 1654250003Sadrian OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2) & 1655250003Sadrian ~(AR_PHY_BB_PANIC_RST_ENABLE | AR_PHY_BB_PANIC_IRQ_ENABLE)); 1656250003Sadrian /* disable panic in non-IDLE mode, disable in IDLE mode */ 1657250003Sadrian OS_REG_WRITE(ah, AR_PHY_PANIC_WD_CTL_1, 1658250003Sadrian OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_1) & 1659250003Sadrian ~(AR_PHY_BB_PANIC_NON_IDLE_ENABLE | AR_PHY_BB_PANIC_IDLE_ENABLE)); 1660250003Sadrian } 1661250003Sadrian 1662250008Sadrian HALDEBUG(ah, HAL_DEBUG_RFPARAM, "%s: %s BB Panic Watchdog tmo=%ums\n", 1663250003Sadrian __func__, idle_tmo_ms ? "Enabled" : "Disabled", idle_tmo_ms); 1664250003Sadrian#undef HAL_BB_PANIC_IDLE_TIME_OUT 1665250003Sadrian} 1666250003Sadrian 1667250003Sadrian 1668250003Sadrianvoid 1669250003Sadrianar9300_handle_bb_panic(struct ath_hal *ah) 1670250003Sadrian{ 1671250003Sadrian u_int32_t status; 1672250003Sadrian /* 1673250003Sadrian * we want to avoid printing in ISR context so we save 1674250003Sadrian * panic watchdog status to be printed later in DPC context 1675250003Sadrian */ 1676250008Sadrian AH9300(ah)->ah_bb_panic_last_status = status = 1677250003Sadrian OS_REG_READ(ah, AR_PHY_PANIC_WD_STATUS); 1678250003Sadrian /* 1679250003Sadrian * panic watchdog timer should reset on status read 1680250003Sadrian * but to make sure we write 0 to the watchdog status bit 1681250003Sadrian */ 1682250003Sadrian OS_REG_WRITE(ah, AR_PHY_PANIC_WD_STATUS, status & ~AR_PHY_BB_WD_STATUS_CLR); 1683250003Sadrian} 1684250003Sadrian 1685250003Sadrianint 1686250003Sadrianar9300_get_bb_panic_info(struct ath_hal *ah, struct hal_bb_panic_info *bb_panic) 1687250003Sadrian{ 1688250008Sadrian bb_panic->status = AH9300(ah)->ah_bb_panic_last_status; 1689250003Sadrian 1690250003Sadrian /* 1691250003Sadrian * For signature 04000539 do not print anything. 1692250003Sadrian * This is a very common occurence as a compromise between 1693250003Sadrian * BB Panic and AH_FALSE detects (EV71009). It indicates 1694250003Sadrian * radar hang, which can be cleared by reprogramming 1695250003Sadrian * radar related register and does not requre a chip reset 1696250003Sadrian */ 1697250003Sadrian 1698250003Sadrian /* Suppress BB Status mesg following signature */ 1699250003Sadrian switch (bb_panic->status) { 1700250003Sadrian case 0x04000539: 1701250003Sadrian case 0x04008009: 1702250003Sadrian case 0x04000b09: 1703250003Sadrian case 0x1300000a: 1704250003Sadrian return -1; 1705250003Sadrian } 1706250003Sadrian 1707250003Sadrian bb_panic->tsf = ar9300_get_tsf32(ah); 1708250003Sadrian bb_panic->wd = MS(bb_panic->status, AR_PHY_BB_WD_STATUS); 1709250003Sadrian bb_panic->det = MS(bb_panic->status, AR_PHY_BB_WD_DET_HANG); 1710250003Sadrian bb_panic->rdar = MS(bb_panic->status, AR_PHY_BB_WD_RADAR_SM); 1711250003Sadrian bb_panic->r_odfm = MS(bb_panic->status, AR_PHY_BB_WD_RX_OFDM_SM); 1712250003Sadrian bb_panic->r_cck = MS(bb_panic->status, AR_PHY_BB_WD_RX_CCK_SM); 1713250003Sadrian bb_panic->t_odfm = MS(bb_panic->status, AR_PHY_BB_WD_TX_OFDM_SM); 1714250003Sadrian bb_panic->t_cck = MS(bb_panic->status, AR_PHY_BB_WD_TX_CCK_SM); 1715250003Sadrian bb_panic->agc = MS(bb_panic->status, AR_PHY_BB_WD_AGC_SM); 1716250003Sadrian bb_panic->src = MS(bb_panic->status, AR_PHY_BB_WD_SRCH_SM); 1717250003Sadrian bb_panic->phy_panic_wd_ctl1 = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_1); 1718250003Sadrian bb_panic->phy_panic_wd_ctl2 = OS_REG_READ(ah, AR_PHY_PANIC_WD_CTL_2); 1719250003Sadrian bb_panic->phy_gen_ctrl = OS_REG_READ(ah, AR_PHY_GEN_CTRL); 1720250003Sadrian bb_panic->rxc_pcnt = bb_panic->rxf_pcnt = bb_panic->txf_pcnt = 0; 1721250003Sadrian bb_panic->cycles = ar9300_get_mib_cycle_counts_pct(ah, 1722250003Sadrian &bb_panic->rxc_pcnt, 1723250003Sadrian &bb_panic->rxf_pcnt, 1724250003Sadrian &bb_panic->txf_pcnt); 1725250003Sadrian 1726250008Sadrian if (ah->ah_config.ath_hal_show_bb_panic) { 1727250003Sadrian ath_hal_printf(ah, "\n==== BB update: BB status=0x%08x, " 1728250003Sadrian "tsf=0x%08x ====\n", bb_panic->status, bb_panic->tsf); 1729250003Sadrian ath_hal_printf(ah, "** BB state: wd=%u det=%u rdar=%u rOFDM=%d " 1730250003Sadrian "rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n", 1731250003Sadrian bb_panic->wd, bb_panic->det, bb_panic->rdar, 1732250003Sadrian bb_panic->r_odfm, bb_panic->r_cck, bb_panic->t_odfm, 1733250003Sadrian bb_panic->t_cck, bb_panic->agc, bb_panic->src); 1734250003Sadrian ath_hal_printf(ah, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n", 1735250003Sadrian bb_panic->phy_panic_wd_ctl1, bb_panic->phy_panic_wd_ctl2); 1736250003Sadrian ath_hal_printf(ah, "** BB mode: BB_gen_controls=0x%08x **\n", 1737250003Sadrian bb_panic->phy_gen_ctrl); 1738250003Sadrian if (bb_panic->cycles) { 1739250003Sadrian ath_hal_printf(ah, "** BB busy times: rx_clear=%d%%, " 1740250003Sadrian "rx_frame=%d%%, tx_frame=%d%% **\n", bb_panic->rxc_pcnt, 1741250003Sadrian bb_panic->rxf_pcnt, bb_panic->txf_pcnt); 1742250003Sadrian } 1743250003Sadrian ath_hal_printf(ah, "==== BB update: done ====\n\n"); 1744250003Sadrian } 1745250003Sadrian 1746250003Sadrian return 0; //The returned data will be stored for athstats to retrieve it 1747250003Sadrian} 1748250003Sadrian 1749250003Sadrian/* set the reason for HAL reset */ 1750250003Sadrianvoid 1751250003Sadrianar9300_set_hal_reset_reason(struct ath_hal *ah, u_int8_t resetreason) 1752250003Sadrian{ 1753250008Sadrian AH9300(ah)->ah_reset_reason = resetreason; 1754250003Sadrian} 1755250003Sadrian 1756250003Sadrian/* 1757250003Sadrian * Configure 20/40 operation 1758250003Sadrian * 1759250003Sadrian * 20/40 = joint rx clear (control and extension) 1760250003Sadrian * 20 = rx clear (control) 1761250003Sadrian * 1762250003Sadrian * - NOTE: must stop MAC (tx) and requeue 40 MHz packets as 20 MHz 1763250003Sadrian * when changing from 20/40 => 20 only 1764250003Sadrian */ 1765250003Sadrianvoid 1766250003Sadrianar9300_set_11n_mac2040(struct ath_hal *ah, HAL_HT_MACMODE mode) 1767250003Sadrian{ 1768250003Sadrian u_int32_t macmode; 1769250003Sadrian 1770250003Sadrian /* Configure MAC for 20/40 operation */ 1771250003Sadrian if (mode == HAL_HT_MACMODE_2040 && 1772250008Sadrian !ah->ah_config.ath_hal_cwm_ignore_ext_cca) { 1773250003Sadrian macmode = AR_2040_JOINED_RX_CLEAR; 1774250003Sadrian } else { 1775250003Sadrian macmode = 0; 1776250003Sadrian } 1777250003Sadrian OS_REG_WRITE(ah, AR_2040_MODE, macmode); 1778250003Sadrian} 1779250003Sadrian 1780250003Sadrian/* 1781250003Sadrian * Get Rx clear (control/extension channel) 1782250003Sadrian * 1783250003Sadrian * Returns active low (busy) for ctrl/ext channel 1784250003Sadrian * Owl 2.0 1785250003Sadrian */ 1786250003SadrianHAL_HT_RXCLEAR 1787250003Sadrianar9300_get_11n_rx_clear(struct ath_hal *ah) 1788250003Sadrian{ 1789250003Sadrian HAL_HT_RXCLEAR rxclear = 0; 1790250003Sadrian u_int32_t val; 1791250003Sadrian 1792250003Sadrian val = OS_REG_READ(ah, AR_DIAG_SW); 1793250003Sadrian 1794250003Sadrian /* control channel */ 1795250003Sadrian if (val & AR_DIAG_RX_CLEAR_CTL_LOW) { 1796250003Sadrian rxclear |= HAL_RX_CLEAR_CTL_LOW; 1797250003Sadrian } 1798250003Sadrian /* extension channel */ 1799250003Sadrian if (val & AR_DIAG_RX_CLEAR_EXT_LOW) { 1800250003Sadrian rxclear |= HAL_RX_CLEAR_EXT_LOW; 1801250003Sadrian } 1802250003Sadrian return rxclear; 1803250003Sadrian} 1804250003Sadrian 1805250003Sadrian/* 1806250003Sadrian * Set Rx clear (control/extension channel) 1807250003Sadrian * 1808250003Sadrian * Useful for forcing the channel to appear busy for 1809250003Sadrian * debugging/diagnostics 1810250003Sadrian * Owl 2.0 1811250003Sadrian */ 1812250003Sadrianvoid 1813250003Sadrianar9300_set_11n_rx_clear(struct ath_hal *ah, HAL_HT_RXCLEAR rxclear) 1814250003Sadrian{ 1815250003Sadrian /* control channel */ 1816250003Sadrian if (rxclear & HAL_RX_CLEAR_CTL_LOW) { 1817250003Sadrian OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_CTL_LOW); 1818250003Sadrian } else { 1819250003Sadrian OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_CTL_LOW); 1820250003Sadrian } 1821250003Sadrian /* extension channel */ 1822250003Sadrian if (rxclear & HAL_RX_CLEAR_EXT_LOW) { 1823250003Sadrian OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_EXT_LOW); 1824250003Sadrian } else { 1825250003Sadrian OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_CLEAR_EXT_LOW); 1826250003Sadrian } 1827250003Sadrian} 1828250003Sadrian 1829250003Sadrian 1830250003Sadrian/* 1831250003Sadrian * HAL support code for force ppm tracking workaround. 1832250003Sadrian */ 1833250003Sadrian 1834250003Sadrianu_int32_t 1835250003Sadrianar9300_ppm_get_rssi_dump(struct ath_hal *ah) 1836250003Sadrian{ 1837250003Sadrian u_int32_t retval; 1838250003Sadrian u_int32_t off1; 1839250003Sadrian u_int32_t off2; 1840250003Sadrian 1841250003Sadrian if (OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) & AR_PHY_SWAP_ALT_CHAIN) { 1842250003Sadrian off1 = 0x2000; 1843250003Sadrian off2 = 0x1000; 1844250003Sadrian } else { 1845250003Sadrian off1 = 0x1000; 1846250003Sadrian off2 = 0x2000; 1847250003Sadrian } 1848250003Sadrian 1849250003Sadrian retval = ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 )) << 0) | 1850250003Sadrian ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 + off1)) << 8) | 1851250003Sadrian ((0xff & OS_REG_READ(ah, AR_PHY_CHAN_INFO_GAIN_0 + off2)) << 16); 1852250003Sadrian 1853250003Sadrian return retval; 1854250003Sadrian} 1855250003Sadrian 1856250003Sadrianu_int32_t 1857250003Sadrianar9300_ppm_force(struct ath_hal *ah) 1858250003Sadrian{ 1859250003Sadrian u_int32_t data_fine; 1860250003Sadrian u_int32_t data4; 1861250003Sadrian //u_int32_t off1; 1862250003Sadrian //u_int32_t off2; 1863250003Sadrian HAL_BOOL signed_val = AH_FALSE; 1864250003Sadrian 1865250003Sadrian// if (OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) & AR_PHY_SWAP_ALT_CHAIN) { 1866250003Sadrian// off1 = 0x2000; 1867250003Sadrian// off2 = 0x1000; 1868250003Sadrian// } else { 1869250003Sadrian// off1 = 0x1000; 1870250003Sadrian// off2 = 0x2000; 1871250003Sadrian// } 1872250003Sadrian data_fine = 1873250003Sadrian AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK & 1874250003Sadrian OS_REG_READ(ah, AR_PHY_CHNINFO_GAINDIFF); 1875250003Sadrian 1876250003Sadrian /* 1877250003Sadrian * bit [11-0] is new ppm value. bit 11 is the signed bit. 1878250003Sadrian * So check value from bit[10:0]. 1879250003Sadrian * Now get the abs val of the ppm value read in bit[0:11]. 1880250003Sadrian * After that do bound check on abs value. 1881250003Sadrian * if value is off limit, CAP the value and and restore signed bit. 1882250003Sadrian */ 1883250003Sadrian if (data_fine & AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_SIGNED_BIT) 1884250003Sadrian { 1885250003Sadrian /* get the positive value */ 1886250003Sadrian data_fine = (~data_fine + 1) & AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK; 1887250003Sadrian signed_val = AH_TRUE; 1888250003Sadrian } 1889250003Sadrian if (data_fine > AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT) 1890250003Sadrian { 1891250008Sadrian HALDEBUG(ah, HAL_DEBUG_REGIO, 1892250003Sadrian "%s Correcting ppm out of range %x\n", 1893250003Sadrian __func__, (data_fine & 0x7ff)); 1894250003Sadrian data_fine = AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT; 1895250003Sadrian } 1896250003Sadrian /* 1897250003Sadrian * Restore signed value if changed above. 1898250003Sadrian * Use typecast to avoid compilation errors 1899250003Sadrian */ 1900250003Sadrian if (signed_val) { 1901250003Sadrian data_fine = (-(int32_t)data_fine) & 1902250003Sadrian AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK; 1903250003Sadrian } 1904250003Sadrian 1905250003Sadrian /* write value */ 1906250003Sadrian data4 = OS_REG_READ(ah, AR_PHY_TIMING2) & 1907250003Sadrian ~(AR_PHY_TIMING2_USE_FORCE_PPM | AR_PHY_TIMING2_FORCE_PPM_VAL); 1908250003Sadrian OS_REG_WRITE(ah, AR_PHY_TIMING2, 1909250003Sadrian data4 | data_fine | AR_PHY_TIMING2_USE_FORCE_PPM); 1910250003Sadrian 1911250003Sadrian return data_fine; 1912250003Sadrian} 1913250003Sadrian 1914250003Sadrianvoid 1915250003Sadrianar9300_ppm_un_force(struct ath_hal *ah) 1916250003Sadrian{ 1917250003Sadrian u_int32_t data4; 1918250003Sadrian 1919250003Sadrian data4 = OS_REG_READ(ah, AR_PHY_TIMING2) & ~AR_PHY_TIMING2_USE_FORCE_PPM; 1920250003Sadrian OS_REG_WRITE(ah, AR_PHY_TIMING2, data4); 1921250003Sadrian} 1922250003Sadrian 1923250003Sadrianu_int32_t 1924250003Sadrianar9300_ppm_arm_trigger(struct ath_hal *ah) 1925250003Sadrian{ 1926250003Sadrian u_int32_t val; 1927250003Sadrian u_int32_t ret; 1928250003Sadrian 1929250003Sadrian val = OS_REG_READ(ah, AR_PHY_CHAN_INFO_MEMORY); 1930250003Sadrian ret = OS_REG_READ(ah, AR_TSF_L32); 1931250003Sadrian OS_REG_WRITE(ah, AR_PHY_CHAN_INFO_MEMORY, 1932250003Sadrian val | AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK); 1933250003Sadrian 1934250003Sadrian /* return low word of TSF at arm time */ 1935250003Sadrian return ret; 1936250003Sadrian} 1937250003Sadrian 1938250003Sadrianint 1939250003Sadrianar9300_ppm_get_trigger(struct ath_hal *ah) 1940250003Sadrian{ 1941250003Sadrian if (OS_REG_READ(ah, AR_PHY_CHAN_INFO_MEMORY) & 1942250003Sadrian AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK) 1943250003Sadrian { 1944250003Sadrian /* has not triggered yet, return AH_FALSE */ 1945250003Sadrian return 0; 1946250003Sadrian } 1947250003Sadrian 1948250003Sadrian /* else triggered, return AH_TRUE */ 1949250003Sadrian return 1; 1950250003Sadrian} 1951250003Sadrian 1952250003Sadrianvoid 1953250003Sadrianar9300_mark_phy_inactive(struct ath_hal *ah) 1954250003Sadrian{ 1955250003Sadrian OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 1956250003Sadrian} 1957250003Sadrian 1958250003Sadrian/* DEBUG */ 1959250003Sadrianu_int32_t 1960250003Sadrianar9300_ppm_get_force_state(struct ath_hal *ah) 1961250003Sadrian{ 1962250003Sadrian return 1963250003Sadrian OS_REG_READ(ah, AR_PHY_TIMING2) & 1964250003Sadrian (AR_PHY_TIMING2_USE_FORCE_PPM | AR_PHY_TIMING2_FORCE_PPM_VAL); 1965250003Sadrian} 1966250003Sadrian 1967250003Sadrian/* 1968250003Sadrian * Return the Cycle counts for rx_frame, rx_clear, and tx_frame 1969250003Sadrian */ 1970250008SadrianHAL_BOOL 1971250008Sadrianar9300_get_mib_cycle_counts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hs) 1972250003Sadrian{ 1973250008Sadrian /* 1974250008Sadrian * XXX FreeBSD todo: reimplement this 1975250008Sadrian */ 1976250008Sadrian#if 0 1977250003Sadrian p_cnts->tx_frame_count = OS_REG_READ(ah, AR_TFCNT); 1978250003Sadrian p_cnts->rx_frame_count = OS_REG_READ(ah, AR_RFCNT); 1979250003Sadrian p_cnts->rx_clear_count = OS_REG_READ(ah, AR_RCCNT); 1980250003Sadrian p_cnts->cycle_count = OS_REG_READ(ah, AR_CCCNT); 1981250003Sadrian p_cnts->is_tx_active = (OS_REG_READ(ah, AR_TFCNT) == 1982250003Sadrian p_cnts->tx_frame_count) ? AH_FALSE : AH_TRUE; 1983250003Sadrian p_cnts->is_rx_active = (OS_REG_READ(ah, AR_RFCNT) == 1984250003Sadrian p_cnts->rx_frame_count) ? AH_FALSE : AH_TRUE; 1985250008Sadrian#endif 1986250008Sadrian return AH_FALSE; 1987250003Sadrian} 1988250003Sadrian 1989250003Sadrianvoid 1990250003Sadrianar9300_clear_mib_counters(struct ath_hal *ah) 1991250003Sadrian{ 1992250003Sadrian u_int32_t reg_val; 1993250003Sadrian 1994250003Sadrian reg_val = OS_REG_READ(ah, AR_MIBC); 1995250003Sadrian OS_REG_WRITE(ah, AR_MIBC, reg_val | AR_MIBC_CMC); 1996250003Sadrian OS_REG_WRITE(ah, AR_MIBC, reg_val & ~AR_MIBC_CMC); 1997250003Sadrian} 1998250003Sadrian 1999250003Sadrian 2000250003Sadrian/* Enable or Disable RIFS Rx capability as part of SW WAR for Bug 31602 */ 2001250003SadrianHAL_BOOL 2002250003Sadrianar9300_set_rifs_delay(struct ath_hal *ah, HAL_BOOL enable) 2003250003Sadrian{ 2004250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 2005250008Sadrian HAL_CHANNEL_INTERNAL *ichan = 2006250008Sadrian ath_hal_checkchannel(ah, AH_PRIVATE(ah)->ah_curchan); 2007250008Sadrian HAL_BOOL is_chan_2g = IS_CHAN_2GHZ(ichan); 2008250008Sadrian u_int32_t tmp = 0; 2009250003Sadrian 2010250003Sadrian if (enable) { 2011250003Sadrian if (ahp->ah_rifs_enabled == AH_TRUE) { 2012250003Sadrian return AH_TRUE; 2013250003Sadrian } 2014250003Sadrian 2015250003Sadrian OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, ahp->ah_rifs_reg[0]); 2016250003Sadrian OS_REG_WRITE(ah, AR_PHY_RIFS_SRCH, 2017250003Sadrian ahp->ah_rifs_reg[1]); 2018250003Sadrian 2019250003Sadrian ahp->ah_rifs_enabled = AH_TRUE; 2020250003Sadrian OS_MEMZERO(ahp->ah_rifs_reg, sizeof(ahp->ah_rifs_reg)); 2021250003Sadrian } else { 2022250003Sadrian if (ahp->ah_rifs_enabled == AH_TRUE) { 2023250003Sadrian ahp->ah_rifs_reg[0] = OS_REG_READ(ah, 2024250003Sadrian AR_PHY_SEARCH_START_DELAY); 2025250003Sadrian ahp->ah_rifs_reg[1] = OS_REG_READ(ah, AR_PHY_RIFS_SRCH); 2026250003Sadrian } 2027250003Sadrian /* Change rifs init delay to 0 */ 2028250003Sadrian OS_REG_WRITE(ah, AR_PHY_RIFS_SRCH, 2029250003Sadrian (ahp->ah_rifs_reg[1] & ~(AR_PHY_RIFS_INIT_DELAY))); 2030250003Sadrian tmp = 0xfffff000 & OS_REG_READ(ah, AR_PHY_SEARCH_START_DELAY); 2031250003Sadrian if (is_chan_2g) { 2032250008Sadrian if (IEEE80211_IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) { 2033250003Sadrian OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 500); 2034250003Sadrian } else { /* Sowl 2G HT-20 default is 0x134 for search start delay */ 2035250003Sadrian OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 250); 2036250003Sadrian } 2037250003Sadrian } else { 2038250008Sadrian if (IEEE80211_IS_CHAN_HT40(AH_PRIVATE(ah)->ah_curchan)) { 2039250003Sadrian OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 0x370); 2040250003Sadrian } else { /* Sowl 5G HT-20 default is 0x1b8 for search start delay */ 2041250003Sadrian OS_REG_WRITE(ah, AR_PHY_SEARCH_START_DELAY, tmp | 0x1b8); 2042250003Sadrian } 2043250003Sadrian } 2044250003Sadrian 2045250003Sadrian ahp->ah_rifs_enabled = AH_FALSE; 2046250003Sadrian } 2047250003Sadrian return AH_TRUE; 2048250003Sadrian 2049250003Sadrian} /* ar9300_set_rifs_delay () */ 2050250003Sadrian 2051250003Sadrian/* Set the current RIFS Rx setting */ 2052250003SadrianHAL_BOOL 2053250003Sadrianar9300_set_11n_rx_rifs(struct ath_hal *ah, HAL_BOOL enable) 2054250003Sadrian{ 2055250003Sadrian /* Non-Owl 11n chips */ 2056250003Sadrian if ((ath_hal_getcapability(ah, HAL_CAP_RIFS_RX, 0, AH_NULL) == HAL_OK)) { 2057250003Sadrian if (ar9300_get_capability(ah, HAL_CAP_LDPCWAR, 0, AH_NULL) == HAL_OK) { 2058250003Sadrian return ar9300_set_rifs_delay(ah, enable); 2059250003Sadrian } 2060250003Sadrian return AH_FALSE; 2061250003Sadrian } 2062250003Sadrian 2063250003Sadrian return AH_TRUE; 2064250003Sadrian} /* ar9300_set_11n_rx_rifs () */ 2065250003Sadrian 2066250003Sadrianstatic hal_mac_hangs_t 2067250003Sadrianar9300_compare_dbg_hang(struct ath_hal *ah, mac_dbg_regs_t mac_dbg, 2068250003Sadrian hal_mac_hang_check_t hang_check, hal_mac_hangs_t hangs, u_int8_t *dcu_chain) 2069250003Sadrian{ 2070250003Sadrian int i = 0; 2071250003Sadrian hal_mac_hangs_t found_hangs = 0; 2072250003Sadrian 2073250003Sadrian if (hangs & dcu_chain_state) { 2074250003Sadrian for (i = 0; i < 6; i++) { 2075250003Sadrian if (((mac_dbg.dma_dbg_4 >> (5 * i)) & 0x1f) == 2076250003Sadrian hang_check.dcu_chain_state) 2077250003Sadrian { 2078250003Sadrian found_hangs |= dcu_chain_state; 2079250003Sadrian *dcu_chain = i; 2080250003Sadrian } 2081250003Sadrian } 2082250003Sadrian for (i = 0; i < 4; i++) { 2083250003Sadrian if (((mac_dbg.dma_dbg_5 >> (5 * i)) & 0x1f) == 2084250003Sadrian hang_check.dcu_chain_state) 2085250003Sadrian { 2086250003Sadrian found_hangs |= dcu_chain_state; 2087250003Sadrian *dcu_chain = i + 6; 2088250003Sadrian } 2089250003Sadrian } 2090250003Sadrian } 2091250003Sadrian 2092250003Sadrian if (hangs & dcu_complete_state) { 2093250003Sadrian if ((mac_dbg.dma_dbg_6 & 0x3) == hang_check.dcu_complete_state) { 2094250003Sadrian found_hangs |= dcu_complete_state; 2095250003Sadrian } 2096250003Sadrian } 2097250003Sadrian 2098250003Sadrian return found_hangs; 2099250003Sadrian 2100250003Sadrian} /* end - ar9300_compare_dbg_hang */ 2101250003Sadrian 2102250003Sadrian#define NUM_STATUS_READS 50 2103250003SadrianHAL_BOOL 2104250003Sadrianar9300_detect_mac_hang(struct ath_hal *ah) 2105250003Sadrian{ 2106250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 2107250003Sadrian mac_dbg_regs_t mac_dbg; 2108250003Sadrian hal_mac_hang_check_t hang_sig1_val = {0x6, 0x1, 0, 0, 0, 0, 0, 0}; 2109250003Sadrian hal_mac_hangs_t hang_sig1 = (dcu_chain_state | dcu_complete_state); 2110250003Sadrian int i = 0; 2111250003Sadrian u_int8_t dcu_chain = 0, current_dcu_chain_state, shift_val; 2112250003Sadrian 2113250003Sadrian if (!(ahp->ah_hang_wars & HAL_MAC_HANG_WAR)) { 2114250003Sadrian return AH_FALSE; 2115250003Sadrian } 2116250003Sadrian 2117250003Sadrian OS_MEMZERO(&mac_dbg, sizeof(mac_dbg)); 2118250003Sadrian 2119250003Sadrian mac_dbg.dma_dbg_4 = OS_REG_READ(ah, AR_DMADBG_4); 2120250003Sadrian mac_dbg.dma_dbg_5 = OS_REG_READ(ah, AR_DMADBG_5); 2121250003Sadrian mac_dbg.dma_dbg_6 = OS_REG_READ(ah, AR_DMADBG_6); 2122250003Sadrian 2123250003Sadrian HALDEBUG(ah, HAL_DEBUG_DFS, " dma regs: %X %X %X \n", 2124250003Sadrian mac_dbg.dma_dbg_4, mac_dbg.dma_dbg_5, 2125250003Sadrian mac_dbg.dma_dbg_6); 2126250003Sadrian 2127250003Sadrian if (hang_sig1 != 2128250003Sadrian ar9300_compare_dbg_hang(ah, mac_dbg, 2129250003Sadrian hang_sig1_val, hang_sig1, &dcu_chain)) 2130250003Sadrian { 2131250003Sadrian HALDEBUG(ah, HAL_DEBUG_DFS, " hang sig1 not found \n"); 2132250003Sadrian return AH_FALSE; 2133250003Sadrian } 2134250003Sadrian 2135250003Sadrian shift_val = (dcu_chain >= 6) ? (dcu_chain-6) : (dcu_chain); 2136250003Sadrian shift_val *= 5; 2137250003Sadrian 2138250003Sadrian for (i = 1; i <= NUM_STATUS_READS; i++) { 2139250003Sadrian if (dcu_chain < 6) { 2140250003Sadrian mac_dbg.dma_dbg_4 = OS_REG_READ(ah, AR_DMADBG_4); 2141250003Sadrian current_dcu_chain_state = 2142250003Sadrian ((mac_dbg.dma_dbg_4 >> shift_val) & 0x1f); 2143250003Sadrian } else { 2144250003Sadrian mac_dbg.dma_dbg_5 = OS_REG_READ(ah, AR_DMADBG_5); 2145250003Sadrian current_dcu_chain_state = ((mac_dbg.dma_dbg_5 >> shift_val) & 0x1f); 2146250003Sadrian } 2147250003Sadrian mac_dbg.dma_dbg_6 = OS_REG_READ(ah, AR_DMADBG_6); 2148250003Sadrian 2149250003Sadrian if (((mac_dbg.dma_dbg_6 & 0x3) != hang_sig1_val.dcu_complete_state) 2150250003Sadrian || (current_dcu_chain_state != hang_sig1_val.dcu_chain_state)) { 2151250003Sadrian return AH_FALSE; 2152250003Sadrian } 2153250003Sadrian } 2154250003Sadrian HALDEBUG(ah, HAL_DEBUG_DFS, "%s sig5count=%d sig6count=%d ", __func__, 2155250003Sadrian ahp->ah_hang[MAC_HANG_SIG1], ahp->ah_hang[MAC_HANG_SIG2]); 2156250003Sadrian ahp->ah_hang[MAC_HANG_SIG1]++; 2157250003Sadrian return AH_TRUE; 2158250003Sadrian 2159250003Sadrian} /* end - ar9300_detect_mac_hang */ 2160250003Sadrian 2161250003Sadrian/* Determine if the baseband is hung by reading the Observation Bus Register */ 2162250003SadrianHAL_BOOL 2163250003Sadrianar9300_detect_bb_hang(struct ath_hal *ah) 2164250003Sadrian{ 2165250003Sadrian#define N(a) (sizeof(a) / sizeof(a[0])) 2166250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 2167250003Sadrian u_int32_t hang_sig = 0; 2168250003Sadrian int i = 0; 2169250003Sadrian /* Check the PCU Observation Bus 1 register (0x806c) NUM_STATUS_READS times 2170250003Sadrian * 2171250003Sadrian * 4 known BB hang signatures - 2172250003Sadrian * [1] bits 8,9,11 are 0. State machine state (bits 25-31) is 0x1E 2173250003Sadrian * [2] bits 8,9 are 1, bit 11 is 0. State machine state (bits 25-31) is 0x52 2174250003Sadrian * [3] bits 8,9 are 1, bit 11 is 0. State machine state (bits 25-31) is 0x18 2175250003Sadrian * [4] bit 10 is 1, bit 11 is 0. WEP state (bits 12-17) is 0x2, 2176250003Sadrian * Rx State (bits 20-24) is 0x7. 2177250003Sadrian */ 2178250003Sadrian hal_hw_hang_check_t hang_list [] = 2179250003Sadrian { 2180250003Sadrian /* Offset Reg Value Reg Mask Hang Offset */ 2181250003Sadrian {AR_OBS_BUS_1, 0x1E000000, 0x7E000B00, BB_HANG_SIG1}, 2182250003Sadrian {AR_OBS_BUS_1, 0x52000B00, 0x7E000B00, BB_HANG_SIG2}, 2183250003Sadrian {AR_OBS_BUS_1, 0x18000B00, 0x7E000B00, BB_HANG_SIG3}, 2184250003Sadrian {AR_OBS_BUS_1, 0x00702400, 0x7E7FFFEF, BB_HANG_SIG4} 2185250003Sadrian }; 2186250003Sadrian 2187250003Sadrian if (!(ahp->ah_hang_wars & (HAL_RIFS_BB_HANG_WAR | 2188250003Sadrian HAL_DFS_BB_HANG_WAR | 2189250003Sadrian HAL_RX_STUCK_LOW_BB_HANG_WAR))) { 2190250003Sadrian return AH_FALSE; 2191250003Sadrian } 2192250003Sadrian 2193250003Sadrian hang_sig = OS_REG_READ(ah, AR_OBS_BUS_1); 2194250003Sadrian for (i = 1; i <= NUM_STATUS_READS; i++) { 2195250003Sadrian if (hang_sig != OS_REG_READ(ah, AR_OBS_BUS_1)) { 2196250003Sadrian return AH_FALSE; 2197250003Sadrian } 2198250003Sadrian } 2199250003Sadrian 2200250003Sadrian for (i = 0; i < N(hang_list); i++) { 2201250003Sadrian if ((hang_sig & hang_list[i].hang_mask) == hang_list[i].hang_val) { 2202250003Sadrian ahp->ah_hang[hang_list[i].hang_offset]++; 2203250003Sadrian HALDEBUG(ah, HAL_DEBUG_DFS, "%s sig1count=%d sig2count=%d " 2204250003Sadrian "sig3count=%d sig4count=%d\n", __func__, 2205250003Sadrian ahp->ah_hang[BB_HANG_SIG1], ahp->ah_hang[BB_HANG_SIG2], 2206250003Sadrian ahp->ah_hang[BB_HANG_SIG3], ahp->ah_hang[BB_HANG_SIG4]); 2207250003Sadrian return AH_TRUE; 2208250003Sadrian } 2209250003Sadrian } 2210250003Sadrian 2211250003Sadrian HALDEBUG(ah, HAL_DEBUG_DFS, "%s Found an unknown BB hang signature! " 2212250003Sadrian "<0x806c>=0x%x\n", __func__, hang_sig); 2213250003Sadrian 2214250003Sadrian return AH_FALSE; 2215250003Sadrian 2216250003Sadrian#undef N 2217250003Sadrian} /* end - ar9300_detect_bb_hang () */ 2218250003Sadrian 2219250003Sadrian#undef NUM_STATUS_READS 2220250003Sadrian 2221250003SadrianHAL_STATUS 2222250003Sadrianar9300_select_ant_config(struct ath_hal *ah, u_int32_t cfg) 2223250003Sadrian{ 2224250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 2225250008Sadrian const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 2226250008Sadrian HAL_CHANNEL_INTERNAL *ichan = ath_hal_checkchannel(ah, chan); 2227250003Sadrian const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 2228250003Sadrian u_int16_t ant_config; 2229250003Sadrian u_int32_t hal_num_ant_config; 2230250003Sadrian 2231250008Sadrian hal_num_ant_config = IS_CHAN_2GHZ(ichan) ? 2232250008Sadrian p_cap->halNumAntCfg2GHz: p_cap->halNumAntCfg5GHz; 2233250003Sadrian 2234250003Sadrian if (cfg < hal_num_ant_config) { 2235250003Sadrian if (HAL_OK == ar9300_eeprom_get_ant_cfg(ahp, chan, cfg, &ant_config)) { 2236250003Sadrian OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config); 2237250003Sadrian return HAL_OK; 2238250003Sadrian } 2239250003Sadrian } 2240250003Sadrian 2241250003Sadrian return HAL_EINVAL; 2242250003Sadrian} 2243250003Sadrian 2244250003Sadrian/* 2245250003Sadrian * Functions to get/set DCS mode 2246250003Sadrian */ 2247250003Sadrianvoid 2248250003Sadrianar9300_set_dcs_mode(struct ath_hal *ah, u_int32_t mode) 2249250003Sadrian{ 2250250008Sadrian AH9300(ah)->ah_dcs_enable = mode; 2251250003Sadrian} 2252250003Sadrian 2253250003Sadrianu_int32_t 2254250003Sadrianar9300_get_dcs_mode(struct ath_hal *ah) 2255250003Sadrian{ 2256250008Sadrian return AH9300(ah)->ah_dcs_enable; 2257250003Sadrian} 2258250003Sadrian 2259250008Sadrian#if ATH_BT_COEX 2260250003Sadrianvoid 2261250003Sadrianar9300_set_bt_coex_info(struct ath_hal *ah, HAL_BT_COEX_INFO *btinfo) 2262250003Sadrian{ 2263250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 2264250003Sadrian 2265250003Sadrian ahp->ah_bt_module = btinfo->bt_module; 2266250003Sadrian ahp->ah_bt_coex_config_type = btinfo->bt_coex_config; 2267250003Sadrian ahp->ah_bt_active_gpio_select = btinfo->bt_gpio_bt_active; 2268250003Sadrian ahp->ah_bt_priority_gpio_select = btinfo->bt_gpio_bt_priority; 2269250003Sadrian ahp->ah_wlan_active_gpio_select = btinfo->bt_gpio_wlan_active; 2270250003Sadrian ahp->ah_bt_active_polarity = btinfo->bt_active_polarity; 2271250003Sadrian ahp->ah_bt_coex_single_ant = btinfo->bt_single_ant; 2272250003Sadrian ahp->ah_bt_wlan_isolation = btinfo->bt_isolation; 2273250003Sadrian} 2274250003Sadrian 2275250003Sadrianvoid 2276250003Sadrianar9300_bt_coex_config(struct ath_hal *ah, HAL_BT_COEX_CONFIG *btconf) 2277250003Sadrian{ 2278250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 2279250003Sadrian HAL_BOOL rx_clear_polarity; 2280250003Sadrian 2281250003Sadrian /* 2282250003Sadrian * For Kiwi and Osprey, the polarity of rx_clear is active high. 2283250003Sadrian * The bt_rxclear_polarity flag from ath_dev needs to be inverted. 2284250003Sadrian */ 2285250003Sadrian rx_clear_polarity = !btconf->bt_rxclear_polarity; 2286250003Sadrian 2287250003Sadrian ahp->ah_bt_coex_mode = (ahp->ah_bt_coex_mode & AR_BT_QCU_THRESH) | 2288250003Sadrian SM(btconf->bt_time_extend, AR_BT_TIME_EXTEND) | 2289250003Sadrian SM(btconf->bt_txstate_extend, AR_BT_TXSTATE_EXTEND) | 2290250003Sadrian SM(btconf->bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) | 2291250003Sadrian SM(btconf->bt_mode, AR_BT_MODE) | 2292250003Sadrian SM(btconf->bt_quiet_collision, AR_BT_QUIET) | 2293250003Sadrian SM(rx_clear_polarity, AR_BT_RX_CLEAR_POLARITY) | 2294250003Sadrian SM(btconf->bt_priority_time, AR_BT_PRIORITY_TIME) | 2295250003Sadrian SM(btconf->bt_first_slot_time, AR_BT_FIRST_SLOT_TIME); 2296250003Sadrian 2297250003Sadrian ahp->ah_bt_coex_mode2 |= SM(btconf->bt_hold_rxclear, AR_BT_HOLD_RX_CLEAR); 2298250003Sadrian 2299250003Sadrian if (ahp->ah_bt_coex_single_ant == AH_FALSE) { 2300250003Sadrian /* Enable ACK to go out even though BT has higher priority. */ 2301250003Sadrian ahp->ah_bt_coex_mode2 |= AR_BT_DISABLE_BT_ANT; 2302250003Sadrian } 2303250003Sadrian} 2304250003Sadrian 2305250003Sadrianvoid 2306250003Sadrianar9300_bt_coex_set_qcu_thresh(struct ath_hal *ah, int qnum) 2307250003Sadrian{ 2308250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 2309250003Sadrian 2310250003Sadrian /* clear the old value, then set the new value */ 2311250003Sadrian ahp->ah_bt_coex_mode &= ~AR_BT_QCU_THRESH; 2312250003Sadrian ahp->ah_bt_coex_mode |= SM(qnum, AR_BT_QCU_THRESH); 2313250003Sadrian} 2314250003Sadrian 2315250003Sadrianvoid 2316250003Sadrianar9300_bt_coex_set_weights(struct ath_hal *ah, u_int32_t stomp_type) 2317250003Sadrian{ 2318250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 2319250003Sadrian 2320250003Sadrian ahp->ah_bt_coex_bt_weight[0] = AR9300_BT_WGHT; 2321250003Sadrian ahp->ah_bt_coex_bt_weight[1] = AR9300_BT_WGHT; 2322250003Sadrian ahp->ah_bt_coex_bt_weight[2] = AR9300_BT_WGHT; 2323250003Sadrian ahp->ah_bt_coex_bt_weight[3] = AR9300_BT_WGHT; 2324250003Sadrian 2325250003Sadrian switch (stomp_type) { 2326250003Sadrian case HAL_BT_COEX_STOMP_ALL: 2327250003Sadrian ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_ALL_WLAN_WGHT0; 2328250003Sadrian ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_ALL_WLAN_WGHT1; 2329250003Sadrian break; 2330250003Sadrian case HAL_BT_COEX_STOMP_LOW: 2331250003Sadrian ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_LOW_WLAN_WGHT0; 2332250003Sadrian ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_LOW_WLAN_WGHT1; 2333250003Sadrian break; 2334250003Sadrian case HAL_BT_COEX_STOMP_ALL_FORCE: 2335250003Sadrian ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_ALL_FORCE_WLAN_WGHT0; 2336250003Sadrian ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_ALL_FORCE_WLAN_WGHT1; 2337250003Sadrian break; 2338250003Sadrian case HAL_BT_COEX_STOMP_LOW_FORCE: 2339250003Sadrian ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_LOW_FORCE_WLAN_WGHT0; 2340250003Sadrian ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_LOW_FORCE_WLAN_WGHT1; 2341250003Sadrian break; 2342250003Sadrian case HAL_BT_COEX_STOMP_NONE: 2343250003Sadrian case HAL_BT_COEX_NO_STOMP: 2344250003Sadrian ahp->ah_bt_coex_wlan_weight[0] = AR9300_STOMP_NONE_WLAN_WGHT0; 2345250003Sadrian ahp->ah_bt_coex_wlan_weight[1] = AR9300_STOMP_NONE_WLAN_WGHT1; 2346250003Sadrian break; 2347250003Sadrian default: 2348250003Sadrian /* There is a force_weight from registry */ 2349250003Sadrian ahp->ah_bt_coex_wlan_weight[0] = stomp_type; 2350250003Sadrian ahp->ah_bt_coex_wlan_weight[1] = stomp_type; 2351250003Sadrian break; 2352250003Sadrian } 2353250003Sadrian} 2354250003Sadrian 2355250003Sadrianvoid 2356250003Sadrianar9300_bt_coex_setup_bmiss_thresh(struct ath_hal *ah, u_int32_t thresh) 2357250003Sadrian{ 2358250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 2359250003Sadrian 2360250003Sadrian /* clear the old value, then set the new value */ 2361250003Sadrian ahp->ah_bt_coex_mode2 &= ~AR_BT_BCN_MISS_THRESH; 2362250003Sadrian ahp->ah_bt_coex_mode2 |= SM(thresh, AR_BT_BCN_MISS_THRESH); 2363250003Sadrian} 2364250003Sadrian 2365250003Sadrianstatic void 2366250003Sadrianar9300_bt_coex_antenna_diversity(struct ath_hal *ah, u_int32_t value) 2367250003Sadrian{ 2368250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 2369250003Sadrian#if ATH_ANT_DIV_COMB 2370250008Sadrian //struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 2371250008Sadrian const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan; 2372250003Sadrian#endif 2373250003Sadrian 2374250003Sadrian if (ahp->ah_bt_coex_flag & HAL_BT_COEX_FLAG_ANT_DIV_ALLOW) 2375250003Sadrian { 2376250003Sadrian if (ahp->ah_diversity_control == HAL_ANT_VARIABLE) 2377250003Sadrian { 2378250003Sadrian /* Config antenna diversity */ 2379250003Sadrian#if ATH_ANT_DIV_COMB 2380250003Sadrian ar9300_ant_ctrl_set_lna_div_use_bt_ant(ah, value, chan); 2381250003Sadrian#endif 2382250003Sadrian } 2383250003Sadrian } 2384250003Sadrian} 2385250003Sadrian 2386250003Sadrian 2387250003Sadrianvoid 2388250003Sadrianar9300_bt_coex_set_parameter(struct ath_hal *ah, u_int32_t type, 2389250003Sadrian u_int32_t value) 2390250003Sadrian{ 2391250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 2392250003Sadrian struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 2393250003Sadrian 2394250003Sadrian switch (type) { 2395250003Sadrian case HAL_BT_COEX_SET_ACK_PWR: 2396250003Sadrian if (value) { 2397250003Sadrian ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_LOW_ACK_PWR; 2398250003Sadrian } else { 2399250003Sadrian ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_LOW_ACK_PWR; 2400250003Sadrian } 2401250008Sadrian ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit, 2402250008Sadrian ahpriv->ah_extraTxPow, 0); 2403250003Sadrian break; 2404250003Sadrian 2405250003Sadrian case HAL_BT_COEX_ANTENNA_DIVERSITY: 2406250003Sadrian if (AR_SREV_POSEIDON(ah)) { 2407250003Sadrian ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_ANT_DIV_ALLOW; 2408250003Sadrian if (value) { 2409250003Sadrian ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_ANT_DIV_ENABLE; 2410250003Sadrian } 2411250003Sadrian else { 2412250003Sadrian ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_ANT_DIV_ENABLE; 2413250003Sadrian } 2414250003Sadrian ar9300_bt_coex_antenna_diversity(ah, value); 2415250003Sadrian } 2416250003Sadrian break; 2417250003Sadrian case HAL_BT_COEX_LOWER_TX_PWR: 2418250003Sadrian if (value) { 2419250003Sadrian ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_LOWER_TX_PWR; 2420250003Sadrian } 2421250003Sadrian else { 2422250003Sadrian ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_LOWER_TX_PWR; 2423250003Sadrian } 2424250008Sadrian ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit, 2425250008Sadrian ahpriv->ah_extraTxPow, 0); 2426250003Sadrian break; 2427250003Sadrian#if ATH_SUPPORT_MCI 2428250003Sadrian case HAL_BT_COEX_MCI_MAX_TX_PWR: 2429250008Sadrian if ((ah->ah_config.ath_hal_mci_config & 2430250003Sadrian ATH_MCI_CONFIG_CONCUR_TX) == ATH_MCI_CONCUR_TX_SHARED_CHN) 2431250003Sadrian { 2432250003Sadrian if (value) { 2433250003Sadrian ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR; 2434250003Sadrian ahp->ah_mci_concur_tx_en = AH_TRUE; 2435250003Sadrian } 2436250003Sadrian else { 2437250003Sadrian ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR; 2438250003Sadrian ahp->ah_mci_concur_tx_en = AH_FALSE; 2439250003Sadrian } 2440250008Sadrian ar9300_set_tx_power_limit(ah, ahpriv->ah_powerLimit, 2441250008Sadrian ahpriv->ah_extraTxPow, 0); 2442250003Sadrian } 2443250003Sadrian HALDEBUG(ah, HAL_DEBUG_BT_COEX, "(MCI) concur_tx_en = %d\n", 2444250003Sadrian ahp->ah_mci_concur_tx_en); 2445250003Sadrian break; 2446250003Sadrian case HAL_BT_COEX_MCI_FTP_STOMP_RX: 2447250003Sadrian if (value) { 2448250003Sadrian ahp->ah_bt_coex_flag |= HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX; 2449250003Sadrian } 2450250003Sadrian else { 2451250003Sadrian ahp->ah_bt_coex_flag &= ~HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX; 2452250003Sadrian } 2453250003Sadrian break; 2454250003Sadrian#endif 2455250003Sadrian default: 2456250003Sadrian break; 2457250003Sadrian } 2458250003Sadrian} 2459250003Sadrian 2460250003Sadrianvoid 2461250003Sadrianar9300_bt_coex_disable(struct ath_hal *ah) 2462250003Sadrian{ 2463250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 2464250003Sadrian 2465250003Sadrian /* Always drive rx_clear_external output as 0 */ 2466250008Sadrian ath_hal_gpioCfgOutput(ah, ahp->ah_wlan_active_gpio_select, 2467250003Sadrian HAL_GPIO_OUTPUT_MUX_AS_OUTPUT); 2468250003Sadrian 2469250003Sadrian if (ahp->ah_bt_coex_single_ant == AH_TRUE) { 2470250003Sadrian OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1); 2471250003Sadrian OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0); 2472250003Sadrian } 2473250003Sadrian 2474250003Sadrian OS_REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE); 2475250003Sadrian OS_REG_WRITE(ah, AR_BT_COEX_MODE2, 0); 2476250003Sadrian OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, 0); 2477250003Sadrian OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, 0); 2478250003Sadrian OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS0, 0); 2479250003Sadrian OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS1, 0); 2480250003Sadrian OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS2, 0); 2481250003Sadrian OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS3, 0); 2482250003Sadrian 2483250003Sadrian ahp->ah_bt_coex_enabled = AH_FALSE; 2484250003Sadrian} 2485250003Sadrian 2486250003Sadrianint 2487250003Sadrianar9300_bt_coex_enable(struct ath_hal *ah) 2488250003Sadrian{ 2489250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 2490250003Sadrian 2491250003Sadrian /* Program coex mode and weight registers to actually enable coex */ 2492250003Sadrian OS_REG_WRITE(ah, AR_BT_COEX_MODE, ahp->ah_bt_coex_mode); 2493250003Sadrian OS_REG_WRITE(ah, AR_BT_COEX_MODE2, ahp->ah_bt_coex_mode2); 2494250003Sadrian OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, ahp->ah_bt_coex_wlan_weight[0]); 2495250003Sadrian OS_REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, ahp->ah_bt_coex_wlan_weight[1]); 2496250003Sadrian OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS0, ahp->ah_bt_coex_bt_weight[0]); 2497250003Sadrian OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS1, ahp->ah_bt_coex_bt_weight[1]); 2498250003Sadrian OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS2, ahp->ah_bt_coex_bt_weight[2]); 2499250003Sadrian OS_REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS3, ahp->ah_bt_coex_bt_weight[3]); 2500250003Sadrian 2501250003Sadrian if (ahp->ah_bt_coex_flag & HAL_BT_COEX_FLAG_LOW_ACK_PWR) { 2502250003Sadrian OS_REG_WRITE(ah, AR_TPC, HAL_BT_COEX_LOW_ACK_POWER); 2503250003Sadrian } else { 2504250003Sadrian OS_REG_WRITE(ah, AR_TPC, HAL_BT_COEX_HIGH_ACK_POWER); 2505250003Sadrian } 2506250003Sadrian 2507250003Sadrian OS_REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1); 2508250003Sadrian if (ahp->ah_bt_coex_single_ant == AH_TRUE) { 2509250003Sadrian OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 1); 2510250003Sadrian } else { 2511250003Sadrian OS_REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0); 2512250003Sadrian } 2513250003Sadrian 2514250003Sadrian if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_3WIRE) { 2515250003Sadrian /* For 3-wire, configure the desired GPIO port for rx_clear */ 2516250008Sadrian ath_hal_gpioCfgOutput(ah, 2517250003Sadrian ahp->ah_wlan_active_gpio_select, 2518250003Sadrian HAL_GPIO_OUTPUT_MUX_AS_WLAN_ACTIVE); 2519250003Sadrian } 2520250003Sadrian else if ((ahp->ah_bt_coex_config_type >= HAL_BT_COEX_CFG_2WIRE_2CH) && 2521250003Sadrian (ahp->ah_bt_coex_config_type <= HAL_BT_COEX_CFG_2WIRE_CH0)) 2522250003Sadrian { 2523250003Sadrian /* For 2-wire, configure the desired GPIO port for TX_FRAME output */ 2524250008Sadrian ath_hal_gpioCfgOutput(ah, 2525250003Sadrian ahp->ah_wlan_active_gpio_select, 2526250003Sadrian HAL_GPIO_OUTPUT_MUX_AS_TX_FRAME); 2527250003Sadrian } 2528250003Sadrian 2529250003Sadrian /* 2530250003Sadrian * Enable a weak pull down on BT_ACTIVE. 2531250003Sadrian * When BT device is disabled, BT_ACTIVE might be floating. 2532250003Sadrian */ 2533250003Sadrian OS_REG_RMW(ah, AR_HOSTIF_REG(ah, AR_GPIO_PDPU), 2534250003Sadrian (AR_GPIO_PULL_DOWN << (ahp->ah_bt_active_gpio_select * 2)), 2535250003Sadrian (AR_GPIO_PDPU_OPTION << (ahp->ah_bt_active_gpio_select * 2))); 2536250003Sadrian 2537250003Sadrian ahp->ah_bt_coex_enabled = AH_TRUE; 2538250003Sadrian 2539250003Sadrian return 0; 2540250003Sadrian} 2541250003Sadrian 2542250003Sadrianu_int32_t ar9300_get_bt_active_gpio(struct ath_hal *ah, u_int32_t reg) 2543250003Sadrian{ 2544250003Sadrian return 0; 2545250003Sadrian} 2546250003Sadrian 2547250003Sadrianu_int32_t ar9300_get_wlan_active_gpio(struct ath_hal *ah, u_int32_t reg,u_int32_t bOn) 2548250003Sadrian{ 2549250003Sadrian return bOn; 2550250003Sadrian} 2551250003Sadrian 2552250003Sadrianvoid 2553250003Sadrianar9300_init_bt_coex(struct ath_hal *ah) 2554250003Sadrian{ 2555250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 2556250003Sadrian 2557250003Sadrian if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_3WIRE) { 2558250003Sadrian OS_REG_SET_BIT(ah, AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), 2559250003Sadrian (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB | 2560250003Sadrian AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB)); 2561250003Sadrian 2562250003Sadrian /* 2563250003Sadrian * Set input mux for bt_prority_async and 2564250003Sadrian * bt_active_async to GPIO pins 2565250003Sadrian */ 2566250003Sadrian OS_REG_RMW_FIELD(ah, 2567250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1), 2568250003Sadrian AR_GPIO_INPUT_MUX1_BT_ACTIVE, 2569250003Sadrian ahp->ah_bt_active_gpio_select); 2570250003Sadrian OS_REG_RMW_FIELD(ah, 2571250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1), 2572250003Sadrian AR_GPIO_INPUT_MUX1_BT_PRIORITY, 2573250003Sadrian ahp->ah_bt_priority_gpio_select); 2574250003Sadrian 2575250003Sadrian /* Configure the desired GPIO ports for input */ 2576250008Sadrian ath_hal_gpioCfgInput(ah, ahp->ah_bt_active_gpio_select); 2577250008Sadrian ath_hal_gpioCfgInput(ah, ahp->ah_bt_priority_gpio_select); 2578250003Sadrian 2579250003Sadrian if (ahp->ah_bt_coex_enabled) { 2580250003Sadrian ar9300_bt_coex_enable(ah); 2581250003Sadrian } else { 2582250003Sadrian ar9300_bt_coex_disable(ah); 2583250003Sadrian } 2584250003Sadrian } 2585250003Sadrian else if ((ahp->ah_bt_coex_config_type >= HAL_BT_COEX_CFG_2WIRE_2CH) && 2586250003Sadrian (ahp->ah_bt_coex_config_type <= HAL_BT_COEX_CFG_2WIRE_CH0)) 2587250003Sadrian { 2588250003Sadrian /* 2-wire */ 2589250003Sadrian if (ahp->ah_bt_coex_enabled) { 2590250003Sadrian /* Connect bt_active_async to baseband */ 2591250003Sadrian OS_REG_CLR_BIT(ah, 2592250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), 2593250003Sadrian (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF | 2594250003Sadrian AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF)); 2595250003Sadrian OS_REG_SET_BIT(ah, 2596250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_INPUT_EN_VAL), 2597250003Sadrian AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB); 2598250003Sadrian 2599250003Sadrian /* 2600250003Sadrian * Set input mux for bt_prority_async and 2601250003Sadrian * bt_active_async to GPIO pins 2602250003Sadrian */ 2603250003Sadrian OS_REG_RMW_FIELD(ah, 2604250003Sadrian AR_HOSTIF_REG(ah, AR_GPIO_INPUT_MUX1), 2605250003Sadrian AR_GPIO_INPUT_MUX1_BT_ACTIVE, 2606250003Sadrian ahp->ah_bt_active_gpio_select); 2607250003Sadrian 2608250003Sadrian /* Configure the desired GPIO ports for input */ 2609250008Sadrian ath_hal_gpioCfgInput(ah, ahp->ah_bt_active_gpio_select); 2610250003Sadrian 2611250003Sadrian /* Enable coexistence on initialization */ 2612250003Sadrian ar9300_bt_coex_enable(ah); 2613250003Sadrian } 2614250003Sadrian } 2615250003Sadrian#if ATH_SUPPORT_MCI 2616250003Sadrian else if (ahp->ah_bt_coex_config_type == HAL_BT_COEX_CFG_MCI) { 2617250003Sadrian if (ahp->ah_bt_coex_enabled) { 2618250003Sadrian ar9300_mci_bt_coex_enable(ah); 2619250003Sadrian } 2620250003Sadrian else { 2621250003Sadrian ar9300_mci_bt_coex_disable(ah); 2622250003Sadrian } 2623250003Sadrian } 2624250003Sadrian#endif /* ATH_SUPPORT_MCI */ 2625250003Sadrian} 2626250003Sadrian 2627250003Sadrian#endif /* ATH_BT_COEX */ 2628250003Sadrian 2629250003SadrianHAL_STATUS ar9300_set_proxy_sta(struct ath_hal *ah, HAL_BOOL enable) 2630250003Sadrian{ 2631250003Sadrian u_int32_t val; 2632250003Sadrian int wasp_mm_rev; 2633250003Sadrian 2634250003Sadrian#define AR_SOC_RST_REVISION_ID 0xB8060090 2635250003Sadrian#define REG_READ(_reg) *((volatile u_int32_t *)(_reg)) 2636250003Sadrian wasp_mm_rev = (REG_READ(AR_SOC_RST_REVISION_ID) & 2637250003Sadrian AR_SREV_REVISION_WASP_MINOR_MINOR_MASK) >> 2638250003Sadrian AR_SREV_REVISION_WASP_MINOR_MINOR_SHIFT; 2639250003Sadrian#undef AR_SOC_RST_REVISION_ID 2640250003Sadrian#undef REG_READ 2641250003Sadrian 2642250003Sadrian /* 2643250003Sadrian * Azimuth (ProxySTA) Mode is only supported correctly by 2644250003Sadrian * Peacock or WASP 1.3.0.1 or later (hopefully) chips. 2645250003Sadrian * 2646250003Sadrian * Enable this feature for Scorpion at this time. The silicon 2647250003Sadrian * still needs to be validated. 2648250003Sadrian */ 2649250003Sadrian if (!(AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_AR9580) && 2650250003Sadrian !(AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_SCORPION) && 2651250003Sadrian !((AH_PRIVATE((ah))->ah_macVersion == AR_SREV_VERSION_WASP) && 2652250003Sadrian ((AH_PRIVATE((ah))->ah_macRev > AR_SREV_REVISION_WASP_13) || 2653250003Sadrian (AH_PRIVATE((ah))->ah_macRev == AR_SREV_REVISION_WASP_13 && 2654250003Sadrian wasp_mm_rev >= 0 /* 1 */)))) 2655250003Sadrian { 2656250003Sadrian HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, "%s error: current chip (ver 0x%x, " 2657250003Sadrian "rev 0x%x, minor minor rev 0x%x) cannot support Azimuth Mode\n", 2658250003Sadrian __func__, AH_PRIVATE((ah))->ah_macVersion, 2659250003Sadrian AH_PRIVATE((ah))->ah_macRev, wasp_mm_rev); 2660250003Sadrian return HAL_ENOTSUPP; 2661250003Sadrian } 2662250003Sadrian 2663250003Sadrian OS_REG_WRITE(ah, 2664250003Sadrian AR_MAC_PCU_LOGIC_ANALYZER, AR_MAC_PCU_LOGIC_ANALYZER_PSTABUG75996); 2665250003Sadrian 2666250003Sadrian /* turn on mode bit[24] for proxy sta */ 2667250003Sadrian OS_REG_WRITE(ah, AR_PCU_MISC_MODE2, 2668250003Sadrian OS_REG_READ(ah, AR_PCU_MISC_MODE2) | AR_PCU_MISC_MODE2_PROXY_STA); 2669250003Sadrian 2670250003Sadrian val = OS_REG_READ(ah, AR_AZIMUTH_MODE); 2671250003Sadrian if (enable) { 2672250003Sadrian val |= AR_AZIMUTH_KEY_SEARCH_AD1 | 2673250003Sadrian AR_AZIMUTH_CTS_MATCH_TX_AD2 | 2674250003Sadrian AR_AZIMUTH_BA_USES_AD1; 2675250003Sadrian /* turn off filter pass hold (bit 9) */ 2676250003Sadrian val &= ~AR_AZIMUTH_FILTER_PASS_HOLD; 2677250003Sadrian } else { 2678250003Sadrian val &= ~(AR_AZIMUTH_KEY_SEARCH_AD1 | 2679250003Sadrian AR_AZIMUTH_CTS_MATCH_TX_AD2 | 2680250003Sadrian AR_AZIMUTH_BA_USES_AD1); 2681250003Sadrian } 2682250003Sadrian OS_REG_WRITE(ah, AR_AZIMUTH_MODE, val); 2683250003Sadrian 2684250003Sadrian /* enable promiscous mode */ 2685250003Sadrian OS_REG_WRITE(ah, AR_RX_FILTER, 2686250003Sadrian OS_REG_READ(ah, AR_RX_FILTER) | HAL_RX_FILTER_PROM); 2687250003Sadrian /* enable promiscous in azimuth mode */ 2688250003Sadrian OS_REG_WRITE(ah, AR_PCU_MISC_MODE2, AR_PCU_MISC_MODE2_PROM_VC_MODE); 2689250003Sadrian OS_REG_WRITE(ah, AR_MAC_PCU_LOGIC_ANALYZER, AR_MAC_PCU_LOGIC_ANALYZER_VC_MODE); 2690250003Sadrian 2691250003Sadrian /* turn on filter pass hold (bit 9) */ 2692250003Sadrian OS_REG_WRITE(ah, AR_AZIMUTH_MODE, 2693250003Sadrian OS_REG_READ(ah, AR_AZIMUTH_MODE) | AR_AZIMUTH_FILTER_PASS_HOLD); 2694250003Sadrian 2695250003Sadrian return HAL_OK; 2696250003Sadrian} 2697250003Sadrian 2698250008Sadrian#if 0 2699250003Sadrianvoid ar9300_mat_enable(struct ath_hal *ah, int enable) 2700250003Sadrian{ 2701250003Sadrian /* 2702250003Sadrian * MAT (s/w ProxySTA) implementation requires to turn off interrupt 2703250003Sadrian * mitigation and turn on key search always for better performance. 2704250003Sadrian */ 2705250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 2706250003Sadrian struct ath_hal_private *ap = AH_PRIVATE(ah); 2707250003Sadrian 2708250003Sadrian ahp->ah_intr_mitigation_rx = !enable; 2709250003Sadrian if (ahp->ah_intr_mitigation_rx) { 2710250003Sadrian /* 2711250003Sadrian * Enable Interrupt Mitigation for Rx. 2712250003Sadrian * If no build-specific limits for the rx interrupt mitigation 2713250003Sadrian * timer have been specified, use conservative defaults. 2714250003Sadrian */ 2715250003Sadrian #ifndef AH_RIMT_VAL_LAST 2716250003Sadrian #define AH_RIMT_LAST_MICROSEC 500 2717250003Sadrian #endif 2718250003Sadrian #ifndef AH_RIMT_VAL_FIRST 2719250003Sadrian #define AH_RIMT_FIRST_MICROSEC 2000 2720250003Sadrian #endif 2721250003Sadrian OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, AH_RIMT_LAST_MICROSEC); 2722250003Sadrian OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, AH_RIMT_FIRST_MICROSEC); 2723250003Sadrian } else { 2724250003Sadrian OS_REG_WRITE(ah, AR_RIMT, 0); 2725250003Sadrian } 2726250003Sadrian 2727250008Sadrian ahp->ah_enable_keysearch_always = !!enable; 2728250008Sadrian ar9300_enable_keysearch_always(ah, ahp->ah_enable_keysearch_always); 2729250003Sadrian} 2730250008Sadrian#endif 2731250003Sadrian 2732250003Sadrianvoid ar9300_enable_tpc(struct ath_hal *ah) 2733250003Sadrian{ 2734250003Sadrian u_int32_t val = 0; 2735250003Sadrian 2736250008Sadrian ah->ah_config.ath_hal_desc_tpc = 1; 2737250003Sadrian 2738250003Sadrian /* Enable TPC */ 2739250003Sadrian OS_REG_RMW_FIELD(ah, AR_PHY_PWRTX_MAX, AR_PHY_PER_PACKET_POWERTX_MAX, 1); 2740250003Sadrian 2741250003Sadrian /* 2742250003Sadrian * Disable per chain power reduction since we are already 2743250003Sadrian * accounting for this in our calculations 2744250003Sadrian */ 2745250003Sadrian val = OS_REG_READ(ah, AR_PHY_POWER_TX_SUB); 2746250003Sadrian if (AR_SREV_WASP(ah)) { 2747250003Sadrian OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB, 2748250003Sadrian val & AR_PHY_POWER_TX_SUB_2_DISABLE); 2749250003Sadrian } else { 2750250003Sadrian OS_REG_WRITE(ah, AR_PHY_POWER_TX_SUB, 2751250003Sadrian val & AR_PHY_POWER_TX_SUB_3_DISABLE); 2752250003Sadrian } 2753250003Sadrian} 2754250003Sadrian 2755250003Sadrian 2756250003Sadrian/* 2757250003Sadrian * ar9300_force_tsf_sync 2758250003Sadrian * This function forces the TSF sync to the given bssid, this is implemented 2759250003Sadrian * as a temp hack to get the AoW demo, and is primarily used in the WDS client 2760250003Sadrian * mode of operation, where we sync the TSF to RootAP TSF values 2761250003Sadrian */ 2762250003Sadrianvoid 2763250003Sadrianar9300_force_tsf_sync(struct ath_hal *ah, const u_int8_t *bssid, 2764250003Sadrian u_int16_t assoc_id) 2765250003Sadrian{ 2766250003Sadrian ar9300_set_operating_mode(ah, HAL_M_STA); 2767250003Sadrian ar9300_write_associd(ah, bssid, assoc_id); 2768250003Sadrian} 2769250003Sadrian 2770250003Sadrianvoid ar9300_chk_rssi_update_tx_pwr(struct ath_hal *ah, int rssi) 2771250003Sadrian{ 2772250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 2773250003Sadrian u_int32_t temp_obdb_reg_val = 0, temp_tcp_reg_val; 2774250003Sadrian u_int32_t temp_powertx_rate9_reg_val; 2775250003Sadrian int8_t olpc_power_offset = 0; 2776250003Sadrian int8_t tmp_olpc_val = 0; 2777250003Sadrian HAL_RSSI_TX_POWER old_greentx_status; 2778250003Sadrian u_int8_t target_power_val_t[ar9300_rate_size]; 2779250003Sadrian int8_t tmp_rss1_thr1, tmp_rss1_thr2; 2780250003Sadrian 2781250003Sadrian if ((AH_PRIVATE(ah)->ah_opmode != HAL_M_STA) || 2782250008Sadrian !ah->ah_config.ath_hal_sta_update_tx_pwr_enable) { 2783250003Sadrian return; 2784250003Sadrian } 2785250003Sadrian 2786250008Sadrian old_greentx_status = AH9300(ah)->green_tx_status; 2787250003Sadrian if (ahp->ah_hw_green_tx_enable) { 2788250003Sadrian tmp_rss1_thr1 = AR9485_HW_GREEN_TX_THRES1_DB; 2789250003Sadrian tmp_rss1_thr2 = AR9485_HW_GREEN_TX_THRES2_DB; 2790250003Sadrian } else { 2791250003Sadrian tmp_rss1_thr1 = WB225_SW_GREEN_TX_THRES1_DB; 2792250003Sadrian tmp_rss1_thr2 = WB225_SW_GREEN_TX_THRES2_DB; 2793250003Sadrian } 2794250003Sadrian 2795250008Sadrian if ((ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S1) 2796250003Sadrian && (rssi > tmp_rss1_thr1)) 2797250003Sadrian { 2798250003Sadrian if (old_greentx_status != HAL_RSSI_TX_POWER_SHORT) { 2799250008Sadrian AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_SHORT; 2800250003Sadrian } 2801250008Sadrian } else if (ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S2 2802250003Sadrian && (rssi > tmp_rss1_thr2)) 2803250003Sadrian { 2804250003Sadrian if (old_greentx_status != HAL_RSSI_TX_POWER_MIDDLE) { 2805250008Sadrian AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_MIDDLE; 2806250003Sadrian } 2807250008Sadrian } else if (ah->ah_config.ath_hal_sta_update_tx_pwr_enable_S3) { 2808250003Sadrian if (old_greentx_status != HAL_RSSI_TX_POWER_LONG) { 2809250008Sadrian AH9300(ah)->green_tx_status = HAL_RSSI_TX_POWER_LONG; 2810250003Sadrian } 2811250003Sadrian } 2812250003Sadrian 2813250003Sadrian /* If status is not change, don't do anything */ 2814250008Sadrian if (old_greentx_status == AH9300(ah)->green_tx_status) { 2815250003Sadrian return; 2816250003Sadrian } 2817250003Sadrian 2818250003Sadrian /* for Poseidon which ath_hal_sta_update_tx_pwr_enable is enabled */ 2819250008Sadrian if ((AH9300(ah)->green_tx_status != HAL_RSSI_TX_POWER_NONE) 2820250003Sadrian && AR_SREV_POSEIDON(ah)) 2821250003Sadrian { 2822250003Sadrian if (ahp->ah_hw_green_tx_enable) { 2823250008Sadrian switch (AH9300(ah)->green_tx_status) { 2824250003Sadrian case HAL_RSSI_TX_POWER_SHORT: 2825250003Sadrian /* 1. TxPower Config */ 2826250003Sadrian OS_MEMCPY(target_power_val_t, ar9485_hw_gtx_tp_distance_short, 2827250003Sadrian sizeof(target_power_val_t)); 2828250003Sadrian /* 1.1 Store OLPC Delta Calibration Offset*/ 2829250003Sadrian olpc_power_offset = 0; 2830250003Sadrian /* 2. Store OB/DB */ 2831250003Sadrian /* 3. Store TPC settting */ 2832250003Sadrian temp_tcp_reg_val = (SM(14, AR_TPC_ACK) | 2833250003Sadrian SM(14, AR_TPC_CTS) | 2834250003Sadrian SM(14, AR_TPC_CHIRP) | 2835250003Sadrian SM(14, AR_TPC_RPT)); 2836250003Sadrian /* 4. Store BB_powertx_rate9 value */ 2837250003Sadrian temp_powertx_rate9_reg_val = 2838250003Sadrian AR9485_BBPWRTXRATE9_HW_GREEN_TX_SHORT_VALUE; 2839250003Sadrian break; 2840250003Sadrian case HAL_RSSI_TX_POWER_MIDDLE: 2841250003Sadrian /* 1. TxPower Config */ 2842250003Sadrian OS_MEMCPY(target_power_val_t, ar9485_hw_gtx_tp_distance_middle, 2843250003Sadrian sizeof(target_power_val_t)); 2844250003Sadrian /* 1.1 Store OLPC Delta Calibration Offset*/ 2845250003Sadrian olpc_power_offset = 0; 2846250003Sadrian /* 2. Store OB/DB */ 2847250003Sadrian /* 3. Store TPC settting */ 2848250003Sadrian temp_tcp_reg_val = (SM(18, AR_TPC_ACK) | 2849250003Sadrian SM(18, AR_TPC_CTS) | 2850250003Sadrian SM(18, AR_TPC_CHIRP) | 2851250003Sadrian SM(18, AR_TPC_RPT)); 2852250003Sadrian /* 4. Store BB_powertx_rate9 value */ 2853250003Sadrian temp_powertx_rate9_reg_val = 2854250003Sadrian AR9485_BBPWRTXRATE9_HW_GREEN_TX_MIDDLE_VALUE; 2855250003Sadrian break; 2856250003Sadrian case HAL_RSSI_TX_POWER_LONG: 2857250003Sadrian default: 2858250003Sadrian /* 1. TxPower Config */ 2859250003Sadrian OS_MEMCPY(target_power_val_t, ahp->ah_default_tx_power, 2860250003Sadrian sizeof(target_power_val_t)); 2861250003Sadrian /* 1.1 Store OLPC Delta Calibration Offset*/ 2862250003Sadrian olpc_power_offset = 0; 2863250003Sadrian /* 2. Store OB/DB1/DB2 */ 2864250003Sadrian /* 3. Store TPC settting */ 2865250003Sadrian temp_tcp_reg_val = 2866250008Sadrian AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC]; 2867250003Sadrian /* 4. Store BB_powertx_rate9 value */ 2868250003Sadrian temp_powertx_rate9_reg_val = 2869250008Sadrian AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9]; 2870250003Sadrian break; 2871250003Sadrian } 2872250003Sadrian } else { 2873250008Sadrian switch (AH9300(ah)->green_tx_status) { 2874250003Sadrian case HAL_RSSI_TX_POWER_SHORT: 2875250003Sadrian /* 1. TxPower Config */ 2876250003Sadrian OS_MEMCPY(target_power_val_t, wb225_sw_gtx_tp_distance_short, 2877250003Sadrian sizeof(target_power_val_t)); 2878250003Sadrian /* 1.1 Store OLPC Delta Calibration Offset*/ 2879250003Sadrian olpc_power_offset = 2880250003Sadrian wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_SHORT_VALUE] - 2881250003Sadrian wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE]; 2882250003Sadrian /* 2. Store OB/DB */ 2883250003Sadrian temp_obdb_reg_val = 2884250008Sadrian AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB]; 2885250003Sadrian temp_obdb_reg_val &= ~(AR_PHY_65NM_CH0_TXRF2_DB2G | 2886250003Sadrian AR_PHY_65NM_CH0_TXRF2_OB2G_CCK | 2887250003Sadrian AR_PHY_65NM_CH0_TXRF2_OB2G_PSK | 2888250003Sadrian AR_PHY_65NM_CH0_TXRF2_OB2G_QAM); 2889250003Sadrian temp_obdb_reg_val |= (SM(5, AR_PHY_65NM_CH0_TXRF2_DB2G) | 2890250003Sadrian SM(WB225_OB_GREEN_TX_SHORT_VALUE, 2891250003Sadrian AR_PHY_65NM_CH0_TXRF2_OB2G_CCK) | 2892250003Sadrian SM(WB225_OB_GREEN_TX_SHORT_VALUE, 2893250003Sadrian AR_PHY_65NM_CH0_TXRF2_OB2G_PSK) | 2894250003Sadrian SM(WB225_OB_GREEN_TX_SHORT_VALUE, 2895250003Sadrian AR_PHY_65NM_CH0_TXRF2_OB2G_QAM)); 2896250003Sadrian /* 3. Store TPC settting */ 2897250003Sadrian temp_tcp_reg_val = (SM(6, AR_TPC_ACK) | 2898250003Sadrian SM(6, AR_TPC_CTS) | 2899250003Sadrian SM(6, AR_TPC_CHIRP) | 2900250003Sadrian SM(6, AR_TPC_RPT)); 2901250003Sadrian /* 4. Store BB_powertx_rate9 value */ 2902250003Sadrian temp_powertx_rate9_reg_val = 2903250003Sadrian WB225_BBPWRTXRATE9_SW_GREEN_TX_SHORT_VALUE; 2904250003Sadrian break; 2905250003Sadrian case HAL_RSSI_TX_POWER_MIDDLE: 2906250003Sadrian /* 1. TxPower Config */ 2907250003Sadrian OS_MEMCPY(target_power_val_t, wb225_sw_gtx_tp_distance_middle, 2908250003Sadrian sizeof(target_power_val_t)); 2909250003Sadrian /* 1.1 Store OLPC Delta Calibration Offset*/ 2910250003Sadrian olpc_power_offset = 2911250003Sadrian wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_MIDDLE_VALUE] - 2912250003Sadrian wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE]; 2913250003Sadrian /* 2. Store OB/DB */ 2914250003Sadrian temp_obdb_reg_val = 2915250008Sadrian AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB]; 2916250003Sadrian temp_obdb_reg_val &= ~(AR_PHY_65NM_CH0_TXRF2_DB2G | 2917250003Sadrian AR_PHY_65NM_CH0_TXRF2_OB2G_CCK | 2918250003Sadrian AR_PHY_65NM_CH0_TXRF2_OB2G_PSK | 2919250003Sadrian AR_PHY_65NM_CH0_TXRF2_OB2G_QAM); 2920250003Sadrian temp_obdb_reg_val |= (SM(5, AR_PHY_65NM_CH0_TXRF2_DB2G) | 2921250003Sadrian SM(WB225_OB_GREEN_TX_MIDDLE_VALUE, 2922250003Sadrian AR_PHY_65NM_CH0_TXRF2_OB2G_CCK) | 2923250003Sadrian SM(WB225_OB_GREEN_TX_MIDDLE_VALUE, 2924250003Sadrian AR_PHY_65NM_CH0_TXRF2_OB2G_PSK) | 2925250003Sadrian SM(WB225_OB_GREEN_TX_MIDDLE_VALUE, 2926250003Sadrian AR_PHY_65NM_CH0_TXRF2_OB2G_QAM)); 2927250003Sadrian /* 3. Store TPC settting */ 2928250003Sadrian temp_tcp_reg_val = (SM(14, AR_TPC_ACK) | 2929250003Sadrian SM(14, AR_TPC_CTS) | 2930250003Sadrian SM(14, AR_TPC_CHIRP) | 2931250003Sadrian SM(14, AR_TPC_RPT)); 2932250003Sadrian /* 4. Store BB_powertx_rate9 value */ 2933250003Sadrian temp_powertx_rate9_reg_val = 2934250003Sadrian WB225_BBPWRTXRATE9_SW_GREEN_TX_MIDDLE_VALUE; 2935250003Sadrian break; 2936250003Sadrian case HAL_RSSI_TX_POWER_LONG: 2937250003Sadrian default: 2938250003Sadrian /* 1. TxPower Config */ 2939250003Sadrian OS_MEMCPY(target_power_val_t, ahp->ah_default_tx_power, 2940250003Sadrian sizeof(target_power_val_t)); 2941250003Sadrian /* 1.1 Store OLPC Delta Calibration Offset*/ 2942250003Sadrian olpc_power_offset = 2943250003Sadrian wb225_gtx_olpc_cal_offset[WB225_OB_GREEN_TX_LONG_VALUE] - 2944250003Sadrian wb225_gtx_olpc_cal_offset[WB225_OB_CALIBRATION_VALUE]; 2945250003Sadrian /* 2. Store OB/DB1/DB2 */ 2946250003Sadrian temp_obdb_reg_val = 2947250008Sadrian AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_OBDB]; 2948250003Sadrian /* 3. Store TPC settting */ 2949250003Sadrian temp_tcp_reg_val = 2950250008Sadrian AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_TPC]; 2951250003Sadrian /* 4. Store BB_powertx_rate9 value */ 2952250003Sadrian temp_powertx_rate9_reg_val = 2953250008Sadrian AH9300(ah)->ah_ob_db1[POSEIDON_STORED_REG_BB_PWRTX_RATE9]; 2954250003Sadrian break; 2955250003Sadrian } 2956250003Sadrian } 2957250003Sadrian /* 1.1 Do OLPC Delta Calibration Offset */ 2958250003Sadrian tmp_olpc_val = 2959250008Sadrian (int8_t) AH9300(ah)->ah_db2[POSEIDON_STORED_REG_G2_OLPC_OFFSET]; 2960250003Sadrian tmp_olpc_val += olpc_power_offset; 2961250003Sadrian OS_REG_RMW(ah, AR_PHY_TPC_11_B0, 2962250003Sadrian (tmp_olpc_val << AR_PHY_TPC_OLPC_GAIN_DELTA_S), 2963250003Sadrian AR_PHY_TPC_OLPC_GAIN_DELTA); 2964250003Sadrian 2965250003Sadrian /* 1.2 TxPower Config */ 2966250003Sadrian ar9300_transmit_power_reg_write(ah, target_power_val_t); 2967250003Sadrian /* 2. Config OB/DB */ 2968250003Sadrian if (!ahp->ah_hw_green_tx_enable) { 2969250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF2, temp_obdb_reg_val); 2970250003Sadrian } 2971250003Sadrian /* 3. config TPC settting */ 2972250003Sadrian OS_REG_WRITE(ah, AR_TPC, temp_tcp_reg_val); 2973250003Sadrian /* 4. config BB_powertx_rate9 value */ 2974250003Sadrian OS_REG_WRITE(ah, AR_PHY_BB_POWERTX_RATE9, temp_powertx_rate9_reg_val); 2975250003Sadrian } 2976250003Sadrian} 2977250003Sadrian 2978250008Sadrian#if 0 2979250003Sadrianvoid 2980250003Sadrianar9300_get_vow_stats( 2981250003Sadrian struct ath_hal *ah, HAL_VOWSTATS* p_stats, u_int8_t vow_reg_flags) 2982250003Sadrian{ 2983250003Sadrian if (vow_reg_flags & AR_REG_TX_FRM_CNT) { 2984250003Sadrian p_stats->tx_frame_count = OS_REG_READ(ah, AR_TFCNT); 2985250003Sadrian } 2986250003Sadrian if (vow_reg_flags & AR_REG_RX_FRM_CNT) { 2987250003Sadrian p_stats->rx_frame_count = OS_REG_READ(ah, AR_RFCNT); 2988250003Sadrian } 2989250003Sadrian if (vow_reg_flags & AR_REG_RX_CLR_CNT) { 2990250003Sadrian p_stats->rx_clear_count = OS_REG_READ(ah, AR_RCCNT); 2991250003Sadrian } 2992250003Sadrian if (vow_reg_flags & AR_REG_CYCLE_CNT) { 2993250003Sadrian p_stats->cycle_count = OS_REG_READ(ah, AR_CCCNT); 2994250003Sadrian } 2995250003Sadrian if (vow_reg_flags & AR_REG_EXT_CYCLE_CNT) { 2996250003Sadrian p_stats->ext_cycle_count = OS_REG_READ(ah, AR_EXTRCCNT); 2997250003Sadrian } 2998250003Sadrian} 2999250008Sadrian#endif 3000250008Sadrian 3001250003Sadrian/* 3002250003Sadrian * ar9300_is_skip_paprd_by_greentx 3003250003Sadrian * 3004250003Sadrian * This function check if we need to skip PAPRD tuning 3005250003Sadrian * when GreenTx in specific state. 3006250003Sadrian */ 3007250008SadrianHAL_BOOL 3008250003Sadrianar9300_is_skip_paprd_by_greentx(struct ath_hal *ah) 3009250003Sadrian{ 3010250003Sadrian if (AR_SREV_POSEIDON(ah) && 3011250008Sadrian ah->ah_config.ath_hal_sta_update_tx_pwr_enable && 3012250008Sadrian ((AH9300(ah)->green_tx_status == HAL_RSSI_TX_POWER_SHORT) || 3013250008Sadrian (AH9300(ah)->green_tx_status == HAL_RSSI_TX_POWER_MIDDLE))) 3014250003Sadrian { 3015250003Sadrian return AH_TRUE; 3016250003Sadrian } 3017250003Sadrian return AH_FALSE; 3018250003Sadrian} 3019250003Sadrian 3020250003Sadrianvoid 3021250003Sadrianar9300_control_signals_for_green_tx_mode(struct ath_hal *ah) 3022250003Sadrian{ 3023250003Sadrian unsigned int valid_obdb_0_b0 = 0x2d; // 5,5 - dB[0:2],oB[5:3] 3024250003Sadrian unsigned int valid_obdb_1_b0 = 0x25; // 4,5 - dB[0:2],oB[5:3] 3025250003Sadrian unsigned int valid_obdb_2_b0 = 0x1d; // 3,5 - dB[0:2],oB[5:3] 3026250003Sadrian unsigned int valid_obdb_3_b0 = 0x15; // 2,5 - dB[0:2],oB[5:3] 3027250003Sadrian unsigned int valid_obdb_4_b0 = 0xd; // 1,5 - dB[0:2],oB[5:3] 3028250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 3029250003Sadrian 3030250003Sadrian if (AR_SREV_POSEIDON(ah) && ahp->ah_hw_green_tx_enable) { 3031250003Sadrian OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, 3032250003Sadrian AR_PHY_PAPRD_VALID_OBDB_0, valid_obdb_0_b0); 3033250003Sadrian OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, 3034250003Sadrian AR_PHY_PAPRD_VALID_OBDB_1, valid_obdb_1_b0); 3035250003Sadrian OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, 3036250003Sadrian AR_PHY_PAPRD_VALID_OBDB_2, valid_obdb_2_b0); 3037250003Sadrian OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, 3038250003Sadrian AR_PHY_PAPRD_VALID_OBDB_3, valid_obdb_3_b0); 3039250003Sadrian OS_REG_RMW_FIELD_ALT(ah, AR_PHY_PAPRD_VALID_OBDB_POSEIDON, 3040250003Sadrian AR_PHY_PAPRD_VALID_OBDB_4, valid_obdb_4_b0); 3041250003Sadrian } 3042250003Sadrian} 3043250003Sadrian 3044250003Sadrianvoid ar9300_hwgreentx_set_pal_spare(struct ath_hal *ah, int value) 3045250003Sadrian{ 3046250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 3047250003Sadrian 3048250003Sadrian if (AR_SREV_POSEIDON(ah) && ahp->ah_hw_green_tx_enable) { 3049250003Sadrian if ((value == 0) || (value == 1)) { 3050250003Sadrian OS_REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_TXRF3, 3051250003Sadrian AR_PHY_65NM_CH0_TXRF3_OLD_PAL_SPARE, value); 3052250003Sadrian } 3053250003Sadrian } 3054250003Sadrian} 3055250003Sadrian 3056250003Sadrianvoid ar9300_reset_hw_beacon_proc_crc(struct ath_hal *ah) 3057250003Sadrian{ 3058250003Sadrian OS_REG_SET_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_RESET_CRC); 3059250003Sadrian} 3060250003Sadrian 3061250003Sadrianint32_t ar9300_get_hw_beacon_rssi(struct ath_hal *ah) 3062250003Sadrian{ 3063250003Sadrian int32_t val = OS_REG_READ_FIELD(ah, AR_BCN_RSSI_AVE, AR_BCN_RSSI_AVE_VAL); 3064250003Sadrian 3065250003Sadrian /* RSSI format is 8.4. Ignore lowest four bits */ 3066250003Sadrian val = val >> 4; 3067250003Sadrian return val; 3068250003Sadrian} 3069250003Sadrian 3070250003Sadrianvoid ar9300_set_hw_beacon_rssi_threshold(struct ath_hal *ah, 3071250003Sadrian u_int32_t rssi_threshold) 3072250003Sadrian{ 3073250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 3074250003Sadrian 3075250003Sadrian OS_REG_RMW_FIELD(ah, AR_RSSI_THR, AR_RSSI_THR_VAL, rssi_threshold); 3076250003Sadrian 3077250003Sadrian /* save value for restoring after chip reset */ 3078250003Sadrian ahp->ah_beacon_rssi_threshold = rssi_threshold; 3079250003Sadrian} 3080250003Sadrian 3081250003Sadrianvoid ar9300_reset_hw_beacon_rssi(struct ath_hal *ah) 3082250003Sadrian{ 3083250003Sadrian OS_REG_SET_BIT(ah, AR_RSSI_THR, AR_RSSI_BCN_RSSI_RST); 3084250003Sadrian} 3085250003Sadrian 3086250003Sadrianvoid ar9300_set_hw_beacon_proc(struct ath_hal *ah, HAL_BOOL on) 3087250003Sadrian{ 3088250003Sadrian if (on) { 3089250003Sadrian OS_REG_SET_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_CRC_ENABLE | 3090250003Sadrian AR_HWBCNPROC1_EXCLUDE_TIM_ELM); 3091250003Sadrian } 3092250003Sadrian else { 3093250003Sadrian OS_REG_CLR_BIT(ah, AR_HWBCNPROC1, AR_HWBCNPROC1_CRC_ENABLE | 3094250003Sadrian AR_HWBCNPROC1_EXCLUDE_TIM_ELM); 3095250003Sadrian } 3096250003Sadrian} 3097250003Sadrian/* 3098250003Sadrian * Gets the contents of the specified key cache entry. 3099250003Sadrian */ 3100250003SadrianHAL_BOOL 3101250003Sadrianar9300_print_keycache(struct ath_hal *ah) 3102250003Sadrian{ 3103250003Sadrian 3104250003Sadrian const HAL_CAPABILITIES *p_cap = &AH_PRIVATE(ah)->ah_caps; 3105250003Sadrian u_int32_t key0, key1, key2, key3, key4; 3106250003Sadrian u_int32_t mac_hi, mac_lo; 3107250003Sadrian u_int16_t entry = 0; 3108250003Sadrian u_int32_t valid = 0; 3109250003Sadrian u_int32_t key_type; 3110250003Sadrian 3111250003Sadrian ath_hal_printf(ah, "Slot Key\t\t\t Valid Type Mac \n"); 3112250003Sadrian 3113250008Sadrian for (entry = 0 ; entry < p_cap->halKeyCacheSize; entry++) { 3114250003Sadrian key0 = OS_REG_READ(ah, AR_KEYTABLE_KEY0(entry)); 3115250003Sadrian key1 = OS_REG_READ(ah, AR_KEYTABLE_KEY1(entry)); 3116250003Sadrian key2 = OS_REG_READ(ah, AR_KEYTABLE_KEY2(entry)); 3117250003Sadrian key3 = OS_REG_READ(ah, AR_KEYTABLE_KEY3(entry)); 3118250003Sadrian key4 = OS_REG_READ(ah, AR_KEYTABLE_KEY4(entry)); 3119250003Sadrian 3120250003Sadrian key_type = OS_REG_READ(ah, AR_KEYTABLE_TYPE(entry)); 3121250003Sadrian 3122250003Sadrian mac_lo = OS_REG_READ(ah, AR_KEYTABLE_MAC0(entry)); 3123250003Sadrian mac_hi = OS_REG_READ(ah, AR_KEYTABLE_MAC1(entry)); 3124250003Sadrian 3125250003Sadrian if (mac_hi & AR_KEYTABLE_VALID) { 3126250003Sadrian valid = 1; 3127250003Sadrian } else { 3128250003Sadrian valid = 0; 3129250003Sadrian } 3130250003Sadrian 3131250003Sadrian if ((mac_hi != 0) && (mac_lo != 0)) { 3132250003Sadrian mac_hi &= ~0x8000; 3133250003Sadrian mac_hi <<= 1; 3134250003Sadrian mac_hi |= ((mac_lo & (1 << 31) )) >> 31; 3135250003Sadrian mac_lo <<= 1; 3136250003Sadrian } 3137250003Sadrian 3138250003Sadrian ath_hal_printf(ah, 3139250003Sadrian "%03d " 3140250003Sadrian "%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x" 3141250003Sadrian " %02d %02d " 3142250003Sadrian "%02x:%02x:%02x:%02x:%02x:%02x \n", 3143250003Sadrian entry, 3144250003Sadrian (key0 << 24) >> 24, (key0 << 16) >> 24, 3145250003Sadrian (key0 << 8) >> 24, key0 >> 24, 3146250003Sadrian (key1 << 24) >> 24, (key1 << 16) >> 24, 3147250003Sadrian //(key1 << 8) >> 24, key1 >> 24, 3148250003Sadrian (key2 << 24) >> 24, (key2 << 16) >> 24, 3149250003Sadrian (key2 << 8) >> 24, key2 >> 24, 3150250003Sadrian (key3 << 24) >> 24, (key3 << 16) >> 24, 3151250003Sadrian //(key3 << 8) >> 24, key3 >> 24, 3152250003Sadrian (key4 << 24) >> 24, (key4 << 16) >> 24, 3153250003Sadrian (key4 << 8) >> 24, key4 >> 24, 3154250003Sadrian valid, key_type, 3155250003Sadrian (mac_lo << 24) >> 24, (mac_lo << 16) >> 24, (mac_lo << 8) >> 24, 3156250003Sadrian (mac_lo) >> 24, (mac_hi << 24) >> 24, (mac_hi << 16) >> 24 ); 3157250003Sadrian } 3158250003Sadrian 3159250003Sadrian return AH_TRUE; 3160250003Sadrian} 3161250003Sadrian 3162250003Sadrian/* enable/disable smart antenna mode */ 3163250008SadrianHAL_BOOL 3164250008Sadrianar9300_set_smart_antenna(struct ath_hal *ah, HAL_BOOL enable) 3165250003Sadrian{ 3166250003Sadrian struct ath_hal_9300 *ahp = AH9300(ah); 3167250003Sadrian 3168250003Sadrian if (enable) { 3169250003Sadrian OS_REG_SET_BIT(ah, AR_XRTO, AR_ENABLE_SMARTANTENNA); 3170250003Sadrian } else { 3171250003Sadrian OS_REG_CLR_BIT(ah, AR_XRTO, AR_ENABLE_SMARTANTENNA); 3172250003Sadrian } 3173250003Sadrian 3174250003Sadrian /* if scropion and smart antenna is enabled, write swcom1 with 0x440 3175250003Sadrian * and swcom2 with 0 3176250003Sadrian * FIXME Ideally these registers need to be made read from caldata. 3177250003Sadrian * Until the calibration team gets them, keep them along with board 3178250003Sadrian * configuration. 3179250003Sadrian */ 3180250003Sadrian if (enable && AR_SREV_SCORPION(ah) && 3181250003Sadrian (HAL_OK == ar9300_get_capability(ah, HAL_CAP_SMARTANTENNA, 0,0))) { 3182250003Sadrian 3183250003Sadrian OS_REG_WRITE(ah, AR_PHY_SWITCH_COM, 0x440); 3184250003Sadrian OS_REG_WRITE(ah, AR_PHY_SWITCH_COM_2, 0); 3185250003Sadrian } 3186250003Sadrian 3187250003Sadrian ahp->ah_smartantenna_enable = enable; 3188250003Sadrian return 1; 3189250003Sadrian} 3190250003Sadrian 3191250003Sadrian#ifdef ATH_TX99_DIAG 3192250003Sadrian#ifndef ATH_SUPPORT_HTC 3193250008Sadrianvoid 3194250003Sadrianar9300_tx99_channel_pwr_update(struct ath_hal *ah, HAL_CHANNEL *c, 3195250003Sadrian u_int32_t txpower) 3196250003Sadrian{ 3197250003Sadrian#define PWR_MAS(_r, _s) (((_r) & 0x3f) << (_s)) 3198250003Sadrian static int16_t p_pwr_array[ar9300_rate_size] = { 0 }; 3199250003Sadrian int32_t i; 3200250003Sadrian 3201250003Sadrian /* The max power is limited to 63 */ 3202250003Sadrian if (txpower <= AR9300_MAX_RATE_POWER) { 3203250003Sadrian for (i = 0; i < ar9300_rate_size; i++) { 3204250003Sadrian p_pwr_array[i] = txpower; 3205250003Sadrian } 3206250003Sadrian } else { 3207250003Sadrian for (i = 0; i < ar9300_rate_size; i++) { 3208250003Sadrian p_pwr_array[i] = AR9300_MAX_RATE_POWER; 3209250003Sadrian } 3210250003Sadrian } 3211250003Sadrian 3212250003Sadrian OS_REG_WRITE(ah, 0xa458, 0); 3213250003Sadrian 3214250003Sadrian /* Write the OFDM power per rate set */ 3215250003Sadrian /* 6 (LSB), 9, 12, 18 (MSB) */ 3216250003Sadrian OS_REG_WRITE(ah, 0xa3c0, 3217250003Sadrian PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 24) 3218250003Sadrian | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 16) 3219250003Sadrian | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 8) 3220250003Sadrian | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0) 3221250003Sadrian ); 3222250003Sadrian /* 24 (LSB), 36, 48, 54 (MSB) */ 3223250003Sadrian OS_REG_WRITE(ah, 0xa3c4, 3224250003Sadrian PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_54], 24) 3225250003Sadrian | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_48], 16) 3226250003Sadrian | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_36], 8) 3227250003Sadrian | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0) 3228250003Sadrian ); 3229250003Sadrian 3230250003Sadrian /* Write the CCK power per rate set */ 3231250003Sadrian /* 1L (LSB), reserved, 2L, 2S (MSB) */ 3232250003Sadrian OS_REG_WRITE(ah, 0xa3c8, 3233250003Sadrian PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 24) 3234250003Sadrian | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 16) 3235250003Sadrian /* | PWR_MAS(txPowerTimes2, 8) */ /* this is reserved for Osprey */ 3236250003Sadrian | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0) 3237250003Sadrian ); 3238250003Sadrian /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */ 3239250003Sadrian OS_REG_WRITE(ah, 0xa3cc, 3240250003Sadrian PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_11S], 24) 3241250003Sadrian | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_11L], 16) 3242250003Sadrian | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_5S], 8) 3243250003Sadrian | PWR_MAS(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0) 3244250003Sadrian ); 3245250003Sadrian 3246250003Sadrian /* Write the HT20 power per rate set */ 3247250003Sadrian /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */ 3248250003Sadrian OS_REG_WRITE(ah, 0xa3d0, 3249250003Sadrian PWR_MAS(p_pwr_array[ALL_TARGET_HT20_5], 24) 3250250003Sadrian | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_4], 16) 3251250003Sadrian | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_1_3_9_11_17_19], 8) 3252250003Sadrian | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_0_8_16], 0) 3253250003Sadrian ); 3254250003Sadrian 3255250003Sadrian /* 6 (LSB), 7, 12, 13 (MSB) */ 3256250003Sadrian OS_REG_WRITE(ah, 0xa3d4, 3257250003Sadrian PWR_MAS(p_pwr_array[ALL_TARGET_HT20_13], 24) 3258250003Sadrian | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_12], 16) 3259250003Sadrian | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_7], 8) 3260250003Sadrian | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_6], 0) 3261250003Sadrian ); 3262250003Sadrian 3263250003Sadrian /* 14 (LSB), 15, 20, 21 */ 3264250003Sadrian OS_REG_WRITE(ah, 0xa3e4, 3265250003Sadrian PWR_MAS(p_pwr_array[ALL_TARGET_HT20_21], 24) 3266250003Sadrian | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_20], 16) 3267250003Sadrian | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_15], 8) 3268250003Sadrian | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_14], 0) 3269250003Sadrian ); 3270250003Sadrian 3271250003Sadrian /* Mixed HT20 and HT40 rates */ 3272250003Sadrian /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */ 3273250003Sadrian OS_REG_WRITE(ah, 0xa3e8, 3274250003Sadrian PWR_MAS(p_pwr_array[ALL_TARGET_HT40_23], 24) 3275250003Sadrian | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_22], 16) 3276250003Sadrian | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_23], 8) 3277250003Sadrian | PWR_MAS(p_pwr_array[ALL_TARGET_HT20_22], 0) 3278250003Sadrian ); 3279250003Sadrian 3280250003Sadrian /* Write the HT40 power per rate set */ 3281250003Sadrian /* correct PAR difference between HT40 and HT20/LEGACY */ 3282250003Sadrian /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */ 3283250003Sadrian OS_REG_WRITE(ah, 0xa3d8, 3284250003Sadrian PWR_MAS(p_pwr_array[ALL_TARGET_HT40_5], 24) 3285250003Sadrian | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_4], 16) 3286250003Sadrian | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_1_3_9_11_17_19], 8) 3287250003Sadrian | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_0_8_16], 0) 3288250003Sadrian ); 3289250003Sadrian 3290250003Sadrian /* 6 (LSB), 7, 12, 13 (MSB) */ 3291250003Sadrian OS_REG_WRITE(ah, 0xa3dc, 3292250003Sadrian PWR_MAS(p_pwr_array[ALL_TARGET_HT40_13], 24) 3293250003Sadrian | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_12], 16) 3294250003Sadrian | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_7], 8) 3295250003Sadrian | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_6], 0) 3296250003Sadrian ); 3297250003Sadrian 3298250003Sadrian /* 14 (LSB), 15, 20, 21 */ 3299250003Sadrian OS_REG_WRITE(ah, 0xa3ec, 3300250003Sadrian PWR_MAS(p_pwr_array[ALL_TARGET_HT40_21], 24) 3301250003Sadrian | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_20], 16) 3302250003Sadrian | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_15], 8) 3303250003Sadrian | PWR_MAS(p_pwr_array[ALL_TARGET_HT40_14], 0) 3304250003Sadrian ); 3305250003Sadrian#undef PWR_MAS 3306250003Sadrian} 3307250003Sadrian 3308250003Sadrianvoid 3309250003Sadrianar9300_tx99_chainmsk_setup(struct ath_hal *ah, int tx_chainmask) 3310250003Sadrian{ 3311250003Sadrian if (tx_chainmask == 0x5) { 3312250003Sadrian OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP, 3313250003Sadrian OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | AR_PHY_SWAP_ALT_CHAIN); 3314250003Sadrian } 3315250003Sadrian OS_REG_WRITE(ah, AR_PHY_RX_CHAINMASK, tx_chainmask); 3316250003Sadrian OS_REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, tx_chainmask); 3317250003Sadrian 3318250003Sadrian OS_REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask); 3319250003Sadrian if (tx_chainmask == 0x5) { 3320250003Sadrian OS_REG_WRITE(ah, AR_PHY_ANALOG_SWAP, 3321250003Sadrian OS_REG_READ(ah, AR_PHY_ANALOG_SWAP) | AR_PHY_SWAP_ALT_CHAIN); 3322250003Sadrian } 3323250003Sadrian} 3324250003Sadrian 3325250003Sadrianvoid 3326250003Sadrianar9300_tx99_set_single_carrier(struct ath_hal *ah, int tx_chain_mask, 3327250003Sadrian int chtype) 3328250003Sadrian{ 3329250003Sadrian OS_REG_WRITE(ah, 0x98a4, OS_REG_READ(ah, 0x98a4) | (0x7ff << 11) | 0x7ff); 3330250003Sadrian OS_REG_WRITE(ah, 0xa364, OS_REG_READ(ah, 0xa364) | (1 << 7) | (1 << 1)); 3331250003Sadrian OS_REG_WRITE(ah, 0xa350, 3332250003Sadrian (OS_REG_READ(ah, 0xa350) | (1 << 31) | (1 << 15)) & ~(1 << 13)); 3333250003Sadrian 3334250003Sadrian /* 11G mode */ 3335250003Sadrian if (!chtype) { 3336250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, 3337250003Sadrian OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) | (0x1 << 3) | (0x1 << 2)); 3338250003Sadrian if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3339250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, 3340250003Sadrian OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4)); 3341250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, 3342250003Sadrian (OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) 3343250003Sadrian | (0x1 << 26) | (0x7 << 24)) 3344250003Sadrian & ~(0x1 << 22)); 3345250003Sadrian } else { 3346250003Sadrian OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, 3347250003Sadrian OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4)); 3348250003Sadrian OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, 3349250003Sadrian (OS_REG_READ(ah, AR_HORNET_CH0_TOP2) 3350250003Sadrian | (0x1 << 26) | (0x7 << 24)) 3351250003Sadrian & ~(0x1 << 22)); 3352250003Sadrian } 3353250003Sadrian 3354250003Sadrian /* chain zero */ 3355250003Sadrian if ((tx_chain_mask & 0x01) == 0x01) { 3356250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX1, 3357250003Sadrian (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX1) 3358250003Sadrian | (0x1 << 31) | (0x5 << 15) 3359250003Sadrian | (0x3 << 9)) & ~(0x1 << 27) 3360250003Sadrian & ~(0x1 << 12)); 3361250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, 3362250003Sadrian (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) 3363250003Sadrian | (0x1 << 12) | (0x1 << 10) 3364250003Sadrian | (0x1 << 9) | (0x1 << 8) 3365250003Sadrian | (0x1 << 7)) & ~(0x1 << 11)); 3366250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, 3367250003Sadrian (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) 3368250003Sadrian | (0x1 << 29) | (0x1 << 25) 3369250003Sadrian | (0x1 << 23) | (0x1 << 19) 3370250003Sadrian | (0x1 << 10) | (0x1 << 9) 3371250003Sadrian | (0x1 << 8) | (0x1 << 3)) 3372250003Sadrian & ~(0x1 << 28)& ~(0x1 << 24) 3373250003Sadrian & ~(0x1 << 22)& ~(0x1 << 7)); 3374250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, 3375250003Sadrian (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) 3376250003Sadrian | (0x1 << 23))& ~(0x1 << 21)); 3377250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB1, 3378250003Sadrian OS_REG_READ(ah, AR_PHY_65NM_CH0_BB1) 3379250003Sadrian | (0x1 << 12) | (0x1 << 10) 3380250003Sadrian | (0x1 << 9) | (0x1 << 8) 3381250003Sadrian | (0x1 << 6) | (0x1 << 5) 3382250003Sadrian | (0x1 << 4) | (0x1 << 3) 3383250003Sadrian | (0x1 << 2)); 3384250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB2, 3385250003Sadrian OS_REG_READ(ah, AR_PHY_65NM_CH0_BB2) | (0x1 << 31)); 3386250003Sadrian } 3387250003Sadrian if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3388250003Sadrian /* chain one */ 3389250003Sadrian if ((tx_chain_mask & 0x02) == 0x02 ) { 3390250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX1, 3391250003Sadrian (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX1) 3392250003Sadrian | (0x1 << 31) | (0x5 << 15) 3393250003Sadrian | (0x3 << 9)) & ~(0x1 << 27) 3394250003Sadrian & ~(0x1 << 12)); 3395250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, 3396250003Sadrian (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) 3397250003Sadrian | (0x1 << 12) | (0x1 << 10) 3398250003Sadrian | (0x1 << 9) | (0x1 << 8) 3399250003Sadrian | (0x1 << 7)) & ~(0x1 << 11)); 3400250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, 3401250003Sadrian (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) 3402250003Sadrian | (0x1 << 29) | (0x1 << 25) 3403250003Sadrian | (0x1 << 23) | (0x1 << 19) 3404250003Sadrian | (0x1 << 10) | (0x1 << 9) 3405250003Sadrian | (0x1 << 8) | (0x1 << 3)) 3406250003Sadrian & ~(0x1 << 28)& ~(0x1 << 24) 3407250003Sadrian & ~(0x1 << 22)& ~(0x1 << 7)); 3408250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, 3409250003Sadrian (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) 3410250003Sadrian | (0x1 << 23))& ~(0x1 << 21)); 3411250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB1, 3412250003Sadrian OS_REG_READ(ah, AR_PHY_65NM_CH1_BB1) 3413250003Sadrian | (0x1 << 12) | (0x1 << 10) 3414250003Sadrian | (0x1 << 9) | (0x1 << 8) 3415250003Sadrian | (0x1 << 6) | (0x1 << 5) 3416250003Sadrian | (0x1 << 4) | (0x1 << 3) 3417250003Sadrian | (0x1 << 2)); 3418250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB2, 3419250003Sadrian OS_REG_READ(ah, AR_PHY_65NM_CH1_BB2) | (0x1 << 31)); 3420250003Sadrian } 3421250003Sadrian } 3422250003Sadrian if (AR_SREV_OSPREY(ah)) { 3423250003Sadrian /* chain two */ 3424250003Sadrian if ((tx_chain_mask & 0x04) == 0x04 ) { 3425250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX1, 3426250003Sadrian (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX1) 3427250003Sadrian | (0x1 << 31) | (0x5 << 15) 3428250003Sadrian | (0x3 << 9)) & ~(0x1 << 27) 3429250003Sadrian & ~(0x1 << 12)); 3430250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, 3431250003Sadrian (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) 3432250003Sadrian | (0x1 << 12) | (0x1 << 10) 3433250003Sadrian | (0x1 << 9) | (0x1 << 8) 3434250003Sadrian | (0x1 << 7)) & ~(0x1 << 11)); 3435250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, 3436250003Sadrian (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) 3437250003Sadrian | (0x1 << 29) | (0x1 << 25) 3438250003Sadrian | (0x1 << 23) | (0x1 << 19) 3439250003Sadrian | (0x1 << 10) | (0x1 << 9) 3440250003Sadrian | (0x1 << 8) | (0x1 << 3)) 3441250003Sadrian & ~(0x1 << 28)& ~(0x1 << 24) 3442250003Sadrian & ~(0x1 << 22)& ~(0x1 << 7)); 3443250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, 3444250003Sadrian (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) 3445250003Sadrian | (0x1 << 23))& ~(0x1 << 21)); 3446250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB1, 3447250003Sadrian OS_REG_READ(ah, AR_PHY_65NM_CH2_BB1) 3448250003Sadrian | (0x1 << 12) | (0x1 << 10) 3449250003Sadrian | (0x1 << 9) | (0x1 << 8) 3450250003Sadrian | (0x1 << 6) | (0x1 << 5) 3451250003Sadrian | (0x1 << 4) | (0x1 << 3) 3452250003Sadrian | (0x1 << 2)); 3453250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB2, 3454250003Sadrian OS_REG_READ(ah, AR_PHY_65NM_CH2_BB2) | (0x1 << 31)); 3455250003Sadrian } 3456250003Sadrian } 3457250003Sadrian 3458250003Sadrian OS_REG_WRITE(ah, 0xa28c, 0x11111); 3459250003Sadrian OS_REG_WRITE(ah, 0xa288, 0x111); 3460250003Sadrian } else { 3461250003Sadrian /* chain zero */ 3462250003Sadrian if ((tx_chain_mask & 0x01) == 0x01) { 3463250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX1, 3464250003Sadrian (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX1) 3465250003Sadrian | (0x1 << 31) | (0x1 << 27) 3466250003Sadrian | (0x3 << 23) | (0x1 << 19) 3467250003Sadrian | (0x1 << 15) | (0x3 << 9)) 3468250003Sadrian & ~(0x1 << 12)); 3469250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, 3470250003Sadrian (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) 3471250003Sadrian | (0x1 << 12) | (0x1 << 10) 3472250003Sadrian | (0x1 << 9) | (0x1 << 8) 3473250003Sadrian | (0x1 << 7) | (0x1 << 3) 3474250003Sadrian | (0x1 << 2) | (0x1 << 1)) 3475250003Sadrian & ~(0x1 << 11)& ~(0x1 << 0)); 3476250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, 3477250003Sadrian (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) 3478250003Sadrian | (0x1 << 29) | (0x1 << 25) 3479250003Sadrian | (0x1 << 23) | (0x1 << 19) 3480250003Sadrian | (0x1 << 10) | (0x1 << 9) 3481250003Sadrian | (0x1 << 8) | (0x1 << 3)) 3482250003Sadrian & ~(0x1 << 28)& ~(0x1 << 24) 3483250003Sadrian & ~(0x1 << 22)& ~(0x1 << 7)); 3484250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, 3485250003Sadrian (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) 3486250003Sadrian | (0x1 << 23))& ~(0x1 << 21)); 3487250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF2, 3488250003Sadrian OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF2) 3489250003Sadrian | (0x3 << 3) | (0x3 << 0)); 3490250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF3, 3491250003Sadrian (OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF3) 3492250003Sadrian | (0x3 << 29) | (0x3 << 26) 3493250003Sadrian | (0x2 << 23) | (0x2 << 20) 3494250003Sadrian | (0x2 << 17))& ~(0x1 << 14)); 3495250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB1, 3496250003Sadrian OS_REG_READ(ah, AR_PHY_65NM_CH0_BB1) 3497250003Sadrian | (0x1 << 12) | (0x1 << 10) 3498250003Sadrian | (0x1 << 9) | (0x1 << 8) 3499250003Sadrian | (0x1 << 6) | (0x1 << 5) 3500250003Sadrian | (0x1 << 4) | (0x1 << 3) 3501250003Sadrian | (0x1 << 2)); 3502250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_BB2, 3503250003Sadrian OS_REG_READ(ah, AR_PHY_65NM_CH0_BB2) | (0x1 << 31)); 3504250003Sadrian if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3505250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, 3506250003Sadrian OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4)); 3507250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, 3508250003Sadrian OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) 3509250003Sadrian | (0x1 << 26) | (0x7 << 24) 3510250003Sadrian | (0x3 << 22)); 3511250003Sadrian } else { 3512250003Sadrian OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, 3513250003Sadrian OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4)); 3514250003Sadrian OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, 3515250003Sadrian OS_REG_READ(ah, AR_HORNET_CH0_TOP2) 3516250003Sadrian | (0x1 << 26) | (0x7 << 24) 3517250003Sadrian | (0x3 << 22)); 3518250003Sadrian } 3519250003Sadrian 3520250003Sadrian if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3521250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, 3522250003Sadrian (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) 3523250003Sadrian | (0x1 << 3) | (0x1 << 2) 3524250003Sadrian | (0x1 << 1)) & ~(0x1 << 0)); 3525250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, 3526250003Sadrian OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) 3527250003Sadrian | (0x1 << 19) | (0x1 << 3)); 3528250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, 3529250003Sadrian OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) | (0x1 << 23)); 3530250003Sadrian } 3531250003Sadrian if (AR_SREV_OSPREY(ah)) { 3532250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, 3533250003Sadrian (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) 3534250003Sadrian | (0x1 << 3) | (0x1 << 2) 3535250003Sadrian | (0x1 << 1)) & ~(0x1 << 0)); 3536250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, 3537250003Sadrian OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) 3538250003Sadrian | (0x1 << 19) | (0x1 << 3)); 3539250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, 3540250003Sadrian OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) | (0x1 << 23)); 3541250003Sadrian } 3542250003Sadrian } 3543250003Sadrian if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3544250003Sadrian /* chain one */ 3545250003Sadrian if ((tx_chain_mask & 0x02) == 0x02 ) { 3546250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, 3547250003Sadrian (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) 3548250003Sadrian | (0x1 << 3) | (0x1 << 2) 3549250003Sadrian | (0x1 << 1)) & ~(0x1 << 0)); 3550250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, 3551250003Sadrian OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) 3552250003Sadrian | (0x1 << 19) | (0x1 << 3)); 3553250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, 3554250003Sadrian OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) | (0x1 << 23)); 3555250003Sadrian if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3556250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, 3557250003Sadrian OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4)); 3558250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, 3559250003Sadrian OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) 3560250003Sadrian | (0x1 << 26) | (0x7 << 24) 3561250003Sadrian | (0x3 << 22)); 3562250003Sadrian } else { 3563250003Sadrian OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, 3564250003Sadrian OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4)); 3565250003Sadrian OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, 3566250003Sadrian OS_REG_READ(ah, AR_HORNET_CH0_TOP2) 3567250003Sadrian | (0x1 << 26) | (0x7 << 24) 3568250003Sadrian | (0x3 << 22)); 3569250003Sadrian } 3570250003Sadrian 3571250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX1, 3572250003Sadrian (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX1) 3573250003Sadrian | (0x1 << 31) | (0x1 << 27) 3574250003Sadrian | (0x3 << 23) | (0x1 << 19) 3575250003Sadrian | (0x1 << 15) | (0x3 << 9)) 3576250003Sadrian & ~(0x1 << 12)); 3577250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, 3578250003Sadrian (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) 3579250003Sadrian | (0x1 << 12) | (0x1 << 10) 3580250003Sadrian | (0x1 << 9) | (0x1 << 8) 3581250003Sadrian | (0x1 << 7) | (0x1 << 3) 3582250003Sadrian | (0x1 << 2) | (0x1 << 1)) 3583250003Sadrian & ~(0x1 << 11)& ~(0x1 << 0)); 3584250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, 3585250003Sadrian (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) 3586250003Sadrian | (0x1 << 29) | (0x1 << 25) 3587250003Sadrian | (0x1 << 23) | (0x1 << 19) 3588250003Sadrian | (0x1 << 10) | (0x1 << 9) 3589250003Sadrian | (0x1 << 8) | (0x1 << 3)) 3590250003Sadrian & ~(0x1 << 28)& ~(0x1 << 24) 3591250003Sadrian & ~(0x1 << 22)& ~(0x1 << 7)); 3592250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, 3593250003Sadrian (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) 3594250003Sadrian | (0x1 << 23))& ~(0x1 << 21)); 3595250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF2, 3596250003Sadrian OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF2) 3597250003Sadrian | (0x3 << 3) | (0x3 << 0)); 3598250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF3, 3599250003Sadrian (OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF3) 3600250003Sadrian | (0x3 << 29) | (0x3 << 26) 3601250003Sadrian | (0x2 << 23) | (0x2 << 20) 3602250003Sadrian | (0x2 << 17))& ~(0x1 << 14)); 3603250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB1, 3604250003Sadrian OS_REG_READ(ah, AR_PHY_65NM_CH1_BB1) 3605250003Sadrian | (0x1 << 12) | (0x1 << 10) 3606250003Sadrian | (0x1 << 9) | (0x1 << 8) 3607250003Sadrian | (0x1 << 6) | (0x1 << 5) 3608250003Sadrian | (0x1 << 4) | (0x1 << 3) 3609250003Sadrian | (0x1 << 2)); 3610250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH1_BB2, 3611250003Sadrian OS_REG_READ(ah, AR_PHY_65NM_CH1_BB2) | (0x1 << 31)); 3612250003Sadrian 3613250003Sadrian if (AR_SREV_OSPREY(ah)) { 3614250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, 3615250003Sadrian (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) 3616250003Sadrian | (0x1 << 3) | (0x1 << 2) 3617250003Sadrian | (0x1 << 1)) & ~(0x1 << 0)); 3618250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, 3619250003Sadrian OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) 3620250003Sadrian | (0x1 << 19) | (0x1 << 3)); 3621250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, 3622250003Sadrian OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) | (0x1 << 23)); 3623250003Sadrian } 3624250003Sadrian } 3625250003Sadrian } 3626250003Sadrian if (AR_SREV_OSPREY(ah)) { 3627250003Sadrian /* chain two */ 3628250003Sadrian if ((tx_chain_mask & 0x04) == 0x04 ) { 3629250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX2, 3630250003Sadrian (OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX2) 3631250003Sadrian | (0x1 << 3) | (0x1 << 2) 3632250003Sadrian | (0x1 << 1)) & ~(0x1 << 0)); 3633250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_RXTX3, 3634250003Sadrian OS_REG_READ(ah, AR_PHY_65NM_CH0_RXTX3) 3635250003Sadrian | (0x1 << 19) | (0x1 << 3)); 3636250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TXRF1, 3637250003Sadrian OS_REG_READ(ah, AR_PHY_65NM_CH0_TXRF1) | (0x1 << 23)); 3638250003Sadrian if (AR_SREV_OSPREY(ah) || AR_SREV_WASP(ah)) { 3639250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP, 3640250003Sadrian OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP) & ~(0x1 << 4)); 3641250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH0_TOP2, 3642250003Sadrian OS_REG_READ(ah, AR_PHY_65NM_CH0_TOP2) 3643250003Sadrian | (0x1 << 26) | (0x7 << 24) 3644250003Sadrian | (0x3 << 22)); 3645250003Sadrian } else { 3646250003Sadrian OS_REG_WRITE(ah, AR_HORNET_CH0_TOP, 3647250003Sadrian OS_REG_READ(ah, AR_HORNET_CH0_TOP) & ~(0x1 << 4)); 3648250003Sadrian OS_REG_WRITE(ah, AR_HORNET_CH0_TOP2, 3649250003Sadrian OS_REG_READ(ah, AR_HORNET_CH0_TOP2) 3650250003Sadrian | (0x1 << 26) | (0x7 << 24) 3651250003Sadrian | (0x3 << 22)); 3652250003Sadrian } 3653250003Sadrian 3654250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX2, 3655250003Sadrian (OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX2) 3656250003Sadrian | (0x1 << 3) | (0x1 << 2) 3657250003Sadrian | (0x1 << 1)) & ~(0x1 << 0)); 3658250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH1_RXTX3, 3659250003Sadrian OS_REG_READ(ah, AR_PHY_65NM_CH1_RXTX3) 3660250003Sadrian | (0x1 << 19) | (0x1 << 3)); 3661250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH1_TXRF1, 3662250003Sadrian OS_REG_READ(ah, AR_PHY_65NM_CH1_TXRF1) | (0x1 << 23)); 3663250003Sadrian 3664250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX1, 3665250003Sadrian (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX1) 3666250003Sadrian | (0x1 << 31) | (0x1 << 27) 3667250003Sadrian | (0x3 << 23) | (0x1 << 19) 3668250003Sadrian | (0x1 << 15) | (0x3 << 9)) 3669250003Sadrian & ~(0x1 << 12)); 3670250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX2, 3671250003Sadrian (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX2) 3672250003Sadrian | (0x1 << 12) | (0x1 << 10) 3673250003Sadrian | (0x1 << 9) | (0x1 << 8) 3674250003Sadrian | (0x1 << 7) | (0x1 << 3) 3675250003Sadrian | (0x1 << 2) | (0x1 << 1)) 3676250003Sadrian & ~(0x1 << 11)& ~(0x1 << 0)); 3677250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH2_RXTX3, 3678250003Sadrian (OS_REG_READ(ah, AR_PHY_65NM_CH2_RXTX3) 3679250003Sadrian | (0x1 << 29) | (0x1 << 25) 3680250003Sadrian | (0x1 << 23) | (0x1 << 19) 3681250003Sadrian | (0x1 << 10) | (0x1 << 9) 3682250003Sadrian | (0x1 << 8) | (0x1 << 3)) 3683250003Sadrian & ~(0x1 << 28)& ~(0x1 << 24) 3684250003Sadrian & ~(0x1 << 22)& ~(0x1 << 7)); 3685250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF1, 3686250003Sadrian (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF1) 3687250003Sadrian | (0x1 << 23))& ~(0x1 << 21)); 3688250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF2, 3689250003Sadrian OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF2) 3690250003Sadrian | (0x3 << 3) | (0x3 << 0)); 3691250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH2_TXRF3, 3692250003Sadrian (OS_REG_READ(ah, AR_PHY_65NM_CH2_TXRF3) 3693250003Sadrian | (0x3 << 29) | (0x3 << 26) 3694250003Sadrian | (0x2 << 23) | (0x2 << 20) 3695250003Sadrian | (0x2 << 17))& ~(0x1 << 14)); 3696250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB1, 3697250003Sadrian OS_REG_READ(ah, AR_PHY_65NM_CH2_BB1) 3698250003Sadrian | (0x1 << 12) | (0x1 << 10) 3699250003Sadrian | (0x1 << 9) | (0x1 << 8) 3700250003Sadrian | (0x1 << 6) | (0x1 << 5) 3701250003Sadrian | (0x1 << 4) | (0x1 << 3) 3702250003Sadrian | (0x1 << 2)); 3703250003Sadrian OS_REG_WRITE(ah, AR_PHY_65NM_CH2_BB2, 3704250003Sadrian OS_REG_READ(ah, AR_PHY_65NM_CH2_BB2) | (0x1 << 31)); 3705250003Sadrian } 3706250003Sadrian } 3707250003Sadrian 3708250003Sadrian OS_REG_WRITE(ah, 0xa28c, 0x22222); 3709250003Sadrian OS_REG_WRITE(ah, 0xa288, 0x222); 3710250003Sadrian } 3711250003Sadrian} 3712250003Sadrian 3713250003Sadrianvoid 3714250003Sadrianar9300_tx99_start(struct ath_hal *ah, u_int8_t *data) 3715250003Sadrian{ 3716250003Sadrian u_int32_t val; 3717250003Sadrian u_int32_t qnum = (u_int32_t)data; 3718250003Sadrian 3719250003Sadrian /* Disable AGC to A2 */ 3720250003Sadrian OS_REG_WRITE(ah, AR_PHY_TEST, (OS_REG_READ(ah, AR_PHY_TEST) | PHY_AGC_CLR)); 3721250003Sadrian OS_REG_WRITE(ah, 0x9864, OS_REG_READ(ah, 0x9864) | 0x7f000); 3722250003Sadrian OS_REG_WRITE(ah, 0x9924, OS_REG_READ(ah, 0x9924) | 0x7f00fe); 3723250003Sadrian OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) &~ AR_DIAG_RX_DIS); 3724250003Sadrian 3725250003Sadrian OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* set receive disable */ 3726250003Sadrian /* set CW_MIN and CW_MAX both to 0, AIFS=2 */ 3727250003Sadrian OS_REG_WRITE(ah, AR_DLCL_IFS(qnum), 0); 3728250003Sadrian OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); /* 50 OK */ 3729250003Sadrian OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20); 3730250003Sadrian /* 200 ok for HT20, 400 ok for HT40 */ 3731250003Sadrian OS_REG_WRITE(ah, AR_TIME_OUT, 0x00000400); 3732250003Sadrian OS_REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff); 3733250003Sadrian 3734250003Sadrian /* set QCU modes to early termination */ 3735250003Sadrian val = OS_REG_READ(ah, AR_QMISC(qnum)); 3736250003Sadrian OS_REG_WRITE(ah, AR_QMISC(qnum), val | AR_Q_MISC_DCU_EARLY_TERM_REQ); 3737250003Sadrian} 3738250003Sadrian 3739250003Sadrianvoid 3740250003Sadrianar9300_tx99_stop(struct ath_hal *ah) 3741250003Sadrian{ 3742250003Sadrian /* this should follow the setting of start */ 3743250003Sadrian OS_REG_WRITE(ah, AR_PHY_TEST, OS_REG_READ(ah, AR_PHY_TEST) &~ PHY_AGC_CLR); 3744250003Sadrian OS_REG_WRITE(ah, AR_DIAG_SW, OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_RX_DIS); 3745250003Sadrian} 3746250003Sadrian#endif /* ATH_TX99_DIAG */ 3747250003Sadrian#endif /* ATH_SUPPORT_HTC */ 3748250003Sadrian 3749250003SadrianHAL_BOOL 3750250003Sadrianar9300Get3StreamSignature(struct ath_hal *ah) 3751250003Sadrian{ 3752250003Sadrian return AH_FALSE; 3753250003Sadrian} 3754250003Sadrian 3755250003SadrianHAL_BOOL 3756250003Sadrianar9300ForceVCS(struct ath_hal *ah) 3757250003Sadrian{ 3758250003Sadrian return AH_FALSE; 3759250003Sadrian} 3760250003Sadrian 3761250003SadrianHAL_BOOL 3762250003Sadrianar9300SetDfs3StreamFix(struct ath_hal *ah, u_int32_t val) 3763250003Sadrian{ 3764250003Sadrian return AH_FALSE; 3765250003Sadrian} 3766