1183878Sraj/*- 2183878Sraj * Copyright (c) 2008 Semihalf, Rafal Czubak 3183878Sraj * All rights reserved. 4183878Sraj * 5183878Sraj * Redistribution and use in source and binary forms, with or without 6183878Sraj * modification, are permitted provided that the following conditions 7183878Sraj * are met: 8183878Sraj * 1. Redistributions of source code must retain the above copyright 9183878Sraj * notice, this list of conditions and the following disclaimer. 10183878Sraj * 2. Redistributions in binary form must reproduce the above copyright 11183878Sraj * notice, this list of conditions and the following disclaimer in the 12183878Sraj * documentation and/or other materials provided with the distribution. 13183878Sraj * 14183878Sraj * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15183878Sraj * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16183878Sraj * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17183878Sraj * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18183878Sraj * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19183878Sraj * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20183878Sraj * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21183878Sraj * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22183878Sraj * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23183878Sraj * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24183878Sraj * SUCH DAMAGE. 25183878Sraj * 26183878Sraj * $FreeBSD$ 27183878Sraj */ 28183878Sraj 29183878Sraj#include <machine/asm.h> 30248962Sian#include <machine/armreg.h> 31183878Sraj 32183878Sraj/* 33183878Sraj * Entry point to the loader that U-Boot passes control to. 34183878Sraj */ 35183878Sraj .text 36183878Sraj .globl _start 37183878Sraj_start: 38183878Sraj /* Hint where to look for the API signature */ 39183878Sraj ldr ip, =uboot_address 40183878Sraj str sp, [ip] 41183878Sraj 42183878Sraj /* Save U-Boot's r8 */ 43183878Sraj ldr ip, =saved_regs 44183878Sraj str r8, [ip, #0] 45183878Sraj 46248962Sian#ifdef _ARM_ARCH_6 47248962Sian mrc p15, 0, r2, c1, c0, 0 48248962Sian orr r2, r2, #(CPU_CONTROL_UNAL_ENABLE) 49248962Sian orr r2, r2, #(CPU_CONTROL_AFLT_ENABLE) 50248962Sian mcr p15, 0, r2, c1, c0, 0 51248962Sian#endif 52248962Sian 53183878Sraj /* Start loader */ 54183878Sraj b main 55183878Sraj 56183878Sraj/* 57183878Sraj * syscall() 58183878Sraj */ 59183878SrajENTRY(syscall) 60234908Skientzle /* Save caller's lr and r8 */ 61183878Sraj ldr ip, =saved_regs 62183878Sraj str lr, [ip, #4] 63183878Sraj str r8, [ip, #8] 64183878Sraj /* Restore U-Boot's r8 */ 65183878Sraj ldr r8, [ip, #0] 66183878Sraj /* Call into U-Boot */ 67183878Sraj ldr lr, =return_from_syscall 68183878Sraj ldr ip, =syscall_ptr 69183878Sraj ldr pc, [ip] 70183878Srajreturn_from_syscall: 71234908Skientzle /* Restore loader's r8 and lr */ 72183878Sraj ldr ip, =saved_regs 73183878Sraj ldr r8, [ip, #8] 74183878Sraj ldr lr, [ip, #4] 75183878Sraj /* Return to caller */ 76183878Sraj mov pc, lr 77183878Sraj 78183878Sraj/* 79183878Sraj * Data section 80183878Sraj */ 81183878Sraj .data 82183878Sraj .align 4 83183878Sraj .globl syscall_ptr 84183878Srajsyscall_ptr: 85183878Sraj .long 0 86183878Sraj 87183878Sraj .globl uboot_address 88183878Srajuboot_address: 89183878Sraj .long 0 90183878Sraj 91183878Srajsaved_regs: 92183878Sraj .long 0 /* U-Boot's r8 */ 93183878Sraj .long 0 /* Loader's r8 */ 94183878Sraj .long 0 /* Loader's lr */ 95