1/*-
2 * Copyright (c) 2006 Benno Rice.  All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 *    notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 *    notice, this list of conditions and the following disclaimer in the
11 *    documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 */
24
25#include <sys/cdefs.h>
26__FBSDID("$FreeBSD$");
27
28#include <sys/param.h>
29#include <sys/systm.h>
30#include <sys/bus.h>
31#include <sys/kernel.h>
32#include <sys/module.h>
33#include <sys/malloc.h>
34#include <sys/rman.h>
35#include <sys/timetc.h>
36#include <machine/bus.h>
37#include <machine/cpu.h>
38#include <machine/frame.h>
39#include <machine/intr.h>
40
41#include <arm/xscale/pxa/pxavar.h>
42#include <arm/xscale/pxa/pxareg.h>
43
44#define	PXA_TIMER_FREQUENCY	3686400
45#define	PXA_TIMER_TICK		(PXA_TIMER_FREQUENCY / hz)
46
47struct pxa_timer_softc {
48	struct resource	*	pt_res[5];
49	bus_space_tag_t		pt_bst;
50	bus_space_handle_t	pt_bsh;
51};
52
53static struct resource_spec pxa_timer_spec[] = {
54	{ SYS_RES_MEMORY,	0,	RF_ACTIVE },
55	{ SYS_RES_IRQ,		0,	RF_ACTIVE },
56	{ SYS_RES_IRQ,		1,	RF_ACTIVE },
57	{ SYS_RES_IRQ,		2,	RF_ACTIVE },
58	{ SYS_RES_IRQ,		3,	RF_ACTIVE },
59	{ -1, 0 }
60};
61
62static struct pxa_timer_softc *timer_softc = NULL;
63
64static int	pxa_timer_probe(device_t);
65static int	pxa_timer_attach(device_t);
66
67static driver_filter_t	pxa_hardclock;
68
69static unsigned	pxa_timer_get_timecount(struct timecounter *);
70
71uint32_t	pxa_timer_get_osmr(int);
72void		pxa_timer_set_osmr(int, uint32_t);
73uint32_t	pxa_timer_get_oscr(void);
74void		pxa_timer_set_oscr(uint32_t);
75uint32_t	pxa_timer_get_ossr(void);
76void		pxa_timer_clear_ossr(uint32_t);
77void		pxa_timer_watchdog_enable(void);
78void		pxa_timer_watchdog_disable(void);
79void		pxa_timer_interrupt_enable(int);
80void		pxa_timer_interrupt_disable(int);
81
82static struct timecounter pxa_timer_timecounter = {
83	.tc_get_timecount = pxa_timer_get_timecount,
84	.tc_name = "OS Timer",
85	.tc_frequency = PXA_TIMER_FREQUENCY,
86	.tc_counter_mask = ~0u,
87	.tc_quality = 1000,
88};
89
90static int
91pxa_timer_probe(device_t dev)
92{
93
94	device_set_desc(dev, "OS Timer");
95	return (0);
96}
97
98static int
99pxa_timer_attach(device_t dev)
100{
101	int	error;
102	void	*ihl;
103	struct	pxa_timer_softc *sc;
104
105	sc = (struct pxa_timer_softc *)device_get_softc(dev);
106
107	if (timer_softc != NULL)
108		return (ENXIO);
109
110	error = bus_alloc_resources(dev, pxa_timer_spec, sc->pt_res);
111	if (error) {
112		device_printf(dev, "could not allocate resources\n");
113		return (ENXIO);
114	}
115
116	sc->pt_bst = rman_get_bustag(sc->pt_res[0]);
117	sc->pt_bsh = rman_get_bushandle(sc->pt_res[0]);
118
119	timer_softc = sc;
120
121	pxa_timer_interrupt_disable(-1);
122	pxa_timer_watchdog_disable();
123
124	if (bus_setup_intr(dev, sc->pt_res[1], INTR_TYPE_CLK,
125	    pxa_hardclock, NULL, NULL, &ihl) != 0) {
126		bus_release_resources(dev, pxa_timer_spec, sc->pt_res);
127		device_printf(dev, "could not setup hardclock interrupt\n");
128		return (ENXIO);
129	}
130
131	return (0);
132}
133
134static int
135pxa_hardclock(void *arg)
136{
137	struct		trapframe *frame;
138
139	frame = (struct trapframe *)arg;
140
141	/* Clear the interrupt */
142	pxa_timer_clear_ossr(OST_SR_CH0);
143
144	/* Schedule next tick */
145	pxa_timer_set_osmr(0, pxa_timer_get_oscr() + PXA_TIMER_TICK);
146
147	/* Do what we came here for */
148	hardclock(TRAPF_USERMODE(frame), TRAPF_PC(frame));
149
150	return (FILTER_HANDLED);
151}
152
153static device_method_t pxa_timer_methods[] = {
154	DEVMETHOD(device_probe, pxa_timer_probe),
155	DEVMETHOD(device_attach, pxa_timer_attach),
156
157	{0, 0}
158};
159
160static driver_t pxa_timer_driver = {
161	"timer",
162	pxa_timer_methods,
163	sizeof(struct pxa_timer_softc),
164};
165
166static devclass_t pxa_timer_devclass;
167
168DRIVER_MODULE(pxatimer, pxa, pxa_timer_driver, pxa_timer_devclass, 0, 0);
169
170static unsigned
171pxa_timer_get_timecount(struct timecounter *tc)
172{
173
174	return (pxa_timer_get_oscr());
175}
176
177void
178cpu_initclocks(void)
179{
180
181	pxa_timer_set_oscr(0);
182	pxa_timer_set_osmr(0, PXA_TIMER_TICK);
183	pxa_timer_interrupt_enable(0);
184
185	tc_init(&pxa_timer_timecounter);
186}
187
188void
189cpu_reset(void)
190{
191	uint32_t	val;
192
193	(void)disable_interrupts(I32_bit|F32_bit);
194
195	val = pxa_timer_get_oscr();
196	val += PXA_TIMER_FREQUENCY;
197	pxa_timer_set_osmr(3, val);
198	pxa_timer_watchdog_enable();
199
200	for(;;);
201}
202
203void
204DELAY(int usec)
205{
206	uint32_t	val;
207
208	if (timer_softc == NULL) {
209		for (; usec > 0; usec--)
210			for (val = 100; val > 0; val--)
211				;
212		return;
213	}
214
215	val = pxa_timer_get_oscr();
216	val += (PXA_TIMER_FREQUENCY * usec) / 1000000;
217	while (pxa_timer_get_oscr() <= val);
218}
219
220uint32_t
221pxa_timer_get_osmr(int which)
222{
223
224	return (bus_space_read_4(timer_softc->pt_bst,
225	    timer_softc->pt_bsh, which * 0x4));
226}
227
228void
229pxa_timer_set_osmr(int which, uint32_t val)
230{
231
232	bus_space_write_4(timer_softc->pt_bst,
233	    timer_softc->pt_bsh, which * 0x4, val);
234}
235
236uint32_t
237pxa_timer_get_oscr()
238{
239
240	return (bus_space_read_4(timer_softc->pt_bst,
241	    timer_softc->pt_bsh, OST_CR));
242}
243
244void
245pxa_timer_set_oscr(uint32_t val)
246{
247
248	bus_space_write_4(timer_softc->pt_bst,
249	    timer_softc->pt_bsh, OST_CR, val);
250}
251
252uint32_t
253pxa_timer_get_ossr()
254{
255
256	return (bus_space_read_4(timer_softc->pt_bst,
257	    timer_softc->pt_bsh, OST_SR));
258}
259
260void
261pxa_timer_clear_ossr(uint32_t val)
262{
263
264	bus_space_write_4(timer_softc->pt_bst,
265	    timer_softc->pt_bsh, OST_SR, val);
266}
267
268void
269pxa_timer_watchdog_enable()
270{
271
272	bus_space_write_4(timer_softc->pt_bst,
273	    timer_softc->pt_bsh, OST_WR, 0x1);
274}
275
276void
277pxa_timer_watchdog_disable()
278{
279
280	bus_space_write_4(timer_softc->pt_bst,
281	    timer_softc->pt_bsh, OST_WR, 0x0);
282}
283
284void
285pxa_timer_interrupt_enable(int which)
286{
287	uint32_t	oier;
288
289	if (which == -1) {
290		bus_space_write_4(timer_softc->pt_bst,
291		    timer_softc->pt_bsh, OST_IR, 0xf);
292		return;
293	}
294
295	oier = bus_space_read_4(timer_softc->pt_bst,
296	    timer_softc->pt_bsh, OST_IR);
297	oier |= 1 << which;
298	bus_space_write_4(timer_softc->pt_bst,
299	    timer_softc->pt_bsh, OST_IR, oier);
300}
301
302void
303pxa_timer_interrupt_disable(int which)
304{
305	uint32_t	oier;
306
307	if (which == -1) {
308		bus_space_write_4(timer_softc->pt_bst,
309		    timer_softc->pt_bsh, OST_IR, 0);
310	}
311
312	oier = bus_space_read_4(timer_softc->pt_bst,
313	    timer_softc->pt_bsh, OST_IR);
314	oier &= ~(1 << which);
315	bus_space_write_4(timer_softc->pt_bst,
316	    timer_softc->pt_bsh, OST_IR, oier);
317}
318