1/*- 2 * Copyright (c) 2006 Olivier Houchard 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 16 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR 18 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 19 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 20 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 22 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 23 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 24 * POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28__FBSDID("$FreeBSD$"); 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/bus.h> 33#include <sys/kernel.h> 34#include <sys/module.h> 35#include <sys/types.h> 36#include <sys/rman.h> 37 38#include <machine/bus.h> 39#include <machine/cpu.h> 40#include <machine/pcb.h> 41#include <vm/vm.h> 42#include <vm/pmap.h> 43#include <vm/vm_extern.h> 44#include <machine/pmap.h> 45 46#include <arm/xscale/i8134x/i81342reg.h> 47#include <arm/xscale/i8134x/i81342var.h> 48 49#include <dev/pci/pcivar.h> 50#include <dev/pci/pcib_private.h> 51#include "pcib_if.h" 52 53#include <dev/pci/pcireg.h> 54 55static pcib_read_config_t i81342_pci_read_config; 56static pcib_write_config_t i81342_pci_write_config; 57 58static int 59i81342_pci_probe(device_t dev) 60{ 61 struct i81342_pci_softc *sc; 62 63 sc = device_get_softc(dev); 64 if (device_get_unit(dev) == 0) { 65 device_set_desc(dev, "i81342 PCI-X bus"); 66 sc->sc_is_atux = 1; 67 } else { 68 device_set_desc(dev, "i81342 PCIe bus"); 69 sc->sc_is_atux = 0; 70 } 71 return (0); 72} 73 74#define PCI_MAPREG_MEM_PREFETCHABLE_MASK 0x00000008 75#define PCI_MAPREG_MEM_TYPE_64BIT 0x00000004 76 77static int 78i81342_pci_attach(device_t dev) 79{ 80 struct i81342_softc *parent_sc; 81 struct i81342_pci_softc *sc; 82 uint32_t memsize, memstart; 83 uint32_t reg; 84 int func; 85 uint32_t busno; 86 87 sc = device_get_softc(dev); 88 parent_sc = device_get_softc(device_get_parent(dev)); 89 sc->sc_atu_sh = sc->sc_is_atux ? parent_sc->sc_atux_sh : 90 parent_sc->sc_atue_sh; 91 sc->sc_st = parent_sc->sc_st; 92 if (bus_space_read_4(sc->sc_st, parent_sc->sc_sh, IOP34X_ESSTSR0) 93 & IOP34X_INT_SEL_PCIX) { 94 if (sc->sc_is_atux) 95 func = 5; 96 else 97 func = 0; 98 } else { 99 if (sc->sc_is_atux) 100 func = 0; 101 else 102 func = 5; 103 } 104 i81342_io_bs_init(&sc->sc_pciio, sc); 105 i81342_mem_bs_init(&sc->sc_pcimem, sc); 106 i81342_sdram_bounds(sc->sc_st, IOP34X_VADDR, &memstart, &memsize); 107 if (sc->sc_is_atux) { 108 reg = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCSR); 109 if (reg & ATUX_P_RSTOUT) { 110 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_PCSR, 111 reg &~ ATUX_P_RSTOUT); 112 DELAY(200); 113 } 114 } 115 /* Setup the Inbound windows. */ 116 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IABAR0, 0); 117 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IAUBAR0, 0); 118 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR0, 0); 119 120 /* Set the mapping Physical address <=> PCI address */ 121 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IABAR1, 122 memstart | PCI_MAPREG_MEM_PREFETCHABLE_MASK | 123 PCI_MAPREG_MEM_TYPE_64BIT); 124 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IAUBAR1, 0); 125 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR1, ~(memsize - 1) 126 &~(0xfff)); 127 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IATVR1, memstart); 128 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IAUTVR1, 0); 129 130 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IABAR2, 0); 131 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IAUBAR2, 0); 132 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_IALR2, 0); 133 134 /* Setup the Outbound IO Bar */ 135 if (sc->sc_is_atux) 136 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OIOBAR, 137 (IOP34X_PCIX_OIOBAR >> 4) | func); 138 else 139 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OIOBAR, 140 (IOP34X_PCIE_OIOBAR >> 4) | func); 141 142 /* Setup the Outbound windows */ 143 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OUMBAR0, 0); 144 if (sc->sc_is_atux) 145 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OUMBAR1, 146 (IOP34X_PCIX_OMBAR >> 32) | (func << ATU_OUMBAR_FUNC) | 147 ATU_OUMBAR_EN); 148 else 149 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OUMBAR1, 150 (IOP34X_PCIE_OMBAR >> 32) | (func << ATU_OUMBAR_FUNC) | 151 ATU_OUMBAR_EN); 152 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OUMWTVR1, 0); 153 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OUMBAR2, 0); 154 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_OUMBAR3, 0); 155 156 /* Enable the outbound windows. */ 157 reg = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_CR); 158 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_CR, 159 reg | ATU_CR_OUT_EN); 160 161 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_ISR, 162 bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_ISR) & ATUX_ISR_ERRMSK); 163 /* 164 * Enable bus mastering, memory access, SERR, and parity 165 * checking on the ATU. 166 */ 167 if (sc->sc_is_atux) { 168 busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR); 169 busno = PCIXSR_BUSNO(busno); 170 } else { 171 busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCSR); 172 busno = PCIE_BUSNO(busno); 173 } 174 reg = bus_space_read_2(sc->sc_st, sc->sc_atu_sh, ATU_CMD); 175 reg |= PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_PERRESPEN | 176 PCIM_CMD_SERRESPEN; 177 bus_space_write_2(sc->sc_st, sc->sc_atu_sh, ATU_CMD, reg); 178 sc->sc_busno = busno; 179 /* Initialize memory and i/o rmans. */ 180 sc->sc_io_rman.rm_type = RMAN_ARRAY; 181 sc->sc_io_rman.rm_descr = "I81342 PCI I/O Ports"; 182 if (rman_init(&sc->sc_io_rman) != 0 || 183 rman_manage_region(&sc->sc_io_rman, 184 sc->sc_is_atux ? IOP34X_PCIX_OIOBAR_VADDR : 185 IOP34X_PCIE_OIOBAR_VADDR, 186 (sc->sc_is_atux ? IOP34X_PCIX_OIOBAR_VADDR : 187 IOP34X_PCIE_OIOBAR_VADDR) + IOP34X_OIOBAR_SIZE) != 0) { 188 panic("i81342_pci_probe: failed to set up I/O rman"); 189 } 190 sc->sc_mem_rman.rm_type = RMAN_ARRAY; 191 sc->sc_mem_rman.rm_descr = "I81342 PCI Memory"; 192 if (rman_init(&sc->sc_mem_rman) != 0 || 193 rman_manage_region(&sc->sc_mem_rman, 194 0, 0xffffffff) != 0) { 195 panic("i81342_pci_attach: failed to set up memory rman"); 196 } 197 sc->sc_irq_rman.rm_type = RMAN_ARRAY; 198 sc->sc_irq_rman.rm_descr = "i81342 PCI IRQs"; 199 if (sc->sc_is_atux) { 200 if (rman_init(&sc->sc_irq_rman) != 0 || 201 rman_manage_region(&sc->sc_irq_rman, ICU_INT_XINT0, 202 ICU_INT_XINT3) != 0) 203 panic("i83142_pci_attach: failed to set up IRQ rman"); 204 } else { 205 if (rman_init(&sc->sc_irq_rman) != 0 || 206 rman_manage_region(&sc->sc_irq_rman, ICU_INT_ATUE_MA, 207 ICU_INT_ATUE_MD) != 0) 208 panic("i81342_pci_attach: failed to set up IRQ rman"); 209 210 } 211 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_ISR, 212 bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_ISR) & ATUX_ISR_ERRMSK); 213 device_add_child(dev, "pci", busno); 214 return (bus_generic_attach(dev)); 215} 216 217static int 218i81342_pci_maxslots(device_t dev) 219{ 220 221 return (PCI_SLOTMAX); 222} 223 224static void 225i81342_pci_conf_setup(struct i81342_pci_softc *sc, int bus, int slot, int func, 226 int reg, uint32_t *addr) 227{ 228 uint32_t busno; 229 230 if (sc->sc_is_atux) { 231 busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCIXSR); 232 busno = PCIXSR_BUSNO(busno); 233 } else { 234 busno = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_PCSR); 235 busno = PCIE_BUSNO(busno); 236 } 237 bus &= 0xff; 238 slot &= 0x1f; 239 func &= 0x7; 240 if (sc->sc_is_atux) { 241 if (busno == bus) 242 *addr = (1 << (slot + 16)) | (slot << 11) | 243 (func << 8) | reg; 244 else 245 *addr = (bus << 16) | (slot << 11) | (func << 11) | 246 reg | 1; 247 } else { 248 *addr = (bus << 24) | (slot << 19) | (func << 16) | reg; 249 if (bus != busno) 250 *addr |= 1; 251 } 252} 253 254static u_int32_t 255i81342_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func, 256 u_int reg, int bytes) 257{ 258 struct i81342_pci_softc *sc = device_get_softc(dev); 259 uint32_t addr; 260 uint32_t ret = 0; 261 uint32_t isr; 262 int err = 0; 263 vm_offset_t va; 264 265 i81342_pci_conf_setup(sc, bus, slot, func, reg & ~3, &addr); 266 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, sc->sc_is_atux ? 267 ATUX_OCCAR : ATUE_OCCAR, addr); 268 if (sc->sc_is_atux) 269 va = sc->sc_atu_sh + ATUX_OCCDR; 270 else 271 va = sc->sc_atu_sh + ATUE_OCCDR; 272 switch (bytes) { 273 case 1: 274 err = badaddr_read((void*)(va + (reg & 3)), 1, &ret); 275 break; 276 case 2: 277 err = badaddr_read((void*)(va + (reg & 3)), 2, &ret); 278 break; 279 case 4: 280 err = badaddr_read((void *)(va) , 4, &ret); 281 break; 282 default: 283 printf("i81342_read_config: invalid size %d\n", bytes); 284 ret = -1; 285 } 286 if (err) { 287 isr = bus_space_read_4(sc->sc_st, sc->sc_atu_sh, ATU_ISR); 288 if (sc->sc_is_atux) 289 isr &= ATUX_ISR_ERRMSK; 290 else 291 isr &= ATUE_ISR_ERRMSK; 292 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, ATU_ISR, isr); 293 ret = -1; 294 } 295 296 return (ret); 297} 298 299static void 300i81342_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func, 301 u_int reg, u_int32_t data, int bytes) 302{ 303 struct i81342_pci_softc *sc = device_get_softc(dev); 304 uint32_t addr; 305 vm_offset_t va; 306 307 i81342_pci_conf_setup(sc, bus, slot, func, reg & ~3, &addr); 308 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, sc->sc_is_atux ? 309 ATUX_OCCAR : ATUE_OCCAR, addr); 310 va = sc->sc_is_atux ? ATUX_OCCDR : ATUE_OCCDR; 311 switch (bytes) { 312 case 1: 313 bus_space_write_1(sc->sc_st, sc->sc_atu_sh, va + (reg & 3) 314 , data); 315 break; 316 case 2: 317 bus_space_write_2(sc->sc_st, sc->sc_atu_sh, va + (reg & 3) 318 , data); 319 break; 320 case 4: 321 bus_space_write_4(sc->sc_st, sc->sc_atu_sh, va, data); 322 break; 323 default: 324 printf("i81342_pci_write_config: Invalid size : %d\n", bytes); 325 } 326 327 328} 329 330static struct resource * 331i81342_pci_alloc_resource(device_t bus, device_t child, int type, int *rid, 332 u_long start, u_long end, u_long count, u_int flags) 333{ 334 struct i81342_pci_softc *sc = device_get_softc(bus); 335 struct resource *rv; 336 struct rman *rm; 337 bus_space_tag_t bt = NULL; 338 bus_space_handle_t bh = 0; 339 340 switch (type) { 341 case SYS_RES_IRQ: 342 rm = &sc->sc_irq_rman; 343 break; 344 case SYS_RES_MEMORY: 345 rm = &sc->sc_mem_rman; 346 bt = &sc->sc_pcimem; 347 bh = 0; 348 break; 349 case SYS_RES_IOPORT: 350 rm = &sc->sc_io_rman; 351 bt = &sc->sc_pciio; 352 bh = sc->sc_is_atux ? IOP34X_PCIX_OIOBAR_VADDR : 353 IOP34X_PCIE_OIOBAR_VADDR; 354 start += bh; 355 end += bh; 356 break; 357 default: 358 return (NULL); 359 } 360 361 rv = rman_reserve_resource(rm, start, end, count, flags, child); 362 if (rv == NULL) 363 return (NULL); 364 rman_set_rid(rv, *rid); 365 if (type != SYS_RES_IRQ) { 366 if (type == SYS_RES_MEMORY) 367 bh += (rman_get_start(rv)); 368 rman_set_bustag(rv, bt); 369 rman_set_bushandle(rv, bh); 370 if (flags & RF_ACTIVE) { 371 if (bus_activate_resource(child, type, *rid, rv)) { 372 rman_release_resource(rv); 373 return (NULL); 374 } 375 } 376 } 377 return (rv); 378 379 380 return (NULL); 381} 382 383static int 384i81342_pci_activate_resource(device_t bus, device_t child, int type, int rid, 385 struct resource *r) 386{ 387 u_long p; 388 int error; 389 390 if (type == SYS_RES_MEMORY) { 391 error = bus_space_map(rman_get_bustag(r), 392 rman_get_bushandle(r), rman_get_size(r), 0, &p); 393 if (error) 394 return (error); 395 rman_set_bushandle(r, p); 396 397 } 398 return (rman_activate_resource(r)); 399} 400 401static int 402i81342_pci_setup_intr(device_t dev, device_t child, struct resource *ires, 403 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg, 404 void **cookiep) 405{ 406 407 return (BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, 408 filt, intr, arg, cookiep)); 409} 410 411 412 413static int 414i81342_pci_teardown_intr(device_t dev, device_t child, struct resource *res, 415 void *cookie) 416{ 417 return (BUS_TEARDOWN_INTR(device_get_parent(dev), child, res, cookie)); 418} 419 420static int 421i81342_pci_route_interrupt(device_t pcib, device_t dev, int pin) 422{ 423 struct i81342_pci_softc *sc; 424 int device; 425 426 device = pci_get_slot(dev); 427 sc = device_get_softc(pcib); 428 /* XXX: Is board specific */ 429 if (sc->sc_is_atux) { 430 /* PCI-X */ 431 switch(device) { 432 case 1: 433 switch (pin) { 434 case 1: 435 return (ICU_INT_XINT1); 436 case 2: 437 return (ICU_INT_XINT2); 438 case 3: 439 return (ICU_INT_XINT3); 440 case 4: 441 return (ICU_INT_XINT0); 442 default: 443 break; 444 } 445 case 2: 446 switch (pin) { 447 case 1: 448 return (ICU_INT_XINT2); 449 case 2: 450 return (ICU_INT_XINT3); 451 case 3: 452 return (ICU_INT_XINT2); 453 case 4: 454 return (ICU_INT_XINT3); 455 default: 456 break; 457 } 458 } 459 460 } else { 461 switch (pin) { 462 case 1: 463 return (ICU_INT_ATUE_MA); 464 case 2: 465 return (ICU_INT_ATUE_MB); 466 case 3: 467 return (ICU_INT_ATUE_MC); 468 case 4: 469 return (ICU_INT_ATUE_MD); 470 default: 471 break; 472 } 473 } 474 printf("Warning: couldn't map %s IRQ for device %d pin %d\n", 475 sc->sc_is_atux ? "PCI-X" : "PCIe", device, pin); 476 return (-1); 477} 478 479static int 480i81342_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 481{ 482 struct i81342_pci_softc *sc = device_get_softc(dev); 483 switch (which) { 484 case PCIB_IVAR_DOMAIN: 485 *result = 0; 486 return (0); 487 case PCIB_IVAR_BUS: 488 *result = sc->sc_busno; 489 return (0); 490 491 } 492 return (ENOENT); 493} 494 495static int 496i81342_write_ivar(device_t dev, device_t child, int which, uintptr_t result) 497{ 498 struct i81342_pci_softc * sc = device_get_softc(dev); 499 500 switch (which) { 501 case PCIB_IVAR_DOMAIN: 502 return (EINVAL); 503 case PCIB_IVAR_BUS: 504 sc->sc_busno = result; 505 return (0); 506 } 507 return (ENOENT); 508} 509 510static device_method_t i81342_pci_methods[] = { 511 /* Device interface */ 512 DEVMETHOD(device_probe, i81342_pci_probe), 513 DEVMETHOD(device_attach, i81342_pci_attach), 514 DEVMETHOD(device_shutdown, bus_generic_shutdown), 515 DEVMETHOD(device_suspend, bus_generic_suspend), 516 DEVMETHOD(device_resume, bus_generic_resume), 517 518 /* Bus interface */ 519 DEVMETHOD(bus_read_ivar, i81342_read_ivar), 520 DEVMETHOD(bus_write_ivar, i81342_write_ivar), 521 DEVMETHOD(bus_alloc_resource, i81342_pci_alloc_resource), 522 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 523 DEVMETHOD(bus_activate_resource, i81342_pci_activate_resource), 524 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 525 DEVMETHOD(bus_setup_intr, i81342_pci_setup_intr), 526 DEVMETHOD(bus_teardown_intr, i81342_pci_teardown_intr), 527 528 /* pcib interface */ 529 DEVMETHOD(pcib_maxslots, i81342_pci_maxslots), 530 DEVMETHOD(pcib_read_config, i81342_pci_read_config), 531 DEVMETHOD(pcib_write_config, i81342_pci_write_config), 532 DEVMETHOD(pcib_route_interrupt, i81342_pci_route_interrupt), 533 534 DEVMETHOD_END 535}; 536 537static driver_t i81342_pci_driver = { 538 "pcib", 539 i81342_pci_methods, 540 sizeof(struct i81342_pci_softc), 541}; 542 543static devclass_t i81342_pci_devclass; 544 545DRIVER_MODULE(ipci, iq, i81342_pci_driver, i81342_pci_devclass, 0, 0); 546