1/*-
2 * Copyright (c) 2011
3 *	Ben Gray <ben.r.gray@gmail.com>.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD$
28 */
29#ifndef _TI_MMCHS_H_
30#define _TI_MMCHS_H_
31
32/**
33 * Header file for the TI MMC/SD/SDIO driver.
34 *
35 * Simply contains register addresses and bit flags.
36 */
37
38/* Register offsets within each of the MMC/SD/SDIO controllers */
39#define MMCHS_SYSCONFIG             0x010
40#define MMCHS_SYSSTATUS             0x014
41#define MMCHS_CSRE                  0x024
42#define MMCHS_SYSTEST               0x028
43#define MMCHS_CON                   0x02C
44#define MMCHS_PWCNT                 0x030
45#define MMCHS_BLK                   0x104
46#define MMCHS_ARG                   0x108
47#define MMCHS_CMD                   0x10C
48#define MMCHS_RSP10                 0x110
49#define MMCHS_RSP32                 0x114
50#define MMCHS_RSP54                 0x118
51#define MMCHS_RSP76                 0x11C
52#define MMCHS_DATA                  0x120
53#define MMCHS_PSTATE                0x124
54#define MMCHS_HCTL                  0x128
55#define MMCHS_SYSCTL                0x12C
56#define MMCHS_STAT                  0x130
57#define MMCHS_IE                    0x134
58#define MMCHS_ISE                   0x138
59#define MMCHS_AC12                  0x13C
60#define MMCHS_CAPA                  0x140
61#define MMCHS_CUR_CAPA              0x148
62#define MMCHS_REV                   0x1FC
63
64/* OMAP4 and OMAP4 have different register addresses */
65#define OMAP3_MMCHS_REG_OFFSET      0x000
66#define OMAP4_MMCHS_REG_OFFSET      0x100
67#define AM335X_MMCHS_REG_OFFSET     0x100
68
69/* Register bit settings */
70#define	MMCHS_SYSCONFIG_CLK_FUN	    (2 << 8)
71#define	MMCHS_SYSCONFIG_CLK_IFC	    (1 << 8)
72#define	MMCHS_SYSCONFIG_SIDL	    (2 << 3)
73#define	MMCHS_SYSCONFIG_ENW	    (1 << 2)
74#define	MMCHS_SYSCONFIG_SRST	    (1 << 1)
75#define	MMCHS_SYSCONFIG_AIDL	    (1 << 0)
76#define MMCHS_STAT_BADA             (1UL << 29)
77#define MMCHS_STAT_CERR             (1UL << 28)
78#define MMCHS_STAT_ACE              (1UL << 24)
79#define MMCHS_STAT_DEB              (1UL << 22)
80#define MMCHS_STAT_DCRC             (1UL << 21)
81#define MMCHS_STAT_DTO              (1UL << 20)
82#define MMCHS_STAT_CIE              (1UL << 19)
83#define MMCHS_STAT_CEB              (1UL << 18)
84#define MMCHS_STAT_CCRC             (1UL << 17)
85#define MMCHS_STAT_CTO              (1UL << 16)
86#define MMCHS_STAT_ERRI             (1UL << 15)
87#define MMCHS_STAT_OBI              (1UL << 9)
88#define MMCHS_STAT_CIRQ             (1UL << 8)
89#define MMCHS_STAT_BRR              (1UL << 5)
90#define MMCHS_STAT_BWR              (1UL << 4)
91#define MMCHS_STAT_BGE              (1UL << 2)
92#define MMCHS_STAT_TC               (1UL << 1)
93#define MMCHS_STAT_CC               (1UL << 0)
94
95#define MMCHS_STAT_CLEAR_MASK       0x3BFF8337UL
96
97#define MMCHS_SYSCTL_SRD            (1UL << 26)
98#define MMCHS_SYSCTL_SRC            (1UL << 25)
99#define MMCHS_SYSCTL_SRA            (1UL << 24)
100#define MMCHS_SYSCTL_DTO(x)         (((x) & 0xf) << 16)
101#define MMCHS_SYSCTL_DTO_MASK       MMCHS_SYSCTL_DTO(0xf)
102#define MMCHS_SYSCTL_CLKD(x)        (((x) & 0x3ff) << 6)
103#define MMCHS_SYSCTL_CLKD_MASK      MMCHS_SYSCTL_CLKD(0x3ff)
104#define MMCHS_SYSCTL_CEN            (1UL << 2)
105#define MMCHS_SYSCTL_ICS            (1UL << 1)
106#define MMCHS_SYSCTL_ICE            (1UL << 0)
107
108#define MMCHS_HCTL_OBWE             (1UL << 27)
109#define MMCHS_HCTL_REM              (1UL << 26)
110#define MMCHS_HCTL_INS              (1UL << 25)
111#define MMCHS_HCTL_IWE              (1UL << 24)
112#define MMCHS_HCTL_IBG              (1UL << 19)
113#define MMCHS_HCTL_RWC              (1UL << 18)
114#define MMCHS_HCTL_CR               (1UL << 17)
115#define MMCHS_HCTL_SBGR             (1UL << 16)
116#define MMCHS_HCTL_SDVS_MASK        (7UL << 9)
117#define MMCHS_HCTL_SDVS_V18         (5UL << 9)
118#define MMCHS_HCTL_SDVS_V30         (6UL << 9)
119#define MMCHS_HCTL_SDVS_V33         (7UL << 9)
120#define MMCHS_HCTL_SDBP             (1UL << 8)
121#define MMCHS_HCTL_DTW              (1UL << 1)
122
123#define MMCHS_CAPA_VS18             (1UL << 26)
124#define MMCHS_CAPA_VS30             (1UL << 25)
125#define MMCHS_CAPA_VS33             (1UL << 24)
126
127#define MMCHS_CMD_CMD_TYPE_IO_ABORT (3UL << 21)
128#define MMCHS_CMD_CMD_TYPE_FUNC_SEL (2UL << 21)
129#define MMCHS_CMD_CMD_TYPE_SUSPEND  (1UL << 21)
130#define MMCHS_CMD_CMD_TYPE_OTHERS   (0UL << 21)
131#define MMCHS_CMD_CMD_TYPE_MASK     (3UL << 22)
132
133#define MMCHS_CMD_DP                (1UL << 21)
134#define MMCHS_CMD_CICE              (1UL << 20)
135#define MMCHS_CMD_CCCE              (1UL << 19)
136
137#define MMCHS_CMD_RSP_TYPE_MASK     (3UL << 16)
138#define MMCHS_CMD_RSP_TYPE_NO       (0UL << 16)
139#define MMCHS_CMD_RSP_TYPE_136      (1UL << 16)
140#define MMCHS_CMD_RSP_TYPE_48       (2UL << 16)
141#define MMCHS_CMD_RSP_TYPE_48_BSY   (3UL << 16)
142
143#define MMCHS_CMD_MSBS              (1UL << 5)
144#define MMCHS_CMD_DDIR              (1UL << 4)
145#define MMCHS_CMD_ACEN              (1UL << 2)
146#define MMCHS_CMD_BCE               (1UL << 1)
147#define MMCHS_CMD_DE                (1UL << 0)
148
149#define MMCHS_CON_CLKEXTFREE        (1UL << 16)
150#define MMCHS_CON_PADEN             (1UL << 15)
151#define MMCHS_CON_OBIE              (1UL << 14)
152#define MMCHS_CON_OBIP              (1UL << 13)
153#define MMCHS_CON_CEATA             (1UL << 12)
154#define MMCHS_CON_CTPL              (1UL << 11)
155
156#define MMCHS_CON_DVAL_8_4MS        (3UL << 9)
157#define MMCHS_CON_DVAL_1MS          (2UL << 9)
158#define MMCHS_CON_DVAL_231US        (1UL << 9)
159#define MMCHS_CON_DVAL_33US         (0UL << 9)
160#define MMCHS_CON_DVAL_MASK         (3UL << 9)
161
162#define MMCHS_CON_WPP               (1UL << 8)
163#define MMCHS_CON_CDP               (1UL << 7)
164#define MMCHS_CON_MIT               (1UL << 6)
165#define MMCHS_CON_DW8               (1UL << 5)
166#define MMCHS_CON_MODE              (1UL << 4)
167#define MMCHS_CON_STR               (1UL << 3)
168#define MMCHS_CON_HR                (1UL << 2)
169#define MMCHS_CON_INIT              (1UL << 1)
170#define MMCHS_CON_OD                (1UL << 0)
171
172#define MMCHS_CAPA_VS18             (1UL << 26)
173#define MMCHS_CAPA_VS30             (1UL << 25)
174#define MMCHS_CAPA_VS33             (1UL << 24)
175
176#endif  /* _TI_MMCHS_H_ */
177