db88f5xxx.c revision 186932
1/*- 2 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD. 3 * All rights reserved. 4 * 5 * Developed by Semihalf. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of MARVELL nor the names of contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 */ 31 32#include <sys/cdefs.h> 33__FBSDID("$FreeBSD: head/sys/arm/mv/orion/db88f5xxx.c 186932 2009-01-09 10:20:51Z raj $"); 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/bus.h> 38#include <sys/kernel.h> 39 40#include <vm/vm.h> 41#include <vm/pmap.h> 42 43#include <machine/bus.h> 44#include <machine/pte.h> 45#include <machine/pmap.h> 46#include <machine/vmparam.h> 47 48#include <arm/mv/mvreg.h> 49#include <arm/mv/mvvar.h> 50 51/* 52 * Virtual address space layout: 53 * ----------------------------- 54 * 0x0000_0000 - 0xbfff_ffff : user process 55 * 56 * 0xc040_0000 - virtual_avail : kernel reserved (text, data, page tables 57 * : structures, ARM stacks etc.) 58 * virtual_avail - 0xefff_ffff : KVA (virtual_avail is typically < 0xc0a0_0000) 59 * 0xf000_0000 - 0xf0ff_ffff : no-cache allocation area (16MB) 60 * 0xf100_0000 - 0xf10f_ffff : SoC integrated devices registers range (1MB) 61 * 0xf110_0000 - 0xf11f_ffff : PCI-Express I/O space (1MB) 62 * 0xf120_0000 - 0xf12f_ffff : PCI I/O space (1MB) 63 * 0xf130_0000 - 0xf52f_ffff : PCI-Express memory space (64MB) 64 * 0xf530_0000 - 0xf92f_ffff : PCI memory space (64MB) 65 * 0xf930_0000 - 0xfffe_ffff : unused (~108MB) 66 * 0xffff_0000 - 0xffff_0fff : 'high' vectors page (4KB) 67 * 0xffff_1000 - 0xffff_1fff : ARM_TP_ADDRESS/RAS page (4KB) 68 * 0xffff_2000 - 0xffff_ffff : unused (~55KB) 69 */ 70 71const struct pmap_devmap *pmap_devmap_bootstrap_table; 72vm_offset_t pmap_bootstrap_lastaddr; 73int platform_pci_get_irq(u_int bus, u_int slot, u_int func, u_int pin); 74 75/* Static device mappings. */ 76static const struct pmap_devmap pmap_devmap[] = { 77 /* 78 * Map the on-board devices VA == PA so that we can access them 79 * with the MMU on or off. 80 */ 81 { /* SoC integrated peripherals registers range */ 82 MV_BASE, 83 MV_PHYS_BASE, 84 MV_SIZE, 85 VM_PROT_READ | VM_PROT_WRITE, 86 PTE_NOCACHE, 87 }, 88 { /* PCIE I/O */ 89 MV_PCIE_IO_BASE, 90 MV_PCIE_IO_PHYS_BASE, 91 MV_PCIE_IO_SIZE, 92 VM_PROT_READ | VM_PROT_WRITE, 93 PTE_NOCACHE, 94 }, 95 { /* PCIE Memory */ 96 MV_PCIE_MEM_BASE, 97 MV_PCIE_MEM_PHYS_BASE, 98 MV_PCIE_MEM_SIZE, 99 VM_PROT_READ | VM_PROT_WRITE, 100 PTE_NOCACHE, 101 }, 102 { /* PCI I/O */ 103 MV_PCI_IO_BASE, 104 MV_PCI_IO_PHYS_BASE, 105 MV_PCI_IO_SIZE, 106 VM_PROT_READ | VM_PROT_WRITE, 107 PTE_NOCACHE, 108 }, 109 { /* PCI Memory */ 110 MV_PCI_MEM_BASE, 111 MV_PCI_MEM_PHYS_BASE, 112 MV_PCI_MEM_SIZE, 113 VM_PROT_READ | VM_PROT_WRITE, 114 PTE_NOCACHE, 115 }, 116 { /* 7-seg LED */ 117 MV_DEV_CS0_BASE, 118 MV_DEV_CS0_PHYS_BASE, 119 MV_DEV_CS0_SIZE, 120 VM_PROT_READ | VM_PROT_WRITE, 121 PTE_NOCACHE, 122 }, 123 { 0, 0, 0, 0, 0, } 124}; 125 126/* 127 * The pci_irq_map table consists of 3 columns: 128 * - PCI slot number (less than zero means ANY). 129 * - PCI IRQ pin (less than zero means ANY). 130 * - PCI IRQ (less than zero marks end of table). 131 * 132 * IRQ number from the first matching entry is used to configure PCI device 133 */ 134 135/* PCI IRQ Map for DB-88F5281 */ 136const struct obio_pci_irq_map pci_irq_map[] = { 137 { 7, -1, GPIO2IRQ(12) }, 138 { 8, -1, GPIO2IRQ(13) }, 139 { 9, -1, GPIO2IRQ(13) }, 140 { -1, -1, -1 } 141}; 142 143#if 0 144/* PCI IRQ Map for DB-88F5182 */ 145const struct obio_pci_irq_map pci_irq_map[] = { 146 { 7, -1, GPIO2IRQ(0) }, 147 { 8, -1, GPIO2IRQ(1) }, 148 { 9, -1, GPIO2IRQ(1) }, 149 { -1, -1, -1 } 150}; 151#endif 152 153/* 154 * mv_gpio_config row structure: 155 * <GPIO number>, <GPIO flags>, <GPIO mode> 156 * 157 * - GPIO pin number (less than zero marks end of table) 158 * - GPIO flags: 159 * MV_GPIO_BLINK 160 * MV_GPIO_POLAR_LOW 161 * MV_GPIO_EDGE 162 * MV_GPIO_LEVEL 163 * - GPIO mode: 164 * 1 - Output, set to HIGH. 165 * 0 - Output, set to LOW. 166 * -1 - Input. 167 */ 168 169/* GPIO Configuration for DB-88F5281 */ 170const struct gpio_config mv_gpio_config[] = { 171 { 12, MV_GPIO_POLAR_LOW | MV_GPIO_LEVEL, -1 }, 172 { 13, MV_GPIO_POLAR_LOW | MV_GPIO_LEVEL, -1 }, 173 { -1, -1, -1 } 174}; 175 176#if 0 177/* GPIO Configuration for DB-88F5182 */ 178const struct gpio_config mv_gpio_config[] = { 179 { 0, MV_GPIO_POLAR_LOW | MV_GPIO_LEVEL, -1 }, 180 { 1, MV_GPIO_POLAR_LOW | MV_GPIO_LEVEL, -1 }, 181 { -1, -1, -1 } 182}; 183#endif 184 185int 186platform_pmap_init(void) 187{ 188 189 pmap_bootstrap_lastaddr = MV_BASE - ARM_NOCACHE_KVA_SIZE; 190 pmap_devmap_bootstrap_table = &pmap_devmap[0]; 191 192 return (0); 193} 194 195void 196platform_mpp_init(void) 197{ 198 199 /* 200 * MPP configuration for DB-88F5281 201 * 202 * MPP[2]: PCI_REQn[3] 203 * MPP[3]: PCI_GNTn[3] 204 * MPP[4]: PCI_REQn[4] 205 * MPP[5]: PCI_GNTn[4] 206 * MPP[6]: <UNKNOWN> 207 * MPP[7]: <UNKNOWN> 208 * MPP[8]: <UNKNOWN> 209 * MPP[9]: <UNKNOWN> 210 * MPP[14]: NAND Flash REn[2] 211 * MPP[15]: NAND Flash WEn[2] 212 * MPP[16]: UA1_RXD 213 * MPP[17]: UA1_TXD 214 * MPP[18]: UA1_CTS 215 * MPP[19]: UA1_RTS 216 * 217 * Others: GPIO 218 * 219 * <UNKNOWN> entries are not documented, not on the schematics etc. 220 */ 221 bus_space_write_4(obio_tag, MV_MPP_BASE, MPP_CONTROL0, 0x33222203); 222 bus_space_write_4(obio_tag, MV_MPP_BASE, MPP_CONTROL1, 0x44000033); 223 bus_space_write_4(obio_tag, MV_MPP_BASE, MPP_CONTROL2, 0x00000000); 224 225#if 0 226 /* 227 * MPP configuration for DB-88F5182 228 * 229 * MPP[2]: PCI_REQn[3] 230 * MPP[3]: PCI_GNTn[3] 231 * MPP[4]: PCI_REQn[4] 232 * MPP[5]: PCI_GNTn[4] 233 * MPP[6]: SATA0_ACT 234 * MPP[7]: SATA1_ACT 235 * MPP[12]: SATA0_PRESENT 236 * MPP[13]: SATA1_PRESENT 237 * MPP[14]: NAND_FLASH_REn[2] 238 * MPP[15]: NAND_FLASH_WEn[2] 239 * MPP[16]: UA1_RXD 240 * MPP[17]: UA1_TXD 241 * MPP[18]: UA1_CTS 242 * MPP[19]: UA1_RTS 243 * 244 * Others: GPIO 245 */ 246 bus_space_write_4(obio_tag, MV_MPP_BASE, MPP_CONTROL0, 0x55222203); 247 bus_space_write_4(obio_tag, MV_MPP_BASE, MPP_CONTROL1, 0x44550000); 248 bus_space_write_4(obio_tag, MV_MPP_BASE, MPP_CONTROL2, 0x00000000); 249#endif 250} 251 252static void 253platform_identify(void *dummy) 254{ 255 256 soc_identify(); 257 258 /* 259 * XXX Board identification e.g. read out from FPGA or similar should 260 * go here 261 */ 262} 263SYSINIT(platform_identify, SI_SUB_CPU, SI_ORDER_SECOND, platform_identify, NULL); 264