1/*-
2 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
3 * All rights reserved.
4 *
5 * Developed by Semihalf.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of MARVELL nor the names of contributors
16 *    may be used to endorse or promote products derived from this software
17 *    without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32#include <sys/cdefs.h>
33__FBSDID("$FreeBSD$");
34
35#include <sys/param.h>
36#include <sys/systm.h>
37#include <sys/bus.h>
38#include <sys/kernel.h>
39
40#include <vm/vm.h>
41#include <vm/pmap.h>
42
43#include <machine/bus.h>
44#include <machine/intr.h>
45#include <machine/pte.h>
46#include <machine/pmap.h>
47#include <machine/vmparam.h>
48
49#include <arm/mv/mvreg.h>
50#include <arm/mv/mvvar.h>
51#include <arm/mv/mvwin.h>
52
53/*
54 * Virtual address space layout:
55 * -----------------------------
56 * 0x0000_0000 - 0xbfff_ffff	: user process
57 *
58 * 0xc040_0000 - virtual_avail	: kernel reserved (text, data, page tables
59 *				: structures, ARM stacks etc.)
60 * virtual_avail - 0xefff_ffff	: KVA (virtual_avail is typically < 0xc0a0_0000)
61 * 0xf000_0000 - 0xf0ff_ffff	: no-cache allocation area (16MB)
62 * 0xf100_0000 - 0xf10f_ffff	: SoC integrated devices registers range (1MB)
63 * 0xf110_0000 - 0xf11f_ffff	: PCI-Express I/O space (1MB)
64 * 0xf120_0000 - 0xf12f_ffff	: PCI I/O space (1MB)
65 * 0xf130_0000 - 0xf52f_ffff	: PCI-Express memory space (64MB)
66 * 0xf530_0000 - 0xf92f_ffff	: PCI memory space (64MB)
67 * 0xf930_0000 - 0xfffe_ffff	: unused (~108MB)
68 * 0xffff_0000 - 0xffff_0fff	: 'high' vectors page (4KB)
69 * 0xffff_1000 - 0xffff_1fff	: ARM_TP_ADDRESS/RAS page (4KB)
70 * 0xffff_2000 - 0xffff_ffff	: unused (~55KB)
71 */
72
73
74#if 0
75int platform_pci_get_irq(u_int bus, u_int slot, u_int func, u_int pin);
76
77/* Static device mappings. */
78const struct pmap_devmap pmap_devmap[] = {
79	/*
80	 * Map the on-board devices VA == PA so that we can access them
81	 * with the MMU on or off.
82	 */
83	{ /* SoC integrated peripherals registers range */
84		MV_BASE,
85		MV_PHYS_BASE,
86		MV_SIZE,
87		VM_PROT_READ | VM_PROT_WRITE,
88		PTE_NOCACHE,
89	},
90	{ /* PCIE I/O */
91		MV_PCIE_IO_BASE,
92		MV_PCIE_IO_PHYS_BASE,
93		MV_PCIE_IO_SIZE,
94		VM_PROT_READ | VM_PROT_WRITE,
95		PTE_NOCACHE,
96	},
97	{ /* PCIE Memory */
98		MV_PCIE_MEM_BASE,
99		MV_PCIE_MEM_PHYS_BASE,
100		MV_PCIE_MEM_SIZE,
101		VM_PROT_READ | VM_PROT_WRITE,
102		PTE_NOCACHE,
103	},
104	{ /* PCI I/O */
105		MV_PCI_IO_BASE,
106		MV_PCI_IO_PHYS_BASE,
107		MV_PCI_IO_SIZE,
108		VM_PROT_READ | VM_PROT_WRITE,
109		PTE_NOCACHE,
110	},
111	{ /* PCI Memory */
112		MV_PCI_MEM_BASE,
113		MV_PCI_MEM_PHYS_BASE,
114		MV_PCI_MEM_SIZE,
115		VM_PROT_READ | VM_PROT_WRITE,
116		PTE_NOCACHE,
117	},
118	{ /* 7-seg LED */
119		MV_DEV_CS0_BASE,
120		MV_DEV_CS0_PHYS_BASE,
121		MV_DEV_CS0_SIZE,
122		VM_PROT_READ | VM_PROT_WRITE,
123		PTE_NOCACHE,
124	},
125	{ 0, 0, 0, 0, 0, }
126};
127
128/*
129 * The pci_irq_map table consists of 3 columns:
130 * - PCI slot number (less than zero means ANY).
131 * - PCI IRQ pin (less than zero means ANY).
132 * - PCI IRQ (less than zero marks end of table).
133 *
134 * IRQ number from the first matching entry is used to configure PCI device
135 */
136
137/* PCI IRQ Map for DB-88F5281 */
138const struct obio_pci_irq_map pci_irq_map[] = {
139	{ 7, -1, GPIO2IRQ(12) },
140	{ 8, -1, GPIO2IRQ(13) },
141	{ 9, -1, GPIO2IRQ(13) },
142	{ -1, -1, -1 }
143};
144
145/* PCI IRQ Map for DB-88F5182 */
146const struct obio_pci_irq_map pci_irq_map[] = {
147	{ 7, -1, GPIO2IRQ(0) },
148	{ 8, -1, GPIO2IRQ(1) },
149	{ 9, -1, GPIO2IRQ(1) },
150	{ -1, -1, -1 }
151};
152#endif
153
154#if 0
155/*
156 * mv_gpio_config row structure:
157 *	<GPIO number>, <GPIO flags>, <GPIO mode>
158 *
159 * - GPIO pin number (less than zero marks end of table)
160 * - GPIO flags:
161 *	MV_GPIO_BLINK
162 *	MV_GPIO_POLAR_LOW
163 *	MV_GPIO_EDGE
164 *	MV_GPIO_LEVEL
165 * - GPIO mode:
166 *	1	- Output, set to HIGH.
167 *	0	- Output, set to LOW.
168 *	-1	- Input.
169 */
170
171/* GPIO Configuration for DB-88F5281 */
172const struct gpio_config mv_gpio_config[] = {
173	{ 12, MV_GPIO_POLAR_LOW | MV_GPIO_LEVEL, -1 },
174	{ 13, MV_GPIO_POLAR_LOW | MV_GPIO_LEVEL, -1 },
175	{ -1, -1, -1 }
176};
177
178#if 0
179/* GPIO Configuration for DB-88F5182 */
180const struct gpio_config mv_gpio_config[] = {
181	{ 0, MV_GPIO_POLAR_LOW | MV_GPIO_LEVEL, -1 },
182	{ 1, MV_GPIO_POLAR_LOW | MV_GPIO_LEVEL, -1 },
183	{ -1, -1, -1 }
184};
185#endif
186
187#endif
188