db88f5xxx.c revision 183840 
1/*-
2 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
3 * All rights reserved.
4 *
5 * Developed by Semihalf.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of MARVELL nor the names of contributors
16 *    may be used to endorse or promote products derived from this software
17 *    without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 */
31
32#include <sys/cdefs.h>
33__FBSDID("$FreeBSD: head/sys/arm/mv/orion/db88f5xxx.c 183840 2008-10-13 20:07:13Z raj $");
34
35#include <sys/param.h>
36#include <sys/systm.h>
37#include <sys/bus.h>
38#include <sys/kernel.h>
39
40#include <vm/vm.h>
41#include <vm/pmap.h>
42
43#include <machine/pte.h>
44#include <machine/pmap.h>
45#include <machine/vmparam.h>
46
47#include <arm/mv/mvreg.h>
48#include <arm/mv/mvvar.h>
49
50/*
51 * Virtual address space layout:
52 * -----------------------------
53 * 0x0000_0000 - 0xbfff_ffff	: user process
54 *
55 * 0xc040_0000 - virtual_avail	: kernel reserved (text, data, page tables
56 *				: structures, ARM stacks etc.)
57 * virtual_avail - 0xefff_ffff	: KVA (virtual_avail is typically < 0xc0a0_0000)
58 * 0xf000_0000 - 0xf0ff_ffff	: no-cache allocation area (16MB)
59 * 0xf100_0000 - 0xf10f_ffff	: SoC integrated devices registers range (1MB)
60 * 0xf110_0000 - 0xfffe_ffff	: PCI, PCIE (MEM+IO) outbound windows (~238MB)
61 * 0xffff_0000 - 0xffff_0fff	: 'high' vectors page (4KB)
62 * 0xffff_1000 - 0xffff_1fff	: ARM_TP_ADDRESS/RAS page (4KB)
63 * 0xffff_2000 - 0xffff_ffff	: unused (~55KB)
64 */
65
66const struct pmap_devmap *pmap_devmap_bootstrap_table;
67vm_offset_t pmap_bootstrap_lastaddr;
68
69/* Static device mappings. */
70static const struct pmap_devmap pmap_devmap[] = {
71	/*
72	 * Map the on-board devices VA == PA so that we can access them
73	 * with the MMU on or off.
74	 */
75	{ /* SoC integrated peripherals registers range */
76		MV_BASE,
77		MV_PHYS_BASE,
78		MV_SIZE,
79		VM_PROT_READ | VM_PROT_WRITE,
80		PTE_NOCACHE,
81	},
82	{ /* PCIE I/O */
83		MV_PCIE_IO_BASE,
84		MV_PCIE_IO_PHYS_BASE,
85		MV_PCIE_IO_SIZE,
86		VM_PROT_READ | VM_PROT_WRITE,
87		PTE_NOCACHE,
88	},
89	{ /* PCIE Memory */
90		MV_PCIE_MEM_BASE,
91		MV_PCIE_MEM_PHYS_BASE,
92		MV_PCIE_MEM_SIZE,
93		VM_PROT_READ | VM_PROT_WRITE,
94		PTE_NOCACHE,
95	},
96	{ /* PCI I/O */
97		MV_PCI_IO_BASE,
98		MV_PCI_IO_PHYS_BASE,
99		MV_PCI_IO_SIZE,
100		VM_PROT_READ | VM_PROT_WRITE,
101		PTE_NOCACHE,
102	},
103	{ /* PCI Memory */
104		MV_PCI_MEM_BASE,
105		MV_PCI_MEM_PHYS_BASE,
106		MV_PCI_MEM_SIZE,
107		VM_PROT_READ | VM_PROT_WRITE,
108		PTE_NOCACHE,
109	},
110	{ /* 7-seg LED */
111		MV_DEV_CS0_BASE,
112		MV_DEV_CS0_PHYS_BASE,
113		MV_DEV_CS0_SIZE,
114		VM_PROT_READ | VM_PROT_WRITE,
115		PTE_NOCACHE,
116	},
117	{ 0, 0, 0, 0, 0, }
118};
119
120#if 0
121int platform_pci_get_irq(u_int bus, u_int slot, u_int func, u_int pin)
122{
123	int irq;
124
125	switch (slot) {
126	case 7:
127		irq = GPIO2IRQ(12);	/* GPIO 0 for DB-88F5182  */
128		break;			/* GPIO 12 for DB-88F5281 */
129	case 8:
130	case 9:
131		irq = GPIO2IRQ(13);	/* GPIO 1 for DB-88F5182  */
132		break;			/* GPIO 13 for DB-88F5281 */
133	default:
134		irq = -1;
135		break;
136	};
137
138	/*
139	 * XXX This isn't the right place to setup GPIO, but it makes sure
140	 * that PCI works on 5XXX targets where U-Boot doesn't set up the GPIO
141	 * correctly to handle PCI IRQs (e.g., on 5182). This code will go
142	 * away once we set up GPIO in a generic way in a proper place (TBD).
143	 */
144	if (irq >= 0)
145		mv_gpio_configure(IRQ2GPIO(irq), MV_GPIO_POLARITY |
146		    MV_GPIO_LEVEL, ~0u);
147
148	return(irq);
149}
150#endif
151
152int
153platform_pmap_init(void)
154{
155
156	pmap_bootstrap_lastaddr = MV_BASE - ARM_NOCACHE_KVA_SIZE;
157	pmap_devmap_bootstrap_table = &pmap_devmap[0];
158
159	return (0);
160}
161
162static void
163platform_identify(void *dummy)
164{
165
166	soc_identify();
167
168	/*
169	 * XXX Board identification e.g. read out from FPGA or similar should
170	 * go here
171	 */
172}
173SYSINIT(platform_identify, SI_SUB_CPU, SI_ORDER_SECOND, platform_identify, NULL);
174
175/*
176 * TODO routine setting GPIO/MPP pins
177 */
178