1183840Sraj/*- 2183840Sraj * Copyright (c) 1994-1998 Mark Brinicombe. 3183840Sraj * Copyright (c) 1994 Brini. 4183840Sraj * All rights reserved. 5183840Sraj * 6183840Sraj * This code is derived from software written for Brini by Mark Brinicombe 7183840Sraj * 8183840Sraj * Redistribution and use in source and binary forms, with or without 9183840Sraj * modification, are permitted provided that the following conditions 10183840Sraj * are met: 11183840Sraj * 1. Redistributions of source code must retain the above copyright 12183840Sraj * notice, this list of conditions and the following disclaimer. 13183840Sraj * 2. Redistributions in binary form must reproduce the above copyright 14183840Sraj * notice, this list of conditions and the following disclaimer in the 15183840Sraj * documentation and/or other materials provided with the distribution. 16183840Sraj * 3. All advertising materials mentioning features or use of this software 17183840Sraj * must display the following acknowledgement: 18183840Sraj * This product includes software developed by Brini. 19183840Sraj * 4. The name of the company nor the name of the author may be used to 20183840Sraj * endorse or promote products derived from this software without specific 21183840Sraj * prior written permission. 22183840Sraj * 23183840Sraj * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 24183840Sraj * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25183840Sraj * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26183840Sraj * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27183840Sraj * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28183840Sraj * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29183840Sraj * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30183840Sraj * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31183840Sraj * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32183840Sraj * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33183840Sraj * SUCH DAMAGE. 34183840Sraj * 35183840Sraj * from: FreeBSD: //depot/projects/arm/src/sys/arm/at91/kb920x_machdep.c, rev 45 36183840Sraj */ 37183840Sraj 38183840Sraj#include "opt_ddb.h" 39209131Sraj#include "opt_platform.h" 40183840Sraj 41183840Sraj#include <sys/cdefs.h> 42183840Sraj__FBSDID("$FreeBSD$"); 43183840Sraj 44183840Sraj#define _ARM32_BUS_DMA_PRIVATE 45183840Sraj#include <sys/param.h> 46183840Sraj#include <sys/systm.h> 47183840Sraj#include <sys/bus.h> 48183840Sraj 49183840Sraj#include <vm/vm.h> 50183840Sraj#include <vm/pmap.h> 51242531Sandrew 52242531Sandrew#include <machine/bus.h> 53242531Sandrew#include <machine/frame.h> /* For trapframe_t, used in <machine/machdep.h> */ 54242531Sandrew#include <machine/machdep.h> 55183840Sraj#include <machine/pmap.h> 56183840Sraj 57209131Sraj#include <arm/mv/mvreg.h> /* XXX */ 58183840Sraj#include <arm/mv/mvvar.h> /* XXX eventually this should be eliminated */ 59196531Sraj#include <arm/mv/mvwin.h> 60183840Sraj 61242531Sandrew#include <dev/fdt/fdt_common.h> 62183840Sraj 63209131Srajstatic int platform_mpp_init(void); 64250292Sgber#if defined(SOC_MV_ARMADAXP) 65250293Sgbervoid armadaxp_init_coher_fabric(void); 66250292Sgbervoid armadaxp_l2_init(void); 67250292Sgber#endif 68183840Sraj 69239277Sgonzo#define MPP_PIN_MAX 68 70209131Sraj#define MPP_PIN_CELLS 2 71209131Sraj#define MPP_PINS_PER_REG 8 72209131Sraj#define MPP_SEL(pin,func) (((func) & 0xf) << \ 73209131Sraj (((pin) % MPP_PINS_PER_REG) * 4)) 74209131Sraj 75209131Srajstatic int 76209131Srajplatform_mpp_init(void) 77209131Sraj{ 78209131Sraj pcell_t pinmap[MPP_PIN_MAX * MPP_PIN_CELLS]; 79209131Sraj int mpp[MPP_PIN_MAX]; 80209131Sraj uint32_t ctrl_val, ctrl_offset; 81209131Sraj pcell_t reg[4]; 82209131Sraj u_long start, size; 83209131Sraj phandle_t node; 84209131Sraj pcell_t pin_cells, *pinmap_ptr, pin_count; 85209131Sraj ssize_t len; 86209131Sraj int par_addr_cells, par_size_cells; 87209131Sraj int tuple_size, tuples, rv, pins, i, j; 88209131Sraj int mpp_pin, mpp_function; 89209131Sraj 90209131Sraj /* 91209131Sraj * Try to access the MPP node directly i.e. through /aliases/mpp. 92209131Sraj */ 93228201Sjchandra if ((node = OF_finddevice("mpp")) != -1) 94209131Sraj if (fdt_is_compatible(node, "mrvl,mpp")) 95209131Sraj goto moveon; 96209131Sraj /* 97209131Sraj * Find the node the long way. 98209131Sraj */ 99228201Sjchandra if ((node = OF_finddevice("/")) == -1) 100209131Sraj return (ENXIO); 101209131Sraj 102209131Sraj if ((node = fdt_find_compatible(node, "simple-bus", 0)) == 0) 103209131Sraj return (ENXIO); 104209131Sraj 105209131Sraj if ((node = fdt_find_compatible(node, "mrvl,mpp", 0)) == 0) 106239277Sgonzo /* 107239277Sgonzo * No MPP node. Fall back to how MPP got set by the 108239277Sgonzo * first-stage loader and try to continue booting. 109239277Sgonzo */ 110239277Sgonzo return (0); 111209131Srajmoveon: 112209131Sraj /* 113209131Sraj * Process 'reg' prop. 114209131Sraj */ 115209131Sraj if ((rv = fdt_addrsize_cells(OF_parent(node), &par_addr_cells, 116209131Sraj &par_size_cells)) != 0) 117209131Sraj return(ENXIO); 118209131Sraj 119209131Sraj tuple_size = sizeof(pcell_t) * (par_addr_cells + par_size_cells); 120209131Sraj len = OF_getprop(node, "reg", reg, sizeof(reg)); 121209131Sraj tuples = len / tuple_size; 122209131Sraj if (tuple_size <= 0) 123209131Sraj return (EINVAL); 124209131Sraj 125209131Sraj /* 126209131Sraj * Get address/size. XXX we assume only the first 'reg' tuple is used. 127209131Sraj */ 128209131Sraj rv = fdt_data_to_res(reg, par_addr_cells, par_size_cells, 129209131Sraj &start, &size); 130209131Sraj if (rv != 0) 131209131Sraj return (rv); 132209131Sraj start += fdt_immr_va; 133209131Sraj 134209131Sraj /* 135209131Sraj * Process 'pin-count' and 'pin-map' props. 136209131Sraj */ 137209131Sraj if (OF_getprop(node, "pin-count", &pin_count, sizeof(pin_count)) <= 0) 138209131Sraj return (ENXIO); 139209131Sraj pin_count = fdt32_to_cpu(pin_count); 140209131Sraj if (pin_count > MPP_PIN_MAX) 141209131Sraj return (ERANGE); 142209131Sraj 143209131Sraj if (OF_getprop(node, "#pin-cells", &pin_cells, sizeof(pin_cells)) <= 0) 144209131Sraj pin_cells = MPP_PIN_CELLS; 145209131Sraj pin_cells = fdt32_to_cpu(pin_cells); 146209131Sraj if (pin_cells > MPP_PIN_CELLS) 147209131Sraj return (ERANGE); 148209131Sraj tuple_size = sizeof(pcell_t) * pin_cells; 149209131Sraj 150209131Sraj bzero(pinmap, sizeof(pinmap)); 151209131Sraj len = OF_getprop(node, "pin-map", pinmap, sizeof(pinmap)); 152209131Sraj if (len <= 0) 153209131Sraj return (ERANGE); 154209131Sraj if (len % tuple_size) 155209131Sraj return (ERANGE); 156209131Sraj pins = len / tuple_size; 157209131Sraj if (pins > pin_count) 158209131Sraj return (ERANGE); 159209131Sraj /* 160209131Sraj * Fill out a "mpp[pin] => function" table. All pins unspecified in 161209131Sraj * the 'pin-map' property are defaulted to 0 function i.e. GPIO. 162209131Sraj */ 163209131Sraj bzero(mpp, sizeof(mpp)); 164209131Sraj pinmap_ptr = pinmap; 165209131Sraj for (i = 0; i < pins; i++) { 166209131Sraj mpp_pin = fdt32_to_cpu(*pinmap_ptr); 167209131Sraj mpp_function = fdt32_to_cpu(*(pinmap_ptr + 1)); 168209131Sraj mpp[mpp_pin] = mpp_function; 169209131Sraj pinmap_ptr += pin_cells; 170209131Sraj } 171209131Sraj 172209131Sraj /* 173209131Sraj * Prepare and program MPP control register values. 174209131Sraj */ 175209131Sraj ctrl_offset = 0; 176209131Sraj for (i = 0; i < pin_count;) { 177209131Sraj ctrl_val = 0; 178209131Sraj 179209131Sraj for (j = 0; j < MPP_PINS_PER_REG; j++) { 180209131Sraj if (i + j == pin_count - 1) 181209131Sraj break; 182209131Sraj ctrl_val |= MPP_SEL(i + j, mpp[i + j]); 183209131Sraj } 184209131Sraj i += MPP_PINS_PER_REG; 185209131Sraj bus_space_write_4(fdtbus_bs_tag, start, ctrl_offset, 186209131Sraj ctrl_val); 187209131Sraj 188209131Sraj#if defined(SOC_MV_ORION) 189209131Sraj /* 190209131Sraj * Third MPP reg on Orion SoC is placed 191209131Sraj * non-linearly (with different offset). 192209131Sraj */ 193209131Sraj if (i == (2 * MPP_PINS_PER_REG)) 194209131Sraj ctrl_offset = 0x50; 195209131Sraj else 196209131Sraj#endif 197209131Sraj ctrl_offset += 4; 198209131Sraj } 199209131Sraj 200209131Sraj return (0); 201209131Sraj} 202209131Sraj 203240846Sandrewvm_offset_t 204240846Sandrewinitarm_lastaddr(void) 205240846Sandrew{ 206240846Sandrew 207240846Sandrew if (fdt_immr_addr(MV_BASE) != 0) 208240846Sandrew while (1); 209240846Sandrew 210240846Sandrew /* Platform-specific initialisation */ 211240846Sandrew return (fdt_immr_va - ARM_NOCACHE_KVA_SIZE); 212240846Sandrew} 213240846Sandrew 214240846Sandrewvoid 215240846Sandrewinitarm_gpio_init(void) 216240846Sandrew{ 217240846Sandrew 218240846Sandrew /* 219240846Sandrew * Re-initialise MPP. It is important to call this prior to using 220240846Sandrew * console as the physical connection can be routed via MPP. 221240846Sandrew */ 222240846Sandrew if (platform_mpp_init() != 0) 223240846Sandrew while (1); 224240846Sandrew} 225240846Sandrew 226240846Sandrewvoid 227240846Sandrewinitarm_late_init(void) 228240846Sandrew{ 229240846Sandrew /* 230240846Sandrew * Re-initialise decode windows 231240846Sandrew */ 232240846Sandrew#if !defined(SOC_MV_FREY) 233240846Sandrew if (soc_decode_win() != 0) 234240846Sandrew printf("WARNING: could not re-initialise decode windows! " 235240846Sandrew "Running with existing settings...\n"); 236240846Sandrew#else 237240846Sandrew /* Disable watchdog and timers */ 238240846Sandrew write_cpu_ctrl(CPU_TIMERS_BASE + CPU_TIMER_CONTROL, 0); 239240846Sandrew#endif 240250292Sgber#if defined(SOC_MV_ARMADAXP) 241250293Sgber#if !defined(SMP) 242250293Sgber /* For SMP case it should be initialized after APs are booted */ 243250293Sgber armadaxp_init_coher_fabric(); 244250293Sgber#endif 245250292Sgber armadaxp_l2_init(); 246250292Sgber#endif 247240846Sandrew} 248240846Sandrew 249239277Sgonzo#define FDT_DEVMAP_MAX (MV_WIN_CPU_MAX + 2) 250209131Srajstatic struct pmap_devmap fdt_devmap[FDT_DEVMAP_MAX] = { 251209131Sraj { 0, 0, 0, 0, 0, } 252209131Sraj}; 253209131Sraj 254239277Sgonzostatic int 255239277Sgonzoplatform_sram_devmap(struct pmap_devmap *map) 256239277Sgonzo{ 257239277Sgonzo#if !defined(SOC_MV_ARMADAXP) 258239277Sgonzo phandle_t child, root; 259239277Sgonzo u_long base, size; 260239277Sgonzo /* 261239277Sgonzo * SRAM range. 262239277Sgonzo */ 263239277Sgonzo if ((child = OF_finddevice("/sram")) != 0) 264239277Sgonzo if (fdt_is_compatible(child, "mrvl,cesa-sram") || 265239277Sgonzo fdt_is_compatible(child, "mrvl,scratchpad")) 266239277Sgonzo goto moveon; 267239277Sgonzo 268239277Sgonzo if ((root = OF_finddevice("/")) == 0) 269239277Sgonzo return (ENXIO); 270239277Sgonzo 271239277Sgonzo if ((child = fdt_find_compatible(root, "mrvl,cesa-sram", 0)) == 0 && 272239277Sgonzo (child = fdt_find_compatible(root, "mrvl,scratchpad", 0)) == 0) 273239277Sgonzo goto out; 274239277Sgonzo 275239277Sgonzomoveon: 276239277Sgonzo if (fdt_regsize(child, &base, &size) != 0) 277239277Sgonzo return (EINVAL); 278239277Sgonzo 279239277Sgonzo map->pd_va = MV_CESA_SRAM_BASE; /* XXX */ 280239277Sgonzo map->pd_pa = base; 281239277Sgonzo map->pd_size = size; 282239277Sgonzo map->pd_prot = VM_PROT_READ | VM_PROT_WRITE; 283239277Sgonzo map->pd_cache = PTE_NOCACHE; 284239277Sgonzo 285239277Sgonzo return (0); 286239277Sgonzoout: 287239277Sgonzo#endif 288239277Sgonzo return (ENOENT); 289239277Sgonzo 290239277Sgonzo} 291239277Sgonzo 292209131Sraj/* 293245954Sian * Supply a default do-nothing implementation of fdt_pci_devmap() via a weak 294245954Sian * alias. Many Marvell platforms don't support a PCI interface, but to support 295245954Sian * those that do, we end up with a reference to this function below, in 296245954Sian * platform_devmap_init(). If "device pci" appears in the kernel config, the 297245954Sian * real implementation of this function in dev/fdt/fdt_pci.c overrides the weak 298245954Sian * alias defined here. 299245954Sian */ 300245954Sianint mv_default_fdt_pci_devmap(phandle_t node, struct pmap_devmap *devmap, 301245954Sian vm_offset_t io_va, vm_offset_t mem_va); 302245954Sianint 303245954Sianmv_default_fdt_pci_devmap(phandle_t node, struct pmap_devmap *devmap, 304245954Sian vm_offset_t io_va, vm_offset_t mem_va) 305245954Sian{ 306245954Sian 307245954Sian return (0); 308245954Sian} 309245954Sian__weak_reference(mv_default_fdt_pci_devmap, fdt_pci_devmap); 310245954Sian 311245954Sian/* 312235609Sgber * XXX: When device entry in devmap has pd_size smaller than section size, 313235609Sgber * system will freeze during initialization 314235609Sgber */ 315235609Sgber 316235609Sgber/* 317209131Sraj * Construct pmap_devmap[] with DT-derived config data. 318209131Sraj */ 319242531Sandrewint 320209131Srajplatform_devmap_init(void) 321209131Sraj{ 322209131Sraj phandle_t root, child; 323235609Sgber pcell_t bank_count; 324235609Sgber int i, num_mapped; 325209131Sraj 326235609Sgber i = 0; 327235609Sgber pmap_devmap_bootstrap_table = &fdt_devmap[0]; 328235609Sgber 329209131Sraj /* 330209131Sraj * IMMR range. 331209131Sraj */ 332209131Sraj fdt_devmap[i].pd_va = fdt_immr_va; 333209131Sraj fdt_devmap[i].pd_pa = fdt_immr_pa; 334209131Sraj fdt_devmap[i].pd_size = fdt_immr_size; 335209131Sraj fdt_devmap[i].pd_prot = VM_PROT_READ | VM_PROT_WRITE; 336209131Sraj fdt_devmap[i].pd_cache = PTE_NOCACHE; 337209131Sraj i++; 338209131Sraj 339209131Sraj /* 340239277Sgonzo * SRAM range. 341239277Sgonzo */ 342239277Sgonzo if (i < FDT_DEVMAP_MAX) 343239277Sgonzo if (platform_sram_devmap(&fdt_devmap[i]) == 0) 344239277Sgonzo i++; 345239277Sgonzo 346239277Sgonzo /* 347239277Sgonzo * PCI range(s). 348235609Sgber * PCI range(s) and localbus. 349209131Sraj */ 350228201Sjchandra if ((root = OF_finddevice("/")) == -1) 351209131Sraj return (ENXIO); 352235609Sgber for (child = OF_child(root); child != 0; child = OF_peer(child)) { 353239277Sgonzo if (fdt_is_type(child, "pci") || fdt_is_type(child, "pciep")) { 354209131Sraj /* 355209131Sraj * Check space: each PCI node will consume 2 devmap 356209131Sraj * entries. 357209131Sraj */ 358239277Sgonzo if (i + 1 >= FDT_DEVMAP_MAX) 359209131Sraj return (ENOMEM); 360209131Sraj 361209131Sraj /* 362209131Sraj * XXX this should account for PCI and multiple ranges 363209131Sraj * of a given kind. 364209131Sraj */ 365239277Sgonzo if (fdt_pci_devmap(child, &fdt_devmap[i], MV_PCI_VA_IO_BASE, 366239277Sgonzo MV_PCI_VA_MEM_BASE) != 0) 367209131Sraj return (ENXIO); 368209131Sraj i += 2; 369209131Sraj } 370209131Sraj 371235609Sgber if (fdt_is_compatible(child, "mrvl,lbc")) { 372235609Sgber /* Check available space */ 373235609Sgber if (OF_getprop(child, "bank-count", (void *)&bank_count, 374235609Sgber sizeof(bank_count)) <= 0) 375235609Sgber /* If no property, use default value */ 376235609Sgber bank_count = 1; 377235609Sgber else 378235609Sgber bank_count = fdt32_to_cpu(bank_count); 379235609Sgber 380235609Sgber if ((i + bank_count) >= FDT_DEVMAP_MAX) 381235609Sgber return (ENOMEM); 382235609Sgber 383235609Sgber /* Add all localbus ranges to device map */ 384235609Sgber num_mapped = 0; 385235609Sgber 386235609Sgber if (fdt_localbus_devmap(child, &fdt_devmap[i], 387235609Sgber (int)bank_count, &num_mapped) != 0) 388235609Sgber return (ENXIO); 389235609Sgber 390235609Sgber i += num_mapped; 391235609Sgber } 392235609Sgber } 393235609Sgber 394209131Sraj return (0); 395209131Sraj} 396209131Sraj 397183840Srajstruct arm32_dma_range * 398183840Srajbus_dma_get_range(void) 399183840Sraj{ 400183840Sraj 401183840Sraj return (NULL); 402183840Sraj} 403183840Sraj 404183840Srajint 405183840Srajbus_dma_get_range_nb(void) 406183840Sraj{ 407183840Sraj 408183840Sraj return (0); 409183840Sraj} 410239277Sgonzo 411239277Sgonzo#if defined(CPU_MV_PJ4B) 412239277Sgonzo#ifdef DDB 413239277Sgonzo#include <ddb/ddb.h> 414239277Sgonzo 415239277SgonzoDB_SHOW_COMMAND(cp15, db_show_cp15) 416239277Sgonzo{ 417239277Sgonzo u_int reg; 418239277Sgonzo 419239277Sgonzo __asm __volatile("mrc p15, 0, %0, c0, c0, 0" : "=r" (reg)); 420239277Sgonzo db_printf("Cpu ID: 0x%08x\n", reg); 421239277Sgonzo __asm __volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (reg)); 422239277Sgonzo db_printf("Current Cache Lvl ID: 0x%08x\n",reg); 423239277Sgonzo 424239277Sgonzo __asm __volatile("mrc p15, 0, %0, c1, c0, 0" : "=r" (reg)); 425239277Sgonzo db_printf("Ctrl: 0x%08x\n",reg); 426239277Sgonzo __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (reg)); 427239277Sgonzo db_printf("Aux Ctrl: 0x%08x\n",reg); 428239277Sgonzo 429239277Sgonzo __asm __volatile("mrc p15, 0, %0, c0, c1, 0" : "=r" (reg)); 430239277Sgonzo db_printf("Processor Feat 0: 0x%08x\n", reg); 431239277Sgonzo __asm __volatile("mrc p15, 0, %0, c0, c1, 1" : "=r" (reg)); 432239277Sgonzo db_printf("Processor Feat 1: 0x%08x\n", reg); 433239277Sgonzo __asm __volatile("mrc p15, 0, %0, c0, c1, 2" : "=r" (reg)); 434239277Sgonzo db_printf("Debug Feat 0: 0x%08x\n", reg); 435239277Sgonzo __asm __volatile("mrc p15, 0, %0, c0, c1, 3" : "=r" (reg)); 436239277Sgonzo db_printf("Auxiliary Feat 0: 0x%08x\n", reg); 437239277Sgonzo __asm __volatile("mrc p15, 0, %0, c0, c1, 4" : "=r" (reg)); 438239277Sgonzo db_printf("Memory Model Feat 0: 0x%08x\n", reg); 439239277Sgonzo __asm __volatile("mrc p15, 0, %0, c0, c1, 5" : "=r" (reg)); 440239277Sgonzo db_printf("Memory Model Feat 1: 0x%08x\n", reg); 441239277Sgonzo __asm __volatile("mrc p15, 0, %0, c0, c1, 6" : "=r" (reg)); 442239277Sgonzo db_printf("Memory Model Feat 2: 0x%08x\n", reg); 443239277Sgonzo __asm __volatile("mrc p15, 0, %0, c0, c1, 7" : "=r" (reg)); 444239277Sgonzo db_printf("Memory Model Feat 3: 0x%08x\n", reg); 445239277Sgonzo 446239277Sgonzo __asm __volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (reg)); 447239277Sgonzo db_printf("Aux Func Modes Ctrl 0: 0x%08x\n",reg); 448239277Sgonzo __asm __volatile("mrc p15, 1, %0, c15, c2, 1" : "=r" (reg)); 449239277Sgonzo db_printf("Aux Func Modes Ctrl 1: 0x%08x\n",reg); 450239277Sgonzo 451239277Sgonzo __asm __volatile("mrc p15, 1, %0, c15, c12, 0" : "=r" (reg)); 452239277Sgonzo db_printf("CPU ID code extension: 0x%08x\n",reg); 453239277Sgonzo} 454239277Sgonzo 455239277SgonzoDB_SHOW_COMMAND(vtop, db_show_vtop) 456239277Sgonzo{ 457239277Sgonzo u_int reg; 458239277Sgonzo 459239277Sgonzo if (have_addr) { 460239277Sgonzo __asm __volatile("mcr p15, 0, %0, c7, c8, 0" : : "r" (addr)); 461239277Sgonzo __asm __volatile("mrc p15, 0, %0, c7, c4, 0" : "=r" (reg)); 462239277Sgonzo db_printf("Physical address reg: 0x%08x\n",reg); 463239277Sgonzo } else 464239277Sgonzo db_printf("show vtop <virt_addr>\n"); 465239277Sgonzo} 466239277Sgonzo#endif /* DDB */ 467239277Sgonzo#endif /* CPU_MV_PJ4B */ 468239277Sgonzo 469