1/*- 2 * Copyright (c) 1994-1998 Mark Brinicombe. 3 * Copyright (c) 1994 Brini. 4 * All rights reserved. 5 * 6 * This code is derived from software written for Brini by Mark Brinicombe 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Brini. 19 * 4. The name of the company nor the name of the author may be used to 20 * endorse or promote products derived from this software without specific 21 * prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 29 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * from: FreeBSD: //depot/projects/arm/src/sys/arm/at91/kb920x_machdep.c, rev 45 36 */ 37 38#include "opt_ddb.h" 39#include "opt_platform.h" 40 41#include <sys/cdefs.h> 42__FBSDID("$FreeBSD$"); 43 44#define _ARM32_BUS_DMA_PRIVATE 45#include <sys/param.h> 46#include <sys/systm.h> 47#include <sys/bus.h> 48 49#include <vm/vm.h> 50#include <vm/pmap.h> 51 52#include <machine/bus.h> 53#include <machine/frame.h> /* For trapframe_t, used in <machine/machdep.h> */ 54#include <machine/machdep.h> 55#include <machine/pmap.h> 56 57#include <arm/mv/mvreg.h> /* XXX */ 58#include <arm/mv/mvvar.h> /* XXX eventually this should be eliminated */ 59#include <arm/mv/mvwin.h> 60 61#include <dev/fdt/fdt_common.h> 62 63static int platform_mpp_init(void); 64#if defined(SOC_MV_ARMADAXP) 65void armadaxp_init_coher_fabric(void); 66void armadaxp_l2_init(void); 67#endif 68 69#define MPP_PIN_MAX 68 70#define MPP_PIN_CELLS 2 71#define MPP_PINS_PER_REG 8 72#define MPP_SEL(pin,func) (((func) & 0xf) << \ 73 (((pin) % MPP_PINS_PER_REG) * 4)) 74 75static int 76platform_mpp_init(void) 77{ 78 pcell_t pinmap[MPP_PIN_MAX * MPP_PIN_CELLS]; 79 int mpp[MPP_PIN_MAX]; 80 uint32_t ctrl_val, ctrl_offset; 81 pcell_t reg[4]; 82 u_long start, size; 83 phandle_t node; 84 pcell_t pin_cells, *pinmap_ptr, pin_count; 85 ssize_t len; 86 int par_addr_cells, par_size_cells; 87 int tuple_size, tuples, rv, pins, i, j; 88 int mpp_pin, mpp_function; 89 90 /* 91 * Try to access the MPP node directly i.e. through /aliases/mpp. 92 */ 93 if ((node = OF_finddevice("mpp")) != -1) 94 if (fdt_is_compatible(node, "mrvl,mpp")) 95 goto moveon; 96 /* 97 * Find the node the long way. 98 */ 99 if ((node = OF_finddevice("/")) == -1) 100 return (ENXIO); 101 102 if ((node = fdt_find_compatible(node, "simple-bus", 0)) == 0) 103 return (ENXIO); 104 105 if ((node = fdt_find_compatible(node, "mrvl,mpp", 0)) == 0) 106 /* 107 * No MPP node. Fall back to how MPP got set by the 108 * first-stage loader and try to continue booting. 109 */ 110 return (0); 111moveon: 112 /* 113 * Process 'reg' prop. 114 */ 115 if ((rv = fdt_addrsize_cells(OF_parent(node), &par_addr_cells, 116 &par_size_cells)) != 0) 117 return(ENXIO); 118 119 tuple_size = sizeof(pcell_t) * (par_addr_cells + par_size_cells); 120 len = OF_getprop(node, "reg", reg, sizeof(reg)); 121 tuples = len / tuple_size; 122 if (tuple_size <= 0) 123 return (EINVAL); 124 125 /* 126 * Get address/size. XXX we assume only the first 'reg' tuple is used. 127 */ 128 rv = fdt_data_to_res(reg, par_addr_cells, par_size_cells, 129 &start, &size); 130 if (rv != 0) 131 return (rv); 132 start += fdt_immr_va; 133 134 /* 135 * Process 'pin-count' and 'pin-map' props. 136 */ 137 if (OF_getprop(node, "pin-count", &pin_count, sizeof(pin_count)) <= 0) 138 return (ENXIO); 139 pin_count = fdt32_to_cpu(pin_count); 140 if (pin_count > MPP_PIN_MAX) 141 return (ERANGE); 142 143 if (OF_getprop(node, "#pin-cells", &pin_cells, sizeof(pin_cells)) <= 0) 144 pin_cells = MPP_PIN_CELLS; 145 pin_cells = fdt32_to_cpu(pin_cells); 146 if (pin_cells > MPP_PIN_CELLS) 147 return (ERANGE); 148 tuple_size = sizeof(pcell_t) * pin_cells; 149 150 bzero(pinmap, sizeof(pinmap)); 151 len = OF_getprop(node, "pin-map", pinmap, sizeof(pinmap)); 152 if (len <= 0) 153 return (ERANGE); 154 if (len % tuple_size) 155 return (ERANGE); 156 pins = len / tuple_size; 157 if (pins > pin_count) 158 return (ERANGE); 159 /* 160 * Fill out a "mpp[pin] => function" table. All pins unspecified in 161 * the 'pin-map' property are defaulted to 0 function i.e. GPIO. 162 */ 163 bzero(mpp, sizeof(mpp)); 164 pinmap_ptr = pinmap; 165 for (i = 0; i < pins; i++) { 166 mpp_pin = fdt32_to_cpu(*pinmap_ptr); 167 mpp_function = fdt32_to_cpu(*(pinmap_ptr + 1)); 168 mpp[mpp_pin] = mpp_function; 169 pinmap_ptr += pin_cells; 170 } 171 172 /* 173 * Prepare and program MPP control register values. 174 */ 175 ctrl_offset = 0; 176 for (i = 0; i < pin_count;) { 177 ctrl_val = 0; 178 179 for (j = 0; j < MPP_PINS_PER_REG; j++) { 180 if (i + j == pin_count - 1) 181 break; 182 ctrl_val |= MPP_SEL(i + j, mpp[i + j]); 183 } 184 i += MPP_PINS_PER_REG; 185 bus_space_write_4(fdtbus_bs_tag, start, ctrl_offset, 186 ctrl_val); 187 188#if defined(SOC_MV_ORION) 189 /* 190 * Third MPP reg on Orion SoC is placed 191 * non-linearly (with different offset). 192 */ 193 if (i == (2 * MPP_PINS_PER_REG)) 194 ctrl_offset = 0x50; 195 else 196#endif 197 ctrl_offset += 4; 198 } 199 200 return (0); 201} 202 203vm_offset_t 204initarm_lastaddr(void) 205{ 206 207 if (fdt_immr_addr(MV_BASE) != 0) 208 while (1); 209 210 /* Platform-specific initialisation */ 211 return (fdt_immr_va - ARM_NOCACHE_KVA_SIZE); 212} 213 214void 215initarm_gpio_init(void) 216{ 217 218 /* 219 * Re-initialise MPP. It is important to call this prior to using 220 * console as the physical connection can be routed via MPP. 221 */ 222 if (platform_mpp_init() != 0) 223 while (1); 224} 225 226void 227initarm_late_init(void) 228{ 229 /* 230 * Re-initialise decode windows 231 */ 232#if !defined(SOC_MV_FREY) 233 if (soc_decode_win() != 0) 234 printf("WARNING: could not re-initialise decode windows! " 235 "Running with existing settings...\n"); 236#else 237 /* Disable watchdog and timers */ 238 write_cpu_ctrl(CPU_TIMERS_BASE + CPU_TIMER_CONTROL, 0); 239#endif 240#if defined(SOC_MV_ARMADAXP) 241#if !defined(SMP) 242 /* For SMP case it should be initialized after APs are booted */ 243 armadaxp_init_coher_fabric(); 244#endif 245 armadaxp_l2_init(); 246#endif 247} 248 249#define FDT_DEVMAP_MAX (MV_WIN_CPU_MAX + 2) 250static struct pmap_devmap fdt_devmap[FDT_DEVMAP_MAX] = { 251 { 0, 0, 0, 0, 0, } 252}; 253 254static int 255platform_sram_devmap(struct pmap_devmap *map) 256{ 257#if !defined(SOC_MV_ARMADAXP) 258 phandle_t child, root; 259 u_long base, size; 260 /* 261 * SRAM range. 262 */ 263 if ((child = OF_finddevice("/sram")) != 0) 264 if (fdt_is_compatible(child, "mrvl,cesa-sram") || 265 fdt_is_compatible(child, "mrvl,scratchpad")) 266 goto moveon; 267 268 if ((root = OF_finddevice("/")) == 0) 269 return (ENXIO); 270 271 if ((child = fdt_find_compatible(root, "mrvl,cesa-sram", 0)) == 0 && 272 (child = fdt_find_compatible(root, "mrvl,scratchpad", 0)) == 0) 273 goto out; 274 275moveon: 276 if (fdt_regsize(child, &base, &size) != 0) 277 return (EINVAL); 278 279 map->pd_va = MV_CESA_SRAM_BASE; /* XXX */ 280 map->pd_pa = base; 281 map->pd_size = size; 282 map->pd_prot = VM_PROT_READ | VM_PROT_WRITE; 283 map->pd_cache = PTE_NOCACHE; 284 285 return (0); 286out: 287#endif 288 return (ENOENT); 289 290} 291 292/* 293 * Supply a default do-nothing implementation of fdt_pci_devmap() via a weak 294 * alias. Many Marvell platforms don't support a PCI interface, but to support 295 * those that do, we end up with a reference to this function below, in 296 * platform_devmap_init(). If "device pci" appears in the kernel config, the 297 * real implementation of this function in dev/fdt/fdt_pci.c overrides the weak 298 * alias defined here. 299 */ 300int mv_default_fdt_pci_devmap(phandle_t node, struct pmap_devmap *devmap, 301 vm_offset_t io_va, vm_offset_t mem_va); 302int 303mv_default_fdt_pci_devmap(phandle_t node, struct pmap_devmap *devmap, 304 vm_offset_t io_va, vm_offset_t mem_va) 305{ 306 307 return (0); 308} 309__weak_reference(mv_default_fdt_pci_devmap, fdt_pci_devmap); 310 311/* 312 * XXX: When device entry in devmap has pd_size smaller than section size, 313 * system will freeze during initialization 314 */ 315 316/* 317 * Construct pmap_devmap[] with DT-derived config data. 318 */ 319int 320platform_devmap_init(void) 321{ 322 phandle_t root, child; 323 pcell_t bank_count; 324 int i, num_mapped; 325 326 i = 0; 327 pmap_devmap_bootstrap_table = &fdt_devmap[0]; 328 329 /* 330 * IMMR range. 331 */ 332 fdt_devmap[i].pd_va = fdt_immr_va; 333 fdt_devmap[i].pd_pa = fdt_immr_pa; 334 fdt_devmap[i].pd_size = fdt_immr_size; 335 fdt_devmap[i].pd_prot = VM_PROT_READ | VM_PROT_WRITE; 336 fdt_devmap[i].pd_cache = PTE_NOCACHE; 337 i++; 338 339 /* 340 * SRAM range. 341 */ 342 if (i < FDT_DEVMAP_MAX) 343 if (platform_sram_devmap(&fdt_devmap[i]) == 0) 344 i++; 345 346 /* 347 * PCI range(s). 348 * PCI range(s) and localbus. 349 */ 350 if ((root = OF_finddevice("/")) == -1) 351 return (ENXIO); 352 for (child = OF_child(root); child != 0; child = OF_peer(child)) { 353 if (fdt_is_type(child, "pci") || fdt_is_type(child, "pciep")) { 354 /* 355 * Check space: each PCI node will consume 2 devmap 356 * entries. 357 */ 358 if (i + 1 >= FDT_DEVMAP_MAX) 359 return (ENOMEM); 360 361 /* 362 * XXX this should account for PCI and multiple ranges 363 * of a given kind. 364 */ 365 if (fdt_pci_devmap(child, &fdt_devmap[i], MV_PCI_VA_IO_BASE, 366 MV_PCI_VA_MEM_BASE) != 0) 367 return (ENXIO); 368 i += 2; 369 } 370 371 if (fdt_is_compatible(child, "mrvl,lbc")) { 372 /* Check available space */ 373 if (OF_getprop(child, "bank-count", (void *)&bank_count, 374 sizeof(bank_count)) <= 0) 375 /* If no property, use default value */ 376 bank_count = 1; 377 else 378 bank_count = fdt32_to_cpu(bank_count); 379 380 if ((i + bank_count) >= FDT_DEVMAP_MAX) 381 return (ENOMEM); 382 383 /* Add all localbus ranges to device map */ 384 num_mapped = 0; 385 386 if (fdt_localbus_devmap(child, &fdt_devmap[i], 387 (int)bank_count, &num_mapped) != 0) 388 return (ENXIO); 389 390 i += num_mapped; 391 } 392 } 393 394 return (0); 395} 396 397struct arm32_dma_range * 398bus_dma_get_range(void) 399{ 400 401 return (NULL); 402} 403 404int 405bus_dma_get_range_nb(void) 406{ 407 408 return (0); 409} 410 411#if defined(CPU_MV_PJ4B) 412#ifdef DDB 413#include <ddb/ddb.h> 414 415DB_SHOW_COMMAND(cp15, db_show_cp15) 416{ 417 u_int reg; 418 419 __asm __volatile("mrc p15, 0, %0, c0, c0, 0" : "=r" (reg)); 420 db_printf("Cpu ID: 0x%08x\n", reg); 421 __asm __volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (reg)); 422 db_printf("Current Cache Lvl ID: 0x%08x\n",reg); 423 424 __asm __volatile("mrc p15, 0, %0, c1, c0, 0" : "=r" (reg)); 425 db_printf("Ctrl: 0x%08x\n",reg); 426 __asm __volatile("mrc p15, 0, %0, c1, c0, 1" : "=r" (reg)); 427 db_printf("Aux Ctrl: 0x%08x\n",reg); 428 429 __asm __volatile("mrc p15, 0, %0, c0, c1, 0" : "=r" (reg)); 430 db_printf("Processor Feat 0: 0x%08x\n", reg); 431 __asm __volatile("mrc p15, 0, %0, c0, c1, 1" : "=r" (reg)); 432 db_printf("Processor Feat 1: 0x%08x\n", reg); 433 __asm __volatile("mrc p15, 0, %0, c0, c1, 2" : "=r" (reg)); 434 db_printf("Debug Feat 0: 0x%08x\n", reg); 435 __asm __volatile("mrc p15, 0, %0, c0, c1, 3" : "=r" (reg)); 436 db_printf("Auxiliary Feat 0: 0x%08x\n", reg); 437 __asm __volatile("mrc p15, 0, %0, c0, c1, 4" : "=r" (reg)); 438 db_printf("Memory Model Feat 0: 0x%08x\n", reg); 439 __asm __volatile("mrc p15, 0, %0, c0, c1, 5" : "=r" (reg)); 440 db_printf("Memory Model Feat 1: 0x%08x\n", reg); 441 __asm __volatile("mrc p15, 0, %0, c0, c1, 6" : "=r" (reg)); 442 db_printf("Memory Model Feat 2: 0x%08x\n", reg); 443 __asm __volatile("mrc p15, 0, %0, c0, c1, 7" : "=r" (reg)); 444 db_printf("Memory Model Feat 3: 0x%08x\n", reg); 445 446 __asm __volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (reg)); 447 db_printf("Aux Func Modes Ctrl 0: 0x%08x\n",reg); 448 __asm __volatile("mrc p15, 1, %0, c15, c2, 1" : "=r" (reg)); 449 db_printf("Aux Func Modes Ctrl 1: 0x%08x\n",reg); 450 451 __asm __volatile("mrc p15, 1, %0, c15, c12, 0" : "=r" (reg)); 452 db_printf("CPU ID code extension: 0x%08x\n",reg); 453} 454 455DB_SHOW_COMMAND(vtop, db_show_vtop) 456{ 457 u_int reg; 458 459 if (have_addr) { 460 __asm __volatile("mcr p15, 0, %0, c7, c8, 0" : : "r" (addr)); 461 __asm __volatile("mrc p15, 0, %0, c7, c4, 0" : "=r" (reg)); 462 db_printf("Physical address reg: 0x%08x\n",reg); 463 } else 464 db_printf("show vtop <virt_addr>\n"); 465} 466#endif /* DDB */ 467#endif /* CPU_MV_PJ4B */ 468 469