1/*- 2 * Copyright (c) 2011 Jakub Wojciech Klama <jceel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 */ 27 28#include <sys/cdefs.h> 29__FBSDID("$FreeBSD$"); 30 31#include <sys/param.h> 32#include <sys/systm.h> 33#include <sys/bio.h> 34#include <sys/bus.h> 35#include <sys/conf.h> 36#include <sys/endian.h> 37#include <sys/kernel.h> 38#include <sys/kthread.h> 39#include <sys/lock.h> 40#include <sys/malloc.h> 41#include <sys/module.h> 42#include <sys/mutex.h> 43#include <sys/queue.h> 44#include <sys/resource.h> 45#include <sys/rman.h> 46#include <sys/time.h> 47#include <sys/timetc.h> 48#include <sys/watchdog.h> 49 50#include <sys/kdb.h> 51 52#include <dev/ofw/ofw_bus.h> 53#include <dev/ofw/ofw_bus_subr.h> 54 55#include <arm/lpc/lpcreg.h> 56#include <arm/lpc/lpcvar.h> 57 58struct lpc_dmac_channel 59{ 60 struct lpc_dmac_channel_config *ldc_config; 61 int ldc_flags; 62}; 63 64struct lpc_dmac_softc 65{ 66 device_t ld_dev; 67 struct mtx ld_mtx; 68 struct resource * ld_mem_res; 69 struct resource * ld_irq_res; 70 bus_space_tag_t ld_bst; 71 bus_space_handle_t ld_bsh; 72 void * ld_intrhand; 73 struct lpc_dmac_channel ld_channels[8]; 74}; 75 76static struct lpc_dmac_softc *lpc_dmac_sc = NULL; 77 78static int lpc_dmac_probe(device_t); 79static int lpc_dmac_attach(device_t); 80static void lpc_dmac_intr(void *); 81 82#define lpc_dmac_read_4(_sc, _reg) \ 83 bus_space_read_4(_sc->ld_bst, _sc->ld_bsh, _reg) 84#define lpc_dmac_write_4(_sc, _reg, _value) \ 85 bus_space_write_4(_sc->ld_bst, _sc->ld_bsh, _reg, _value) 86#define lpc_dmac_read_ch_4(_sc, _n, _reg) \ 87 bus_space_read_4(_sc->ld_bst, _sc->ld_bsh, (_reg + LPC_DMAC_CHADDR(_n))) 88#define lpc_dmac_write_ch_4(_sc, _n, _reg, _value) \ 89 bus_space_write_4(_sc->ld_bst, _sc->ld_bsh, (_reg + LPC_DMAC_CHADDR(_n)), _value) 90 91static int lpc_dmac_probe(device_t dev) 92{ 93 if (!ofw_bus_is_compatible(dev, "lpc,dmac")) 94 return (ENXIO); 95 96 device_set_desc(dev, "LPC32x0 General Purpose DMA controller"); 97 return (BUS_PROBE_DEFAULT); 98} 99 100static int lpc_dmac_attach(device_t dev) 101{ 102 struct lpc_dmac_softc *sc = device_get_softc(dev); 103 int rid; 104 105 rid = 0; 106 sc->ld_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 107 RF_ACTIVE); 108 if (!sc->ld_mem_res) { 109 device_printf(dev, "cannot allocate memory window\n"); 110 return (ENXIO); 111 } 112 113 sc->ld_bst = rman_get_bustag(sc->ld_mem_res); 114 sc->ld_bsh = rman_get_bushandle(sc->ld_mem_res); 115 116 rid = 0; 117 sc->ld_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 118 RF_ACTIVE); 119 if (!sc->ld_irq_res) { 120 device_printf(dev, "cannot allocate cmd interrupt\n"); 121 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->ld_mem_res); 122 return (ENXIO); 123 } 124 125 if (bus_setup_intr(dev, sc->ld_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 126 NULL, lpc_dmac_intr, sc, &sc->ld_intrhand)) 127 { 128 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->ld_mem_res); 129 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->ld_irq_res); 130 device_printf(dev, "cannot setup interrupt handler\n"); 131 return (ENXIO); 132 } 133 134 lpc_dmac_sc = sc; 135 136 lpc_pwr_write(dev, LPC_CLKPWR_DMACLK_CTRL, LPC_CLKPWR_DMACLK_CTRL_EN); 137 lpc_dmac_write_4(sc, LPC_DMAC_CONFIG, LPC_DMAC_CONFIG_ENABLE); 138 139 lpc_dmac_write_4(sc, LPC_DMAC_INTTCCLEAR, 0xff); 140 lpc_dmac_write_4(sc, LPC_DMAC_INTERRCLEAR, 0xff); 141 142 return (0); 143} 144 145static void lpc_dmac_intr(void *arg) 146{ 147 struct lpc_dmac_softc *sc = (struct lpc_dmac_softc *)arg; 148 struct lpc_dmac_channel *ch; 149 uint32_t intstat, tcstat, errstat; 150 int i; 151 152 do { 153 intstat = lpc_dmac_read_4(sc, LPC_DMAC_INTSTAT); 154 155 for (i = 0; i < LPC_DMAC_CHNUM; i++) { 156 if ((intstat & (1 << i)) == 0) 157 continue; 158 159 ch = &sc->ld_channels[i]; 160 tcstat = lpc_dmac_read_4(sc, LPC_DMAC_INTTCSTAT); 161 errstat = lpc_dmac_read_4(sc, LPC_DMAC_INTERRSTAT); 162 163 if (tcstat & (1 << i)) { 164 ch->ldc_config->ldc_success_handler( 165 ch->ldc_config->ldc_handler_arg); 166 lpc_dmac_write_4(sc, LPC_DMAC_INTTCCLEAR, (1 << i)); 167 } 168 169 if (errstat & (1 << i)) { 170 ch->ldc_config->ldc_error_handler( 171 ch->ldc_config->ldc_handler_arg); 172 lpc_dmac_write_4(sc, LPC_DMAC_INTERRCLEAR, (1 << i)); 173 } 174 } 175 176 } while (intstat); 177} 178 179int 180lpc_dmac_config_channel(device_t dev, int chno, struct lpc_dmac_channel_config *cfg) 181{ 182 struct lpc_dmac_softc *sc = lpc_dmac_sc; 183 struct lpc_dmac_channel *ch; 184 185 if (sc == NULL) 186 return (ENXIO); 187 188 ch = &sc->ld_channels[chno]; 189 ch->ldc_config = cfg; 190 191 return 0; 192} 193 194int 195lpc_dmac_setup_transfer(device_t dev, int chno, bus_addr_t src, bus_addr_t dst, 196 bus_size_t size, int flags) 197{ 198 struct lpc_dmac_softc *sc = lpc_dmac_sc; 199 struct lpc_dmac_channel *ch; 200 uint32_t ctrl, cfg; 201 202 if (sc == NULL) 203 return (ENXIO); 204 205 ch = &sc->ld_channels[chno]; 206 207 ctrl = LPC_DMAC_CH_CONTROL_I | 208 (ch->ldc_config->ldc_dst_incr ? LPC_DMAC_CH_CONTROL_DI : 0) | 209 (ch->ldc_config->ldc_src_incr ? LPC_DMAC_CH_CONTROL_SI : 0) | 210 LPC_DMAC_CH_CONTROL_DWIDTH(ch->ldc_config->ldc_dst_width) | 211 LPC_DMAC_CH_CONTROL_SWIDTH(ch->ldc_config->ldc_src_width) | 212 LPC_DMAC_CH_CONTROL_DBSIZE(ch->ldc_config->ldc_dst_burst) | 213 LPC_DMAC_CH_CONTROL_SBSIZE(ch->ldc_config->ldc_src_burst) | 214 size; 215 216 cfg = LPC_DMAC_CH_CONFIG_ITC | LPC_DMAC_CH_CONFIG_IE | 217 LPC_DMAC_CH_CONFIG_FLOWCNTL(ch->ldc_config->ldc_fcntl) | 218 LPC_DMAC_CH_CONFIG_DESTP(ch->ldc_config->ldc_dst_periph) | 219 LPC_DMAC_CH_CONFIG_SRCP(ch->ldc_config->ldc_src_periph) | LPC_DMAC_CH_CONFIG_E; 220 lpc_dmac_write_ch_4(sc, chno, LPC_DMAC_CH_SRCADDR, src); 221 lpc_dmac_write_ch_4(sc, chno, LPC_DMAC_CH_DSTADDR, dst); 222 lpc_dmac_write_ch_4(sc, chno, LPC_DMAC_CH_LLI, 0); 223 lpc_dmac_write_ch_4(sc, chno, LPC_DMAC_CH_CONTROL, ctrl); 224 lpc_dmac_write_ch_4(sc, chno, LPC_DMAC_CH_CONFIG, cfg); 225 226 return 0; 227} 228 229int 230lpc_dmac_enable_channel(device_t dev, int chno) 231{ 232 struct lpc_dmac_softc *sc = lpc_dmac_sc; 233 uint32_t cfg; 234 235 if (sc == NULL) 236 return (ENXIO); 237 238 cfg = lpc_dmac_read_ch_4(sc, chno, LPC_DMAC_CH_CONFIG); 239 cfg |= LPC_DMAC_CH_CONFIG_E; 240 241 lpc_dmac_write_ch_4(sc, chno, LPC_DMAC_CH_CONFIG, cfg); 242 243 return 0; 244} 245 246int 247lpc_dmac_disable_channel(device_t dev, int chno) 248{ 249 struct lpc_dmac_softc *sc = lpc_dmac_sc; 250 uint32_t cfg; 251 252 if (sc == NULL) 253 return (ENXIO); 254 255 cfg = lpc_dmac_read_ch_4(sc, chno, LPC_DMAC_CH_CONFIG); 256 cfg &= ~LPC_DMAC_CH_CONFIG_E; 257 258 lpc_dmac_write_ch_4(sc, chno, LPC_DMAC_CH_CONFIG, cfg); 259 260 return 0; 261} 262 263int 264lpc_dmac_start_burst(device_t dev, int id) 265{ 266 struct lpc_dmac_softc *sc = lpc_dmac_sc; 267 268 lpc_dmac_write_4(sc, LPC_DMAC_SOFTBREQ, (1 << id)); 269 return (0); 270} 271 272static device_method_t lpc_dmac_methods[] = { 273 /* Device interface */ 274 DEVMETHOD(device_probe, lpc_dmac_probe), 275 DEVMETHOD(device_attach, lpc_dmac_attach), 276 277 { 0, 0 }, 278}; 279 280static devclass_t lpc_dmac_devclass; 281 282static driver_t lpc_dmac_driver = { 283 "dmac", 284 lpc_dmac_methods, 285 sizeof(struct lpc_dmac_softc), 286}; 287 288DRIVER_MODULE(dmac, simplebus, lpc_dmac_driver, lpc_dmac_devclass, 0, 0); 289